Semiconductor device and electrical contact structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor device, an electrical contact structure and a manufacturing method thereof. By connecting the tops of at least two contact plugs formed at the boundary of the core component area, a combined contact structure with a larger top cross-sectional area is formed at the boundary of the core component area. Therefore, sufficient process margin is provided for the subsequent process of forming an electrical structure above the contact structure at the boundary of the core component area, so that the size of the electrical structure at the boundary is increased, the contact impedance is reduced, and the density difference of the circuit pattern between the core component area and the peripheral circuit area is buffered by the electrical structure with an increased size at the boundary, the optical proximity effect is improved, the consistency of the electrical structure above the contact plug within the boundary of the core component area is ensured, and the electrical structure above the contact plug at the boundary is prevented from collapsing, thereby improving device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, an electrical contact structure and a manufacturing method thereof. Background Art

[0002] Various technologies are being used to integrate more circuit patterns within the limited area of ​​a semiconductor substrate or wafer. Due to the varying pitches between circuit patterns, integrated circuits are generally divided into dense regions (Dense), sparse regions (ISO), and isolated regions. Dense regions are areas with a higher device density (i.e., densely packed devices), sparse regions are areas with a lower device density (i.e., sparsely packed devices), and isolated regions are areas separated from the dense and sparse regions. As the critical dimensions of semiconductor devices continue to decrease, the density of circuit patterns and / or device heights continue to increase. This, coupled with the resolution limitations of optical exposure tools and the density difference between dense and sparse regions (i.e., the dense / sparse effect of circuit patterns), significantly increases the difficulty in performing photolithography and / or etching processes (e.g., reduces process margins), thereby impacting the performance of the resulting semiconductor devices.

[0003] For example, in a dynamic random access memory (DRAM) device, a large number of memory cells are gathered to form an array memory area, and a peripheral circuit area exists next to the array memory area. The peripheral circuit area includes other transistor elements and contact structures. The array memory area serves as a device-intensive area of ​​the DRAM and is used to store data. The peripheral circuit area serves as a device-sparse area of ​​the DRAM and is used to provide input and output signals required by the array memory area. Each memory cell in the array memory area may be composed of a metal oxide semiconductor (MOS) transistor and a capacitor structure connected in series. The capacitor is located in the array memory area, wherein the capacitor is stacked above the bit line and electrically coupled to the storage node contact corresponding to the capacitor, and the storage node contact is electrically coupled to the active area thereunder. With the continuous development of semiconductor technology, the critical dimensions of devices are constantly decreasing, and the gaps between memory cells in DRAM devices are becoming narrower. When forming storage node contacts through the self-aligned contact (SAC) process, the resolution limit of the optical exposure tool (optical exposure tool) and the density difference effect between the dense device area and the sparse device area are affected. As a result, the contact holes formed within the array storage area are inconsistent, and the contact holes at the boundaries of the dense device area are abnormal. This leads to a decrease in the contact area between the capacitor formed above and the contact plug in the contact hole and an increase in contact impedance. This may cause some storage bits to fail due to open circuit or short circuit problems of the contact plug, and the capacitor at the boundary of the array storage area to collapse. These problems affect and limit the improvement of DRAM performance. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device, an electrical contact structure and a manufacturing method thereof, so as to solve the problems in existing semiconductor devices such as dynamic random access memory, such as inconsistent electrical structures connected to contact plugs inside the core component area and abnormal electrical structures connected to contact plugs at the boundaries of the core component area due to optical proximity effects and dense / sparse effects of circuit patterns.

[0005] In order to solve the above technical problems, the present invention provides an electrical contact structure of a semiconductor device, the electrical contact structure comprising:

[0006] A plurality of contact plugs are formed above the core element of the core element region of the semiconductor device, and the bottom of each contact plug contacts the active area of ​​the corresponding core element.

[0007] The tops of at least two contact plugs formed at the boundary of the core device region are connected together, and the contact plugs with the connected tops include the outermost contact plug at the boundary.

[0008] Based on the same inventive concept, the present invention further provides a semiconductor device, comprising:

[0009] A semiconductor substrate having a core component region in which a plurality of core components are formed;

[0010] an interlayer dielectric layer covering the semiconductor substrate; and

[0011] As described in the electrical contact structure of the semiconductor device of the present invention, the electrical contact structure is formed in the interlayer dielectric layer, the bottom of each contact plug of the electrical contact structure is in contact with the active area of ​​the corresponding core component, and the tops of at least two contact plugs formed at the boundary of the core component area in the electrical contact structure are connected together, and all the contact plugs connected at the top include the outermost contact plug at the boundary.

[0012] Based on the same inventive concept, the present invention also provides a method for manufacturing an electrical contact structure of a semiconductor device, comprising:

[0013] Providing a semiconductor substrate, wherein the semiconductor substrate has a core component region, and a plurality of core components are formed in the core component region;

[0014] forming an interlayer dielectric layer on the semiconductor substrate, and forming a plurality of contact holes in the interlayer dielectric layer, wherein each of the contact holes penetrates the interlayer dielectric layer and exposes an active area of ​​a corresponding core component;

[0015] Contact plugs are formed in the contact holes, and the bottom of each contact plug contacts the active area of ​​the corresponding core component, and the tops of at least two contact plugs formed at the boundary of the core component area are connected together, and all the contact plugs with the tops connected together include the outermost contact plug at the boundary.

[0016] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising: using the method for manufacturing the electrical contact structure of a semiconductor device described in the present invention to form an electrical contact structure that is electrically in contact with a corresponding core component on a semiconductor substrate having a core component area.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] By connecting the tops of at least two contact plugs formed at the boundary of the core component area, a combined contact structure with a larger top cross-sectional area is formed at the boundary of the core component area. Therefore, on the one hand, sufficient process margin can be provided for the subsequent process of forming an electrical structure (such as the lower plate of a DRAM capacitor) above the combined contact structure at the boundary of the core component area, which is beneficial to increase the size of the electrical structure at the boundary and avoid abnormalities or collapse of the electrical structure at the boundary; on the other hand, the electrical structure at the boundary and the combined contact structure can have a larger contact area, so the contact impedance is reduced, which is beneficial to improving the electrical performance of the device; more importantly, the size of the electrical structure at the boundary is increased, which can buffer the density difference of the circuit pattern between the core component area and the peripheral circuit area, thereby improving the optical proximity effect in the lithography process and / or etching process of forming all electrical structures in the core component area, reducing the sparse / dense load effect, ensuring the consistency of the electrical structure above the contact plug within the boundary of the core component area, and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1A to 1D is a schematic cross-sectional view of a method for manufacturing an electrical contact structure of a semiconductor device according to an embodiment of the present invention;

[0020] Figures 2A to 2D is a schematic cross-sectional structural diagram of a method for manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention;

[0021] Figure 3A is a schematic top view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0022] Figures 3B to 11 The present invention is an embodiment of a method for manufacturing a semiconductor device along the Figure 3A Schematic diagram of the cross-sectional structure of line aa'. DETAILED DESCRIPTION

[0023] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0024] Figure 1D FIG is a cross-sectional view showing an electrical contact structure of a semiconductor device according to an embodiment of the present invention. Figure 1DAn electrical contact structure for a semiconductor device provided by one embodiment of the present invention includes a plurality of contact plugs 106a and 106b, wherein the contact plugs 106a and 106b are formed above a core component (not shown) in a core component region I of the semiconductor device, and the bottom of each contact plug 106a and 106b contacts the active area 101 of the corresponding core component. The core component region I includes a boundary (or referred to as a boundary region, junction region, or interface region) I-2 and a central region I-1 located within the boundary I-2. The tops of at least two contact plugs 106b formed at the boundary I-2 of the core component region I are connected together. The core component region I is a device-intensive region, and the peripheral circuit region II surrounding it is a device-sparse region.

[0025] Each of the contact plugs 106a, 106b, 106c may include a barrier metal layer (not shown) and a metal layer (not shown). The barrier metal layer may include, for example, Ti, Ta, Mo, Ti x N y 、Ta x N y 、TixZry、Ti x Zr y N z 、Nb x N y 、Zr x N y 、W x N y 、V x N y , Hf x N y 、Mo x N y 、Ru x N y and / or Ti x Si y N z The metal layer may include, for example, tungsten, copper and / or aluminum.

[0026] All the contact plugs 106b connected together at the top of I-2 at the boundary of the core component area I form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, all the contact plugs 106b connected together at the top of I-2 at the boundary of the core component area I form a combined contact structure with a larger top cross-sectional area at the boundary I-2.

[0027] Please combine Figure 1D and Figure 11In this embodiment, the semiconductor device is a dynamic random access memory (DRAM), the core component area is the memory array area of ​​the DRAM memory, the core component is a memory transistor, and the electrical contact structure is a storage node contact portion, which is connected to a capacitor structure (i.e., a storage node). That is, each contact plug 106a in the central area I-1 of the core component area I is connected to a capacitor structure (e.g., Figure 11 705a), a capacitor structure is connected to a combined contact structure in I-2 at the boundary of the core component area I (as shown in FIG. Figure 11 As shown in 705b in FIG, the capacitor structure at the boundary I-2 has a first width W1, and the capacitor structure within the boundary I-2 of the core component area I (i.e., the central area I-1) has a second width W2. Due to the existence of the combined contact structure with a larger top cross-sectional area formed at the boundary I-2 of the core component area I, sufficient process margin can be provided for the formation process of the capacitor structure at the boundary I-2, so as to facilitate increasing the first width W1 of the capacitor structure at the boundary I-2, so that the first width W1 is greater than the second width W2, and thus, on the one hand, the capacitor structure formed at the boundary is prevented from collapsing; on the other hand, the capacitor structure at the boundary is made to be closer to the combined contact structure below it. The contact structures can have a larger contact area, which reduces the contact impedance and is conducive to improving the electrical performance of the device; more importantly, the size of the capacitor structure at the boundary is increased, which can buffer the density difference of the circuit pattern between the core component area I and the peripheral circuit area II, thereby improving the optical proximity effect when performing the photolithography process and / or etching process, reducing the sparse / dense load effect, and ensuring the consistency of the capacitor structure above the contact plug 106a in the area I-1 within I-2 at the boundary of the core component area I (i.e., the central area), and preventing the capacitor structure above the contact plug at some positions in the core component area I from being abnormal or the capacitor structure above the contact plug at the boundary I-2 from collapsing. Optionally, the first width W1 is greater than 1.5 times the second width W2.

[0028] Please refer to Figure 3A and Figure 11The semiconductor device includes a plurality of word lines WL and a plurality of bit lines BL, each of the word lines WL intersecting with a plurality of the active areas AA1 in the core component area I, the word lines WL may be buried word lines, the bit lines BL being formed above the core components of the core component area I and perpendicular to the word lines WL, a structure formed by all contact plugs connected together at the top (for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure) spans at least one of the word lines WL and is aligned with (i.e., parallel to) the bit lines BL, for example, the formed inverted U-shaped electrical contact structure spans a word line WL in an active area AA1 on the outermost boundary of the core component area I (i.e., the side of the boundary I-2 closest to the peripheral circuit area II, i.e., the outermost side of the boundary I-2). It should be noted that, in this embodiment, although the semiconductor device is DRAM as an example, the technical solution of the present invention is not limited to this. The semiconductor device can also be any suitable electrical device, such as a memory of other architectures. In this case, the capacitor structure can be replaced by a corresponding electrical structure, such as a resistor.

[0029] Figures 1A to 1D FIG is a schematic cross-sectional view of a device in a method for manufacturing an electrical contact structure of a semiconductor device according to this embodiment. Figures 1A to 1D This embodiment further provides a method for manufacturing an electrical contact structure of a semiconductor device, comprising the following steps:

[0030] First, please refer to Figure 1A A semiconductor substrate 100 is provided, which includes a core component region I and a peripheral circuit region II. The semiconductor substrate 100 can be selected from a silicon substrate, a silicon-on-insulator substrate (SOI), a germanium substrate, a germanium-on-insulator substrate (GOI), a silicon-germanium substrate, etc. A plurality of shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100. The shallow trench isolation structures are formed by etching the semiconductor substrate 100 to form trenches, and then filling the trenches with an insulating material. The material of the shallow trench isolation structures can include silicon oxide, silicon nitride, or silicon oxynitride. The shallow trench isolation structure defines the boundary between the core component region I and the peripheral circuit region II in a two-dimensional plane (i.e., defines the boundary I-2 of the core component region I), and also defines the active region 101 corresponding to each core component in the core component region I and the active region 101 corresponding to the peripheral components in the peripheral circuit region II.

[0031] Next, please continue to refer to Figure 1AAn interlayer dielectric layer 102 is formed over the semiconductor substrate 100. The interlayer dielectric layer 102 may be configured to have a single-layer structure or a multi-layer structure. The interlayer dielectric layer 102 may include at least one of silicon nitride, silicon oxynitride, and a low-k dielectric material. The low-k dielectric material has a dielectric constant k lower than that of a silicon oxide layer and may be used as an intermetallic dielectric (IMD) layer. Examples of such materials include high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), undoped silicate glass (USG), phospho-silicate glass (PSG), boron silicate glass (BSG), boron phospho-silicate glass (BPSG), fluorinated silicate glass (FSG), spin-on glass (SOG), and the like. Furthermore, an etch stop layer (not shown) may be formed between the semiconductor substrate 100 and the interlayer dielectric layer 102. The etch stop layer may include SiN, SiON, SiC, SiCN, boron nitride (BN), or any combination thereof. The etch stop layer and the interlayer dielectric layer 102 may be formed using plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), atmospheric pressure CVD (APCVD), and / or spin coating processes.

[0032] Then, please continue to refer to Figure 1A , through a first photolithography process, a first mask pattern 103 is formed on the interlayer dielectric layer 102, and the first mask pattern 103 defines the positions of each contact plug. Then, using the first mask pattern 103 as an etching mask, the interlayer dielectric layer 102 is anisotropically etched to form contact holes 102a, 102b and 102c that penetrate the interlayer dielectric layer 102 and expose the corresponding active area 101 below. The contact holes 102a, 102b and 102c are independent of each other. Each contact hole 102a is located in the central area I-1 of the core component area I and exposes the active area 101 of the corresponding core component in the central area I-1. Each contact hole 102b is located at the boundary I-2 of the core component area I and exposes the active area 101 of the corresponding core component in the boundary I-2. Each contact hole 102c is located in the peripheral circuit area II and exposes the active area 101 of the corresponding peripheral component.

[0033] Then, please refer to Figure 1B After forming the contact holes 102a-102c, an ashing process or a wet cleaning process may be performed to remove the first mask pattern 103 and fill each of the contact holes 102a-102c with a sacrificial layer 104. The sacrificial layer 104 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL), so that the contact holes 102a-102c having a high aspect ratio can be filled with the sacrificial layer 104.

[0034] Next, please continue to refer to Figure 1BA second photolithography process can be performed to form a second mask pattern 105 on the interlayer dielectric layer 102 and the sacrificial layer 104. The second mask pattern 105 defines a trench 102d for connecting the tops of at least two corresponding contact holes 102b at the boundary I-2. Using the second mask pattern 105 as a mask, the interlayer dielectric layer at the boundary I-2 is etched to form a trench 102d connecting the tops of at least two corresponding contact holes 102b at the boundary. The trench 102d exposes at least one of the outermost contact holes at the boundary I-2 (for example, the trench 102d exposes at least one of the outermost contact holes in a row at the core boundary I-2).

[0035] Please refer to Figure 1C The sacrificial layer 104 and the second mask pattern 105 in the contact holes 102a-102c, 102d may be removed by an ashing process using oxygen, ozone or ultraviolet rays or by a wet cleaning process to re-expose the contact holes 102a-102c and the trench 102d.

[0036] Please refer to Figure 1D A barrier metal layer (not shown) may be formed in the contact holes 102a-102c and the trench 102d. For example, the barrier metal layer may uniformly cover the inner walls of the contact holes and trenches and the top surface of the interlayer dielectric layer 102. The barrier metal layer can reduce or prevent the metal material disposed in the contact holes and trenches from diffusing into the interlayer dielectric layer 102. For example, the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, and may be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). A metal layer is then filled into each of the contact holes 102a-102c and the trench 102d to form contact plugs 106a, 106c and the combined contact structure 106b. The metal layer may be formed of one or more refractory metals (e.g., cobalt, iron, nickel, tungsten, and / or molybdenum). In addition, a metal layer can be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The metal layer formed between the layers also covers the surface of the interlayer dielectric layer 102 around the contact hole. Thereafter, a chemical mechanical polishing (CMP) process can be used to chemically mechanically polish the top surface of the deposited metal layer until the top surface of the interlayer dielectric layer 102 is exposed, thereby forming contact plugs 106a, 106c and a combined contact structure 106b located in the interlayer dielectric layer 102.

[0037] Please refer to Figure 2DAnother embodiment of the present invention provides an electrical contact structure for a semiconductor device, comprising a plurality of contact plugs 106, wherein the tops of at least two contact plugs 106 formed at the boundary (or referred to as the boundary region, junction region, or interface region) I-2 of the core component region I of the semiconductor device are connected together via a contact pad 109b having a larger area. The core component region I is a device-intensive region, and the peripheral circuit region II surrounding it is a device-sparse region. The tops of the contact plugs 106 in the region I-1 within the boundary I-2 of the core component region I (referred to as the central region) are provided with independent contact pads 109a, and each contact pad 109a is in one-to-one electrical contact with the top of the corresponding contact plug 106.

[0038] All the contact plugs 106 connected together at the top through the corresponding contact pads 109b at the boundary I-2 of the core component area I form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, all the contact plugs 106 connected together at the top of I-2 at the boundary of the core component area I form a combined contact structure with a larger top cross-sectional area at the boundary I-2.

[0039] Figures 1A to 1D The method shown can reduce the number of deposition processes under the same number of photolithography steps, so that all the contact plugs 106 connected together at the top are formed in one piece.

[0040] Please combine Figure 2D and Figure 11 In another embodiment of the present invention, the semiconductor device is a dynamic random access memory (DRAM), the core component area is a memory array area of ​​the DRAM memory, the core component is a memory transistor, and the electrical contact structure is a storage node contact portion, which is connected to a capacitor structure. That is, each contact plug in the central area I-1 of the core component area I is connected to a capacitor structure (such as Figure 11 705a), a capacitor structure is connected to a combined contact structure in I-2 at the boundary of the core component area I (as shown in FIG. Figure 11As shown in 705b in FIG, the capacitor structure at the boundary has a first width W1, and the capacitor structure within the boundary I-2 of the core component area I has a second width W2. Due to the existence of the combined contact structure with a larger top cross-sectional area formed at the boundary I-2 of the core component area I, sufficient process margin can be provided for the formation process of the capacitor structure at the boundary, so as to facilitate increasing the first width W1 of the capacitor structure at the boundary I-2, so that the first width W1 is greater than the second width W2, and thus, on the one hand, the capacitor structure formed at the boundary is prevented from collapsing; on the other hand, a contact can be provided between the capacitor structure at the boundary and the combined contact structure thereunder. There is a larger contact area, which reduces the contact impedance and is conducive to improving the electrical performance of the device; more importantly, the size of the capacitor structure at the boundary is increased, which can buffer the density difference of the circuit pattern between the core component area I and the peripheral circuit area II, thereby improving the optical proximity effect when performing the photolithography process and / or etching process, reducing the sparse / dense load effect, and ensuring the consistency of the capacitor structure above the contact plug 106a in the area (i.e., the central area) I-1 within I-2 at the boundary of the core component area I, preventing the capacitor structure above some positions in the core component area I from being abnormal or the capacitor structure above the contact plug at the boundary I-2 from collapsing. Optionally, the first width W1 is greater than 1.5 times the second width W2.

[0041] Figures 2A to 2D FIG is a schematic cross-sectional view of a device in a method for manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention. Figures 2A to 2D This embodiment further provides a method for manufacturing an electrical contact structure of a semiconductor device, comprising the following steps:

[0042] First, please refer to Figure 2A A semiconductor substrate 100 is provided, which includes a core component region I and a peripheral circuit region II. A plurality of shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100. The shallow trench isolation structures define the boundary between the core component region I and the peripheral circuit region II in a two-dimensional plane (i.e., define the boundary I-2 of the core component region I). Furthermore, the shallow trench isolation structures define active regions 101 corresponding to the core components in the core component region I and active regions 101 corresponding to the peripheral components in the peripheral circuit region II.

[0043] Next, please continue to refer to Figure 2A, a first interlayer dielectric layer 102 is covered on the semiconductor substrate 100 . In addition, an etching stop layer (not shown) can be formed between the semiconductor substrate 100 and the first interlayer dielectric layer 102; through a first photolithography process, a first mask pattern 103 is formed on the first interlayer dielectric layer 102, and the first mask pattern 103 defines the positions of each contact plug. Then, using the first mask pattern 103 as an etching mask, the first interlayer dielectric layer 102 is anisotropically etched to form contact holes 102a, 102b and 102c that penetrate the first interlayer dielectric layer 102 and expose the corresponding active area 101 below. Each contact hole 102a is located in the central area I-1 of the core component area I and exposes the active area 101 of the corresponding core component in the central area I-1. Each contact hole 102b is located at the boundary I-2 of the core component area I and exposes the active area 101 of the corresponding core component in the boundary I-2. Each contact hole 102c is located in the peripheral circuit area II and exposes the active area 101 of the corresponding peripheral component.

[0044] Then, please refer to Figure 2B After forming the contact holes 102a-102c, an ashing process or a wet cleaning process may be performed to remove the first mask pattern 103. A barrier metal layer (not shown) made of a material such as TiN and a metal layer (not shown) made of a material such as tungsten are then filled into each of the contact holes 102a-102c. Furthermore, a chemical mechanical polishing (CMP) process is used to chemically mechanically polish the top surface of the deposited metal layer until the top surface of the first interlayer dielectric layer 102 is exposed, thereby forming contact plugs 106 in the interlayer dielectric layer 102. The bottom of each of the contact plugs 106 in the core component region I contacts the active area 101 of the corresponding core component. The bottom of each of the contact plugs 106 in the peripheral circuit region II contacts the active area 101 of the corresponding peripheral component.

[0045] Next, please refer to Figure 2CA second interlayer dielectric layer 107 and a second mask pattern 105 can be formed on the first interlayer dielectric layer 102 and the contact plugs 106. The second mask pattern 105 is formed by a second photolithography process and defines trenches for connecting the tops of at least two contact plugs 106 corresponding to the boundary I-2. Using the second mask pattern 105 as a mask, the second interlayer dielectric layer 108 is etched to form trenches that expose the tops of the corresponding contact plugs 106. The trench 108b corresponding to the boundary I-2 exposes the tops of at least two contact plugs 106 and the spaces therebetween. The trench 108a within the boundary I-2 of the core component region I (i.e., the central region I-1) exposes the tops of the corresponding contact plugs 106. The trench 108c in the peripheral circuit region II exposes the tops of the corresponding contact plugs 106. Trench 108b exposes at least the top of the outermost contact plug 106 at the boundary I-2.

[0046] Please refer to Figure 2D The second mask pattern 105 can be removed using an ashing process using oxygen, ozone, or ultraviolet light, or by a wet cleaning process. A barrier metal layer (not shown) and a metal layer (not shown) are then sequentially formed in the trenches 108a-108c. The barrier metal layer can reduce or prevent the metal material disposed in the contact holes and trenches from diffusing into the interlayer dielectric layer 102. A metal layer is then filled into each of the contact hole trenches 108a-108c to form independent contact pads 109a, 109b, and 109c. The contact pad 109a is formed on the top of the contact plug 106 in the central area I-1 of the core component area I, and is electrically contacted with the top of the corresponding contact plug 106 one by one. The contact pad 109b is formed on the top of the contact plug 106 at the boundary I-2 of the core component area I, and is electrically contacted with the top of the corresponding contact plug 106 one by one, so that all the contact plugs 106 connected together at the top in the boundary I-2 form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.

[0047] Figures 2A to 2D The method shown can divide each contact plug (including contact plugs connected together at the top and independent contact plugs) into two height sections for production under the same number of photolithography times, thereby reducing the aspect ratio of the contact hole or trench corresponding to the etching process and filling process corresponding to each height section, thereby ensuring the performance of the formed electrical contact structure.

[0048] Please refer to Figure 1D and Figure 2DAn embodiment of the present invention further provides a semiconductor device, comprising a semiconductor substrate 100, wherein the semiconductor substrate 100 has a core component region I, in which a plurality of core components are formed; an interlayer dielectric layer 102, covering the semiconductor substrate 100; and an electrical contact structure of the semiconductor device as described in each embodiment of the present invention, wherein the electrical contact structure is formed in the interlayer dielectric layer 102, the bottom of each contact plug of the electrical contact structure contacts the active region 101 of the corresponding core component, and the tops of at least two contact plugs I-2 formed at the boundary of the core component region in the electrical contact structure are connected together.

[0049] Please combine Figure 2D and Figure 11 The semiconductor device further includes a capacitor structure formed on the interlayer dielectric layer 107 and having its bottom in contact with the electrical contact structure. The capacitor structure I-2 at the boundary (e.g. Figure 11 705b in FIG) has a first width W1, and the capacitor structure (eg, Figure 11 705a in FIG) has a second width W2, and the first width W1 is greater than the second width W2.

[0050] It should be noted that the technical solution of the present invention is not limited to the above-mentioned method for forming the electrical contact structure. Methods that can be used to form independent contact plugs and contact plugs connected together at the top can also be applied to the technical solution of the present invention. For example, in another example of the present invention, when forming Figure 1A After the structure is formed and the mask pattern 103 is removed, the sacrificial layer is no longer filled, but the material of the contact plug (including the barrier metal layer and the metal layer) is directly filled to form an independent contact plug, and then a dielectric layer is formed on the interlayer dielectric layer 102 and the independent contact plug. Figure 1B The mask pattern 105 in the middle is removed, and the interlayer dielectric layer 102 is further etched to form a trench 102d exposing the top sidewalls of at least two contact plugs 102b at the boundary I-2. A conductive material is then filled in the trench 102d to form a contact pad (not shown) that connects the tops of the contact plugs 102b exposed by the trench 102d.

[0051] In the following, reference will be made to Figures 3A to 11 The semiconductor device and the manufacturing method thereof according to an embodiment of the present invention are described in detail. Figure 3A is a schematic top view of a device structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention; Figures 3B to 11 The present invention is a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3A Schematic diagram of the device structure cross-section along line aa' in FIG.

[0052] First, please refer to Figure 3A and 3B , providing a semiconductor substrate 300 having a plurality of core components (ie, storage transistors), the specific process includes:

[0053] First, please refer to Figure 3A and Figure 3B A semiconductor substrate 300a is provided, which includes a core component region I and a peripheral circuit region II. In this embodiment, the core component region I is a storage region. The core components to be formed in the core component region I include selection elements, and data storage elements are subsequently connected above the core elements. The selection elements are, for example, MOS transistors or diodes, and the data storage elements are, for example, capacitors, variable resistors, etc. A selection element and a corresponding data storage element constitute a storage cell. Peripheral circuits TR (for example, NMOS transistors and PMOS transistors, diodes, or resistors) can be formed in the peripheral circuit region II to control the storage cell. Multiple shallow trench isolation structures 301 are formed in the semiconductor substrate 300a. The shallow trench isolation structures 301 define the boundary between the core component region I and the peripheral circuit region II in a two-dimensional plane (i.e., define the boundary I-2 of the core component region I). They also define the active area AA1 corresponding to each core component in the core component region I and the active area AA2 corresponding to the peripheral components in the peripheral circuit region II. The active areas AA1 are distributed in a strip shape on a two-dimensional plane and extend along the first direction. The active areas AA1 may be arranged in a staggered manner on the surface of the semiconductor substrate 300 a .

[0054] Then, a buried word line WL is formed in the semiconductor substrate 300a. The buried word line WL is typically buried at a predetermined depth within the semiconductor substrate 300a, extending in a second direction (i.e., the row direction) through the shallow trench isolation structure 301 and the active area AA1. The second direction is not perpendicular to the first direction of the active area AA1. The buried word line WL serves as a gate to control the switching of the memory cell. It may be made of, but not limited to, a doped semiconductor material (e.g., doped silicon), a metal material (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal material (e.g., titanium nitride, tantalum nitride, or tungsten nitride), or a metal-semiconductor compound (e.g., silicon nitride). Typically, the sidewalls and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried within the gate cap layer 302. Since the buried word line WL is not the focus of the present invention, its related fabrication process can refer to known technical solutions in the art and will not be described in detail here. In addition, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word line WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials, and the gate cap layer 302 may include silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.

[0055] Furthermore, a second type of dopant, such as P-type or N-type dopant, may be doped into the active area AA1 on either side of the buried word line WL to form source and drain regions (collectively defined as S / D1). One of the AA1 regions on either side of the buried word line WL is located at a predetermined location corresponding to a bitline contact structure at the center of AA1, while the other is located at a predetermined location corresponding to a storage node contact structure at the end of the active area AA1. The word line WL and S / D1 may constitute or define multiple MOS memory transistors formed in the core component region I of the semiconductor device. Furthermore, while S / D1 is being formed, source and drain regions (collectively defined as S / D2) corresponding to peripheral transistors may also be formed in the peripheral circuit region II. After forming S / D1 and S / D2, an etch stop layer 303 may be further formed on the semiconductor substrate 300a. The etch stop layer 303 may be made of, for example, silicon nitride (SiN) and / or silicon oxide (SiO2).

[0056] Then, a plurality of bit line contact plugs (not shown) are formed on the drain region S / D1 of the core device area I, along with bit lines BL located above the bit line contact plugs. The bit line contact plugs can be formed by first etching the S / D1 between two adjacent WLs formed in an active area AA1 to form a groove, and then forming a metal silicide in the groove. The plurality of bit lines BL are parallel to each other and extend along a third direction (i.e., the column direction) perpendicular to the buried word lines WL, and simultaneously cross the active area AA1 and the buried word lines WL. Each bit line BL, for example, includes a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., including Ti or TiN, not shown), a metal layer (e.g., tungsten, aluminum, or copper, not shown), and a mask layer (e.g., including silicon oxide, silicon nitride, or silicon carbonitride, not shown), which are stacked in sequence.

[0057] In addition, at least one gate structure G1 is formed on the peripheral circuit region II of the semiconductor substrate 300a, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence. In one specific example, the gate layer of the gate structure G1 and the semiconductor layer or metal layer of the bit line BL are formed together. Furthermore, different processes or the same process can be used to form the sidewalls 304 surrounding each bit line BL and the gate structure G1. For example, the sidewalls of the gate structure G1 can be first fabricated so that the sidewalls 304 of the gate structure G1 include silicon oxide or silicon oxynitride (SiON), and then the sidewalls of the bit line BL can be fabricated so that the sidewalls of the bit line BL include silicon nitride. In addition, during the fabrication process of the sidewalls of the gate structure G1, an etching back process can be performed to make the overall height of the gate structure G1 lower than that of the bit line BL.

[0058] Then, the present invention can be used Figures 1A to 1D or Figures 2A to 2D The method for manufacturing the electrical contact structure of the semiconductor device shown in FIG. 1 is used to form a storage node contact structure. Figures 1A to 1D The method for manufacturing the electrical contact structure of the semiconductor device shown in the figure takes the formation of a storage node contact structure as an example, and the specific process is as follows:

[0059] First, please refer to Figure 4 After providing a semiconductor substrate 300 having bit lines BL, source regions, and drain regions S / D1 of core components, an interlayer dielectric layer 400 is formed on the semiconductor substrate 300. The interlayer dielectric layer 400 may be made of, for example, silicon oxide, silicon nitride, or a low-K dielectric. Specifically, the interlayer dielectric layer 400 is first deposited over the semiconductor substrate 300 through a deposition process, filling the spaces between the bit lines BL and burying the bit lines BL, the gate structure G1, and its sidewall spacers 304. The interlayer dielectric layer 400 is then planarized through a process such as chemical mechanical polishing (CMP) to form an overall flat top surface. The top surface of the planarized interlayer dielectric layer 400 is at least not lower than the top surface of the bit lines BL.

[0060] Next, please refer to Figure 4 A first mask pattern (not shown) is formed on the interlayer dielectric layer 400 through a photolithography process. The first mask pattern defines the positions of the contact structures of the storage node. Then, the interlayer dielectric layer 400 is anisotropically etched using the first mask pattern as an etching mask to form contact holes 401a, 401b and 401d, 401e that penetrate the interlayer dielectric layer 400 and expose the corresponding source regions S / D1 below. Each contact hole 401a is located in the central area I-1 of the core component area I and exposes the source region S / D1 of the corresponding core component in the central area I-1. Each contact hole 401b is located at the boundary I-2 of the core component area I and exposes the source region S / D1 of the corresponding core component in the boundary I-2. Each contact hole 401d, 401e is located in the peripheral circuit area II and exposes the source / drain region S / D2 or gate structure G1 of the corresponding peripheral component.

[0061] Then, please refer to Figure 5After forming the contact holes 401a, 401b, 401d, and 401e, an ashing process or a wet cleaning process may be performed to remove the first mask pattern and fill the contact holes 401a, 401b, 401d, and 401e with a sacrificial layer 501. The sacrificial layer 501 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL), so that the contact holes 401a, 401b, 401d, and 401e having a high aspect ratio can be filled with the sacrificial layer 501.

[0062] Next, please continue to refer to Figure 4 and 5 A second mask pattern (not shown) can be formed on the interlayer dielectric layer 400 and the sacrificial layer 501. The second mask pattern defines a trench 401c for connecting the tops of at least two contact holes 401b corresponding to the boundary I-2. Using the second mask pattern as a mask, the interlayer dielectric layer 400 at the boundary I-2 is etched to form a trench 401c connecting the tops of at least two contact holes 401b corresponding to the boundary I-2 (including at least one of the contact holes in the row closest to the peripheral circuit region II). The trench 401c at least crosses the outermost word line WL at the boundary I-2.

[0063] Then, please refer to Figure 6 The sacrificial layer 501 and the second mask pattern in the contact holes 401a, 401b, 401d, and 401e can be removed by an ashing process using oxygen, ozone, or ultraviolet light, or by a wet cleaning process, to re-expose the respective contact holes 401a, 401b, 401d, and 401e and the trench 401c.

[0064] Next, please refer to Figure 7A barrier metal layer (not shown) may be formed in the contact holes 401a, 401b, 401d, 401e, and the trench 401c. For example, the barrier metal layer may uniformly cover the inner walls of the contact holes 401a, 401b, 401d, 401e, and the trench 401c, as well as the top surface of the interlayer dielectric layer 400. The barrier metal layer can reduce or prevent the metal material disposed in the contact holes 401a, 401b, 401d, 401e, and the trench 401c from diffusing into the interlayer dielectric layer 400. For example, the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, and may be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). Then, a metal layer is filled in each of the contact holes 401a, 401b, 401d, 401e and the trench 401c to form contact plugs 501a, 501d, 501e and a combined contact structure 501b. The metal layer can be formed of (one or more) refractory metals (e.g., cobalt, iron, nickel, tungsten and / or molybdenum). In addition, the metal layer can be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) (e.g., sputtering). The formed metal layer also covers the surface of the interlayer dielectric layer 400 around the contact holes and trenches. Thereafter, a chemical mechanical polishing (CMP) process can be used to chemically mechanically polish the top surface of the deposited metal layer until the top surface of the interlayer dielectric layer 400 is exposed to form the contact plugs 501a, 501d, 501e and the combined contact structure 501b located in the interlayer dielectric layer 400. Contact plug 501a serves as a storage node contact structure in central region I-1 of core component region I, connecting to a capacitor structure subsequently formed above central region I-1. Combined contact structure 501b is formed by at least two top-connected contact plugs in boundary region I-2 of core component region I (including the outermost contact plug at the boundary region that is electrically contacted with the outermost source region at boundary region I-2). Combined contact structure 501b serves as a storage node contact structure in boundary region I-2 of core component region I, connecting to a capacitor structure subsequently formed above boundary region I-2. The top structure of combined contact structure 501b (i.e., the top connection structure formed by all the top-connected contact plugs) is located above bit line BL and spans at least one word line WL. Combined contact structure 501b is aligned and parallel to bit line BL. Combined contact structure 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, and can span at least one word line WL in the outermost active region AA1 at boundary region I-2.The contact plug 501d serves as a contact structure of the gate structure G1 of the peripheral circuit region II, and is used to lead the gate structure G1 outward. The contact plug 501e serves as a contact structure of the source region or drain region S / D2 of the peripheral circuit region II, and is used to lead the source region or drain region S / D2 of the peripheral circuit region II outward.

[0065] Afterwards, a conventional method for manufacturing a capacitor structure in the art can be used to manufacture a corresponding capacitor structure on the core component area I. Figures 8-11 The specific process is as follows:

[0066] First, please refer to Figure 8 A bottom support layer 600, a first sacrificial layer 611, an intermediate support layer 601, a second sacrificial layer 612, and a top support layer 602 can be sequentially formed on the surfaces of the interlayer dielectric layer 400, the contact plugs 501a, 501d, 501e, and the combined contact structure 501b through processes such as chemical vapor deposition and spin coating. The bottom support layer 600 serves to provide bottom support for the subsequently formed lower electrode layer and to isolate the internal components of the semiconductor substrate 300 from components such as capacitors above. The bottom support layer 600 can also be formed by thermal oxidation. The materials of the bottom support layer 600, the intermediate support layer 601, and the top support layer 602 include, but are not limited to, silicon nitride. The materials of the first sacrificial layer 611 and the second sacrificial layer 612 include, but are not limited to, silicon oxide. The thickness of the first sacrificial layer 611 defines the height of the subsequently formed intermediate support layer 601. Therefore, the thickness of the first sacrificial layer 611 can be adjusted according to the desired height of the intermediate support layer 601. When the thicknesses of the first sacrificial layer 611 and the intermediate support layer 601 are determined, the thickness of the second sacrificial layer 612 defines the height of the subsequently formed top support layer 602. Therefore, the thickness of the second sacrificial layer 612 can be adjusted according to the desired height of the top support layer 602. In other embodiments of the present invention, to better support the lower electrode layer, two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602, with sacrificial layers separating adjacent intermediate support layers.

[0067] Next, please refer to Figure 9As shown, a plurality of capacitor holes 700a and 700b are formed in the sacrificial layer and the support layer on the core component area I. The capacitor hole 700a is formed in the central area I-1 of the core component area I and exposes the surface of the contact plug 501a in the central area I-1, which is used to form a capacitor structure in the central area I-1. The capacitor hole 700b is formed at the boundary I-2 of the core component area I and exposes the surface of the combined contact structure 501b at the boundary I-2, which is used to form a capacitor structure in the boundary I-2. The capacitor holes 700a and 700b are arranged in an array, and the capacitor hole 700b has a first width W1, and the capacitor hole 700a has a second width W2. Optionally, W1 is not less than 1.5*W2. Specifically, a mask layer (not shown) is formed on the top supporting layer 602, and the mask layer is patterned to expose the area where the capacitor holes 700a and 700b are to be formed. Then, using the patterned mask layer as a mask, the top supporting layer 602, the second sacrificial layer 612, the intermediate supporting layer 601, the first sacrificial layer 611, and the bottom supporting layer 600 are sequentially etched to remove the supporting layer and the sacrificial layer on the edge area of ​​the peripheral circuit area II and the core component area I, and to form a plurality of capacitor holes 700a and 700b in the core component area I. Then, the patterned mask layer is removed. The capacitor holes 700a and 700b sequentially penetrate the top supporting layer 602, the second sacrificial layer 612, the intermediate supporting layer 601, the first sacrificial layer 611, and the bottom supporting layer 600 to expose the surfaces of the corresponding contact plugs 501a and the combined contact structure 501b of the core component area I. Optionally, all the capacitor holes are arranged in a hexagonal close-packed manner. Furthermore, the capacitor hole may be an inverted trapezoidal hole, a rectangular hole, or the like, and its sidewalls may have irregular morphologies, such as curved sidewalls, without specific limitation herein. Furthermore, in this embodiment, the bottom support layer 600 is retained on the peripheral circuit region II to protect the device surface of the peripheral circuit region II during the subsequent capacitor formation process.

[0068] It is understandable that, because the area of ​​the combined contact structure 501b is large, sufficient process margin can be provided for the production of the capacitor hole 700b at the boundary I-2, and the width of the capacitor hole 700b at the boundary I-2 is large, thereby avoiding abnormal deformation or collapse of the capacitor hole 700b at the boundary, and at the same time, the capacitor structure formed subsequently at the boundary and the combined contact structure have a larger contact area, thereby reducing the contact impedance, which is conducive to improving the electrical performance of the device. In addition, because the width of the capacitor hole 700b at the boundary I-2 is large, it can buffer the density difference of the circuit pattern in the peripheral circuit area II and the core component area I, thereby improving the optical proximity effect when performing the photolithography process and / or etching process of the capacitor hole, reducing the sparse / dense load effect, ensuring the consistency of the capacitor hole within the boundary of the core component area, and preventing the capacitor hole above the contact plug at some positions in the core component area from being abnormal and causing the failure of the subsequently formed capacitor structure.

[0069] Please refer to Figure 10As shown, a lower electrode layer 701 is formed to cover the sidewalls and bottom walls of the capacitor holes 700a and 700b. The portion of the lower electrode layer 701 located within the capacitor holes 700a and 700b has a shape consistent with that of the capacitor holes 700a and 700b, thereby forming a cylindrical structure within the capacitor holes 700a and 700b. Specifically, the lower electrode layer 701 can be formed on the basis of a deposition process combined with a planarization process. For example, first, a graphic protective layer such as photoresist (not shown) can be used to protect the peripheral circuit area II, and expose the top surface of the top support layer 602 in the core component area I and the surface of the capacitor holes 700a and 700b; then, a physical vapor deposition or chemical vapor deposition process is used to form an electrode material layer on the graphic protective layer and the exposed surface of the core component area I, and the electrode material layer covers the bottom and side walls of the capacitor holes 700a and 700b, and covers the top support layer 602 of the core component area I and the top surface of the graphic protective layer of the peripheral circuit area II; then, a planarization process (for example, a chemical mechanical polishing process CMP) is performed to remove the portion of the electrode material layer located above the top support layer 602, so that the remaining electrode material layer is only formed in the capacitor holes 700a and 700b to form a lower electrode layer 701 having multiple tubular structures, and then the graphic protective layer is removed. In addition, in this embodiment, the contact plugs 501a and 501b are exposed through the capacitor holes 700a and 700b, respectively, so that the bottom of the tubular structure of the formed lower electrode layer 701 can be in electrical contact with the contact plugs 501a and 501b. Furthermore, the lower electrode layer 701 can be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti can also be used. When the lower electrode layer 701 is a polysilicon electrode, it can be formed using zero-doped and / or doped polysilicon material.

[0070] Please continue to refer to Figure 10As shown, each of the sacrificial layers is removed and each of the supporting layers is retained. All of the supporting layers form a lateral supporting layer to laterally connect the outer walls of the multiple cylindrical structures of the lower electrode layer 701, thereby supporting the lower electrode layer 701 on the side walls of each of the cylindrical structures. Specifically, the top supporting layer 602 is located at the top periphery of the multiple cylindrical structures of the lower electrode layer 701, the middle supporting layer 601 is located in the middle of the multiple cylindrical structures of the lower electrode layer 701, and the bottom supporting layer 600 is located at the bottom periphery of the multiple cylindrical structures of the lower electrode layer 701. The specific process includes: forming a first opening (not shown) in the top support layer 602 and exposing the second sacrificial layer 612; etching and removing the second sacrificial layer 612 by a wet etching process; forming a second opening in the middle support layer 601 to expose the first sacrificial layer 611; etching and removing the first sacrificial layer 611 by a wet etching process; wherein, one first opening overlaps with only one capacitor hole 700a or 700b, or one first opening overlaps with multiple capacitor holes 700a and / or 700b at the same time; one second opening overlaps with only one capacitor hole 700a or 700b, or one second opening overlaps with multiple capacitor holes 700a and / or 700b at the same time. In addition, the second opening can be completely aligned with the first opening.

[0071] Please refer to Figure 11As shown, a capacitor dielectric layer 702 is formed on the inner and outer surfaces of the lower electrode layer 701 and the exposed surfaces of each support layer using a chemical vapor deposition process or an atomic layer deposition process; then, an upper electrode layer 703 is formed on the inner and outer surfaces of the capacitor dielectric layer 702. The capacitor dielectric layer 702 covers the inner and outer surfaces of the tubular structure of the lower electrode layer 701 to fully utilize the two opposing surfaces of the lower electrode layer 701 to form a capacitor with a large electrode surface area. Preferably, the capacitor dielectric layer 702 can be a high-K dielectric layer such as a metal oxide. Furthermore, the capacitor dielectric layer 702 has a multi-layer structure, such as a two-layer structure of halogen oxide and zirconium oxide. The upper electrode layer 703 can have a single-layer structure or a multi-layer structure. When the upper electrode layer 703 has a single-layer structure, it can be, for example, a polysilicon electrode or a metal electrode. When the upper electrode layer 703 has a metal electrode, it can be formed of, for example, titanium nitride (TiN). The upper electrode layer 703 can form a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside and outside the corresponding cylindrical structure. In addition, on the edge area of ​​the core component area I (i.e., the boundary area of ​​the capacitor hole array), due to the presence of the lateral support layer (i.e., the middle support layer 601 and the top support layer 602), the capacitor dielectric layer 702 and the upper electrode layer 703 both have a sidewall structure with an uneven morphology, and the sidewall structure with an uneven morphology corresponds to the middle support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701, thereby causing the portion of the upper electrode layer 703 on the edge area of ​​the core component area I (i.e., the boundary area of ​​the capacitor hole array) to protrude in a direction away from the lower electrode layer 701 corresponding to the middle support layer 601 and the top support layer 602, making the boundary of the capacitor array in the core component area I uneven. In addition, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 also sequentially extend to cover the surface of the bottom support layer 600 retained on the peripheral circuit region II.

[0072] Please refer to Figure 11 As shown, a chemical vapor deposition process can be used to form an upper electrode filling layer 704 on the surface of the upper electrode layer 703. The upper electrode filling layer 704 fills the gaps between the upper electrode layers 703. In other words, the upper electrode filling layer 704 fills the gaps between adjacent cylindrical structures and covers the structure formed above. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon. This completes the production of the capacitor array, that is, a capacitor structure 705a is formed in the central area I-1, and a capacitor structure 705b is formed at the boundary I-2.

[0073] Because the width of capacitor hole 700b is greater than that of capacitor hole 700a, the width of capacitor structure 705b at boundary I-2 (i.e., W1) is greater than the width of capacitor structure 705a at central region I-1 (i.e., W2), for example, W1 = W2 * 1.5. Furthermore, the larger size of capacitor hole 700b facilitates material filling, thereby improving the performance of the capacitor structure formed at boundary I-2.

[0074] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the various embodiments can be referred to in detail. Furthermore, the above description is merely a description of preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes or modifications made by a person skilled in the art based on the above disclosure are within the scope of protection of the technical solution of the present invention.

[0075] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first," "second," and "third" in this specification are used solely to distinguish between components, elements, steps, and the like, and are not used to indicate a logical or sequential relationship between the components, elements, and steps. The term "and / or" herein means both or either of the two.

Claims

1. An electrical contact structure for a semiconductor device, characterized in that: The electrical contact structure comprises: A plurality of contact plugs are formed above the core element of the core element region of the semiconductor device, and the bottom of each contact plug contacts the active area of ​​the corresponding core element. wherein the tops of at least two contact plugs formed at the boundary of the core device region are connected together, and the contact plugs with the connected tops include the outermost contact plug at the boundary; The semiconductor device further includes a plurality of capacitor structures formed above the plurality of contact plugs, and the contact plugs connected together at the top are in electrical contact with a corresponding one of the capacitor structures; The capacitor structure at the boundary has a first width, and the capacitor structure within the boundary of the core component area has a second width, and the first width is greater than the second width.

2. The electrical contact structure of a semiconductor device according to claim 1, wherein: All the contact plugs connected together at the top portion form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.

3. The electrical contact structure of a semiconductor device according to claim 2, wherein: A plurality of word lines intersecting the plurality of active areas and bit lines perpendicular to the word lines are formed in the core element region of the semiconductor device. The structure formed by all the contact plugs connected together at the top crosses at least one of the word lines and is aligned with the bit lines.

4. The electrical contact structure of a semiconductor device according to claim 1, wherein: It also includes independent contact pads formed on top of other contact plugs in the core component area and electrically contacting the tops of the corresponding contact plugs in a one-to-one correspondence.

5. The electrical contact structure of a semiconductor device according to claim 1, wherein: All the contact plugs connected together at the top are an integrally formed structure, or at least two contact plugs at the boundary are connected together at the top by being connected to the same contact pad.

6. The electrical contact structure of a semiconductor device according to claim 1, wherein: The first width is greater than 1.5 times the second width.

7. A semiconductor device, characterized in that: include: A semiconductor substrate having a core component region in which a plurality of core components are formed; an interlayer dielectric layer covering the semiconductor substrate; as well as, The electrical contact structure of a semiconductor device according to any one of claims 1 to 6, wherein the electrical contact structure is formed in the interlayer dielectric layer, the bottom of each contact plug of the electrical contact structure contacts the active area of ​​the corresponding core component, and the tops of at least two contact plugs formed at the boundary of the core component area in the electrical contact structure are connected together, and the contact plugs with the tops connected together include the outermost contact plug at the boundary.

8. The semiconductor device according to claim 7, wherein The semiconductor device is a DRAM, the core component area is a storage area, the core component is a storage transistor, and the electrical contact structure is a storage node contact structure.

9. The semiconductor device according to claim 7, wherein The semiconductor device includes multiple word lines and multiple bit lines, each word line intersects with multiple active areas in the core component area, the bit lines are perpendicular to the word lines, and the structure composed of all contact plugs connected together at the top spans at least one word line and is aligned with the bit line.

10. A method for manufacturing an electrical contact structure of a semiconductor device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a core component region, and a plurality of core components are formed in the core component region; forming an interlayer dielectric layer on the semiconductor substrate, and forming a plurality of contact holes in the interlayer dielectric layer, wherein each of the contact holes penetrates the interlayer dielectric layer and exposes an active area of ​​a corresponding core component; forming contact plugs in the contact holes, with the bottom of each contact plug contacting the active area of ​​the corresponding core component, and the tops of at least two contact plugs formed at the boundary of the core component area being connected together, and all the contact plugs with the connected tops including the outermost contact plug at the boundary; In which, the semiconductor device also includes multiple capacitor structures formed above the multiple contact plugs, and the contact plugs connected together at the top are electrically contacted with a corresponding one of the capacitor structures, and the capacitor structure at the boundary has a first width, and the capacitor structure within the boundary of the core component area has a second width, and the first width is greater than the second width.

11. The method for manufacturing an electrical contact structure of a semiconductor device according to claim 10, wherein: When forming a plurality of contact holes in the interlayer dielectric layer, firstly, mutually independent contact holes are formed in the interlayer dielectric layer by a single photolithography process, and then the interlayer dielectric layer is etched by another photolithography process so that the tops of at least two contact holes at the boundary are connected to form contact plugs with connected tops; or, When forming a plurality of contact holes in the interlayer dielectric layer, mutually independent contact holes are formed in the interlayer dielectric layer by a single photolithography process; then, mutually independent contact plugs are formed in the contact holes, and then, the interlayer dielectric layer is etched by another photolithography process to form trenches exposing the top sidewalls of at least two contact plugs at the boundary, and contact pads are formed in the trenches so that the tops of the corresponding contact plugs are connected together; or, When forming multiple contact holes in the interlayer dielectric layer, independent contact holes are formed in the interlayer dielectric layer through a single photolithography process; then, independent contact plugs are formed in the contact holes, and then another interlayer dielectric layer is formed to cover the interlayer dielectric layer with the contact plugs; then, the other interlayer dielectric layer is etched through another photolithography process to form a trench exposing the tops of at least two contact plugs at the boundary, and a contact pad is formed in the trench to connect the tops of the corresponding contact plugs together.

12. A method for manufacturing a semiconductor device, characterized in that: include: By adopting the method for manufacturing the electrical contact structure of a semiconductor device according to claim 10 or 11, an electrical contact structure electrically contacting the corresponding core component is formed on a semiconductor substrate having a core component area.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The core component area is a storage area, the core component is a storage transistor, the electrical contact structure is a storage node contact structure, and the manufacturing method of the semiconductor device further includes: forming a lower electrode of a capacitor structure on the electrical contact structure; forming a capacitor dielectric covering the lower electrode; and An upper electrode of a capacitor structure is formed on the capacitor dielectric.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of providing a semiconductor substrate having a core device region includes: Providing a semiconductor substrate, wherein a plurality of active regions are defined in the semiconductor substrate; forming a word line in the semiconductor substrate, wherein the word line intersects the active area; forming a source region and a drain region in the active regions on both sides of the word line respectively; forming a bit line contact structure on the drain region; and A bit line is formed on the bit line contact structure, the bit line intersecting the word line, wherein a bottom of a contact plug in the electrical contact structure contacts the source region.

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