Semiconductor device and method of manufacturing the same

Abstract

An embodiment provides a semiconductor device capable of effectively laying out wirings and a manufacturing method thereof. According to one embodiment, the semiconductor device includes: a first substrate; and a logic circuit provided on the first substrate. The device further includes: a storage unit provided above the logic circuit; and a second substrate provided above the storage unit. The device further includes bonding pads provided above the second substrate and electrically connected to the logic circuit. The device further includes wirings provided above the second substrate, electrically connected to the storage unit, and including at least one of a data signal line, a control voltage line, and a power supply line.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2019-37626 (filing date: March 1, 2019). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. Background Art

[0004] Since semiconductor devices, such as three-dimensional memories, generally have a large number of wirings, it is important in design to effectively layout these wirings. For example, it is required that the layout can achieve noise reduction, low resistance, high speed, etc. Summary of the Invention

[0005] Embodiments provide a semiconductor device and a method of manufacturing the same that can effectively layout wirings.

[0006] According to one embodiment, a semiconductor device includes: a first substrate; and a logic circuit disposed on the first substrate. The device further includes: a storage unit disposed above the logic circuit; and a second substrate disposed above the storage unit. The device further includes bonding pads disposed above the second substrate and electrically connected to the logic circuit. The device further includes wirings disposed above the second substrate and electrically connected to the storage unit, including at least one of a data signal line, a control voltage line, and a power supply line.

[0007] The bonding pads and the wirings are preferably included in the same wiring layer disposed above the second substrate.

[0008] The semiconductor device preferably further includes an insulating film disposed on an upper surface of the wiring and having an opening exposing an upper surface of the bonding pad.

[0009] The storage unit is preferably disposed above the logic circuit.

[0010] The wirings are preferably for transmitting an input signal to the semiconductor device or transmitting an output signal from the semiconductor device, for supplying a control voltage to the storage unit, or for supplying power to the semiconductor device.

[0011] The wirings are preferably disposed at a position non-contact with the bonding pads or at a position in contact with the bonding pads.

[0012] According to an embodiment, a semiconductor device capable of effectively laying out wiring and a manufacturing method thereof are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0014] Figure 2 is a cross-sectional view showing the structure of the columnar portion according to the first embodiment.

[0015] Figure 3 is a cross-sectional view for explaining a step of the manufacturing method of the semiconductor device according to the first embodiment.

[0016] Figure 4 is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0017] Figure 5 is a top view showing the structure of the semiconductor device according to the first embodiment.

[0018] Figure 6 and Figure 7 is a cross-sectional view showing the structure of the second plug according to the first embodiment.

[0019] Figure 8 is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment.

[0020] Figure 9 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0021] Figure 10 is a top view showing the structure of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 10 the same or similar components are denoted by the same reference numerals, and repeated description is omitted.

[0023] (First Embodiment)

[0024] Figure 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding a memory array chip 1 (hereinafter, simply referred to as array chip 1) and a circuit chip 2.

[0025] The array chip 1 includes: a memory cell array 11 containing a plurality of memory cells, an insulating layer 12 on the memory cell array 11, a substrate 13 on the insulating layer 12, an insulating layer 14 on the substrate 13, an interlayer insulating film 15 under the memory cell array 11, and a first insulating layer 16 under the interlayer insulating film 15. The insulating layers 12 and 14 are, for example, a silicon oxide film or a silicon nitride film. The substrate 13 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 13 is an example of a second substrate.

[0026] The circuit chip 2 is disposed under the array chip 1. The symbol S represents the bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 includes: a second insulating layer 17, an interlayer insulating film 18 under the second insulating layer 17, and a substrate 19 under the interlayer insulating film 18. The substrate 19 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 19 is an example of a first substrate.

[0027] Figure 1 In this case, two directions parallel to the surfaces S1, S2 of the substrate 13 or the surfaces S3, S4 of the substrate 19 and perpendicular to each other are defined as the X direction and the Y direction, respectively. Here, the direction perpendicular to the paper surface is set as the Y direction. In addition, a Z direction perpendicular to the surfaces S1, S2 of the substrate 13 or the surfaces S3, S4 of the substrate 19 is defined. In this specification, the upward direction of the paper surface is the +Z direction, and the downward direction of the paper surface is the -Z direction. The -Z direction may or may not coincide with the direction of gravity.

[0028] The array chip 1 includes a plurality of word lines WL, a source side select gate SGS, a drain side select gate SGD, and a source line SL as electrode layers in the memory cell array 11. The memory cell array 11 includes a stepped structure portion 21. As Figure 1 shown, the end of each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22, and the source side select gate SGS is electrically connected to the source side select gate wiring layer 25 via a contact plug 24. Further, the drain side select gate SGD is electrically connected to the drain side select gate wiring layer 27 via a contact plug 26, and the source line SL is electrically connected to the source wiring layer 30 via a contact plug 29. A columnar portion CL penetrating the word line WL, the source side select gate SGS, the drain side select gate SGD, and the source line SL is electrically connected to the bit line BL via a plug 28 and is also electrically connected to the substrate 13.

[0029] The circuit chip 2 has a plurality of transistors 31 on the substrate 19. Each transistor 31 includes: a gate electrode 32 provided on the substrate 19 via a gate insulating film; and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 19. The circuit chip 2 further includes: a plurality of plugs 33 provided on the source diffusion layer or the drain diffusion layer of these transistors 31; a wiring layer 34 provided on these plugs 33 and including a plurality of wirings; and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings. The circuit chip 2 further includes: a plurality of via plugs 36 provided on the wiring layer 35; and a plurality of second metal pads 37 provided on these via plugs 36 in the second insulating layer 17. The circuit chip 2 functions as a control circuit (logic circuit) for controlling the array chip 1.

[0030] The array chip 1 includes: a plurality of first metal pads 41 respectively provided in the first insulating layer 16 corresponding to the plurality of second metal pads 37; a plurality of via plugs 42 respectively provided on these plurality of first metal pads 41; and a wiring layer 43 including a plurality of wirings respectively provided on these via plugs 42. Each word line WL or each bit line BL in the present embodiment is electrically connected to a corresponding wiring in the wiring layer 43. The array chip 1 further includes: a first plug 44 provided in the interlayer insulating film 15 and the insulating layer 12 and provided on the wiring layer 43; a second plug 46 provided in the substrate 13 and the insulating layer 14 via the insulating film 45 and provided on the first plug 44; and a pad 47 provided on the insulating layer 14 and provided on the second plug 46. The pad 47 is an external connection pad (bonding pad) of the semiconductor device in the present embodiment and can be connected to a mounting substrate or other device via a solder ball, a metal bump, a bonding wire, etc.

[0031] In addition, in the present embodiment, the first insulating layer 16 is formed on the lower surface of the interlayer insulating film 15, but the first insulating layer 16 may also be integrated by being included in the interlayer insulating film 15. Similarly, in the present embodiment, the second insulating layer 17 is formed on the upper surface of the interlayer insulating film 18, but the second insulating layer 17 may also be integrated by being included in the interlayer insulating film 18.

[0032] Figure 2 It is a cross-sectional view showing the structure of the columnar portion of the first embodiment.

[0033] As Figure 2 shown, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on the interlayer insulating film 15. Each word line WL is, for example, a W (tungsten) layer. Each insulating layer 51 is, for example, a silicon oxide film.

[0034] The columnar portion CL successively includes a blocking insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, a silicon nitride film, and the blocking insulating film 52 is formed on the sides of the word line WL and the insulating layer 51. The channel semiconductor layer 55 is, for example, a silicon layer, and the tunnel insulating film 54 is formed on the side of the charge storage layer 53. Examples of the blocking insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are a silicon oxide film or a metal insulating film.

[0035] Figure 3 It is a cross-sectional view for explaining one step of the manufacturing method of the semiconductor device of the first embodiment.

[0036] Figure 3 It shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The array wafer W1 is also called a memory wafer, and the circuit wafer W2 is also called a CMOS (complementary metal oxide semiconductor) wafer. The array wafer W1 includes a memory cell array 11 formed on a substrate 13 and the like, and the circuit wafer W2 includes transistors 31 formed on a substrate 19 and the like.

[0037] First, the array wafer W1 and the circuit wafer W2 are bonded by mechanical pressure. Thereby, the first insulating layer 16 and the second insulating layer 17 are joined. Next, the array wafer W1 and the circuit wafer W2 are annealed at 400 °C. Thereby, the first metal pad 41 and the second metal pad 37 are joined.

[0038] After that, after thinning the substrates 13 and 19 by CMP (Chemical Mechanical Polishing), the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this way, the Figure 1 semiconductor device is manufactured. In addition, the insulating layer 14, the insulating film 45, the second plug 46, and the pad 47 are formed, for example, on or in the substrate 13 after the substrate 13 is thinned.

[0039] In addition, in the present embodiment, the array wafer W1 and the circuit wafer W2 are bonded, but the array wafers W1 may be bonded to each other and the circuit chips 2 may be separately provided. Refer to Figures 1 to 3 to the above-described content, or refer to Figures 4 to 10 to the following-described content, which can also be applied to the bonding of the array wafers W1 to each other.

[0040] In addition, the array wafer W1 includes the memory cell array 11 of the three-dimensional memory in the present embodiment, but may include the memory cell array of the two-dimensional memory instead.

[0041] In addition, Figure 1 The interface between the first insulating layer 16 and the second insulating layer 17, or the interface between the first metal pad 41 and the second metal pad 37 is shown, but generally these interfaces cannot be observed after the annealing. However, the positions where these interfaces are located can be estimated by detecting, for example, the inclination of the side surface of the first metal pad 41 or the side surface of the second metal pad 37, or the positional deviation between the side surface of the first metal pad 41 and the second metal pad 37.

[0042] Figure 4 is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment, showing the semiconductor device according to the first embodiment from a Figure 1 different perspective. Figure 1 A set of first plugs 44, insulating film 45, and second plugs 46 provided on the wiring layer 43 is shown. In contrast, Figure 4 Four sets of first plugs 44, insulating film 45, and second plugs 46 provided on the wiring layer 43 are shown.

[0043] Figure 4 Furthermore, the wiring layer 20 formed on the insulating layer 14 is shown. The wiring layer 20 is a metal conductive layer such as an Al (aluminum) layer, for example. The wiring layer 20 includes a wiring (routing wiring) 48 that electrically connects a certain part between the substrate 13 and the substrate 19 to other parts. Figure 4 In, one set of the first and second plugs 44, 46 is electrically connected to one end of the wiring 48, and the other set of the first and second plugs 44, 46 is electrically connected to the other end of the wiring 48. Figure 4 The wiring 48 of is electrically connected to the logic circuit in the circuit chip 2 via these ends.

[0044] The wiring layer 20 of the present embodiment includes not only the wiring 48 but also the pad 47. That is, the pad 47 and the wiring 48 of the present embodiment are formed by the same wiring layer 20. Thus, the pad 47 and the wiring 48 can be formed simply. In the present embodiment, after the array wafer W1 and the circuit wafer W2 are bonded (refer to Figure 3 ), the insulating layer 14 and the wiring layer 20 are sequentially formed on the substrate 13, and the wiring layer 20 is processed by etching to form the pad 47 and the wiring 48 from the wiring layer 20.

[0045] In addition, for ease of understanding the description, Figure 4The step difference between the upper surface of the pad 47 and the upper surface of the wiring 48 is shown, but such a step difference may not be provided. Further, in the present embodiment, the wiring 48 is provided at a position non-contact with the pad 47, but may be provided at a position in contact with the pad 47 as in the embodiments described below. Whether to provide the wiring 48 at a position in contact with the pad 47 is determined according to the use of the wiring 48 such as a signal line (data signal line), a control voltage line, a power supply line, etc.

[0046] Figure 4 Furthermore, a passivation film 49 formed on the wiring layer 20 is shown. The passivation film 49 is an insulating film such as a silicon oxide film, for example. The passivation film 49 covers the upper surface of the wiring 48 and has an opening P that exposes the upper surface of the pad 47. Thereby, the wiring 48 can be protected by the passivation film 49, or a solder ball, a metal bump, a bonding wire, etc. can be connected to the pad 47 within the opening P.

[0047] Figure 4 The pads 47 are arranged on two sets of first and second plugs 44 and 46 and are electrically connected to the logic circuit within the chip 2 via these plug circuits. In addition, details of the shapes of these plugs will be described below.

[0048] Figure 5 It is a top view showing the structure of the semiconductor device of the first embodiment. Figure 4 Indicates along Figure 5 The cross-section of the I-I' line in. For ease of explanation, each component in different XY cross-sections is collectively shown in the Figure 5 Top view. For the detailed positional relationship between the components, please refer to the Figure 4 Cross-sectional view, etc.

[0049] Figure 5 Four planes 61 constituting the memory cell array 11 are shown. The memory cell array 11 includes a plurality of memory cells, and these memory cells operate in each unit called a plane 61. Specifically, the write operation, read operation, and delete operation of the memory cells are performed in each plane 61. Figure 5 Furthermore, eight row decoders 62, four data processing circuits 63, and two control voltage generation circuits 64 provided for these planes 61 are shown. The row decoders 62, data processing circuits 63, and control voltage generation circuits 64 are located near the memory cell array 11 within the array chip 1 or within the logic circuit of the circuit chip 2.

[0050] The row decoder 62 applies a control voltage to control wirings such as the word line WL of the memory cell array 11. Examples of such a control voltage include a write voltage (VPRG), an erase voltage (VERASE), an intermediate voltage (VPASS), a source voltage (VSL), and the like. The control voltage is generated by a control voltage generation circuit 64 and supplied to the row decoder 62.

[0051] The data processing circuit 63 processes an input signal to the semiconductor device or an output signal from the semiconductor device. Examples of such a signal include a data signal (DQ), a chip enable signal (CEn), a read enable signal (REn), a write enable signal (WEn), an address latch enable signal (ALE), an instruction latch enable signal (CLE), and the like.

[0052] And Figure 4 Similarly, Figure 5 FIG. further shows the pads 47 and wirings 48 included in the wiring layer 20. As an example, Figure 5 FIG. shows ten pads 47 and ten wirings 48 denoted by symbols A1 to A8, B1, and B2. The wirings 48 are also appropriately denoted as "wirings A1 to A8, B1, B2". Figure 5 Furthermore, the positions of the second plugs 46 electrically connected to these wirings 48 are schematically shown.

[0053] Symbol Wx represents the width of each pad 47 in the X direction, symbol Wy represents the width of each pad 47 in the Y direction, and symbol W represents the width of each wiring 48. The width W of the wiring 48 in the present embodiment is set to be thinner than the widths Wx and Wy of the pad 47 (W < Wx, W < Wy). In addition, the values of the widths Wx and Wy of each pad 47 may also be different from each other. Similarly, the values of the widths W of each wiring 48 may also be different from each other.

[0054] The wirings A1 to A8 electrically connect one data processing circuit 63 to another data processing circuit 63 for transmitting the input signal or the output signal. These wirings A1 to A8 extend in the Y direction, and the width W of the wirings A1 to A8 corresponds to the length of the wirings A1 to A8 in the X direction.

[0055] The wirings B1 and B2 electrically connect one control voltage generation circuit 64 to two row decoders 62 for supplying the control voltage generated by the control voltage generation circuit 64 to the row decoders 62. These wirings B1 and B2 include a first portion extending in the X direction and a second portion extending in the Y direction. The width W of the wirings B1 and B2 corresponds to the length of the wirings B1 and B2 in the Y direction in the first portion and corresponds to the length of the wirings B1 and B2 in the X direction in the second portion.

[0056] Figure 5These portions of the wirings 48 that are connected to the second plug 46 (the ends of the wirings 48 in the example of the figure) are schematically represented by circles. However, note that these circles are shown for the purpose of facilitating understanding of the position of the second plug 46 and do not represent the shape of the wirings 48. Each wiring 48 is electrically connected via the second plug 46 to a row decoder 62, a data processing circuit 63, a control voltage generation circuit 64, etc. The width W of each wiring 48 in the present embodiment is fixed and unchanged in the portion connected to the second plug 46 and other portions.

[0057] Figure 6 and Figure 7 is a cross-sectional view showing the structure of the second plug 46 of the first embodiment.

[0058] Figure 4 Four first plugs 44 are shown, and each of these first plugs 44, as Figure 6 or Figure 7 shown, may also be composed of multiple fine plugs. Figure 6 The first plug 44 provided under the pad 47 and composed of multiple fine plugs V1 is shown. Figure 7 The first plug 44 provided under the wiring 48 and composed of multiple fine plugs V2 is shown.

[0059] According to the present embodiment, by forming each first plug 44 of multiple fine plugs, the resistance can be reduced compared to the case of forming it with one fine plug.

[0060] As Figure 6 shown, the two first plugs 44 under the pad 47 are composed of multiple plugs V1. The two first plugs 44 under the pad 47 are composed of, for example, 100 plugs V1. Additionally, as Figure 7 shown, the two first plugs 44 under the wiring 48 are each composed of multiple plugs V2. The two first plugs 44 under the wiring 48 are each composed of, for example, 50 plugs V2. In this case, in the semiconductor device of the present embodiment, one set of plugs V1 is provided under the pad 47, and two sets of plugs V2 are provided under the wiring 48. One set of plugs V1 includes 100 plugs V1, and one set of plugs V2 includes 50 plugs V2. The reason for the latter number being less than the former number is that the width W of the wiring 48 is thinner than the widths Wx, Wy of the pad 47.

[0061] Furthermore, each second plug 46, similarly to the first plug 44, may also be composed of multiple fine plugs.

[0062] Figure 8 is a circuit diagram showing the configuration of the semiconductor device of the first embodiment.

[0063] Figure 8Shows a plurality of planes 61 constituting the memory cell array 11, and a plurality of row decoders 62, a plurality of SA / DL units 71, a plurality of XDL units 72, and a plurality of YLOG units 73 provided for these planes 61. Figure 8 Furthermore, a series circuit 74, an I / O (Input / Output) circuit 75, a low voltage generation circuit 81, a high voltage generation circuit 82, a row control circuit 83, and a column control circuit 84 are shown. These are located near the memory cell array 11 in the array chip 1 or in the logic circuit in the circuit chip 2. Figure 8 Furthermore, a controller 3 included in the semiconductor device of the present embodiment is shown.

[0064] Each SA / DL unit 71 is a sense amplifier circuit and a data latch circuit that senses data read from the bit line BL of the plane 61. Each XDL unit 72 is a data latch circuit that stores data sent from the SA / DL unit 71 or the I / O circuit 75. Each YLOG unit 73 decodes the column address and selects the latch circuit in the XDL unit 72 based on the decoding result. The series circuit 74 provides a series bus or the like shared by the plurality of planes 61, and the I / O circuit 75 exchanges the input signal or the output signal with the controller 3.

[0065] The low voltage generation circuit 81 and the high voltage generation circuit 82 constitute the control voltage generation circuit 64, and generate a low voltage and a high voltage used as control voltages, respectively. The row control circuit 83 and the column control circuit 84 respectively perform control related to the rows or columns of each plane 61.

[0066] The wirings A1 to A8 (refer to Figure 5 ) of the present embodiment are used, for example, to exchange the input signal or the output signal between the I / O circuit 75 and the XDL unit 72. In addition, the wirings B1, B2 (refer to Figure 5 ) of the present embodiment are used, for example, to supply the control voltage from the low voltage generation circuit 81 or the high voltage generation circuit 82 to the row decoder 62.

[0067] Hereinafter, with reference to Figure 4 and Figure 5 , the semiconductor device of the present embodiment will be described in detail.

[0068] As Figure 4 shown, in the semiconductor device of the present embodiment, a pad 47 is provided at a position higher than the memory cell array 11 or the logic circuit, and a space for arranging structures is reserved near the pad 47. Here, in the present embodiment, a wiring 48 is arranged near the pad 47, and this wiring 48 is used as a signal line or a control voltage line.

[0069] Thus, according to this embodiment, wirings can be efficiently arranged in a semiconductor device as in the following example. For example, by arranging a certain wiring as wiring 48 above the substrate 13 instead of between the substrate 13 and the substrate 19, the congestion of the wirings between the substrate 13 and the substrate 19 can be alleviated. In addition, when the wiring 48 is used as a signal line, since the wiring 48 is located above the substrate 13 where it is not easily affected by noise, the noise of the signal in the signal line can be reduced. In addition, by reducing the number of wirings between the substrate 13 and the substrate 19, the number of wiring layers between the substrate 13 and the substrate 19 can be reduced. As a result, the thickness of the semiconductor device can be thinned, or the operation of the semiconductor device can be speeded up by shortening the length of the wirings. In addition, when the wiring 48 is used as a control voltage line, by making use of the extra space to thicken the wiring 48, the influence of the wiring resistance on the control voltage can be reduced.

[0070] In addition, the wiring 48 of this embodiment is formed by the same wiring layer 20 as the pad 47, but as long as the wiring 48 and the pad 47 are on the same surface (here, on the insulating layer 14), they may also be other wiring layers 20 formed by different processes. However, as described above, if the wiring 48 is also formed as the same wiring layer 20 at the same time during the formation step of the pad 47, for example, the advantage of simplifying the manufacturing steps of the semiconductor device can be obtained.

[0071] As described above, according to this embodiment, by arranging not only the pad 47 but also the wiring 48 above the substrate 13, the wirings can be effectively laid out in the semiconductor device.

[0072] (Second Embodiment)

[0073] Figure 9 It is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0074] Figure 9 It shows the same cross-sectional view as Figure 4 However, Figure 4 the wiring 48 is arranged at a position non-contact with the pad 47, whereas Figure 9 the wiring 48 is arranged at a position in contact with the pad 47. The wiring 48 of this embodiment is formed by the same wiring layer 20 as the pad 47 as in the first embodiment, but may also be formed by a wiring layer 20 different from the pad 47. In addition, for easy understanding of the description, Figure 9 a step difference between the upper surface of the pad 47 and the upper surface of the wiring 48 is shown in

[0075] Figure 10 It is a top view showing the structure of the semiconductor device of the second embodiment. Figure 9 It shows alongFigure 10 The cross-section of the J-J' line in Figure 9 However, in Figure 10 for ease of understanding the description, the position of the second plug 46 under the wiring 48 is different from

[0076] Figure 10 and Figure 9 Similarly, the pads 47 and the wiring 48 included in the wiring layer 20 are shown. Figure 10 As an example, ten pads 47 and two wirings 48 indicated by the symbols C1 and C2 are shown. These pads 47 include two power pads 47a and 47b. The wiring 48 is also appropriately denoted as "wiring C1, C2". Figure 10 Furthermore, the positions of the second plugs 46 electrically connected to these wirings 48 are schematically shown.

[0077] The symbol Wx represents the width of each pad 47 in the X direction, the symbol Wy represents the width of each pad 47 in the Y direction, and the symbol W represents the width of each wiring 48. The width W of the wiring 48 in the present embodiment is set to be narrower than the widths Wx and Wy of the pads 47 (W < Wx, W < Wy), similarly to the first embodiment. In addition, the values of the widths Wx and Wy of each pad 47 may also be different from each other. Similarly, the values of the widths W of each wiring 48 may also be different from each other.

[0078] The wiring C1 electrically connects the power pad 47a to the peripheral circuit of the semiconductor device and is used to supply power to the semiconductor device. Similarly, the wiring C2 electrically connects the power pad 47b to the peripheral circuit of the semiconductor device and is used to supply power to the semiconductor device. These wirings C1 and C2 include a first portion extending in the X direction and a second portion extending in the Y direction. The width W of the wirings C1 and C2 corresponds to the length of the wirings C1 and C2 in the Y direction in the first portion and corresponds to the length of the wirings C1 and C2 in the X direction in the second portion.

[0079] Examples of the wirings C1 and C2 are power supply lines for supplying a ground voltage (VSS voltage), or a power supply voltage (VDD voltage), or other power supply voltages (VDDQ voltage). For example, the wiring C1 is a VSS voltage line and the wiring C2 is a VDD voltage line. In this case, the power pad 47a is used to apply the VSS voltage to the semiconductor device, and the power pad 47b is used to apply the VDD voltage to the semiconductor device.

[0080] Figure 10The position of the second plug 46 electrically connected to these wirings 48 is schematically represented by a circle. However, note that these circles are shown for the sake of easily understanding the position of the second plug 46 and do not represent the shape of the second plug 46. Each wiring 48 is electrically connected to a peripheral circuit of the semiconductor device or the like via these second plugs 46. The width W of each wiring 48 in the present embodiment is set to the same value at the portion directly above these second plugs 46 and other portions. In addition, note that in the semiconductor device of the present embodiment, the second plug 46 is also provided under each pad 47 (refer to Figure 9 ).

[0081] According to the present embodiment, similarly to the first embodiment, wirings can be efficiently arranged in the semiconductor device. For example, when the wiring 48 is used as a power supply line, by making the wiring 48 thicker by utilizing the surplus of the space, the influence of the wiring resistance on the power supply can be reduced.

[0082] In addition, Figure 5 the arrangement of the wiring 48 shown Figure 10 and the arrangement of the wiring 48 shown can also be applied together to the same semiconductor device. In addition, the semiconductor device of the first embodiment or the second embodiment is a three-dimensional memory manufactured from two wafers (array wafer W1 and circuit wafer W2), but these embodiments can also be applied to a semiconductor device manufactured from one wafer or a semiconductor device other than a three-dimensional memory.

[0083] The above describes several embodiments, but these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described in this specification can be implemented in various other ways. In addition, with respect to the embodiments of the devices and methods described in this specification, various omissions, substitutions, and changes can be made without departing from the gist of the invention. The scope of the appended claims and the equivalent scope are intended to include such embodiments or variations included in the scope or gist of the invention.

[0084] [Reference Signs]

[0085] 1 Array chip

[0086] 2 Circuit chip

[0087] 3 Controller

[0088] 11 Memory cell array

[0089] 12 Insulating layer

[0090] 13 Substrate

[0091] 14 Insulating layer

[0092] 15 Interlayer insulating film

[0093] 16th First Insulating Layer

[0094] 17th Second Insulating Layer

[0095] 18th Interlayer Insulating Film

[0096] 19th Substrate

[0097] 20th Wiring Layer

[0098] 21st Step Structure Portion

[0099] 22nd Contact Plug

[0100] 23rd Word Wiring Layer

[0101] 24th Contact Plug

[0102] 25th Source-Side Select Gate Wiring Layer

[0103] 26th Contact Plug

[0104] 27th Drain-Side Select Gate Wiring Layer

[0105] 28th Plug

[0106] 29th Contact Plug

[0107] 30th Source Wiring Layer

[0108] 31st Transistor

[0109] 32nd Gate Electrode

[0110] 33rd Plug

[0111] 34th Wiring Layer

[0112] 35th Wiring Layer

[0113] 36th Through-Hole Plug

[0114] 37th Second Metal Pad

[0115] 41st First Metal Pad

[0116] 42nd Through-Hole Plug

[0117] 43rd Wiring Layer

[0118] 44th First Plug

[0119] 45th Insulating Film

[0120] 46th Second Plug

[0121] 47th Pad

[0122] 47a Power Pad

[0123] 47b Power Pad

[0124] 48 Wiring

[0125] 49 Passivation Film

[0126] 51 Insulation Layer

[0127] 52 Barrier Insulation Film

[0128] 53 Charge Storage Layer

[0129] 54 Tunnel Insulation Film

[0130] 55 Channel Semiconductor Layer

[0131] 56 Core Insulation Film

[0132] 61 Plane (Memory Cell Array)

[0133] 62 Row Decoder

[0134] 63 Data Processing Circuit

[0135] 64 Control Voltage Generation Circuit

[0136] 71 SA / DL Section

[0137] 72 XDL Section

[0138] 73 YLOG Section

[0139] 74 Series Circuit

[0140] 75 I / O Circuit

[0141] 81 Low Voltage Generation Circuit

[0142] 82 High Voltage Generation Circuit

[0143] 83 Row Control Circuit

[0144] 84 Column Control Circuit

Claims

1. A semiconductor device, comprising: A circuit chip having a first substrate and a logic circuit provided on the first substrate; An array chip having a memory cell provided above the circuit chip and a second substrate provided above the memory cell, and being bonded to the circuit chip; A plurality of metal pads provided on a bonding surface of the circuit chip and the array chip, and electrically connecting the logic circuit and the memory cell; A bonding pad provided above the second substrate and electrically connected to the logic circuit via a part of the plurality of metal pads; And A wiring provided above the second substrate and electrically connected to the memory cell via a part of the plurality of metal pads, including at least one of a data signal line, a control voltage line, and a power supply line.

2. The semiconductor device according to claim 1, wherein the bonding pad and the wiring are included in the same wiring layer provided above the second substrate.

3. The semiconductor device according to claim 1 or 2, further comprising an insulating film provided on an upper surface of the wiring and having an opening exposing an upper surface of the bonding pad.

4. The semiconductor device according to claim 1 or 2, wherein the wiring is for transmitting an input signal to the semiconductor device or transmitting an output signal from the semiconductor device, for supplying a control voltage to the memory cell, or for supplying power to the semiconductor device.

5. The semiconductor device according to claim 1 or 2, wherein the wiring is provided at a position non-contact with the bonding pad.

6. The semiconductor device according to claim 1 or 2, wherein the wiring is provided at a position in contact with the bonding pad.

7. A method of manufacturing a semiconductor device, comprising: Forming a circuit chip on a first substrate, the circuit chip having: a logic circuit, a second insulating layer above the logic circuit, and a plurality of second metal pads electrically connected to the logic circuit within the second insulating layer; Forming an array chip below a second substrate, the array chip having: a memory cell, a first insulating layer below the memory cell, and a plurality of first metal pads corresponding to the second metal pads within the first insulating layer and electrically connected to the memory cell; Bonding the second insulating layer of the circuit chip to the first insulating layer of the array chip, and bonding the plurality of first metal pads and the plurality of second metal pads; Forming a bonding pad above the second substrate, the bonding pad being electrically connected to the logic circuit via a part of the plurality of first metal pads; And Forming a wiring above the second substrate, the wiring being electrically connected to the memory cell via a part of the plurality of first metal pads, including at least one of a data signal line, a control voltage line, and a power supply line.

8. The method of manufacturing a semiconductor device according to claim 7, further comprising: Forming a wiring layer above the second substrate; Processing the wiring layer to form the bonding pad and the wiring from the wiring layer.

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