A fast charging and discharging circuit of a switch

Abstract

The present invention relates to a fast charge and discharge circuit for a switch, comprising a fast charge and discharge module, a receiving-end switch, and a transmitting-end switch. The transmitting-end switch is connected to the transmitting end, the receiving-end switch is connected to the receiving end, and the transmitting-end switch and the receiving-end switch jointly output to the antenna end. The control signal of the transmitting-end switch includes mutually opposite signals cr_p and cr_n, and the control signal of the receiving-end switch includes signals cr_n and vg1, with signal vg1 connected to the fast charge and discharge module. The technology of the present invention achieves high-voltage control of the fast charge and discharge path while ensuring device safety through feedback of the voltage at the control end of the switch tube, so that the original charging speed can be maintained as the control voltage increases.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a fast charging and discharging circuit of a switch. Background Art

[0002] With the rapid development of communication systems, the requirements for switching speeds in chip design circuits are becoming increasingly stringent. Chip switches typically include a transmitter, receiver, and antenna. The transmitter and receiver typically utilize switching transistors. The transmitter is controlled by internal chip control signals, while the receiver is controlled by external signals or internal RF signals. The switching speed of a switch is limited by the charge and discharge time of the switch's control terminal. In traditional switch designs, this time is limited by the high resistance of the control terminal and the size of the switch. These resistances and switch size significantly impact key switch performance, such as insertion loss, isolation, and compression point. Summary of the Invention

[0003] To solve the existing technical problems, the present invention provides a fast charge and discharge circuit for a switch, which realizes the rapid charge and discharge of the control end of the switch tube while ensuring the original performance of the switch, so that the switching speed of the switch is no longer limited by the resistance of the control end and the size of the switch tube, greatly reducing the design difficulty and greatly improving the switching speed of the switch.

[0004] The present invention specifically includes a fast charge and discharge module, a receiving-end switch, and a transmitting-end switch. The transmitting-end switch is connected to the transmitting end, the receiving-end switch is connected to the receiving end, and the transmitting-end switch and the receiving-end switch jointly output to the antenna end. The control signal of the transmitting-end switch includes a signal cr_p and a signal cr_n that are opposite to each other. The control signal of the receiving-end switch includes a signal cr_n and a signal vg1. The signal vg1 is connected to the fast charge and discharge module. The fast charge and discharge module includes a fast charge control module 104, a first stacked MOS transistor, and a parallel resistor.

[0005] The first stacked MOS transistor includes several MOS transistors connected in series. The control signal vg1 of the receiving-end switch enters the source end of the first stacked MOS transistor and the fast charging control module 104 respectively. A parallel resistor is provided between the drain end and the source end of the first stacked MOS transistor. The output voltage signal ctr of the fast charging control module 104 enters the gate end of the first stacked MOS transistor, and the cr_p signal is also input into the drain end of the first stacked MOS transistor.

[0006] Furthermore, the receiving end switch includes a second stacked MOS transistor and a third stacked MOS transistor.

[0007] The second stacked MOS transistor includes several MOS transistors connected in series, the drain of the second stacked MOS transistor is connected to the emitter switch, the drain of the third stacked MOS transistor is connected to the source of the second stacked MOS transistor, and the gate of the MOS transistor in the second stacked MOS transistor is connected in series to the signal vg1 through a resistor;

[0008] The third stacked MOS transistor includes several groups of MOS transistors connected in parallel. Each MOS transistor group includes two MOS transistors connected in series. The drain of each MOS transistor group is connected to the second stacked MOS transistor, and the source is grounded. The gate of the third stacked MOS transistor is connected in series to the control signal cr_n through a resistor.

[0009] Furthermore, the transmitter switch includes a fourth stacked MOS transistor and a fifth stacked MOS transistor;

[0010] The fourth stacked MOS transistor includes a plurality of MOS transistors connected in series. The drain end of the fifth stacked MOS transistor is connected to the source end of the fourth stacked MOS transistor. The gate of the MOS transistor in the fourth stacked MOS transistor is connected in series to the control signal cr_n via a resistor.

[0011] The fifth stacked MOS transistor includes several groups of MOS transistors connected in parallel, each group of MOS transistors includes several MOS transistors connected in series, and the gates of the MOS transistors in the fifth stacked MOS transistor are connected in series to the control signal cr_p through resistors.

[0012] Furthermore, the control signal cr_p generates a delayed control signal cr_d_p and a delayed reverse control signal cr_d_n through a delay link, and both the signal cr_d_p and the signal cr_d_n are connected to the fifth stacked MOS transistor.

[0013] Furthermore, the delay chain includes a plurality of cascaded inverters, and the control signal cr_p passes through an even number of inverters to obtain a delayed control signal cr_d_p, and then passes through an odd number of inverters to obtain a delayed reverse control signal cr_d_n.

[0014] Furthermore, the fast charging control module 104 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, an inverter I1 and a capacitor C.

[0015] The power supply voltage VCC of the fast charging control module 104 is connected to resistors R1, R2, and R3 in sequence and then to ground. A voltage signal ctr is output between resistors R1 and R2. The voltage signal ctr is connected to the first stacked MOS transistor. The drain terminal of MOS transistor M1 is connected to the voltage signal ctr, the source terminal is connected to the control signal cr_p, and the gate terminal is connected to the signal cr_d_n.

[0016] The signal vg1 is connected to the gate of the MOS tube M3 through the resistor R4 and the inverter I1;

[0017] MOS tube M2 and MOS tube M3 are respectively connected in parallel with resistor R3;

[0018] The gate of the MOS transistor M2 is connected to the signal cr_d_p.

[0019] Furthermore, the resistors R1, R2, and R3 satisfy that VCC*R2 / (R1+R2) is the same as the high-level turn-on voltage of the MOS tube, and VCC*(R2+R3) / (R1+R2+R3) is the same as the sum of the high-level turn-on voltage and the threshold voltage of the MOS tube.

[0020] Furthermore, the delay link includes a plurality of capacitor-resistor (RC) delay circuits, and the capacitor-resistor (RC) delay circuits are arranged between the inverters.

[0021] The technology of the present invention achieves the effect of rapid charging and discharging by establishing a parallel rapid charging and discharging path with a large resistor at the control end of the switch tube. At the same time, after charging and discharging are completed, the rapid charging and discharging path maintains a high-resistance state, avoiding a negative impact on the switch performance. The technology of the present invention realizes high-voltage control of the rapid charging and discharging path while ensuring the safety of the device through feedback of the voltage at the control end of the switch tube, so that it can still maintain the original charging speed as the control voltage rises. The technology of the present invention uses stacked MOS tubes as a rapid charging and discharging path. The stacking characteristics enable it to maintain high resistance even when the signal amplitude is large, avoiding the impact on the switch compression point, insertion loss and other performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.

[0023] Figure 1 Schematic diagram of the principle of the fast charge and discharge circuit of the switch of the present invention;

[0024] Figure 2 A schematic diagram of the switch structure of the present invention;

[0025] Figure 3 Schematic diagram of the fast charge and discharge module of the present invention;

[0026] Figure 4 Schematic diagram of the delay link of the present invention;

[0027] Figure 5 It is the transient waveform diagram of the present invention. DETAILED DESCRIPTION

[0028] Combine Figure 1-Figure 5This embodiment discloses a fast charge and discharge circuit for a switch, including a fast charge and discharge module 102, a receiving-end switch 100, and a transmitting-end switch 101. The transmitting-end switch 101 is connected to the transmitting end, and the receiving-end switch 100 is connected to the receiving end. The transmitting-end switch 101 and the receiving-end switch 100 jointly output to the antenna end. The fast charge and discharge module 102 includes a fast charge control module 104, a first stacked MOS transistor 105, and a parallel resistor 103.

[0029] The control signal vg1 of the receiving-end switch 100 enters the source terminal of the first stacked MOS transistor 105 and the fast charging control module 104 respectively. A parallel resistor 103 is provided between the drain terminal and the source terminal of the first stacked MOS transistor 105. The output signal ctr of the fast charging control module 104 enters the gate of the first stacked MOS transistor 105.

[0030] The control signals of the transmitter switch 101 include cr_p and cr_n, which are opposite to each other. The cr_p signal is also input to the drain of the first stacked MOS transistor 105, and the cr_n signal is also connected to the receiver switch 100. In this embodiment, the parallel resistor 103 is selected to be 30 kΩ.

[0031] The MOS transistor used in this embodiment is a 2.5V MOS transistor, so the voltage difference between any two terminals of the MOS transistor must not exceed 2.5V. Control signals cr_p and cr_n are inverse receiver control signals. When cr_p = 2.5V and cr_n = 0V, the receiver switch 100 channel is open and the transmitter switch 101 is closed. Conversely, the receiver is closed and the transmitter is open. Generally, when the receiver switch 100 is open, the transmitter switch 101 is closed, and when the transmitter switch 101 is open, the receiver switch 100 is closed, thus dividing the transceiver switch into a transmitting state and a receiving state.

[0032] During charging, the control voltage feedback of the switch tube is used. When the control voltage rises to the threshold voltage, the control voltage of the fast charge and discharge module 102 rises to a higher voltage than the maximum control voltage, so that the first stacked MOS tube 105 always remains in a conductive low-resistance state during the charging process. After charging is completed, the control voltage of the first stacked MOS tube 105 is restored to the maximum control voltage, the stacked MOS tube is turned off, and the current passes through the parallel resistor 103, causing the charging speed to drop sharply without affecting the switch performance. By using the stacked MOS tube as a fast charge and discharge path, its stacking characteristics enable it to maintain high resistance even when the signal amplitude is large, avoiding the impact on the switch compression point, insertion loss and other performance.

[0033] In this embodiment, the receiving end switch and the transmitting end switch can adopt a common structure in the art. The receiving end switch 100 includes a second stacked MOS transistor 201 and a third stacked MOS transistor 202.

[0034] The second stacked MOS transistor 201 includes several MOS transistors connected in series. The drain of the second stacked MOS transistor 201 is connected to the emitter switch 101. The drain of the third stacked MOS transistor 202 is connected to the source of the second stacked MOS transistor 201. The gate of the MOS transistor in the second stacked MOS transistor 201 is connected in series to the signal vg1 via a resistor. In this embodiment, the resistor is 3 kΩ.

[0035] The third stacked MOS transistors 202 include several groups of MOS transistors connected in parallel. Each MOS transistor group includes two MOS transistors connected in series. The drain of each MOS transistor group is connected to the second stacked MOS transistor 201, and the source is grounded. The gate of the third stacked MOS transistor 202 is connected in series to the control signal cr_n via a resistor. In this embodiment, the resistor is 30 kΩ.

[0036] The transmitter switch 101 includes a fourth stacked MOS transistor 203 and a fifth stacked MOS transistor 204;

[0037] The fourth stacked MOS transistor 203 includes several MOS transistors connected in series. The drain of the fifth stacked MOS transistor 204 is connected to the source of the fourth stacked MOS transistor 203. The gates of the MOS transistors in the fourth stacked MOS transistor 203 are connected in series to the control signal cr_n via a resistor. In this embodiment, the resistor is 30 kΩ.

[0038] The fifth stacked MOS transistor 204 includes several MOS transistor groups connected in parallel. Each MOS transistor group includes several MOS transistors connected in series. The gates of the MOS transistors in the fifth stacked MOS transistor 204 are connected in series to the control signal cr_p through a resistor. In this embodiment, the resistor is 30 kΩ.

[0039] In this embodiment, the series MOS transistor group means that the drain of the previous MOS transistor in the MOS transistor group is connected to the source of the next MOS transistor, and the final MOS transistor group has the drain of the first MOS transistor as the drain terminal and the source of the last MOS transistor as the source terminal.

[0040] Since the receiving end of the transceiver switch is at the front end of the RF, its insertion loss significantly affects the noise figure of the entire system. To reduce the insertion loss, the first stacked MOS transistors 105 are all relatively large in size. At the same time, the impedance equivalent to the ground of the MOS transistor gate needs to be large to prevent signal leakage from the gate and affect the insertion loss. Therefore, the gate of the first stacked MOS transistor 105 is charged and discharged relatively slowly.

[0041] like Figure 4As shown, the control signal in this embodiment is generated through a delay chain 401, which includes seven cascaded inverters. RC capacitor-resistor delay circuits are provided between the first and second inverters, between the second and third inverters, and between the fifth and sixth inverters. The input of the delay chain 401 is the control signal cr_p, which passes through four inverters to generate a delayed control signal cr_d_p, and then passes through three inverters to generate a delayed reverse control signal cr_d_n.

[0042] like Figure 3 As shown, the fast charging control module 104 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, an inverter I1 and a capacitor C.

[0043] The power supply voltage VCC of the fast charging control module 104 is connected to resistors R1, R2, and R3 in sequence, and then to ground. A voltage signal ctr is output between resistors R1 and R2, and this voltage signal ctr is connected to the first stacked MOS transistor 105. MOS transistor M1's drain terminal is connected to the voltage signal ctr, its source terminal is connected to the control signal cr_p, and its gate is connected to the signal cr_d_n. Signal vg1 is connected to the gate of MOS transistor M3 via resistor R4 and inverter I1. MOS transistors M2 and M3 are each connected in parallel with resistor R3. The gate of MOS transistor M2 is connected to the signal cr_d_p. In this embodiment, the power supply voltage VCC is selected to be 3.3V.

[0044] like Figure 4 The transient waveform diagram of this embodiment is shown, including the changes of each signal during the discharge and charge process, combined with Figure 4 , the working process of this embodiment is as follows:

[0045] In this embodiment, the control voltage ctr of the fast charge and discharge module 102 is obtained by voltage division using resistors R1, R2, and R3. When both M2 and M3 are turned off, ctr = 3.3*(R2+R3) / (R1+R2+R3) = 2.9V. When either M2 or M3 is turned on, ctr = 3.3*R2 / (R1+R2) = 2.5V.

[0046] In the emission state, cr_p = 0 V, cr_n = 2.5 V. At this time, the delay control signals cr_d_p = 0 V, cr_d_n = 2.5 V. At this time, MOS transistor M1 is turned on, so the signal ctr is shorted to ground. The voltage of the signal ctr is 0, the first stacked MOS transistor 105 is turned off, vg1 = cr_p = 0 V, M2 is turned off, and M3 is turned on.

[0047] The transmitting state switches to the receiving state. At this time, the signal cr_p rises from 0V to 2.5V, and the signal cr_n drops from 2.5V to 0V. The signal cr_p passes through the delay link 401401 to obtain the delayed control signal cr_d_p and its reverse signal cr_d_n. Figure 4 In the timing diagram, during the delay time, the signal cr_d_n is still 2.5V, and the signal cr_p is 2.5V. Therefore, the signal ctr rises from 0 to 2.5V, M1 is turned off, and the first stacked MOS transistor 105 is turned on. At this time, the on-resistance is much smaller than the parallel resistor 103. At this time, vg1 and the entire second stacked MOS transistor 201 are charged. At this time, since the gate resistance of the second stacked MOS transistor 201 is small, about 3K, the charging is relatively fast, which is fast charging.

[0048] As charging progresses, the voltage vg1 continues to rise. Theoretically, if no action is taken, when vg1 rises to 2.5-vth, the first stacked MOS transistor 105 will shut down. At this point, the charging path will pass through parallel resistor 103, which is approximately 30kΩ, and the charging speed will drop sharply. In this solution, during the rising process of vg1, when vg1 exceeds vth, the voltage signal vg_m3 generated after inverter I1 drops from 2.5V to 0V, MOS transistor M3 turns off, and signal cr_d_p remains at 0. At this time, MOS transistor M2 remains off, causing ctr to rise to 2.9V. As a result, the first stacked MOS transistor 105 remains on during the period when vg1 ranges from 0-2.5V, maintaining the fast charging state. Furthermore, since signal ctr only begins to rise to 2.9V after vg1 rises to vth (vth = 0.4V in this embodiment), the voltage difference between the two terminals of the first stacked MOS transistor 105 does not exceed 2.5V. At the same time, when ctr rises to 2.9V, the signal cr_p is 2.5V and the signal cr_d_n is also 2.5V. Therefore, the voltage across the MOS tube M1 does not exceed 2.5V.

[0049] Subsequently, after charging is completed, the delay signals cr_d_p and cr_d_n change, and the signal cr_d_p rises to 2.5V. At this time, the MOS tube M2 is turned on, ctr returns to 2.5V, the signal cr_d_n drops to 0, and the MOS tube M1 is turned off. At this point, fast charging is completed and the switch has switched to the receiving state. In this state, each port of the first stacked MOS tube 105 is 2.5V, which is in a good cut-off state and has a large impedance. Therefore, for the second stacked MOS tube 201, its gate terminal equivalent to ground impedance is very large (much greater than 3k ohms), and the receiving insertion loss is minimally affected by fast charging.

[0050] When the receiving state switches to the transmitting state, the signal cr_p drops from 2.5V to 0V. At this time, the signal cr_d_n is still 0V, and the cr_d_p is still 2.5V. Therefore, the MOS transistor M1 is still turned off, the MOS transistor M2 is still turned on, and ctr remains at 2.5V. At this time, the first stacked MOS transistor 105 is turned on (MOS transistors are symmetrical), and the gate of the second stacked MOS transistor 201 is quickly discharged through the turned-on first stacked MOS transistor 105.

[0051] As discharge progresses, vg1 continuously decreases. When its drop is less than vth, vg_m3 rises to 2.5V, turning M3 on. Subsequently, after discharge is complete, the delay control signal changes, with signal cr_d_n rising to 2.5V and signal cr_d_p falling to 0V. At this point, M2 turns off and M1 turns on. At this point, ctr is pulled down to cr_p, or 0V, through MOS transistor M1, turning off the first stacked MOS transistor 105. At this point, rapid discharge is complete, and the switch has switched to the transmitting state. Simultaneously, in this state, all ports of the first stacked MOS transistor 105 are at 0V, indicating a good cutoff state with high impedance. Therefore, the equivalent impedance from the gate terminal to ground of the second stacked MOS transistor 201 is also high. Therefore, leakage of the transmit signal through the gate terminal of the second stacked MOS transistor 201 is also low, minimally impacting transmit performance.

[0052] In addition, in the transmitting state, the antenna-end signal amplitude is relatively large. At this time, the closer the MOS transistor in the second stacked MOS transistor 201 is to the antenna end, the larger its gate voltage swing is. Therefore, Vg1 also has a relatively large voltage swing. In this solution, the first stacked MOS transistor 105 adopts a stacking method to avoid the situation where the large swing of Vg1 causes the MOS transistor 107 to be turned on, and the signal leaks from this path, affecting the transmission performance.

[0053] Through this solution, the gate end of the second stacked MOS transistor 201 at the larger receiving end in the transceiver switch can be quickly charged, thereby achieving fast switching of transceiver and receiver without affecting the transceiver performance.

[0054] The technology of the present invention realizes high-voltage control of the fast charge and discharge path while ensuring the safety of the device through feedback of the voltage at the control end of the switch tube, so that the original charging speed can be maintained as the control voltage increases.

[0055] This embodiment uses stacked MOS tubes as a fast charge and discharge path. The stacking characteristic enables it to maintain high resistance even when the signal amplitude is large, thereby avoiding affecting the switch compression point, insertion loss and other performance.

[0056] This embodiment utilizes a delay link to generate a delayed control signal to control the rapid charging and discharging process, allowing for rapid charging and discharging within the delay time. This technology allows the charging and discharging speed to be controlled by the delay time, freeing it from the constraints of the switch control terminal resistance and switch size, thereby achieving technically fast switching without compromising switch performance.

[0057] In the above description, many specific details are set forth in order to fully understand the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A fast charge and discharge circuit for a switch, characterized in that: It includes a fast charge and discharge module, a receiving end switch and a transmitting end switch. The transmitting end switch is connected to the transmitting end, the receiving end switch is connected to the receiving end, and the transmitting end switch and the receiving end switch jointly output to the antenna end. The control signal of the transmitting end switch includes a signal cr_p and a signal cr_n that are opposite to each other. The control signal of the receiving end switch includes a signal cr_n and a signal vg1. The signal vg1 is connected to the fast charge and discharge module. The fast charge and discharge module includes a fast charge control module, a first stacked MOS transistor and a parallel resistor. The first stacked MOS transistor includes several MOS transistors connected in series. The control signal vg1 of the receiving-end switch enters the source terminal of the first stacked MOS transistor and the fast charging control module respectively. A parallel resistor is provided between the drain terminal and the source terminal of the first stacked MOS transistor. The output voltage signal ctr of the fast charging control module enters the gate terminal of the first stacked MOS transistor. The cr_p signal is also input to the drain terminal of the first stacked MOS transistor. The receiving end switch includes a second stacked MOS transistor and a third stacked MOS transistor, The second stacked MOS transistor includes several MOS transistors connected in series, the drain of the second stacked MOS transistor is connected to the emitter switch, the drain of the third stacked MOS transistor is connected to the source of the second stacked MOS transistor, and the gate of the MOS transistor in the second stacked MOS transistor is connected in series to the signal vg1 through a resistor; The third stacked MOS transistor includes a plurality of MOS transistor groups connected in parallel, each MOS transistor group includes two MOS transistors connected in series, the drain of each MOS transistor group is connected to the second stacked MOS transistor, the source is grounded, and the gate of the third stacked MOS transistor is connected in series to the control signal cr_n through a resistor; The transmitter switch includes a fourth stacked MOS transistor and a fifth stacked MOS transistor; The fourth stacked MOS transistor includes a plurality of MOS transistors connected in series. The drain end of the fifth stacked MOS transistor is connected to the source end of the fourth stacked MOS transistor. The gate of the MOS transistor in the fourth stacked MOS transistor is connected in series to the control signal cr_n via a resistor. The fifth stacked MOS transistor includes a plurality of MOS transistor groups connected in parallel, each MOS transistor group includes a plurality of MOS transistors connected in series, and the gates of the MOS transistors in the fifth stacked MOS transistor are connected in series to the control signal cr_p through resistors; The control signal cr_p generates a delayed control signal cr_d_p and a delayed reverse control signal cr_d_n through a delay link, and both the signal cr_d_p and the signal cr_d_n are connected to the fifth stacked MOS transistor; The fast charging control module includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, an inverter I1 and a capacitor C. The power supply voltage VCC of the fast charging control module is connected to resistors R1, R2, and R3 in sequence and then to ground. A voltage signal ctr is output between resistors R1 and R2. The voltage signal ctr is connected to the first stacked MOS transistor. The drain terminal of MOS transistor M1 is connected to the voltage signal ctr, the source terminal is connected to the control signal cr_p, and the gate is connected to the signal cr_d_n. The signal vg1 is connected to the gate of the MOS tube M3 through the resistor R4 and the inverter I1; MOS tube M2 and MOS tube M3 are respectively connected in parallel with resistor R3; The gate of MOS tube M2 is connected to signal cr_d_p; The control signal is generated through a delay chain, which includes seven cascaded inverters. RC capacitor-resistor delay circuits are provided between the first and second inverters, between the second and third inverters, and between the fifth and sixth inverters. The input of the delay chain is the control signal cr_p, which passes through four inverters to generate a delayed control signal cr_d_p, and then passes through three inverters to generate a delayed reverse control signal cr_d_n.

2. The fast charge and discharge circuit of a switch according to claim 1, characterized in that: Resistors R1, R2, and R3 satisfy that VCC*R2 / (R1+R2) is the same as the high-level voltage of the MOS transistor, and VCC*(R2+R3) / (R1+R2+R3) is the same as the sum of the high-level voltage of the MOS transistor and the threshold voltage.

3. The fast charge and discharge circuit of a switch according to claim 1, characterized in that: The delay link includes a plurality of capacitor-resistor (RC) delay circuits, and the capacitor-resistor (RC) delay circuits are arranged between the inverters.

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