Process for manufacturing high-voltage capacitive components and corresponding integrated circuit

Abstract

This document describes a process for manufacturing high-voltage capacitive elements and corresponding integrated circuits. A semiconductor substrate has a front side with a first dielectric region. The capacitive element includes a layer stack on the surface of the first dielectric region at the front side, the layer stack including a first conductive region, a second conductive region, and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first conductive region and the third conductive region form one plate of the capacitive element, and the second conductive region forms the other plate of the capacitive element.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1902277, filed on March 6, 2019, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Field of the Invention

[0003] Implementations and embodiments relate to integrated circuits, and more particularly to the manufacture of integrated circuits including high-voltage capacitive elements. Background Art

[0004] The term "high voltage" should be understood to mean a voltage in the order of, for example, 3.5 V to 12 V.

[0005] There are conventional capacitive elements formed on one face of a well formed in a semiconductor substrate typically made of silicon. These conventional capacitive elements include a conductive layer typically made of polysilicon, the conductive layer being insulated from the substrate by a dielectric layer thick enough to allow operation at high voltage.

[0006] One electrode of the capacitive element is formed by the well, and the other electrode is formed by the conductive layer. Thus, the term MOS (metal-oxide-silicon) capacitive element is used.

[0007] A method for forming an electrode of a conductive material layer on one face of such a well typically implements a step of planarizing the conductive material, for example using a chemical mechanical polishing (CMP) process or a controlled etching process such as a poly-etchback (PEB) process.

[0008] An improvement to such a capacitive element includes forming an additional conductive layer on top of the initial conductive layer. The conductive layers are insulated from each other by another dielectric layer.

[0009] The additional conductive layer is coupled to the substrate in a structure referred to as a "sandwich" and belongs to the first electrode of the capacitive element.

[0010] This has become possible due to the existence of manufacturing processes that have prepared for a second operation of forming a conductive layer on top of the first conductive layer and the required second planarization step. For example, techniques for manufacturing floating gate transistors typically prepare for these steps.

[0011] That being said, in the processes for manufacturing integrated circuits, it is difficult to repeatedly perform the operation of forming a conductive layer and the corresponding planarization step typically executed over the entire surface of the substrate (or wafer).

[0012] Specifically, in a process for manufacturing an integrated circuit, for reasons of cost and architectural compatibility, it is desirable to combine the manufacturing steps of various elements in various parts of the integrated circuit.

[0013] At the same time, it is desirable to increase the density of capacitive elements, such as to reduce the footprint of embodiments of the capacitive elements.

[0014] It is also desirable to improve the performance of capacitive elements, particularly to limit the parasitic effects introduced by the capacitive elements into neighboring elements and to improve the linearity of the capacitance value of the capacitive elements. SUMMARY OF THE INVENTION

[0015] According to one aspect, an integrated circuit includes a semiconductor substrate having a front side, a first dielectric region extending from the front side into the substrate, and at least one capacitive element.

[0016] The capacitive element according to this aspect includes a stack of a first conductive region, a second conductive region, and a third conductive region on the surface of the dielectric region at the front side, the second conductive region being electrically insulated from the first conductive region by a second dielectric region and from the third conductive region by a third dielectric region.

[0017] In other words, the capacitive element includes a stack of three conductive layers and is formed on one surface of a dielectric body and does not include any electrical connection to the semiconductor substrate.

[0018] Thus, since it is isolated from the substrate, the capacitive element does not introduce any parasitic effects transmitted to neighboring components via the substrate, and since it does not electrically use the semiconductor substrate, the linearity and density of the capacitive element are improved.

[0019] According to one embodiment, the second dielectric region and the third dielectric region are configured to withstand a voltage higher than 3.5 volts.

[0020] Advantageously, the second dielectric region and the third dielectric region are configured to withstand a voltage higher than 10 volts.

[0021] The second dielectric region may include a high-voltage oxide having a thickness between 10 nm and 20 nm (e.g., 15 nm within 10%), or may include a tunnel oxide having a thickness between 5 nm and 15 nm (e.g., 10 nm within 10%).

[0022] The third dielectric region may include a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, the thickness of the stack being between 10 nm and 17 nm, e.g., 13 nm within 10% or 15 nm within 10%.

[0023] According to one embodiment, a capacitive element includes a first electrode and a second electrode, the first electrode including a first conductive region and a third conductive region, and the second electrode including a second conductive region.

[0024] According to one embodiment, the first conductive region, the second conductive region, and the third conductive region each include polysilicon.

[0025] The integrated circuit may further include an analog or radio frequency receiver device including at least one capacitive element, and a non-volatile memory device including at least one high-voltage transistor and / or at least one memory cell (including a floating-gate transistor and / or a buried vertical-gate transistor).

[0026] Advantageously, according to the respective “and / or” alternatives of this exemplary integrated circuit, the high-voltage transistor includes a gate formed in the material of the second conductive region, the buried vertical-gate transistor includes a vertical gate formed in the material of the first conductive region, and the floating-gate transistor includes a floating gate formed in the material of the second conductive region and / or includes a control gate formed in the material of the third conductive region.

[0027] Advantageously, also according to the respective “and / or” alternatives of this exemplary integrated circuit, the high-voltage transistor includes a high-voltage gate oxide formed in the material of the second dielectric region, or the floating-gate transistor includes a tunnel oxide formed in the material of the second dielectric region, and / or the floating-gate transistor includes a control gate dielectric region formed in the material of the third dielectric region.

[0028] According to another aspect, a process for manufacturing an integrated circuit on a semiconductor substrate having a front side and including an operation of manufacturing at least one capacitive element includes: forming a first dielectric region, including an operation of etching a trench from the front side in the substrate and an operation of filling the trench with a dielectric material; forming a first conductive region on the surface of the dielectric region at the front side; forming a second dielectric region on the first conductive region; forming a second conductive region on the first dielectric region; forming a third dielectric region on the first conductive region; and forming a third conductive region on the second dielectric region.

[0029] According to one embodiment: forming the first conductive region occurs together with the operation of forming the conductive gate region of the buried vertical gate transistor; forming the second dielectric region occurs together with the operation of forming the high-voltage gate oxide of the high-voltage transistor or with the operation of forming the tunnel oxide of the floating gate transistor; forming the second conductive region occurs together with the operation of forming the conductive floating gate region of the floating gate transistor; forming the third dielectric region occurs together with the operation of forming the control gate dielectric region of the floating gate transistor; and forming the third conductive region occurs together with the operation of forming the control gate conductive region of the floating gate transistor.

[0030] In particular, this implementation has the advantage of using manufacturing steps that have already been envisioned for fabricating floating gate transistors and buried vertical gate transistors, for example, for producing memory cells for non-volatile memories. Thus, the cost specific to producing capacitive elements is minimized.

[0031] According to one embodiment, forming the second dielectric region includes forming a high-voltage oxide having a thickness between 10 nm and 20 nm (e.g., 15 nm within 10%), or includes forming a tunnel oxide having a thickness between 5 nm and 15 nm (e.g., 10 nm within 10%).

[0032] According to one embodiment, forming the third dielectric region includes the operation of forming a stack of silicon oxide, silicon nitride, and silicon oxide, the thickness of the stack being between 10 nm and 17 nm, e.g., 13 nm within 10% or 15 nm within 10%.

[0033] According to one embodiment, the process further includes forming a first electrode of the capacitive element, including coupling to the first conductive region and the third conductive region, and forming a second electrode of the capacitive element, including coupling to the second conductive region.

[0034] According to one embodiment, forming the first conductive region, forming the second conductive region, and forming the third conductive region each include forming polysilicon.

[0035] According to one embodiment, manufacturing the at least one capacitive element is included in the operation of manufacturing an analog or radio frequency receiver device of an integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other advantages and features of the present invention will become apparent by referring to the detailed description of non-limiting implementations and embodiments with reference to the accompanying drawings, in which:

[0037] Figures 1 to 9 Steps of a process for producing an exemplary embodiment of an integrated circuit capacitive element are shown. DETAILED DESCRIPTION

[0038] Figures 1 to 9 Shows the result of the steps of an exemplary process for manufacturing a capacitive element, the steps being implemented continuously in the order of the drawing numbers. The drawing shows a cross-section through the semiconductor substrate SUB from the front side FA of the substrate SUB. The front side FA is the side located at the FEOL (front-end-of-line) during integrated circuit manufacturing.

[0039] Two parts of the integrated circuit are schematically shown: one part PCHV corresponds to the part in which a favorable capacitive element CHV is produced ( Figure 9 ). The other part PMEM corresponds to the part that is ultimately intended to include another device of the integrated circuit.

[0040] In the exemplary process described with reference to Figures 1 to 9 the manufacturing steps aimed at forming the devices in the part PMEM are advantageously used in parallel with the manufacturing of the capacitive element CHV. For this purpose, the devices of the integrated circuit in the part PMEM can advantageously include buried vertical gate transistors TA and floating gate transistors FGT, for example in certain known embodiments of memory cells of non-volatile memories.

[0041] Figure 1 Shows the result of step ST01, which includes the operation of forming a dielectric region STI.

[0042] Advantageously, the dielectric region STI is a shallow trench isolation and extends from the front side FA into the substrate SUB. Different from dielectric regions having a layer structure, the dielectric region STI occupies a volume in the substrate.

[0043] The operation of forming the dielectric region STI includes the operation of etching trenches in the substrate SUB from the front side FA and the operation of filling the trenches with a dielectric material.

[0044] Typically for the purpose of lateral electrical insulation between adjacent components, other dielectric regions STI (not shown) are formed elsewhere in the integrated circuit.

[0045] Step ST01 further includes the operation of forming a hard mask HM layer, such as a silicon nitride layer, on the front side FA of the substrate SUB.

[0046] Figure 2Shows the result of step ST2, which includes the operation of etching a portion of the hard mask HM located above the dielectric layer STI at the location where the capacitive element CHV is to be formed. The etching operation includes the operation of forming a photolithography mask MSK2, which includes holes OUV that define the area where the hard mask HM layer is to be etched. Once etched, the hard mask HM includes at the front face FA the same holes OUV thus transferred, which expose the corresponding portions of the dielectric region STI.

[0047] Figure 3 Shows the result of step ST3, which includes the operation of etching one or more trenches TRTA in a portion PMEM of the substrate SUB.

[0048] The trenches TRTA extend perpendicularly to the front face FA into the substrate. The position of the trenches TRTA can be defined by a photolithography step (not shown) including a mask.

[0049] Step ST3 also includes the operation of anisotropically injecting vertically (such as into the bottom of the trenches TRTA in this example) a counter-injection layer CTI, the conductivity type of which (e.g., n-type conductivity) is opposite to that of the substrate SUB (e.g., p-type conductivity) in the semiconductor portion not covered by the hard mask HM.

[0050] The trenches TRTA are intended to accommodate, for example, buried vertical gate transistors, and the injection of the counter-injection layer CTI is intended to form the source region of the buried vertical gate transistors.

[0051] Figure 4 Shows the result of step ST4, which includes the operation of forming a first conductive region P0 on the dielectric region STI.

[0052] The operation of forming the first conductive region P0 on the dielectric region STI includes the operation of filling the holes OUV ( Figure 2 ) with a conductive material P0, which extends beyond the holes above the hard mask HM.

[0053] This overflow can be obtained by overfilling with the conductive material P0.

[0054] For example, the conductive material P0 can include polysilicon.

[0055] Advantageously, the operation of filling the holes OUV is carried out together with the operation of filling the trenches TRTA envisaged in the step of forming the vertical gate of the buried transistor in the portion PMEM of the integrated circuit.

[0056] Figure 5 Shows the result of step ST5, which includes the operation of planarizing the excess conductive layer P0 deposited in step ST4.

[0057] The planarization operation includes an operation of removing an excessive deposition of the conductive material P0 until reaching the surface of the hard mask HM layer, where the hard mask HM layer can be used as a stop layer here.

[0058] The planarization operation can be implemented by means of a chemical mechanical polishing (CMP) technique or possibly by an etching technique such as a polysilicon etch back (PEB) technique parameterized according to the excessive thickness over time.

[0059] Figure 6 The result of step ST6 is shown, which aims to complete the formation of the vertical gate P0GV of the transistor buried in the partial PMEM. Step ST6 includes an operation of removing a part of the remaining conductive material P0 at the front face FA by dry etching through the thickness of the hard mask HM.

[0060] In this step ST6, the first conductive region P0 of the partial PCHV is protected by a mask MSK6 that is impermeable to dry etching.

[0061] For example, dry etching is usually achieved by a controlled etching process such as a polysilicon etch back (PEB) process. The PEB process generally includes an operation of exposing the integrated circuit to an ion beam for a duration during manufacturing, where the energy of the ion beam allows a given material (here the conductive material P0) to be removed, and the duration is selected according to the thickness of the material to be etched.

[0062] Figure 7 The result of step ST7 is illustrated, which includes an operation of removing the hard mask HM layer after the operation of removing the mask MSK6 ( Figure 6 ).

[0063] The operation of removing the hard mask HM layer can include selectively wet etching the material forming the hard mask HM, which is usually silicon nitride.

[0064] Figure 8 The result of step ST8 is shown, which includes an operation of forming a first dielectric layer (second dielectric region) D1 on the first conductive region P0, and subsequently an operation of forming a second conductive region P1 on the first dielectric layer D1.

[0065] According to an advantageous example, the operation of forming the first dielectric layer D1 is performed together with the operation of forming the floating gate or the high voltage oxide dielectric layer HV / TN of the floating gate transistor FGT ( Figure 9 ) formed in the partial PMEM of the substrate SUB, respectively.

[0066] Thus, according to the first alternative, the first dielectric layer D1 includes the high voltage gate oxide HV of the high voltage transistor.

[0067] According to the second alternative, the first dielectric layer D1 includes the tunnel oxide TN of the floating gate transistor FGT.

[0068] Furthermore, the operation of forming the second conductive region P1 can be advantageously carried out together with the operations of forming respectively the floating gate conductive region FG of the floating gate transistor or the gate region of the high-voltage transistor.

[0069] The second conductive region P1 (and the floating gate conductive region FG) can include polysilicon and can be formed, for example, by uniformly depositing a polysilicon layer, typically by epitaxy or chemical vapor deposition, followed by etching defined by a photolithographic mask. The etching can use the first dielectric layer D1 as a stop layer.

[0070] The floating gate dielectric layer TN includes, for example, silicon oxide resting on the front face FA of the semiconductor substrate SUB. The floating gate conductive region rests on the floating gate dielectric layer HV / TN. To store binary data, the floating gate FG allows the storage of charge in a non-volatile manner.

[0071] According to the first alternative mentioned above, the high-voltage oxide HV can be configured to withstand an operating voltage of about 11 V in order to be able to route high voltage to the memory points to inject positive and negative charges, thus allowing the writing of binary data in the floating gate transistor.

[0072] The high-voltage oxide can have a thickness between 10 nm and 20 nm (for example, within 10% of 15 nm).

[0073] According to the second alternative mentioned above, the tunnel oxide TN can be configured to withstand the injection or extraction of charge to / from the floating gate by the Fowler-Nordheim effect, thus allowing the writing of binary data in the floating gate transistor. The tunnel oxide TN can also be configured to withstand the injection of hot carriers, positive charges, and negative charges, thus allowing the writing of binary data in the floating gate transistor.

[0074] The tunnel oxide can have a thickness between 5 nm and 15 nm (for example, within 10% of 10 nm).

[0075] In both cases, the first dielectric layer D1 is configured to withstand a voltage higher than 10 volts, even 12 volts.

[0076] Therefore, the first dielectric layer D1 is capable of withstanding a voltage higher than 3.5 volts in order to allow the use of the capacitive element CHV( Figure 9 ) at a high voltage between 3.5 volts and 10 volts or even 12 volts.

[0077] In these advantageous examples, depending on the corresponding selected alternative, the first dielectric layer D1 naturally has the same structural characteristics as the high-voltage oxide layer or the floating-gate dielectric layer HV / TN.

[0078] Thus, the first dielectric layer D1 can be produced with reference to the operations for manufacturing a floating-gate transistor according to the above-described techniques, and the first dielectric layer D1 has the same structural characteristics without necessarily being produced together with the floating-gate transistor.

[0079] Figure 9 There is shown Figures 1 to 8 an exemplary embodiment of a capacitive element CHV implemented by the last step ST9 of the above-described process.

[0080] Step ST9 includes the operation of forming a second dielectric layer (third dielectric region) D2 on the first conductive region P1 and the operation of forming a third conductive region P2 on the second dielectric region D2.

[0081] These forming operations themselves can also be carried out together with the operations for forming the elements of the floating-gate transistor FGT.

[0082] Specifically, according to an advantageous example, the operation of forming the second dielectric layer D2 is carried out together with the operation of forming the control-gate dielectric region ONO of the floating-gate transistor FGT, and the operation of forming the third conductive region P2 is carried out together with the operation of forming the control-gate conductive region CG of the floating-gate transistor FGT.

[0083] Thus, the second dielectric layer D2 can include a stack ONO of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0084] The stack ONO can have a thickness between 10 nm and 17 nm (e.g., within 10% of 13 nm or within 10% of 15 nm).

[0085] The second dielectric layer D2 is thus configured to withstand a voltage higher than 10 volts, even 12 volts.

[0086] Thus, the second dielectric layer D2 is capable of withstanding a voltage higher than 3.5 volts in order to allow the capacitive element to be used at high voltages between 3.5 volts and 10 volts or even 12 volts.

[0087] The third conductive region P2 can also include polysilicon.

[0088] The third conductive region P2 can also be formed by a uniform deposition technique followed by etching defined by a lithographic mask.

[0089] Finally, a first electrode E1 of the capacitive element CHV is formed, and it includes a first conductive region P0 and a third conductive region P2.

[0090] Meanwhile, a second electrode E2 of the capacitive element includes a second conductive region P1 located between two conductive regions of the first electrode E1, and is electrically insulated therefrom by a first dielectric layer D1 and a second dielectric layer D2.

[0091] The operation of forming the second electrode E2 may simply include the operation of forming a metal silicide film on a part of the second conductive region P1, thereby allowing contacts presenting extremely low resistance.

[0092] The operation of forming the first electrode E1 may simply include the operation of forming a metal silicide film on parts of the first conductive region P0 and the third conductive region P2, and the operation of electrically coupling these regions via contacts presenting extremely low resistance formed by the metal silicide film.

[0093] What has been described is an exemplary manufacturing process, which has the advantage of using manufacturing steps that have been envisioned for manufacturing a floating gate transistor FGT and a buried vertical gate transistor TA for memory cells for producing a non-volatile memory PMEM. According to this example, the cost specific to producing the capacitive element CHV is the lowest.

[0094] However, the process is not limited to this example, but includes all its variants. For example, it is possible to envision implementing the described process such that it is applied to produce capacitive elements, and other materials and other dimensions can be envisioned within the context of the proposed structure.

[0095] Furthermore, since the capacitive element is produced on one surface of a dielectric region body, which is insulated from the substrate and does not introduce any parasitic effects transmitted to neighboring components via the substrate, and since it does not contain any semiconductor regions in its electrodes, the linearity of the capacitance value and the density of the capacitive element are increased.

[0096] Thus, the capacitive element can advantageously include devices in which the capacitive element performs a basic function and / or a large number of them such that they have a considerable occupied area.

[0097] The analog part and the radio frequency receiving chain of an integrated circuit typically require linear capacitance values over a wide voltage range.

[0098] Thus, for example, an integrated circuit CI manufactured according to the example described above with reference to Figures 1 to 9 can advantageously further include analog or radio frequency receiver devices in a part PCHV. The analog or radio frequency receiver devices advantageously include at least one of the said capacitive elements CHV.

[0099] Of course, the integrated circuit CI may include a non-volatile memory device PMEM, which includes at least one memory cell including a floating gate transistor FGT and a buried vertical gate transistor TA.

[0100] For example, the analog portion of the integrated circuit and the radio frequency receive chain may include capacitive elements according to the present invention in decoupling capacitors, compensation circuits in radio frequency filtering devices, or others.

Claims

1. An integrated circuit, comprising: a semiconductor substrate having a front side; shallow trench isolation regions in the semiconductor substrate; a first transistor supported by the semiconductor substrate; a second transistor supported by the semiconductor substrate, a capacitive element on top of the shallow trench isolation regions: wherein the capacitive element includes a first conductive region, a second conductive region, and a third conductive region, wherein the first conductive region contacts the upper surface of the shallow trench isolation region and forms a first electrode of the capacitive element, the second conductive region forms a second electrode of the capacitive element, and the third conductive region forms a third electrode of the capacitive element; wherein the first transistor includes a vertical conductive gate extending into the semiconductor substrate; wherein the second transistor includes a gate that includes a floating gate and a control gate extending over the semiconductor substrate; a first dielectric layer forming an insulating layer between the first conductive region and the second conductive region of the capacitive element, and further forming an insulating layer between the floating gate and the semiconductor substrate; a second dielectric layer forming an insulating layer between the second conductive region and the third conductive region of the capacitive element, and further forming an insulating layer between the control gate and the floating gate; wherein the third conductive region and the control gate are formed of a common conductive layer; wherein the second conductive region and the floating gate are formed of a common conductive layer; and wherein the first conductive region and the vertical conductive gate are formed of a common conductive layer.

2. The integrated circuit according to claim 1, wherein the first transistor and the second transistor form a memory element.

3. The integrated circuit according to claim 1, wherein the first dielectric layer is a tunnel oxide layer, and wherein the second dielectric layer is a stack of oxide / nitride / oxide.

4. The integrated circuit according to claim 1, wherein the capacitive element includes a first electrode formed by the first conductive region and the third conductive region electrically connected to each other and a second electrode formed by the second conductive region.

5. The integrated circuit according to claim 1, wherein the first conductive region, the second conductive region, and the third conductive region are each made of polysilicon.

6. The integrated circuit according to claim 1, wherein the first dielectric layer and the second dielectric layer are configured to withstand a voltage higher than 3.5 volts.

7. The integrated circuit according to claim 1, wherein the first dielectric layer and the second dielectric layer are configured to withstand a voltage higher than 10 volts.

8. The integrated circuit according to claim 1, wherein the first dielectric layer is a tunnel oxide layer having a thickness between 5 nm and 15 nm.

9. The integrated circuit according to claim 1, wherein the second dielectric layer is an insulating stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and the thickness of the insulating stack is between 10 nm and 17 nm.

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