Image Sensor

Abstract

An image sensor is disclosed, comprising a plurality of pixels, at least one of the plurality of pixels comprising: a photodiode configured to generate charge in response to light; and a pixel circuit disposed on a substrate, and the pixel circuit comprising: a storage transistor configured to store the charge generated by the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein when the transfer transistor is in an off state, the potential of a boundary region between the storage transistor and the transfer transistor has a first potential, and when the transfer transistor is in an on state, the potential of the boundary region between the storage transistor and the transfer transistor has a second potential lower than the first potential.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0025715 filed in the Korean Intellectual Property Office on March 6, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods consistent with exemplary embodiments of the present inventive concept relate to image sensors. Background Art

[0004] An image sensor is a semiconductor-based sensor on which light is irradiated to generate an electrical signal. The image sensor may include a pixel array having a plurality of pixels, a logic circuit for driving the pixel array and generating an image, etc. A pixel may include: a photodiode that generates a charge in response to light, and a pixel circuit that outputs a pixel signal using the charge generated by the photodiode. The charge generated by the photodiode may be stored in a storage element of the pixel circuit. In the case where the charge stored in the storage element is not smoothly transferred to a subsequent node, the performance of the image sensor may deteriorate. Summary of the invention

[0005] Exemplary embodiments of the inventive concept may provide an image sensor having improved performance while significantly reducing an increase in the area of ​​a storage element by increasing transfer efficiency of charges from a storage element of a pixel circuit to a floating diffusion node.

[0006] According to one aspect of the embodiments, an image sensor may include a plurality of pixels, at least one of the plurality of pixels including: a photodiode configured to generate charge in response to light; and a pixel circuit disposed on a substrate, and the pixel circuit including: a storage transistor configured to store charge generated by the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein when the transfer transistor is in an off state, a potential of a boundary region between the storage transistor and the transfer transistor has a first potential, and when the transfer transistor is in an on state, a potential of a boundary region between the storage transistor and the transfer transistor has a second potential lower than the first potential.

[0007] According to another aspect of the embodiment, an image sensor may include a plurality of pixels, at least one of the plurality of pixels including: a photodiode configured to generate charge in response to light; and a pixel circuit including: a storage transistor connected to the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein, in the pixel circuit, when the transfer transistor is turned on, the potential between the transfer transistor and the storage transistor gradually decreases in a direction away from the storage transistor.

[0008] According to another aspect of the embodiment, an image sensor may include multiple pixels, at least one of the multiple pixels including: a photodiode configured to generate charges in response to light; and a pixel circuit including multiple transistors, the multiple transistors configured to output pixel signals using the charges, wherein an active region of at least one of the multiple transistors includes a first impurity region and a second impurity region, the impurity concentration of the second impurity region is lower than the impurity concentration of the first impurity region, and wherein the second impurity region and the first impurity region are sequentially arranged according to a transfer direction of the charges. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and other advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1A and Figure 1B is a diagram illustrating an image sensor according to example embodiments;

[0011] Figure 2 and Figure 3 is a block diagram illustrating an image sensor according to example embodiments;

[0012] Figure 4 are diagrams provided to describe the operation of an image sensor according to an embodiment;

[0013] Figure 5 is a circuit diagram illustrating a pixel circuit of a pixel included in an image sensor according to example embodiments;

[0014] Figure 6 is a top view showing a pixel included in an image sensor according to an embodiment;

[0015] Fig. 7A and Figure 7B is shown along Figure 6 A cross-sectional view of a cross section of the image sensor shown taken along direction II';

[0016] Figure 8 and Fig. 9are diagrams provided to describe the operation of an image sensor according to an embodiment;

[0017] Fig.10 is a top view showing a pixel included in an image sensor according to an embodiment;

[0018] Fig.11A and Fig. 11B is shown along Fig.10 A cross-sectional view of a cross section of the image sensor shown taken along direction II-II';

[0019] Fig.12 is a top view showing a pixel included in an image sensor according to an embodiment;

[0020] Fig.13 is shown along Fig.12 A cross-sectional view of a cross section of the image sensor shown taken along direction III-III';

[0021] Fig.14 is a top view showing a pixel included in an image sensor according to an embodiment;

[0022] Fig.15 It shows that along Fig.14 A cross-sectional view of a cross section of the image sensor shown taken along direction IV-IV';

[0023] Fig.16 and Fig.17 is a top view showing a pixel included in an image sensor according to an embodiment;

[0024] Fig.18 is a diagram showing an imaging device including an image sensor according to an embodiment;

[0025] Fig.19 is a block diagram showing an imaging device including an image sensor according to an embodiment;

[0026] Fig. 20 is a circuit diagram showing a pixel circuit of a pixel included in an image sensor according to an embodiment;

[0027] Figure 21 to Figure 23 is a top view showing a pixel included in an image sensor according to an embodiment; and

[0028] Fig.24 is a block diagram illustrating an electronic device including an image sensor according to an embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. These embodiments are exemplary, and therefore, the inventive concept is not limited thereto, and may be implemented in various other forms. The embodiments provided in the following description do not exclude association with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the inventive concept. For example, even if the content described in a particular example is not described in an example different from it, the content may be understood to be associated with or combined with different examples unless otherwise mentioned in its description.

[0030] It will be understood that when an element is referred to as being "on," "over," "on," "connected to," or "coupled to" another element, it can be directly on, over, on, directly connected to, or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on," "over," "on," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Like numbers refer to like elements throughout the drawings.

[0031] For ease of description, spatially relative terms, such as "below", "below", "below", "above", "above", etc., may be used herein to describe the relationship between an element or feature and another one or more elements or features as shown in the drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawings is turned over, the elements described as being "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the term "below" can include both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptors used in this article can be interpreted accordingly.

[0032] Figure 1A and Figure 1B is a diagram illustrating an image sensor according to an exemplary embodiment.

[0033] First reference Figure 1A , the image sensor 1 according to the exemplary embodiment may include a first layer 2, a second layer 3 disposed below the first layer 2, and a third layer 4 disposed below the second layer 3. The first layer 2, the second layer 3, and the third layer 4 may be stacked in directions perpendicular to each other. In an exemplary embodiment, the first layer 2 and the second layer 3 may be stacked on each other at a wafer level, and the third layer 4 may be attached to a lower portion of the second layer 3 at a chip level. The first layer 2, the second layer 3, and the third layer 4 may be provided as a single semiconductor package.

[0034] The first layer 2 may include a sensing area SA and a first pad area PA1, a plurality of pixels PX are arranged on the sensing area SA, and the first pad area PA1 is arranged around the sensing area SA. The first pad area PA1 may include: a plurality of upper pads PAD, which may be connected to a lower pad arranged on the second pad area PA2 and a control logic circuit LC of the second layer 3 through a through hole or the like.

[0035] Each of the pixels PX may include a photodiode that receives light to generate charges and a pixel circuit that processes the charges generated by the photodiode. The pixel circuit may include a plurality of transistors that output a voltage corresponding to the charges generated by the photodiode.

[0036] The second layer 3 may include a plurality of elements providing a control logic circuit LC. The elements included in the control logic circuit LC may provide a circuit for driving the pixels provided on the first layer 2, for example, a row driver, a column driver, and a timing controller. The elements included in the control logic circuit LC may be connected to the pixel circuit through the first pad area PA1 and the second pad area PA2. The control logic circuit LC may obtain a reset voltage and a pixel voltage from a plurality of pixels PX to generate a pixel signal.

[0037] In an exemplary embodiment, at least one of the pixels PX may include a plurality of photodiodes arranged at the same level. Pixel signals generated according to the charge of each of the photodiodes may have a phase difference from each other, and the control logic circuit LC may provide an auto focus function based on the phase difference between the pixel signals generated from the photodiodes included in the single pixel PX.

[0038] The third layer 4 disposed below the second layer 3 may include a memory chip MC, a dummy chip DC, and an encapsulation layer EN encapsulating the memory chip MC and the dummy chip DC. The memory chip MC may be a dynamic random access memory (DRAM) or a static random access memory (SRAM), and the dummy chip DC may not have a function of actually storing data. The memory chip MC may be electrically connected to at least some of the elements included in the control logic circuit LC of the second layer 3 through a bump, and may store information required to provide an autofocus function. In an exemplary embodiment, the bump may be a microbump.

[0039] Next, refer to Figure 1B, the image sensor 5 according to the exemplary embodiment may include a first layer 6 and a second layer 7. The first layer 6 may include: a sensing area SA on which a plurality of pixels PX are disposed; a control logic circuit LC on which elements for driving the pixels PX are disposed; and a first pad area PA1 disposed around the control logic circuit LC. The first pad area PA1 may include: a plurality of upper pads PAD, which may be connected to a memory chip MC disposed on the second layer 7 through a through hole or the like. The second layer 7 may include a memory chip MC, a dummy chip DC, and an encapsulation layer EN encapsulating the memory chip MC and the dummy chip DC.

[0040] Figure 2 and Figure 3 is a block diagram illustrating an image sensor according to an exemplary embodiment.

[0041] First reference Figure 2 , the image sensor 10 may include a controller 20 , a pixel array 30 , and the like.

[0042] The pixel array 30 may include a plurality of pixels PX arranged in an array along a plurality of rows and a plurality of columns. Each of the pixels PX may include: a photodiode that generates a charge in response to a light signal incident from the outside; and a pixel circuit that generates an electrical signal corresponding to the charge generated by the photodiode. For example, the pixel circuit may include a floating diffuser, a storage transistor, a transfer transistor, a reset transistor, a drive transistor, a selection transistor, and the like. The configuration of the pixel PX may vary according to an exemplary embodiment. As an example, each of the pixels PX may include an organic photodiode different from a silicon photodiode, the organic photodiode including an organic material, or each of the pixels PX may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each of the pixels PX may include a comparator, a counter that converts the output of the comparator into a digital signal and outputs the digital signal, and the like.

[0043] The controller 20 may include a plurality of circuits for controlling the pixel array 30. As an example, the controller 20 may include a row driver 21, a readout circuit 22, a column driver 23, a control logic circuit 24, etc. The row driver 21 may drive the pixel array 30 in units of rows. For example, the row driver may generate a transfer control signal for controlling a transfer transistor of a pixel circuit, a reset control signal for controlling a reset transistor, a selection control signal for controlling a selection transistor, etc.

[0044] The readout circuit 22 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler may be connected to the pixels PX included in the row selected by the row selection signal through the column line, and may perform correlated double sampling to detect the reset voltage and the pixel voltage, wherein the row selection signal is provided by the row driver 21. The analog-to-digital converter may convert the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals, and may transmit the digital signals to the column driver 23.

[0045] The column driver 23 may include a latch or buffer circuit, an amplifier circuit, etc., and processes the digital signal received from the readout circuit 22, and the digital signal may be temporarily stored in the latch or buffer circuit. The row driver 21, the readout circuit 22, and the column driver 23 may be controlled by the control logic circuit 24. The control logic circuit 24 may include a timing controller for controlling the operation timing of the row driver 21, the readout circuit 22, and the column driver 23, an image signal processor for processing image data, etc.

[0046] The control logic circuit 24 may perform signal processing on the data output by the readout circuit 22 and the column driver 23 to generate image data. As an example, the image data may include a depth map. In addition, the control logic circuit 24 may use the data output by the readout circuit 22 and the column driver 23 to generate image data.

[0047] Next, refer to Figure 3 , the image sensor 40 according to an exemplary embodiment may include a pixel array 70 and a controller for driving the pixel array 70. The controller may include a row driver 50, a readout circuit 60, etc. The readout circuit 60 may include a ramp voltage generator 61, a sampling circuit 62, an analog-to-digital converter 63, etc. The data output by the analog-to-digital converter 63 may be input to the column driver.

[0048] The pixel array 70 may include a plurality of pixels PX disposed at intersections of a plurality of row lines ROW and a plurality of column lines COL. 11 To PX MN The row driver 50 can be used to control the pixel PX through the row line ROW input. 11 To PX MN As an example, the required signal is input to the pixel PX via the row line ROW 11 To PX MN The signals may include a reset control signal RG, a transfer control signal TG, a selection control signal SEL, etc. The row driver 50 may sequentially select each of the row lines ROW. The row driver 50 may select one of the row lines ROW during a predetermined horizontal period.

[0049] The sampling circuit 62 can obtain the pixel PX 11 To PXMN The reset voltage and the pixel voltage are obtained from some pixels connected to the row lines scanned by the row driver 50 in the sampling circuit 62. The sampling circuit 62 may include a plurality of samplers SA, and the samplers SA may be correlated double samplers. Each of the samplers SA may receive the ramp voltage generated by the ramp voltage generator 61 through a first input terminal, and may also receive the ramp voltage from the pixel PX through a second input terminal. 11 To PX MN Receive a reset voltage and a pixel voltage.

[0050] The image sensor 40 may be operated in a global shutter manner. In the image sensor 40 operated in a global shutter manner, the pixels PX may be 11 To PX MN The photodiodes included in the photodiode are reset simultaneously and exposed to light for a predetermined exposure time. Figure 4 to provide a description.

[0051] Figure 4 are diagrams provided to describe operations of an image sensor according to an exemplary embodiment.

[0052] Figure 4 4 is a diagram for describing the global shutter operation of the image sensor 40. Figure 4 , can be reset at time T RST The pixels PX included in the pixel array 70 are 11 To PX MN As an example, the row driver 50 can reset the photodiodes of the pixels PX by turning on the reset transistor included in the pixel circuit of each pixel. 11 To PX MN The photodiode is connected to a predetermined supply voltage to reset the photodiode.

[0053] Once the photodiode is reset, the pixel PX 11 To PX MN The photodiode included in the EX As an example, the exposure time T EX It may be determined by the operating environment of the image sensor 40 , the shutter speed, the aperture value, and the like.

[0054] When the exposure time T EX The row driver 50 may scan each of the row lines ROW when the time has elapsed. The readout circuit 60 may read the pixels PX according to the order in which the row driver 50 scans the row lines ROW. 11 To PX MN Each of the readout circuits 60 performs a readout operation. The readout circuit 60 can perform a readout operation at the readout time T RO Internal from pixel PX11 To PX MN The reset voltage and the pixel voltage are read in each of them.

[0055] In order to make the readout circuit 60 RO The reset voltage and pixel voltage can be read out during the exposure time T EX The charge generated by the photodiode is stored in the storage area of ​​the pixel circuit. In response to the transfer transistor being turned on, the charge stored in the storage area can be moved to the floating diffusion node of the pixel circuit. The readout circuit 60 can read the pixel PX before the transfer transistor is turned on (i.e., when the charge is stored in the storage area). 11 To PX MN After the transfer transistor is turned on by the row driver 50 and the charge in the storage area is moved to the floating diffusion node, the readout circuit 60 can read the pixel PX 11 To PX MN The pixel voltage.

[0056] Figure 5 is a circuit diagram illustrating a pixel included in an image sensor according to an exemplary embodiment.

[0057] refer to Figure 5 , a pixel PX according to an exemplary embodiment may include a pixel circuit PC and a photodiode PD. A signal generated by the pixel circuit PC using charges generated by the photodiode PD may be output through a column line COL.

[0058] The pixel circuit PC may include a transfer transistor TX, a reset transistor RX, a drive transistor DX, a selection transistor SX, a storage transistor STX, an intermediate transfer transistor TXX, an overflow transistor OX, etc. The overflow transistor OX may be turned on and off by an overflow control signal OG, and may be connected between a power supply node providing a power supply voltage VDD and the photodiode PD to prevent the photodiode PD from being saturated.

[0059] In an image sensor operated in a global shutter manner, the photodiode PD, the charge stored in the storage transistor STX, the floating diffusion node FD, etc. may be reset within a reset time. The photodiode PD is exposed to light within an exposure time after the reset time, and the charge generated by the photodiode PD in response to the light may be stored in the storage transistor STX.

[0060] As described above, in an image sensor operated in a global shutter mode, a readout operation can be performed in a rolling manner after the exposure time expires. As an example, in the readout operation, a reset voltage and a pixel voltage can be output sequentially. For example, the selection transistor SX is turned on so that the reset voltage can be output through the column line COL. After the reset voltage is output, the transfer transistor TX is turned on so that the charge stored in the storage transistor STX can be transferred to the floating diffusion node.

[0061] The voltage of the floating diffusion node FD may vary according to the amount of charge transferred from the storage transistor STX. The drive transistor DX operating as a source follower amplifier may output a pixel voltage corresponding to the amount of charge transferred to the floating diffusion node FD. Therefore, since the transfer efficiency of the charge moved from the storage transistor STX to the floating diffusion node FD is high when the transfer transistor TX is turned on, the performance of the image sensor may be improved.

[0062] In a general pixel circuit, due to the increase in the potential in the region adjacent to the boundary between the storage transistor STX and the transfer transistor TX when the transfer transistor TX is turned on, a potential peak (or barrier) phenomenon that hinders charge transfer may occur. In an exemplary embodiment, in a boundary region adjacent to the boundary between the storage transistor STX and the transfer transistor TX, at least one of the storage transistor STX and the transfer transistor TX may have a structure for preventing potential peaks. As an example, the structure may be formed on at least one of the active region of the storage transistor STX and the gate of the transfer transistor TX. Due to the above structure, when the transfer transistor TX is in the off state, the potential of the boundary region may have a first potential, and when the transfer transistor TX is in the on state, the potential of the boundary region may have a second potential lower than the first potential. Therefore, when the transfer transistor TX is in the on state, the performance of the image sensor can be improved by improving the transfer efficiency of the charge.

[0063] Figure 6 is a top view illustrating pixels included in an image sensor according to an exemplary embodiment.

[0064] refer to Figure 6 , the image sensor 100 according to an exemplary embodiment may include first to fourth pixels PX1 to PX4 arranged in an array form. Figure 6Only some of the plurality of pixels included in the image sensor 100 are shown, and the number of pixels included in the image sensor 100 may be modified differently according to the board shape, resolution, etc. of the image sensor. The first pixel PX1 to the fourth pixel PX4 may have structures similar to each other and may be optically separated from each other by a pixel separation film (DTI). For ease of explanation, the pixel structure will be described below by taking the first pixel PX1 as an example.

[0065] Referring to the first pixel PX1, the first pixel PX may include an active region 103, a photodiode PD, and a plurality of gates formed by doping impurities into the semiconductor substrate 101. The gates may be coupled to the active region 103 to provide a plurality of transistors included in the pixel circuit. As an example, the first pixel PX1 may include an intermediate transfer gate TXG, a storage gate STG, a transfer gate TG, a reset gate RG, an overflow gate OG, a drive gate DG, a select gate SEL, and the like.

[0066] As an example, the image sensor 100 may be operated in a global shutter mode. When the image sensor 100 starts to operate, the charges stored in the photodiodes PD and storage transistors of the first pixel PX1 to the fourth pixel PX4, and the floating diffusion node FD may be reset within the reset time. After the reset time, the photodiodes PD are simultaneously exposed to light within the exposure time, and the charges generated by the photodiodes PD may be stored in the storage transistor STX.

[0067] In the readout time after the exposure time, the readout operation of the first pixel PX1 to the fourth pixel PX4 can be performed in a rolling manner. The reset voltage and the pixel voltage of the first pixel PX1 and the second pixel PX2 that do not share the column line can be output simultaneously, while the reset voltage and the pixel voltage of the first pixel PX1 and the third pixel PX3 that share the column line may not be output simultaneously. In the readout operation of the first pixel PX1 to the fourth pixel PX4, after the reset voltage is output, the transfer transistor can be turned on by the voltage input to the transfer gate TG, and the charge stored in the storage transistor can be transferred to the floating diffusion node FD.

[0068] As described above, when the transfer transistor is turned on and charges are transferred, a problem of hindering the charge transfer may occur due to an increase in potential around the boundary between the storage transistor and the transfer transistor. Figure 6 In an exemplary embodiment, the transfer gate TG may include a first gate region 110 and a second gate region 120, and the first gate region 110 may protrude toward the memory transistor. The first gate region 110 may be disposed on at least a portion of the active region 103 of the memory transistor. In an exemplary embodiment, the memory gate STG may provide a space for accommodating the first gate region 110.

[0069] Through the first gate region 110, when the transfer transistor is turned on, the potential at the boundary between the transfer transistor and the storage transistor may not increase. As an example, when the transistors included in the first pixel PX1 to the fourth pixel PX4 are N-channel metal oxide semiconductor (NMOS) transistors, the transfer transistor can be turned on by applying a high voltage to the transfer gate TG. In this case, by applying a high voltage to the first gate region 110, the potential at the boundary region adjacent to the boundary between the storage transistor and the transfer transistor is reduced, so that the charge can be smoothly transferred to the floating diffusion node FD.

[0070] In addition, by making the first gate region 110 narrower than the second gate region 120, when the transfer transistor is turned on, the potential can be controlled to be inclined only to the floating diffusion node FD in the boundary region. Therefore, reverse transfer of charges from the floating diffusion node FD to the storage transistor can be prevented.

[0071] Fig. 7A and Figure 7B is shown along Figure 6 The illustrated cross-sectional view of the image sensor 100 is taken along a direction II′.

[0072] First reference Fig. 7A , the first pixel PX1 of the image sensor 100 may include a semiconductor substrate 101, a microlens 130, an optical insulating layer 140, and a plurality of transistors. The optical insulating layer 140 may include a color filter, a planarization layer, and the like.

[0073] A pixel separation film DT1, an active region 103 for providing a transistor, and the like may be formed on a semiconductor substrate 101. At least a portion of the active region 103 may be provided as a floating diffusion node FD. Fig. 7A , the first gate region 110 of the transfer gate TG may be disposed on the active region 103 of the memory transistor together with the memory gate STG. That is, the first gate region 110 of the transfer gate TG may overlap at least a portion of the active region of the memory transistor.

[0074] Next, refer to Figure 7B , the first pixel PX1 may further include a barrier layer 105 disposed below the active region 103 of the storage transistor. The barrier layer 105 may be doped with impurities having a conductivity different from that of the main charge carriers of the image sensor 100. As an example, when the photodiode of the image sensor 100 uses electrons generated in response to light as the main charge carriers and the transistor is an NMOS transistor, the barrier layer 105 may be doped with p-type impurities. The barrier layer 105 may prevent the charge stored in the storage transistor from leaking.

[0075] Figure 8 and Fig. 9 are diagrams provided to describe operations of an image sensor according to an exemplary embodiment.

[0076] refer to Figure 8 and Fig. 9 , showing changes in the potentials of the storage transistor, the transfer transistor, and the floating diffusion node FD according to the on / off operation of the transfer transistor. Figure 8 , since the charge is stored in the storage transistor, the potential at the lower portion of the storage gate STG may be relatively low. Figure 6 , Fig. 7A and Figure 7B As described, the transfer gate TG may have the first gate region 110 and the second gate region 120, and when an off voltage is input to the transfer gate TG, a potential at a lower portion of the transfer gate TG maintains a high state so that charges may not be transferred to the floating diffusion node FD.

[0077] When the turn-on voltage is input to the transfer gate TG to turn on the transfer transistor, the potential at the lower portion of the transfer gate TG decreases so that the charge stored in the storage transistor can be transferred to the floating diffusion node FD. By inputting the turn-on voltage to the first gate region 110 overlapping at least a portion of the active region of the storage transistor, the potential at the lower portion of the first gate region 110 can be reduced. Therefore, as Figure 8 As shown, the potential may be gradually reduced at the lower portion of the first gate region 110 corresponding to the boundary region adjacent to the boundary between the storage transistor and the transfer transistor. The potential may be reduced in a direction away from the storage transistor and closer to the floating diffusion node FD.

[0078] In an exemplary embodiment, the potential of the boundary region corresponding to the lower portion of the first gate region 110 may have a first potential when an off voltage is input to the transfer gate TG, and may have a second potential lower than the first potential when an on voltage is input to the transfer gate TG. When the on voltage is input to the transfer gate TG, the charge stored in the storage transistor may be smoothly transferred to the floating diffusion FD. Therefore, the performance of the image sensor may be improved without increasing the area of ​​the storage transistor.

[0079] Fig. 9 1 is a diagram showing a change in potential when the first gate region 110 is not formed (ie, when the transfer gate TG includes only the second gate region 120). Fig. 9Since the first gate region 110 is omitted, a potential peak section where the potential increases may appear in the boundary region adjacent to the boundary between the storage transistor and the transfer transistor. Therefore, even if the transfer transistor TG is turned on, the charge stored in the storage transistor may not be transferred to the floating diffusion node FD.

[0080] As reference Figure 8 As described, in an exemplary embodiment, the potential peak section can be removed by forming the first gate region 110 in the transfer gate TG protruding toward the storage transistor. By inputting the turn-on voltage to the first gate region 110, the potential of the portion of the active region of the storage transistor adjacent to the transfer transistor can be reduced, and thus the potential peak section can be removed.

[0081] Fig.10 is a top plan view illustrating pixels included in an image sensor according to an exemplary embodiment.

[0082] refer to Fig.10 , the image sensor 200 according to the exemplary embodiment may include first to fourth pixels PX1 to PX4 arranged in an array form. Figure 6 similar, Fig.10 Only some of the plurality of pixels included in the image sensor 200 are shown, and the number of pixels included in the image sensor 200 may be variously modified according to the board shape, resolution, etc. of the image sensor. Figure 6 The image sensor 100 has similar contents.

[0083] The charge generated by the photodiode of each of the first to fourth pixels PX1 to PX4 of the image sensor 200 may be stored in the storage transistor and may be transferred to the floating diffusion node FD in response to the on-operation of the transfer transistor. In order to prevent the potential peak section generated between the storage transistor and the transfer transistor from hindering the transfer of the charge, the active region of the storage transistor may include a first impurity region 204 having a relatively high impurity concentration. Fig.10 As shown, the first impurity region 204 may be adjacent to the transfer transistor.

[0084] Fig.11A and Fig. 11B is shown along Fig.10 The illustrated cross-sectional view of the image sensor 200 is taken along the direction II-II′.

[0085] First reference Fig.11A, the first pixel PX1 of the image sensor 200 may include a semiconductor substrate 201, a microlens 230, an optical insulating layer 240, etc., and a pixel separation film DTI and an active region 203 may be formed on the semiconductor substrate 201. The active region 203 providing a storage transistor together with a storage gate STG may include a first impurity region 204 and a second impurity region 205, and the impurity concentration of the second impurity region 205 is lower than the impurity concentration of the first impurity region 204. The first impurity region 204 may be disposed closer to the transfer gate TG than the second impurity region 205.

[0086] As an example, when electrons are the main charge carriers and the transistor included in the pixel circuit is an NMOS transistor, the potential peak section may not appear due to the relatively high impurity concentration of the first impurity region 204. Therefore, when the turn-on voltage is input to the transfer gate TG, the charge stored in the storage transistor can be smoothly transferred to the floating diffusion node FD.

[0087] Next, refer to Fig. 11B , the first pixel PX1 of the image sensor 200 may further include a barrier layer 207 disposed below the active region 203 of the storage transistor. The barrier layer 207 may be doped with impurities having a conductivity different from that of the main charge carriers of the image sensor 100. As an example, when the transistor included in the pixel circuit of the image sensor 200 is an NMOS transistor, the barrier layer 207 may be doped with p-type impurities to prevent the charge stored in the storage transistor from leaking.

[0088] Fig.12 is a top view showing a pixel included in an image sensor according to an exemplary embodiment. In addition, Fig.13 is shown along Fig.12 The image sensor shown is a cross-sectional view of a section taken along direction III-III'.

[0089] refer to Fig.12 and Fig.13 , the pixel PX of the image sensor 300 can be optically separated from other pixels by the pixel separation film DTI. The pixel PX may include a semiconductor substrate 301, a microlens 330, an optical insulation layer 340, etc., and an active region 303 for providing a plurality of transistors may be formed on the semiconductor substrate 301. A plurality of gates STG, TXG, TG, RG, OG, DG, and SEL may be formed of a conductive material together with the active region 303 to provide a plurality of transistors. The transistor may convert the charge generated by the photodiode PD in response to light into an electrical signal.

[0090] exist Fig.12 and Fig.13In the illustrated exemplary embodiment, the transfer gate TG may include a first gate region 310 and a second gate region 320. The first gate region 310 may be a region extending from the second gate region 320 and protruding toward the storage gate STG, and may have a width narrower than that of the second gate region 320.

[0091] In addition, Fig.12 and Fig.13 In the exemplary embodiment shown, the active region providing the memory transistor may include a first impurity region 304 and a second impurity region 305, the second impurity region 305 being defined as a remaining region other than the first impurity region 304. The impurity concentration of the first impurity region 304 may be higher than the impurity concentration of the second impurity region 305, and the first impurity region 304 may be adjacent to the transfer gate TG. As an example, the first impurity region 304 may have a Fig.12 The shape of the first gate region 310 shown corresponds to that of the first gate region 310 and may surround the first gate region 310 in a plane.

[0092] The first impurity region 304 may not overlap with the transfer gate TG including the first gate region 310. Fig.13 As shown, the first impurity regions 304 may be disposed between the second impurity regions 305 in at least one direction.

[0093] Fig.14 is a top view showing a pixel included in an image sensor according to an exemplary embodiment, Fig.15 is shown along Fig.14 The image sensor shown is a cross-sectional view of a section taken along direction IV-IV'.

[0094] refer to Fig.14 and Fig.15 , the pixel PX of the image sensor 300A may be surrounded by a pixel separation film DTI and may be optically and electrically separated from other pixels. The pixel PX may include a semiconductor substrate 301 on which an active region 303 is formed, a microlens 330, an optical insulating layer 340, etc., and a plurality of transistors implementing a pixel circuit may be provided by a plurality of gates STG, TXG, TG, RG, OG, DG, and SEL formed on the semiconductor substrate 301.

[0095] exist Fig.14 and Fig.15In the exemplary embodiment shown, the transfer gate TG may include a first gate region 310 and a second gate region 320. In addition, the active region 303A of the memory transistor may include a first impurity region 304A and a second impurity region 305A. The first gate region 310 may be a region protruding toward the memory transistor, and the impurity concentration of the first impurity region 304A may be higher than the impurity concentration of the second impurity region 305A.

[0096] At least a portion of the first impurity region 304A may be disposed below the transfer gate TG. In the active region 303A of the memory transistor, the first impurity region 304A may not be surrounded by the second impurity region 305A. Fig.14 and Fig.15 In the illustrated exemplary embodiment, the first impurity region 304A may be disposed closer to the transfer gate TG than the second impurity region 305A.

[0097] Fig.16 and Fig.17 is a top view illustrating pixels included in an image sensor according to an exemplary embodiment.

[0098] First reference Fig.16 , a pixel PX of the image sensor 400 may be optically and electrically separated from other pixels by a pixel separation film DTI, and may include an active region 403, a photodiode PD formed on the active region 403 of a semiconductor substrate 401, and a plurality of gates STG, TXG, TG, RG, OG, DG, and SEL disposed on the semiconductor substrate 401. The active region 403 and the gates STG, TXG, TG, RG, OG, DG, and SEL may process charges in the photodiode PD to implement a pixel circuit that generates an electrical signal.

[0099] exist Fig.16 In the exemplary embodiment shown, regions 404, 405, and 406 having relatively high impurity concentrations may be formed under the storage gate STG, the intermediate transfer gate TXG, and the overflow gate OC, respectively. First, a first impurity region 404 having a relatively high impurity concentration and a second impurity region as a remaining active region 403 other than the first impurity region 404 may be disposed under the storage gate STG.

[0100] As an example, the active region under the intermediate transfer gate TXG may have a third impurity region 405 and a fourth impurity region, wherein the third impurity region 405 has a relatively high impurity concentration and is adjacent to the storage gate STG, and the fourth impurity region is the remaining active region 403 except the third impurity region 405. In addition, the active region under the overflow gate OG may have a fifth impurity region 406 and a sixth impurity region, wherein the fifth impurity region 406 has a relatively high impurity concentration and is disposed away from the photodiode PD, and the sixth impurity region is the remaining active region 403 except the fifth impurity region 406.

[0101] The first impurity region 403, the third impurity region 404, and the fifth impurity region 405 may be set in consideration of the transfer direction of the charge. As an example, the charge generated by the photodiode PD may pass through the intermediate transfer gate TXG and may be stored in the storage transistor including the storage gate STG. In addition, when the turn-on voltage is input to the transfer gate TG, the charge may be transferred to the floating diffusion node FD. Therefore, according to the transfer direction of the charge, the third impurity region 405 under the intermediate transfer gate TXG may be adjacent to the storage gate STG, and the first impurity region 404 under the storage gate STG may be adjacent to the transfer gate TG. The charge generated by the photodiode PD may be smoothly transferred to the floating diffusion node FD through the third impurity region 405 under the intermediate transfer gate TXG and the first impurity region 404 under the storage gate STG.

[0102] The fifth impurity region 406 formed under the overflow gate OG can prevent reverse transfer of charges. When the turn-on voltage is input to the overflow gate OG, the charge of the photodiode PD can be removed by the power supply voltage. Fig.16 In the exemplary embodiment shown, the fifth impurity region 406 under the overflow gate OG can significantly reduce the reverse transfer of charge back to the photodiode PD when the turn-on voltage is input to the overflow gate OG, and quickly remove the charge of the photodiode PD, thereby preventing the photodiode PD from saturation.

[0103] Next, refer to Fig.17 In the pixel PX of the image sensor 400A, the transfer gate TG may include a first gate region 410 and a second gate region 420. The first gate region 410 may be a region extending from the second gate region 420 and protruding toward the storage gate STG, and may be accommodated in a space provided in the storage gate ST6. Fig.17 In the exemplary embodiment shown, the first gate region 410 may be formed to prevent a potential peak from occurring between the memory transistor and the transfer transistor.

[0104] refer to Fig.17, the pixel PX of the image sensor 400A may have a third impurity region 405 and a fifth impurity region 406, which each have a relatively high impurity concentration and are formed on the active regions of the intermediate transfer transistor and the overflow transistor, respectively. Fig.16 Unlike the exemplary embodiment shown in FIG. 1 , the first impurity region 404 may not be formed on the active region of the memory transistor. However, according to the exemplary embodiment, as described above with reference to FIG. Fig.12 and Fig.14 As described, the first impurity region 404 may also be added to the active region of the memory transistor.

[0105] Fig.18 is a diagram illustrating an imaging apparatus including an image sensor according to an exemplary embodiment.

[0106] refer to Fig.18 , an imaging device 500 according to an exemplary embodiment may include a light source 501 and a sensor unit 502. The light source 501 may include a light emitting element that outputs a light signal having a specific wavelength band. As an example, the light source 501 may include a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), etc. as a light emitting element. The light source 501 may include a plurality of light emitting elements arranged in an array, and an optical element may also be provided on a processing path of the light signal output by the light emitting element. The light signal output by the light source 501 may be a light signal having an infrared band.

[0107] The light signal output by the light source 501 may be reflected by the object 510, and the sensor unit 502 may be input with the light signal reflected by the object 510 as a received light signal. The sensor unit 502 may include: a pixel array having pixels that generate electrical signals in response to the received light signals; a controller that generates an image using the electrical signals generated by the pixel array, etc. As an example, the image generated by the controller may be a depth map including distance information of the object 510 and the environment around the object 510.

[0108] In an exemplary embodiment, the sensor unit 502 may provide a proximity sensing function for sensing the presence of an object 510 near the imaging device 500, a distance measurement function for calculating the distance between the object 510 and the imaging device 500, and a function for generating a depth map. Since the sensor unit 502 accurately detects a received light signal output by the light source 501 and reflected by the object 510, the above functions may be implemented more accurately. Therefore, in order to increase the sensitivity of the sensor unit 502, the area of ​​the photodiode included in each pixel may be increased.

[0109] Fig.19is a block diagram illustrating an imaging apparatus including an image sensor according to an exemplary embodiment.

[0110] refer to Fig.19 , the imaging device 600 may include a pixel array 610, a controller 620, a light source driver 630, a light source 640, and the like.

[0111] The pixel array 610 may include a plurality of pixels PX arranged in an array along a plurality of rows and a plurality of columns. Each of the pixels PX may include: a photodiode that generates a charge in response to a light signal incident from an object 650; and a pixel circuit that generates an electrical signal corresponding to the charge generated by the photodiode. As an example, the pixel circuit may include a floating diffusion node, an intermediate transfer transistor, a storage transistor, a transfer transistor, a reset transistor, a drive transistor, a selection transistor, and the like. The configuration of the pixel PX may vary according to an exemplary embodiment. As an example, each of the pixels PX may include an organic photodiode different from a silicon photodiode, the organic photodiode including an organic material, or each of the pixels PX may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each of the pixels PX may include a comparator, a counter that converts the output of the comparator into a digital signal and outputs the digital signal, and the like.

[0112] The controller 620 may include a plurality of circuits for controlling the pixel array 610. As an example, the controller 620 may include a row driver 621, a readout circuit 622, a column driver 623, a control logic circuit 624, etc. The row driver 621 may drive the pixel array 610 in units of rows. For example, the row driver 621 may generate a transfer control signal for controlling a transfer transistor of a pixel circuit, a reset control signal for controlling a reset transistor, a selection control signal for controlling a selection transistor, etc.

[0113] The readout circuit 622 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler may be connected to the pixels PX included in the row selected by the row selection signal through the column line, and may perform correlated double sampling to detect the reset voltage and the pixel voltage, wherein the row selection signal is supplied by the row driver 621. The analog-to-digital converter may convert the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals, and may transmit the digital signals to the column driver 623.

[0114] The column driver 623 may include a latch or a buffer circuit, an amplifying circuit, etc., and processes a digital signal received from the readout circuit 622, and the latch or the buffer circuit may temporarily store the digital signal. The row driver 621, the readout circuit 622, and the column driver 623 may be controlled by the control logic circuit 624. The control logic circuit 624 may include a timing controller for controlling the operation timing of the row driver 621, the readout circuit 622, and the column driver 623, an image signal processor for processing image data, etc.

[0115] The control logic circuit 624 may perform signal processing on the data output by the readout circuit 622 and the column driver 623 to generate image data. As an example, the image data may include a depth map. In addition, the control logic circuit 624 may calculate the distance between the object 650 and the imaging device 600 or identify the object 650 near the imaging device 600 by using the data output by the readout circuit 622 and the column driver 623 according to the operation mode of the imaging device 600.

[0116] The imaging device 600 may include a light source 640 that outputs a light signal to an object 650 to generate a depth map. The light source 640 may include one or more light emitting elements, and as an example, a plurality of semiconductor light emitting elements may include semiconductor chips arranged in an array. The light source 640 may be operated by a light source driver 630. The light source driver 630 may be controlled by a controller 620.

[0117] In an exemplary embodiment, the light source driver 630 may generate a predetermined pulse signal to drive the light source 640. The light source driver 630 may determine a period, a duty cycle, a duration, etc. of the pulse signal in response to a control command of the controller 620. As an example, the controller 620 may synchronize at least one of the signals input to the pixel array 610 with the pulse signal input to the light source 640. In an exemplary embodiment, the signal synchronized with the pulse signal input to the light source 640 may be at least one of the signals input to the pixel array 610 by the row driver 621.

[0118] Fig. 20 is a circuit diagram illustrating a pixel circuit of a pixel included in an image sensor according to an exemplary embodiment.

[0119] refer to Fig. 20 In the pixel PX of the image sensor according to the exemplary embodiment, a plurality of pixel circuits PCA, PCB, PCC, and PCD may be connected to a single photodiode PD. Fig. 20In the illustrated exemplary embodiment, the first pixel circuit PCA, the second pixel circuit PCB, the third pixel circuit PCC, and the fourth pixel circuit PCD are shown to be connected to the photodiode PD, but the number of pixel circuits may be changed according to the exemplary embodiment. The first pixel circuit PCA, the second pixel circuit PCB, the third pixel circuit PCC, and the fourth pixel circuit PCD may have substantially the same structure as each other.

[0120] Fig. 20 The image sensor according to the exemplary embodiment shown in FIG. 1 may be a time-of-flight (ToF) sensor that detects a light signal emitted from a separate light source and reflected from an object to determine the shape of the object, the distance to the object, etc. The light signal emitted from the light source may be reflected from the object to generate a phase difference, and the image sensor may determine the shape of the object, the distance to the object, etc. by using the phase difference. As an example, the image sensor may generate a depth map including the shape of the object, the distance to the object, etc. by using information obtained from the separate pixels PX.

[0121] The image sensor applied as a ToF sensor can be operated in a global shutter mode. When the photodiode is exposed to light, the first intermediate transfer transistor TXXA, the second intermediate transfer transistor TXXB, the third intermediate transfer transistor TXXC and the fourth intermediate transfer transistor TXXD included in the first pixel circuit PCA, the second pixel circuit PCB, the third pixel circuit PCC and the fourth pixel circuit PCD can be operated with different phases from each other. As an example, the first intermediate transfer transistor TXXA can be turned on and off with the same phase as the light signal, and the second intermediate transfer transistor TXXB can be turned on and off with a 180-degree phase difference from the light signal. The third intermediate transfer transistor TXXC can be turned on and off with a 90-degree phase difference from the light signal, and the fourth intermediate transfer transistor TXXD can be turned on and off with a 270-degree phase difference from the light signal.

[0122] The image sensor can generate a depth map by using a pixel voltage obtained from the charge stored in the first storage transistor STXA, the second storage transistor STXB, the third storage transistor STXC, and the fourth storage transistor STXD operated according to the above-mentioned phase difference. In the readout operation, the first data corresponding to the charge stored in the first storage transistor STXA can be output through the first column line COL1, and the third data corresponding to the charge in the third storage transistor STXC can be output through the third column line COL3. In addition, the second data corresponding to the charge stored in the second storage transistor STXB can be output through the second column line COL2, and the fourth data corresponding to the charge in the fourth storage transistor STXD can be output through the fourth column line COL4. At the same time, according to an exemplary embodiment, the first pixel circuit PCA and the third pixel circuit PCC can be connected to a single column line, and the second pixel circuit PCB and the fourth pixel circuit PCD can also be connected to a single column line.

[0123] Figure 21 to Figure 23 is a top view illustrating pixels included in an image sensor according to an exemplary embodiment.

[0124] As an example, in Figure 21 to Figure 23 The pixel 700 shown in FIG. 1 may be compared to the pixel 700 shown in FIG. Fig. 20 The pixel PX described above corresponds to the pixel PX described above. Fig.21 , the pixel 700 can be optically and electrically separated from other pixels PX by a pixel separation film DTI formed on the semiconductor substrate 701. In addition, the pixel 700 may include a photodiode PD, and a first photogate PGA, a second photogate PGB, a third photogate PGC, and a fourth photogate PGD may be disposed on the photodiode PD. An active region 703 for providing a plurality of transistors may be formed on the semiconductor substrate 701.

[0125] A first photogate PGA, a second photogate PGB, a third photogate PGC, and a fourth photogate PGD may be provided for connecting the photodiode PD to the first to fourth pixel circuits. As an example, when a turn-on voltage is input to the first intermediate transfer gate TXGA and the first storage gate STGA, the charge generated by the photodiode PD may be stored in the first storage transistor. When a turn-on voltage is input to the first intermediate transfer gate TXGA and the first storage gate STGA, an off voltage may be input to the second intermediate transfer gate TXGB, the third intermediate transfer gate TXGC, and the fourth intermediate transfer gate TXGD and the second storage gate STGB, the third storage gate STGC, and the fourth storage gate STGD.

[0126] exist Fig.21In the exemplary embodiment shown, the first transfer gate TGA may have a protruding area extending toward the first storage gate STGA. The first storage gate STGA may provide a space for accommodating the protruding area of ​​the first transfer gate TGA. The second transfer gate TGB, the third transfer gate TGC, and the fourth transfer gate TGD and the second storage gate STGB, the third storage gate STGC, and the fourth storage gate STGD may have shapes similar to the first transfer gate TGA and the first storage gate STGA, respectively.

[0127] Similar to the above-described exemplary embodiment, a protruding region overlapping at least a portion of the active region 703 of the first storage transistor may be formed in the first transfer gate TGA to prevent a potential peak from occurring when a turn-on voltage is input to the first transfer gate TGA. Therefore, when a turn-on voltage is input to the first transfer gate TGA, charges generated by the photodiode PD and stored in the first storage transistor may be smoothly transferred to the floating diffusion node FD.

[0128] Next, we will refer to Fig. 22 and Fig.23 The structure and operation of the pixels 700A and 700B included in the image sensor according to the exemplary embodiment are described. For convenience of explanation, the structure and operation of the pixels 700A and 700B according to the exemplary embodiment are omitted. Fig.21 The depiction of pixel 700 of the exemplary embodiment shown overlaps the depiction.

[0129] First reference Fig. 22 , the first transfer gate TGA, the second transfer gate TGB, the third transfer gate TGC, and the fourth transfer gate TGD included in the pixel 700A may not include a protruding area. The first pixel circuit will be described as an example. The first impurity region 704 having a relatively high impurity concentration may be formed in a portion of the active region of the first storage transistor adjacent to the first transfer gate TGA. By forming the first impurity region 704, a potential peak at the boundary between the first storage transistor and the first transfer transistor may be prevented, and the transfer efficiency of the charge may be improved. The first impurity region 704 may also be formed on the active regions of the second to fourth storage transistors.

[0130] Next, first refer to Fig.23, the first transfer gate TGA, the second transfer gate TGB, the third transfer gate TGC, and the fourth transfer gate TGD included in the pixel 700B may include a protruding region. In addition, a portion of the active region of the first to fourth storage transistors may be additionally doped with impurities to form a first impurity region 705. Considering the transfer direction of the charge, the first impurity region 705 may be formed to be adjacent to the protruding region of the first transfer gate TGA, the second transfer gate TGB, the third transfer gate TGC, and the fourth transfer gate TGD. Therefore, when the turn-on voltage is input to each of the first transfer gate TGA, the second transfer gate TGB, the third transfer gate TGC, and the fourth transfer gate TGD, the occurrence of a potential peak may be prevented, and the transfer efficiency of the charge may be improved.

[0131] Fig.24 is a block diagram illustrating an electronic device including an image sensor according to an exemplary embodiment.

[0132] according to Fig.24 The electronic device 1000 of the exemplary embodiment shown in FIG. 1 may include a display 1010, an image sensor 1020, a processor 1040, a port 1050, etc. In addition, the electronic device 1000 may further include a wired / wireless communication device, a power supply device, etc. Fig.24 Among the components shown, port 1050 may be a device through which electronic device 1000 communicates with a video card, sound card, memory card, USB device, etc. Electronic device 1000 may be a concept including a general-purpose desktop or laptop computer as well as a smart phone, tablet PC, and smart wearable device.

[0133] The processor 1040 may perform specific operations, instructions, tasks, etc. The processor 1040 may be a central processing unit (CPU), a microprocessor unit (MCU), a system on a chip (SoC), etc., and may communicate with other devices connected to the port 1050 and the display 1010, the sensor unit 1020, and the memory 1030 through the bus 1060.

[0134] The memory 1030 may be a storage medium for storing data required for the operation of the electronic device 1000, multimedia data, etc. The memory 1030 may include a volatile memory such as a random access memory (RAM), or a non-volatile memory such as a flash memory. In addition, the memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. The image sensor 1020 may be used as shown in FIG. Fig.23 The various exemplary embodiments are described in the form of being used in the electronic device 1000 .

[0135] As described above, according to an exemplary embodiment, at least a portion of the gate of the transfer transistor may protrude toward the gate of the storage transistor, or some regions adjacent to the transfer transistor in the active region of the storage transistor may have a relatively high impurity concentration relative to other regions. Therefore, when the transfer transistor is turned on, the potential between the storage transistor and the transfer transistor may gradually decrease as it is closer to the transfer transistor, and the charge transfer efficiency may be improved to improve the performance of the image sensor.

[0136] Various advantages and effects of the present inventive concept are not limited to the above description and can be more easily understood in the description of the exemplary embodiments.

[0137] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims.

Claims

1. An image sensor comprising a plurality of pixels, at least one of the plurality of pixels comprising: a photodiode configured to generate charge in response to light; as well as A pixel circuit comprising: a storage transistor configured to store charges generated by the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein when the transfer transistor is in an off state, the potential of the boundary region between the storage transistor and the transfer transistor has a first potential, and when the transfer transistor is in an on state, the potential of the boundary region between the storage transistor and the transfer transistor has a second potential lower than the first potential, and Wherein, the active region of the storage transistor includes: a first impurity region adjacent to a gate of the transfer transistor, and a second impurity region having an impurity concentration lower than that of the first impurity region, and The first impurity region is disposed on the boundary region.

2. The image sensor according to claim 1, wherein: The gate of the transfer transistor includes a first gate region protruding toward the storage transistor and a second gate region connected to the first gate region, and Wherein, the first gate region is arranged on the boundary region.

3. The image sensor according to claim 2, wherein: The first gate region of the transfer transistor is disposed on at least a portion of an active region of the memory transistor.

4. The image sensor according to claim 2, wherein: In the transfer transistor, a width of the first gate region is smaller than a width of the second gate region.

5. The image sensor according to claim 2, wherein: The gate of the storage transistor provides a space to accommodate the first gate region of the transfer transistor.

6. The image sensor according to claim 5, wherein: The first impurity region is adjacent to the first gate region.

7. The image sensor according to claim 6, wherein: In the memory transistor, the first impurity region is surrounded by the second impurity region.

8. The image sensor according to claim 6, wherein: At least a portion of the first impurity region of the memory transistor is disposed below the first gate region of the transfer transistor.

9. The image sensor according to claim 1, wherein: In the memory transistor, an area of ​​the first impurity region is smaller than an area of ​​the second impurity region.

10. The image sensor according to claim 1, wherein: The pixel circuit also includes an intermediate transfer transistor connected between the photodiode and the storage transistor, and The active region of the intermediate transfer transistor includes a third impurity region and a fourth impurity region, the third impurity region is adjacent to the storage transistor, and the impurity concentration of the fourth impurity region is lower than the impurity concentration of the third impurity region.

11. The image sensor according to claim 1, wherein: The pixel circuit further includes an overflow transistor connected between the photodiode and a first power supply node, and The active region of the overflow transistor includes a fifth impurity region and a sixth impurity region, the fifth impurity region is adjacent to the first power supply node, and the impurity concentration of the sixth impurity region is lower than the impurity concentration of the fifth impurity region.

12. The image sensor according to claim 1, wherein: Each of the plurality of pixels includes the pixel circuit, the pixel circuit including the storage transistor and the transfer transistor, and Wherein, the multiple pixels share the photodiode.

13. The image sensor according to claim 12, wherein: At least one of the plurality of pixels includes a transfer gate including a first gate region protruding toward the memory transistor and a second gate region connected to the first gate region.

14. The image sensor according to claim 12, wherein: At least one of the plurality of pixels includes a first impurity region and a second impurity region, the first impurity region being adjacent to the transfer transistor and the second impurity region having an impurity concentration lower than that of the first impurity region.

15. The image sensor according to claim 1, further comprising: A barrier layer is disposed below the active region of the storage transistor.

16. An image sensor comprising a plurality of pixels, at least one of the plurality of pixels comprising: a photodiode configured to generate charge in response to light; as well as The pixel circuit includes: a storage transistor connected to the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node. Wherein, in the pixel circuit, when the transfer transistor is turned on, the potential between the transfer transistor and the storage transistor gradually decreases in a direction away from the storage transistor, wherein the gate of the storage transistor includes a recess, and The gate of the transfer transistor includes a convex portion corresponding to the concave portion.

17. The image sensor according to claim 16, wherein: When the transfer transistor is turned on, the potential gradually decreases below the concave portion and the convex portion in a direction away from the memory transistor.

18. An image sensor comprising a plurality of pixels, at least one of the plurality of pixels comprising: a photodiode configured to generate charge in response to light; as well as A pixel circuit comprising: a storage transistor configured to store charges generated by the photodiode; and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein at least one of the plurality of pixels comprises a transfer gate, the transfer gate comprising a first gate region protruding toward the storage transistor and a second gate region connected to the first gate region, wherein at least one of the plurality of pixels comprises a first impurity region and a second impurity region, the first impurity region is adjacent to the transfer transistor, the impurity concentration of the second impurity region is lower than the impurity concentration of the first impurity region, and The second impurity region and the first impurity region are sequentially arranged according to a transfer direction of the charges.

Images