Semiconductor device

Abstract

A semiconductor device includes a lower semiconductor substrate, an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite the first surface, an upper gate structure on the first surface of the upper semiconductor substrate, a first interlayer insulating film covering the upper gate structure, wherein the first interlayer insulating film is between the lower semiconductor substrate and the upper semiconductor substrate, and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0027488, filed on March 11, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to semiconductor devices and methods for manufacturing the same. More specifically, this invention relates to three-dimensional stacked semiconductor devices and methods for manufacturing the same. Background Technology

[0004] As an example of a miniaturization technique used to increase the density of semiconductor devices, a multi-gate transistor with a multi-channel active pattern (or silicon body) in the form of fins or nanowires is formed on a substrate, and a gate is formed on the surface of the multi-channel active pattern.

[0005] To further increase the density of semiconductor devices, techniques for stacking semiconductor devices in three dimensions through wafer bonding can be employed. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure located on the first surface of the upper semiconductor substrate; a first interlayer insulating film covering the upper gate structure, wherein the first interlayer insulating film is located between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is located on a side surface of the upper gate structure, wherein the upper contact includes a first portion and a second portion, the first portion penetrating the upper semiconductor substrate, the second portion having a side surface adjacent to the side surface of the upper gate structure, and the width of the first portion decreasing toward the second surface.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a lower semiconductor substrate; a lower gate structure located on a surface of the lower semiconductor substrate; a lower interlayer insulating film located on the lower semiconductor substrate, wherein the lower interlayer insulating film covers the lower gate structure; an upper semiconductor substrate overlapping the lower interlayer insulating film, wherein the upper semiconductor substrate includes a first surface and a second surface opposite to the first surface; an upper gate structure located on the first surface of the upper semiconductor substrate; an upper interlayer insulating film located on the upper semiconductor substrate, wherein the upper interlayer insulating film covers the upper gate structure; and an upper contact located on a side surface of the upper gate structure, wherein the upper contact penetrates the upper semiconductor substrate and the upper interlayer insulating film, wherein the width of the upper contact at the same horizontal height as the second surface is less than the width of the upper contact at the same horizontal height as the first surface, and at least a portion of the side surface of the upper contact contacts the side surface of the upper gate structure.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a lower semiconductor substrate; a conductive pad located on the lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, wherein the upper semiconductor substrate includes a first surface and a second surface opposite to the first surface; an upper gate structure located on the first surface of the upper semiconductor substrate, wherein the upper gate structure includes an upper gate electrode and insulating structures located on a side surface and a bottom surface of the upper gate electrode; an upper interlayer insulating film located between the first surface of the upper semiconductor substrate and the conductive pad; and an upper contact penetrating the upper semiconductor substrate and the upper interlayer insulating film and connected to the conductive pad, wherein the upper contact is located on a side surface of the upper gate structure, wherein the side surface of the insulating structure includes a first recess adjacent to the bottom surface of the insulating structure, and a first portion of the upper contact is disposed in the first recess.

[0009] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a lower interlayer insulating film on a lower semiconductor substrate; forming an upper gate structure on a first surface of an upper semiconductor substrate; forming an upper interlayer insulating film on the upper semiconductor substrate, wherein the upper interlayer insulating film covers the upper gate structure; forming a contact hole penetrating the upper interlayer insulating film and the upper semiconductor substrate using a self-aligned contact (SAC) process; forming a dummy contact in the contact hole; bonding the lower interlayer insulating film and the upper interlayer insulating film; and replacing the dummy contact to form an upper contact connected to the lower semiconductor substrate.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate overlapping the first semiconductor substrate, the second semiconductor substrate including a first surface and a second surface opposite to the first surface; a gate structure located on the first surface of the second semiconductor substrate; an interlayer insulating film overlapping the gate structure, wherein the interlayer insulating film is located between the first semiconductor substrate and the second semiconductor substrate; and a contact connected to the first semiconductor substrate, wherein the contact includes a first portion and a second portion, the first portion passing through the second semiconductor substrate, and the second portion having a protrusion disposed in a recess on one side of the gate structure. Attached Figure Description

[0011] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0013] Figure 2 yes Figure 1 A magnified view of region R1.

[0014] Figure 3 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0015] Figure 4 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0016] Figure 5 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0017] Figure 6 yes Figure 5 A magnified view of region R2.

[0018] Figure 7 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0019] Figure 8 yes Figure 7 A magnified view of region R3.

[0020] Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 These are various cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention.

[0021] Figure 14 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0022] Figure 15 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0023] Figure 16 This is a layout diagram illustrating an exemplary semiconductor device according to a concept of the present invention.

[0024] Figure 17 It is along Figure 16 The cross-sectional view taken from line AA.

[0025] Figure 18 It is along Figure 16 The cross-sectional view of line BB.

[0026] Figure 19 It is along Figure 16 The cross-sectional view taken from line CC.

[0027] Figure 20 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention.

[0028] Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0029] Figure 27 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0030] Figure 28 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0031] Figure 29 , Figure 30 and Figure 31 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0032] In the following text, reference will be made to Figures 1 to 20 A semiconductor device is described according to an exemplary embodiment of the concept of the present invention.

[0033] The accompanying drawings of a semiconductor device according to an exemplary embodiment of the present invention (e.g., Figure 1 In this invention, the semiconductor element formed on the upper semiconductor substrate is shown as a planar transistor (e.g., a field-effect transistor (FET)) or a fin transistor (e.g., a FinFET) as examples, but the inventive concept is not limited thereto. For example, in a semiconductor device according to an exemplary embodiment of the inventive concept, the semiconductor element formed on the upper semiconductor substrate may include a buried channel array transistor (BCAT), a recessed channel array transistor (RCAT), a tunneling transistor (e.g., a tunneling FET), a transistor including nanowires, a transistor including nanosheets, or a vertical transistor (e.g., a vertical FET).

[0034] The accompanying drawings of a semiconductor device according to an exemplary embodiment of the present invention (e.g., Figure 3 The diagram shows that the transistors formed on the lower semiconductor substrate and the transistors formed on the upper semiconductor substrate are of the same type, but the inventive concept is not limited thereto. For example, in a semiconductor device according to an exemplary embodiment of the inventive concept, the semiconductor elements formed on the lower semiconductor substrate and the semiconductor elements formed on the upper semiconductor substrate may have different forms.

[0035] For example, a semiconductor element formed on a lower semiconductor substrate may include a memory cell, while a semiconductor element formed on an upper semiconductor substrate may be a logic element. As another example, a semiconductor element formed on a lower semiconductor substrate may be a logic element, while a semiconductor element formed on an upper semiconductor substrate may include a memory cell. In yet another example, logic elements comprising different types of transistors may be formed on both the lower and upper semiconductor substrates.

[0036] The storage cell can be a volatile storage element or a non-volatile storage element. The storage cell can be, for example, but not limited to, dynamic random access memory (DRAM), static RAM (SRAM), flash memory, etc.

[0037] Figure 1 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. Figure 2 yes Figure 1 A magnified view of region R1.

[0038] Reference Figure 1 and Figure 2 The semiconductor device includes a lower semiconductor substrate 100, a first upper semiconductor substrate 200, a first upper gate structure 220, first interlayer insulating films 140 and 240, and a first upper contact 250.

[0039] The lower semiconductor substrate 100 and the first upper semiconductor substrate 200 can be bulk silicon or silicon-on-insulator (SOI), respectively. Alternatively, the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 can be silicon substrates, or can include other materials, such as, but not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), antimony indium, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0040] The first upper semiconductor substrate 200 may include a first surface 200a and a second surface 200b opposite to each other. The first surface 200a of the first upper semiconductor substrate 200 may face the top surface of the lower semiconductor substrate 100. In other words, the first surface 200a of the first upper semiconductor substrate 200 may be closer to the lower semiconductor substrate 100 than the second surface 200b of the first upper semiconductor substrate 200.

[0041] Multiple transistors may be disposed on the first upper semiconductor substrate 200. For example, multiple first upper gate structures 220 may be formed on the first surface 200a of the first upper semiconductor substrate 200. Each first upper gate structure 220 may include a first upper gate electrode 221, a first upper gate dielectric film 222, and a first upper insulating structure 225.

[0042] The first upper gate electrode 221 may be disposed on the first surface 200a of the first upper semiconductor substrate 200. In an exemplary embodiment of the present invention, the first upper gate electrode 221 may extend longitudinally along one direction. For example, in Figure 1 In this process, the first upper gate electrode 221 can extend longitudinally along a direction perpendicular to the first surface 200a of the first upper semiconductor substrate 200.

[0043] The first upper gate electrode 221 may include, for example, but not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (T). aCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0044] The first upper gate dielectric film 222 may be disposed between the first upper semiconductor substrate 200 and the first upper gate electrode 221. The first upper gate dielectric film 222 may include, for example, a high dielectric constant material with a dielectric constant higher than that of silicon oxide. For example, the first upper gate dielectric film 222 may include, but is not limited to, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0045] A first upper insulating structure 225 may surround the side and bottom surfaces of the first upper gate electrode 221. For example, the first upper insulating structure 225 may include a first upper spacer 226 and a first upper cover pattern 227. The first upper spacer 226 may extend along the side surface of the first upper gate electrode 221, and the first upper cover pattern 227 may extend along the bottom surface of the first upper gate electrode 221. In an exemplary embodiment of the inventive concept, the first upper spacer 226 may extend along the side surfaces of the first upper gate electrode 221 and the first upper cover pattern 227.

[0046] The first upper spacer 226 and the first upper cover pattern 227 may include, for example, but not limited to, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), or combinations thereof.

[0047] exist Figure 1In this illustration, although the first upper gate dielectric film 222 is shown extending along the first surface 200a of the first upper semiconductor substrate 200 and the inner surface of the first upper spacer 226, this is merely an example. For instance, the first upper gate dielectric film 222 may extend only along the first surface 200a of the first upper semiconductor substrate 200.

[0048] First interlayer insulating films 140 and 240 may be disposed between the lower semiconductor substrate 100 and the first upper semiconductor substrate 200. The first interlayer insulating films 140 and 240 may include a lower interlayer insulating film 140 and an upper interlayer insulating film 240. The lower interlayer insulating film 140 may be formed on the top surface of the lower semiconductor substrate 100. The upper interlayer insulating film 240 may be formed on the first surface 200a of the first upper semiconductor substrate 200. For example, the upper interlayer insulating film 240 may be disposed between the first surface 200a of the first upper semiconductor substrate 200 and the lower interlayer insulating film 140. In an exemplary embodiment of the present invention, the upper interlayer insulating film 240 may cover the first upper gate structure 220.

[0049] The lower interlayer insulating film 140 and the upper interlayer insulating film 240 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), Tonen SilaZene (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), degel, aerogel, amorphous fluorinated carbon, organosilicon glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, or combinations thereof.

[0050] The first upper contact 250 may be disposed on the side surface of the first upper gate structure 220. The first upper contact 250 may be formed in a first through-hole 250h that penetrates the upper interlayer insulating film 240 and the first upper semiconductor substrate 200.

[0051] At least a portion of the side surface of the first upper contact 250 may be defined by the side surface of the first upper gate structure 220. For example, as Figure 1 and Figure 2 As shown, at least a portion of the side surface of the first upper contact 250 may extend along the side surface of the first upper gate structure 220. In an exemplary embodiment of the present invention, at least a portion of the side surface of the first upper contact 250 may contact the side surface of the first upper gate structure 220.

[0052] Furthermore, the first upper contact 250 can penetrate the first upper semiconductor substrate 200 and the upper interlayer insulating film 240. In an exemplary embodiment of the present invention, the width of the first upper contact 250 can decrease toward the second surface 200b of the first upper semiconductor substrate 200. Here, "width" can refer to the width in a direction parallel to the top surface of the lower semiconductor substrate 100.

[0053] The first upper contact 250 can be formed by a self-aligned contact (SAC) process performed in the direction from the first upper gate structure 220 to the first upper semiconductor substrate 200. This will be discussed later in... Figures 21 to 26 The description is detailed in the description.

[0054] like Figure 1 As shown, the first upper contact 250 may include a first portion 250a, a second portion 250b, and a third portion 250c.

[0055] A first portion 250a of the first upper contact 250 can penetrate the first upper semiconductor substrate 200. For example, the first portion 250a of the first upper contact 250 can penetrate the source / drain region of a transistor including the first upper gate structure 220. This allows the first upper contact 250 to connect to the source / drain region of the transistor including the first upper gate structure 220.

[0056] In an exemplary embodiment of the present invention, the width of the first portion 250a of the first upper contact 250 may decrease toward the second surface 200b of the first upper semiconductor substrate 200. For example, the width W11 of the first upper contact 250 at the same horizontal height as the second surface 200b of the first upper semiconductor substrate 200 may be smaller than the width W12 of the first upper contact 250 at the same horizontal height as the first surface 200a of the first upper semiconductor substrate 200.

[0057] The second portion 250b of the first upper contact 250 may be disposed below the first portion 250a of the first upper contact 250. The second portion 250b of the first upper contact 250 may be connected to the first portion 250a of the first upper contact 250 in the upper interlayer insulating film 240.

[0058] In an exemplary embodiment of the present invention, the width of the second portion 250b of the first upper contact 250 may decrease toward the first surface 200a of the first upper semiconductor substrate 200. For example, the width W12 of the first upper contact 250 at the same horizontal height as the first surface 200a of the first upper semiconductor substrate 200 may be smaller than the width W13 of the first upper contact 250 at the same horizontal height as the bottom surface of the first upper gate structure 220.

[0059] A side surface of the second portion 250b of the first upper contact 250 may be adjacent to a side surface of the first upper gate structure 220. In an exemplary embodiment of the present invention, the side surface of the second portion 250b of the first upper contact 250 may be defined by a side surface of the first upper gate structure 220. For example, the side surface of the second portion 250b of the first upper contact 250 may extend along a side surface of the first upper gate structure 220. In an exemplary embodiment of the present invention, the side surface of the second portion 250b of the first upper contact 250 may contact the outer surface of the first upper insulating structure 225. In an exemplary embodiment of the present invention, the side surface of the second portion 250b of the first upper contact 250 may contact the outer surface of the first upper spacer 226.

[0060] exist Figure 1 In the illustration, although both side surfaces of the second portion 250b of the first upper contact 250 are shown to be defined by the side surfaces of the first upper gate structure 220, this is merely an example. For instance, only the first side surface of the second portion 250b may be defined by the side surfaces of the first upper gate structure 220, while the second side surface of the second portion 250b opposite to the first side surface may be spaced apart from the first upper gate structure 220.

[0061] In exemplary embodiments of the present invention, such as Figure 2 As shown, the outer surface 225s of the first upper insulating structure 225 may include a first recess 225r. The first recess 225r may be adjacent to the bottom surface 225b of the first upper insulating structure 225 and may have a concave shape. In an exemplary embodiment of the present invention, the side surface of the first upper spacer 226 may include the first recess 225r.

[0062] Since the side surface of the second portion 250b of the first upper contact 250 can be defined by the side surface of the first upper insulating structure 225, a portion of the second portion 250b of the first upper contact 250 can fill the first recess 225r. For example, the second portion 250b of the first upper contact 250 may include a first protrusion 250p filling the first recess 225r. The first protrusion 250p may be adjacent to the bottom surface 225b of the first upper insulating structure 225 and may protrude toward the first upper insulating structure 225. For example, the first protrusion 250p may protrude toward a first upper spacer 226 adjacent to the first upper overlay pattern 227. The first protrusion 250p may protrude toward the first upper insulating structure 225 in a direction parallel to the first surface 200a of the first upper semiconductor substrate 200.

[0063] The third portion 250c of the first upper contact 250 may be disposed below the second portion 250b of the first upper contact 250. The third portion 250c of the first upper contact 250 may be connected to the second portion 250b of the first upper contact 250 in the first interlayer insulating films 140 and 240.

[0064] The first upper contact 250 can be used to connect the first upper semiconductor substrate 200 to the lower semiconductor substrate 100. For example, the lower contact 150 and the first conductive pad 160 can be disposed on the lower semiconductor substrate 100. The lower contact 150 can be connected to various semiconductor elements (e.g., transistors, etc.) formed on the lower semiconductor substrate 100. The first conductive pad 160 can be disposed on and connected to the lower contact 150. In this case, the first upper contact 250 can be connected to the first conductive pad 160. Therefore, the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 can be electrically connected to each other.

[0065] The lower contact 150 and the first conductive pad 160 can be formed, for example, in the lower interlayer insulating film 140. In an exemplary embodiment of the present invention, a third portion 250c of the first upper contact 250 can penetrate a portion of the upper interlayer insulating film 240 and a portion of the lower interlayer insulating film 140, and can be connected to the first conductive pad 160. For example, the third portion 250c of the first upper contact 250 can directly contact the first conductive pad 160. In an exemplary embodiment of the present invention, the bottom surface of the first conductive pad 160 can be connected to the top surface of the lower contact 150, and the top surface of the first conductive pad 160 can be connected to the bottom surface of the first upper contact 250.

[0066] In highly integrated semiconductor devices, self-aligned contact (SAC) processes can be used to form contacts. However, in three-dimensional stacked semiconductor devices, if the upper contact is formed by a self-aligned contact (SAC) process performed in the direction from the first upper semiconductor substrate 200 to the first upper gate structure 220, the first upper gate electrode 221 may not be protected by the first upper insulating structure 225 when misalignment occurs.

[0067] However, in the semiconductor device according to an exemplary embodiment of the present invention, the first upper contact 250 can be formed by a self-aligned contact (SAC) process performed in the direction from the first upper gate structure 220 to the first upper semiconductor substrate 200. Therefore, the semiconductor device according to an exemplary embodiment of the present invention can provide a first upper contact 250 that prevents damage to the first upper gate electrode 221. Thus, an improvement in the integration density and reliability of the semiconductor device according to an exemplary embodiment of the present invention is achieved.

[0068] Figure 3This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. For convenience, the previously referenced [devices] may not be provided. Figure 1 and Figure 2 Description of the components being described.

[0069] Reference Figure 3 In a semiconductor device according to an exemplary embodiment of the present invention, a plurality of transistors are disposed on a lower semiconductor substrate 100.

[0070] For example, multiple lower gate structures 120 may be formed on the lower semiconductor substrate 100. Each lower gate structure 120 may include a lower gate electrode 121, a lower gate dielectric film 122, and a lower insulating structure 125. The lower insulating structure 125 may include, for example, a lower spacer 126 and a lower cover pattern 127.

[0071] The lower gate structure 120 is shown as a transistor of the same form as the first upper gate structure 220, but the inventive concept is not limited thereto. For example, in a semiconductor device according to an exemplary embodiment of the inventive concept, the lower gate structure 120 may have a different form than the first upper gate structure 220. Since the lower gate structure 120 shown is similar to the first upper gate structure 220, its detailed description will not be provided below.

[0072] In an exemplary embodiment of the present invention, the lower contact 150 may be disposed on a side surface of the lower gate structure 120. The lower contact 150 may be connected to the source / drain region of the transistor including the lower gate structure 120. Therefore, the source / drain regions of the first upper semiconductor substrate 200 and the source / drain regions of the lower semiconductor substrate 100 may be electrically connected to each other. In other words, in an exemplary embodiment of the present invention, the first upper contact 250 and the lower contact 150 may be used as a common source / drain contact for the first upper semiconductor substrate 200 and the lower semiconductor substrate 100.

[0073] In an exemplary embodiment of the present invention, the width of the lower contact 150 may decrease toward the top surface of the lower semiconductor substrate 100. This may be due to, for example, the characteristics of the etching process used to form the lower contact 150. For example, the lower contact 150 may be formed by an etching process that etches the lower interlayer insulating film 140 in the direction from the lower gate structure 120 to the lower semiconductor substrate 100.

[0074] Figure 4 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. For convenience, the previously referenced [devices] may not be provided. Figures 1 to 3 Description of the components being described.

[0075] Reference Figure 4In the semiconductor device according to this embodiment, at least a portion of the side surface of the lower contact 150 is defined by the side surface of the lower gate structure 120.

[0076] For example, at least a portion of the side surface of the lower contact 150 may extend along the side surface of the lower gate structure 120. In an exemplary embodiment of the present invention, a portion of the side surface of the lower contact 150 may contact the outer surface of the lower insulating structure 125. In an exemplary embodiment of the present invention, a portion of the side surface of the lower contact 150 may contact the outer surface of the lower spacer 126.

[0077] The lower contact 150 can be formed, for example, by a self-aligned contact (SAC) process performed in the direction from the lower gate structure 120 to the lower semiconductor substrate 100.

[0078] In an exemplary embodiment of the present invention, the outer surface of the lower insulating structure 125 may include a second recess 125r. The second recess 125r may be adjacent to the top surface of the lower insulating structure 125 and may have a concave shape. Since a portion of the side surface of the lower contact 150 may be defined by the side surface of the lower insulating structure 125, a portion of the lower contact 150 may fill the second recess 125r. In other words, a portion of the lower contact 150 may protrude into the second recess 125r.

[0079] Figure 5 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. Figure 6 yes Figure 5 A magnified view of region R2. For convenience, the referenced area can be omitted. Figures 1 to 3 Description of the components being described.

[0080] Reference Figure 5 and Figure 6 In the semiconductor device according to this embodiment, the first upper cover pattern 227 extends along the bottom surface of the first upper gate electrode 221 and the bottom surface of the first upper spacer 226.

[0081] In an exemplary embodiment of the present invention, the side surface of the second portion 250b of the first upper contact 250 may be defined by the outer surface of the first upper spacer 226 and the outer surface of the first upper cover pattern 227.

[0082] In an exemplary embodiment of the present invention, the side surface of the first upper covering pattern 227 may include a first recess 225r. Figure 5 and Figure 6In the illustration, although the first recess 225r is shown as being formed only on the side surface of the first upper overlay pattern 227, this is merely an example. For instance, the first recess 225r could be formed on both the side surface of the first upper overlay pattern 227 and the side surface of the first upper spacer 226.

[0083] Because the side surface of the second portion 250b of the first upper contact 250 can be defined by the side surface of the first upper insulating structure 225, a portion of the first upper contact 250 can fill the first recess 225r. For example, the second portion 250b of the first upper contact 250 may include a first protrusion 250p projecting toward the first upper overlay pattern 227.

[0084] Figure 7 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. Figure 8 yes Figure 7 A magnified view of region R3. For convenience, the referenced area can be omitted. Figures 1 to 3 Description of the components being described.

[0085] Reference Figure 7 and Figure 8 In the semiconductor device according to this embodiment, the first interlayer insulating films 140 and 240 include a third recess 240r.

[0086] The third recess 240r may be adjacent to the bottom surface 225b of the first upper insulating structure 225 and may have a concave shape. In an exemplary embodiment of the present invention, the side surface of the upper interlayer insulating film 240 may include the third recess 240r.

[0087] Since the third portion 250c of the first upper contact 250 can be formed in the first interlayer insulating films 140 and 240, a portion of the third portion 250c of the first upper contact 250 can fill the third recess 240r. For example, the third portion 250c of the first upper contact 250 may include a second protrusion 250q filling the third recess 240r. The second protrusion 250q may be adjacent to the bottom surface 225b of the first upper insulating structure 225 and may protrude toward the first interlayer insulating films 140 and 240. For example, the second protrusion 250q may protrude toward the portion of the upper interlayer insulating film 240 adjacent to the first upper cover pattern 227.

[0088] Figures 9 to 13 Various cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention are shown. For convenience, references may be omitted. Figures 1 to 3 Description of the components being described.

[0089] Reference Figures 9 to 13The semiconductor device according to an exemplary embodiment of the present invention further includes a channel conditioning film 310.

[0090] The channel conditioning film 310 may be disposed on the second surface 200b of the first upper semiconductor substrate 200. In an exemplary embodiment of the present invention, the channel conditioning film 310 may be directly formed on the second surface 200b of the first upper semiconductor substrate 200. The channel conditioning film 310 may adjust the characteristics of the first upper semiconductor substrate 200. For example, the channel conditioning film 310 may adjust the channel characteristics of a transistor including the first upper gate structure 220.

[0091] Reference Figure 9 In an exemplary embodiment of the present invention, the channel conditioning film 310 may apply compressive stress (CS) to the first upper semiconductor substrate 200. For example, the first lattice constant of the material included in the channel conditioning film 310 may be less than the second lattice constant of the material included in the first upper semiconductor substrate 200. For example, when the first upper semiconductor substrate 200 includes silicon (Si), the channel conditioning film 310 may include silicon carbide (SiC).

[0092] In p-type metal-oxide-semiconductor (PMOS) transistors, the mobility of carrier holes can be improved by applying compressive stress to the channel. Therefore, improved performance can be provided for semiconductor devices using PMOS transistors as transistors including a first upper gate structure 220.

[0093] Reference Figure 10 In an exemplary embodiment of the present invention, the channel conditioning film 310 may apply tensile stress (TS) to the first upper semiconductor substrate 200. For example, the first lattice constant of the material included in the channel conditioning film 310 may be greater than the second lattice constant of the material included in the first upper semiconductor substrate 200. For example, when the first upper semiconductor substrate 200 includes silicon (Si), the channel conditioning film 310 may include silicon germanium (SiGe).

[0094] In n-type metal-oxide-semiconductor (NMOS) transistors, the mobility of charge carriers (electrons) can be improved by applying tensile stress to the channel. Therefore, improved performance can be provided for semiconductor devices using NMOS transistors as transistors including a first upper gate structure 220.

[0095] Reference Figure 11In an exemplary embodiment of the present invention, the channel conditioning film 310 may include a ferroelectric material. The channel conditioning film 310 including the ferroelectric material can provide a negative capacitive component to the transistor including the first upper gate structure 220. For example, the channel conditioning film 310 including the ferroelectric material can provide a negative capacitance (C2 < 0) to the first upper gate structure 220 having a positive capacitance (C1 > 0). This can further amplify the voltage applied to the first upper semiconductor substrate 200 (or the channel of the transistor including the first upper gate structure 220) through the first upper gate electrode 221.

[0096] As a result, in a semiconductor device according to an exemplary embodiment of the present invention, a negative capacitance FET (NCFET) having a subthreshold slope (SS) value of approximately 60 mV / decade or less at room temperature can be implemented.

[0097] Reference Figure 12 In an exemplary embodiment of the present invention, the channel conditioning film 310 may include impurities 312. The impurities 312 in the channel conditioning film 310 may diffuse into the first upper semiconductor substrate 200. For example, the channel conditioning film 310 may include borosilicate glass (BPSG). In this case, the impurities 312 diffused into the first upper semiconductor substrate 200 may be boron (B) or phosphorus (P).

[0098] The impurity 312 diffused into the first upper semiconductor substrate 200 can modulate the threshold voltage of the transistor including the first upper gate structure 220. Therefore, improved performance can be provided for semiconductor devices including transistors having the first upper gate structure 220.

[0099] Reference Figure 13 In an exemplary embodiment of the present invention, the channel conditioning film 310 may include a dielectric film 314 and a work function metal film 316. The dielectric film 314 and the work function metal film 316 may be sequentially stacked on the second surface 200b of the first upper semiconductor substrate 200.

[0100] The dielectric film 314 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0101] The work function metal film 316 may include, for example, but not limited to, TiN, TaN, TiC, TaC, TiAlC, or combinations thereof.

[0102] The channel conditioning film 310, including the work function metal film 316, can adjust the threshold voltage of a transistor including the first upper gate structure 220. For example, a voltage can be applied to the work function metal film 316 to adjust the threshold voltage of the transistor including the first upper gate structure 220. Therefore, improved performance can be provided for semiconductor devices including transistors having the first upper gate structure 220.

[0103] Figure 14 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. For convenience, the previously referenced [devices] may not be provided. Figures 1 to 3 Description of the components being described.

[0104] Reference Figure 14 The semiconductor device according to an exemplary embodiment of the present invention further includes a second interlayer insulating film 340.

[0105] The second interlayer insulating film 340 may be disposed on the second surface 200b of the first upper semiconductor substrate 200. In an exemplary embodiment of the present invention, the first upper contact 250 may penetrate the second interlayer insulating film 340. For example, a first portion 250a of the first upper contact 250 may extend beyond the first upper semiconductor substrate 200 and penetrate the second interlayer insulating film 340.

[0106] Therefore, in the semiconductor device according to this embodiment, the transistor formed on the first upper semiconductor substrate 200 can be connected to an integrated circuit formed on the second surface 200b of the first upper semiconductor substrate 200. For example, the second conductive pad 360 and wirings 372 and 374 can be disposed on the second interlayer insulating film 340. The second conductive pad 360 and wirings 372 and 374 can, for example, be formed in a third interlayer insulating film 440 disposed on the second interlayer insulating film 340.

[0107] The second conductive pad 360 can be disposed on and connected to the first upper contact 250. For example, the second conductive pad 360 can be directly connected to the first upper contact 250. Wiring 372 and 374 can be connected to the first upper contact 250 through the second conductive pad 360. Therefore, the first upper semiconductor substrate 200 and wiring 372 and 374 can be electrically connected to each other.

[0108] Figure 15 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. For convenience, the previously referenced [devices] may not be provided. Figures 1 to 3 as well as Figure 14 Description of the components being described.

[0109] Reference Figure 15The semiconductor device according to this embodiment also includes a second upper semiconductor substrate 300, a second upper gate structure 320, a fourth interlayer insulating film 540, and a second upper contact 350.

[0110] The second upper semiconductor substrate 300 may include a third surface 300a and a fourth surface 300b opposite to each other. The third surface 300a of the second upper semiconductor substrate 300 may face the second surface 200b of the first upper semiconductor substrate 200. For example, the third surface 300a of the second upper semiconductor substrate 300 may be closer to the first upper semiconductor substrate 200 than the fourth surface 300b of the second upper semiconductor substrate 300.

[0111] Multiple transistors may be disposed on the second upper semiconductor substrate 300. For example, multiple second upper gate structures 320 may be formed on the second upper semiconductor substrate 300. Each second upper gate structure 320 may include a second upper gate electrode 321, a second upper gate dielectric film 322, and a second upper insulating structure 325. The second upper insulating structure 325 may include, for example, a second upper spacer 326 and a second upper overlay pattern 327.

[0112] The second upper gate structure 320 is shown as a transistor of the same form as the first upper gate structure 220, but the inventive concept is not limited thereto. For example, in the semiconductor device according to this embodiment, the second upper gate structure 320 may have a different form than the first upper gate structure 220. Since the second upper gate structure 320 shown is similar to the first upper gate structure 220, a detailed description thereof will not be provided below.

[0113] The second upper contact 350 may be disposed on a side surface of the second upper gate structure 320. The second upper contact 350 may be formed in a second through-hole 350h that penetrates the fourth interlayer insulating film 540 and the second upper semiconductor substrate 300. The second upper contact 350 may include a fourth portion 350a, a fifth portion 350b, and a sixth portion 350c. In an exemplary embodiment of the present invention, a portion of the second upper contact 350 may fill the fourth recess 325r of the second upper insulating structure 325. Since the second upper contact 350 is similar to the first upper contact 250, its detailed description will not be provided below.

[0114] The second upper contact 350 can be used to connect the second upper semiconductor substrate 300 to the first upper semiconductor substrate 200. For example, the second upper contact 350 can be connected to the second conductive pad 360. For example, the second upper contact 350 can be directly connected to the second conductive pad 360. Therefore, the lower semiconductor substrate 100, the first upper semiconductor substrate 200, and the second upper semiconductor substrate 300 can be electrically connected to each other.

[0115] Figure 16This is a layout diagram illustrating an exemplary semiconductor device according to a concept of the present invention. Figure 17 It is along Figure 16 The cross-sectional view taken from line AA. Figure 18 It is along Figure 16 The cross-sectional view of line BB. Figure 19 It is along Figure 16 A cross-sectional view taken from line CC. For convenience, the referenced section can be omitted. Figures 1 to 3 Description of the components being described.

[0116] Reference Figures 16 to 19 The semiconductor device according to this embodiment includes a fin transistor.

[0117] For example, the semiconductor device according to this embodiment may further include an active pattern 210, an upper field insulating film 205, and an upper source / drain region 230.

[0118] An active pattern 210 may protrude from the first upper semiconductor substrate 200 and may extend longitudinally in one direction. In an exemplary embodiment of the inventive concept, the active pattern 210 may protrude from a first surface 200a of the first upper semiconductor substrate 200. In other words, the active pattern 210 may protrude in a direction toward the lower semiconductor substrate 100.

[0119] The active pattern 210 can extend in a direction intersecting with the first upper gate structure 220. For example, as Figure 16 As shown, the active pattern 210 can extend longitudinally along the first direction, while the first gate structure 220 can extend longitudinally along the second direction intersecting the first direction.

[0120] The active pattern 210 may include silicon or germanium as elemental semiconductor materials. Alternatively, the active pattern 210 may include compound semiconductors, such as group IV-IV compound semiconductors or group III-V compound semiconductors. Group IV-IV compound semiconductors may be, for example, binary or ternary compounds comprising at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping these elements with group IV elements. Group III-V compound semiconductors may be, for example, binary, ternary, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and ammonium (Sb), which are group V elements.

[0121] An upper insulating film 205 can be formed on a first surface 200a of the first upper semiconductor substrate 200. For example... Figure 18 and Figure 19As shown, the upper insulating film 205 can cover a portion of the sidewall of the upper active pattern 210.

[0122] The field insulating film 205 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0123] The upper source / drain region 230 may be formed in the upper active pattern 210 on the side surface of the first upper gate structure 220. However, the upper source / drain region 230 may be insulated from the first upper gate structure 220. For example, the upper source / drain region 230 may be spaced apart from the first upper gate electrode 221 by the first upper spacer 226. The upper source / drain region 230 may contact the first upper spacer 226. The upper source / drain region 230 may be used as the source / drain of a transistor including the first upper gate structure 220.

[0124] The upper source / drain region 230 may include an epitaxial layer formed in the upper active pattern 210. For example... Figure 17 As shown, the upper source / drain region 230 can be a raised source / drain region protruding from the upper active pattern 210. Additionally, the upper source / drain region 230 can include an undercut overlapping the first upper spacer 226. However, this is merely an example, and the inventive concept is not limited thereto. For example, the upper source / drain region 230 can be an impurity region formed in the upper active pattern 210.

[0125] When the semiconductor device according to this embodiment is a PMOS transistor, the upper source / drain region 230 may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the upper source / drain region 230 may include at least one of B, C, In, Ga, and Al, or a combination thereof.

[0126] Additionally, when the semiconductor device according to this embodiment is a PMOS transistor, the upper source / drain region 230 may include a compressive stress material. For example, when the upper active pattern 210 is Si, the upper source / drain region 230 may include a material having a lattice constant larger than that of Si, such as SiGe. The compressive stress material can apply compressive stress to the upper active pattern 210 to improve the carrier mobility in the channel region of the PMOS transistor.

[0127] When the semiconductor device according to this embodiment is an NMOS transistor, the upper source / drain region 230 may include an n-type impurity or an impurity for preventing the diffusion of n-type impurities. For example, the upper source / drain region 230 may include at least one of P, Sb, and As, or a combination thereof.

[0128] Additionally, when the semiconductor device according to this embodiment is an NMOS transistor, the upper source / drain region 230 may include a tensile stress material. For example, when the upper active pattern 210 is Si, the upper source / drain region 230 may include a material having a lattice constant smaller than that of Si, such as SiC. The tensile stress material can apply tensile stress to the upper active pattern 210 to improve the carrier mobility in the channel region of the NMOS transistor.

[0129] Although the upper source / drain region 230 is shown as a single-layer film, the inventive concept is not limited thereto. For example, each upper source / drain region 230 may be formed of a multilayer film containing different concentrations of impurities.

[0130] exist Figure 19 In the diagram, the cross-section of the upper source / drain region 230 is shown as a pentagon, but this is only an example. For example, the cross-section of the upper source / drain region 230 can have various shapes, such as rhombus or hexagon.

[0131] The semiconductor device according to this embodiment may further include a lower active pattern 110, a lower field insulating film 105, and a lower source / drain region 130. Since the lower active pattern 110, the lower field insulating film 105, and the lower source / drain region 130 shown are similar to the upper active pattern 210, the upper field insulating film 205, and the upper source / drain region 230, respectively, a detailed description of them will not be provided below.

[0132] In an exemplary embodiment of the present invention, the first upper contact 250 may penetrate the upper source / drain region 230. For example, a first portion 250a of the first upper contact 250 may penetrate the upper source / drain region 230. Therefore, the first upper contact 250 may be connected to the upper source / drain region 230.

[0133] In an exemplary embodiment of the present invention, the lower contact 150 may be connected to the lower source / drain region 130. For example, the lower contact 150 may penetrate the lower source / drain region 130. Therefore, the lower source / drain region 130 and the upper source / drain region 230 may be electrically connected to each other. In other words, in an exemplary embodiment of the present invention, the first upper contact 250 and the lower contact 150 serve as a common source / drain contact for the upper source / drain region 230 and the lower source / drain region 130.

[0134] Figure 20 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept of the present invention. For convenience, the previously referenced [devices] may not be provided. Figures 1 to 3 , Figures 9 to 13 as well as Figures 17 to 19 Description of the components being described.

[0135] Reference Figure 20The semiconductor device according to this embodiment also includes a channel conditioning film 310.

[0136] The channel conditioning film 310 can be disposed on the second surface 200b of the first upper semiconductor substrate 200. In an exemplary embodiment of the present invention, the channel conditioning film 310 can be directly formed on the second surface 200b of the first upper semiconductor substrate 200. The channel conditioning film 310 can adjust the characteristics of the first upper semiconductor substrate 200. Therefore, the channel conditioning film 310 can adjust the channel characteristics of the transistor including the first upper gate structure 220.

[0137] In an exemplary embodiment of the present invention, the channel conditioning film 310 may apply compressive or tensile stress to the first upper semiconductor substrate 200.

[0138] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include a ferroelectric material. The channel conditioning film 310 including the ferroelectric material can provide a negative capacitance component to the transistor including the first upper gate structure 220.

[0139] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include impurities diffused into the first upper semiconductor substrate 200. For example, the channel conditioning film 310 may include borosilicate glass (BPSG).

[0140] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include an insulating film and a work function metal film sequentially stacked on a second surface 200b of a first upper semiconductor substrate 200.

[0141] In the following text, reference will be made to Figures 1 to 31 A method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention is described.

[0142] Figures 21 to 26 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For convenience, the previously referenced figures may not be provided. Figures 1 to 20 Description of the components being described.

[0143] Reference Figure 21 A first upper semiconductor substrate 200, a first upper gate structure 220, and an upper interlayer insulating film 240 can be formed on the sacrificial film 1110.

[0144] The first upper semiconductor substrate 200 can be formed such that its second surface 200b faces the sacrificial film 1110. A first upper gate electrode 221 and an upper interlayer insulating film 240 can be formed on the first surface 200a of the first upper semiconductor substrate 200. The upper interlayer insulating film 240 can cover the first upper gate electrode 221.

[0145] Reference Figure 22 A first through hole 250h is formed that penetrates the upper interlayer insulating film 240 and the first upper semiconductor substrate 200.

[0146] For example, a mask pattern 1210 can be formed on the upper interlayer insulating film 240. Subsequently, an etching process using the mask pattern 1210 as an etching mask can be performed.

[0147] The first through-hole 250h can be formed using a self-aligned contact (SAC) process. Therefore, at least a portion of the side surface of the first through-hole 250h can be defined by the side surface of the first upper gate structure 220. Furthermore, since the self-aligned contact (SAC) process is performed in the direction from the first upper gate structure 220 to the first upper semiconductor substrate 200, the width of the first through-hole 250h can decrease towards the sacrificial film 1110.

[0148] Although both side surfaces of the first through-hole 250h are shown as being defined by the side surfaces of the first upper gate structure 220, this is merely an example. For instance, only the first side surface of the first through-hole 250h may be defined by the side surfaces of the first upper gate structure 220, while the second side surface of the first through-hole 250h opposite to the first side surface may be spaced apart from the first upper gate structure 220.

[0149] In an exemplary embodiment of the present invention, the outer surface of the first upper insulating structure 225 may include a first recess 225r formed by a self-aligned contact (SAC) process. This may be due to, for example, the difference between the first upper insulating structure 225 and the upper interlayer insulating film 240. The first recess 225r may be adjacent to the bottom surface of the first upper insulating structure 225 and may have a concave shape.

[0150] Reference Figure 23 A dummy contact 1120 is formed in the first through hole 250h.

[0151] Therefore, the dummy contact 1120 can be disposed on the side surface of the first upper gate structure 220. Furthermore, at least a portion of the side surface of the dummy contact 1120 can be defined by the side surface of the first upper gate structure 220. Additionally, the dummy contact 1120 can penetrate the first upper semiconductor substrate 200 and the upper interlayer insulating film 240. In an exemplary embodiment of the present invention, the width of the dummy contact 1120 can decrease towards the sacrificial film 1110.

[0152] In an exemplary embodiment of the present invention, the dummy contact 1120 may include a material having etch selectivity relative to the first upper semiconductor substrate 200, the upper interlayer insulating film 240, and the first upper insulating structure 225. Additionally, in an exemplary embodiment of the present invention, the dummy contact 1120 may include a material having excellent adhesion to the lower interlayer insulating film 140, which will be described later. For example, the dummy contact 1120 may include, but is not limited to, polycrystalline silicon (polycrystalline Si).

[0153] Reference Figure 24 The upper interlayer insulating film 240 is bonded to the lower interlayer insulating film 140.

[0154] For example, a lower semiconductor substrate 100, a lower gate structure 120, and a lower interlayer insulating film 140 may be provided. Subsequently, the lower interlayer insulating film 140 and the upper interlayer insulating film 240 may be combined such that the first surface 200a of the first upper semiconductor substrate 200 faces the top surface of the lower semiconductor substrate 100.

[0155] Typically, when an upper semiconductor substrate is stacked three-dimensionally on a lower semiconductor substrate, the adhesion between the upper contacts, including the metal, and the lower interlayer insulating film is weak, making it difficult to stack the upper contacts. However, in the method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention, since the dummy contact 1120 may include a material with excellent adhesion to the lower interlayer insulating film 140, the lower interlayer insulating film 140 and the upper interlayer insulating film 240 can be more firmly bonded.

[0156] Reference Figure 25 Remove the dummy contact 1120.

[0157] For example, the sacrificial film 1110 on the second surface 200b of the first upper semiconductor substrate 200 can be removed. Subsequently, the dummy contact 1120 exposed by the removed sacrificial film 1110 can be removed.

[0158] Therefore, a first through-hole 250h can be formed that penetrates the first upper semiconductor substrate 200 and the upper interlayer insulating film 240. In an exemplary embodiment of the present invention, the first through-hole 250h can expose a portion of the lower interlayer insulating film 140.

[0159] Reference Figure 26 Remove a portion of the exposed lower interlayer insulating film 140.

[0160] For example, an etching process can be performed to remove a portion of the exposed lower interlayer insulating film 140. The etching process may include, for example, but not limited to, wet etching and / or dry etching processes. Thus, a first through-hole 250h for exposing the first conductive pad 160 can be formed.

[0161] Subsequently, referring to Figures 1 to 2 A first upper contact 250 is formed in the first through-hole 250h. In other words, Figure 24 The dummy contact 1120 is replaced by the first upper contact 250.

[0162] Therefore, the first upper contact 250 can be connected to the first conductive pad 160. The first upper contact 250 can be disposed on a side surface of the first upper gate structure 220. Furthermore, at least a portion of the side surface of the first upper contact 250 can be defined by the side surface of the first upper gate structure 220. Additionally, the first upper contact 250 can penetrate the first upper semiconductor substrate 200 and the upper interlayer insulating film 240. In an exemplary embodiment of the present invention, the width of the first upper contact 250 can decrease towards the first upper semiconductor substrate 200. In an exemplary embodiment of the present invention, a portion of the first upper contact 250 can fill the first recess 225r.

[0163] Therefore, methods for manufacturing semiconductor devices with improved integration and reliability can be provided.

[0164] Figure 27 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For convenience, the previously referenced figures may not be provided. Figures 1 to 26 A description of the described components. For reference, Figure 27 It is shown Figure 25 The diagram for the next stage.

[0165] Reference Figure 27 A portion of the exposed lower interlayer insulating film 140 is removed using a wet etching process.

[0166] Therefore, a first interlayer insulating film 140 and 240 including a third recess 240r can be formed. The third recess 240r may be adjacent to the bottom surface of the first upper insulating structure 225 and may have a concave shape. In an exemplary embodiment of the present invention, the side surface of the upper interlayer insulating film 240 may include the third recess 240r.

[0167] Subsequently, referring to Figure 7 A first upper contact 250 is formed in the first through hole 250h.

[0168] Therefore, a portion of the first upper contact 250 can fill the third recess 240r.

[0169] Figure 28 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For convenience, the previously referenced figures may not be provided. Figures 1 to 26 A description of the described components. For reference, Figure 28 It is shown Figure 1 The diagram for the next stage.

[0170] Reference Figure 28 A channel conditioning film 310 is formed on the second surface 200b of the first upper semiconductor substrate 200.

[0171] In an exemplary embodiment of the present invention, the channel conditioning film 310 can be directly formed on the second surface 200b of the first upper semiconductor substrate 200. Therefore, the channel characteristics of the transistor including the first upper gate structure 220 can be adjusted. The channel conditioning film 310 can be formed, for example, by a deposition process, but is not limited thereto.

[0172] In an exemplary embodiment of the present invention, the channel conditioning film 310 may apply compressive or tensile stress to the first upper semiconductor substrate 200.

[0173] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include a ferroelectric material. The channel conditioning film 310 including the ferroelectric material can provide a negative capacitance component to the transistor including the first upper gate structure 220.

[0174] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include impurities to be diffused into the first upper semiconductor substrate 200. For example, the channel conditioning film 310 may include borosilicate glass (BPSG).

[0175] In an exemplary embodiment of the present invention, the channel conditioning film 310 may include an insulating film and a work function metal film sequentially stacked on a second surface 200b of a first upper semiconductor substrate 200.

[0176] Figures 29 to 31 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For convenience, the previously referenced figures may not be provided. Figures 1 to 26 Description of the components being described.

[0177] Reference Figure 29 A second interlayer insulating film 340, a first upper semiconductor substrate 200, a first upper gate structure 220 and an upper interlayer insulating film 240 are formed on the sacrificial film 1110.

[0178] Due to the formation and reference of the first upper semiconductor substrate 200, the first upper gate structure 220 and the upper interlayer insulating film 240 Figure 21 The descriptions are similar, so no further details will be provided below.

[0179] The second interlayer insulating film 340 may be located between the sacrificial film 1110 and the first upper semiconductor substrate 200. In other words, the second interlayer insulating film 340 may be formed on the second surface 200b of the first upper semiconductor substrate 200.

[0180] Reference Figure 30 A first penetrating hole 250h is formed that penetrates the upper interlayer insulating film 240, the first upper semiconductor substrate 200, and the second interlayer insulating film 340.

[0181] Because, apart from the first through-hole 250h extending beyond the first upper semiconductor substrate 200 and penetrating the second interlayer insulating film 340, this structure is similar to... Figure 22 The structure is similar to that described in the previous section, so a detailed description will not be provided below.

[0182] Then, the above can be executed. Figures 23 to 26 The stages described in the text.

[0183] Subsequently, referring to Figure 31 A first upper contact 250 is formed in the first through hole 250h.

[0184] Therefore, a first upper contact 250 can be formed that extends beyond the first upper semiconductor substrate 200 and penetrates the second interlayer insulating film 340.

[0185] Subsequently, referring to Figure 14 A second conductive pad 360, wiring 372 and 374, and a third interlayer insulating film 440 are formed on the second interlayer insulating film 340.

[0186] Therefore, the transistor formed on the first upper semiconductor substrate 200 can be connected to the integrated circuit formed on the second surface 200b of the first upper semiconductor substrate 200.

[0187] Exemplary embodiments of the present invention provide semiconductor devices with improved integration and reliability by forming self-aligned contacts (SACs) for preventing damage to integrated circuits on the upper semiconductor substrate.

[0188] Exemplary embodiments of the present invention also provide a method for manufacturing semiconductor devices with improved integration and reliability by forming self-aligned contacts (SACs) for preventing damage to integrated circuits on an upper semiconductor substrate.

[0189] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that many variations and modifications may be made to the exemplary embodiments without departing from the principles of the inventive concept set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Lower semiconductor substrate; An upper semiconductor substrate, which overlaps with a lower semiconductor substrate, wherein the upper semiconductor substrate includes a first surface facing the lower semiconductor substrate and a second surface opposite to the first surface; An upper gate structure is located on the first surface of the upper semiconductor substrate, and the upper gate structure includes a top surface adjacent to the first surface of the upper semiconductor substrate and a bottom surface opposite to the top surface; A first interlayer insulating film covers the upper gate structure, wherein the first interlayer insulating film is located between the lower semiconductor substrate and the upper semiconductor substrate; and An upper contact is connected to the lower semiconductor substrate, wherein the upper contact is located on a side surface of the upper gate structure. The upper contact includes a first portion, a second portion, and a third portion. The first portion penetrates the upper semiconductor substrate. The second portion has a side surface adjacent to the side surface of the upper gate structure. The third portion is located below the second portion and is connected to the second portion in the first interlayer insulating film. The width of the first portion decreases towards the second surface. The side surface of the upper gate structure includes a first concave recess adjacent to the bottom surface of the upper gate structure. The second portion includes a first protrusion that projects toward the upper gate structure and fills the first concave recess. The side surface of the first interlayer insulating film includes a second concave recess adjacent to the bottom surface of the upper gate structure, and The third part includes a second protrusion that protrudes toward the first interlayer insulating film and fills the second concave recess.

2. The semiconductor device according to claim 1, further comprising: A conductive pad is attached to the bottom surface of the upper contact in the first interlayer insulating film; and The lower contact penetrates the first interlayer insulating film and connects the lower semiconductor substrate and the conductive pad.

3. The semiconductor device according to claim 1, wherein, The width of the second portion decreases toward the first surface.

4. The semiconductor device according to claim 1, further comprising: A channel conditioning film is disposed on the second surface of the upper semiconductor substrate.

5. The semiconductor device according to claim 4, wherein, The channel conditioning film applies compressive or tensile stress to the upper semiconductor substrate.

6. The semiconductor device according to claim 4, wherein, The channel regulating membrane comprises a ferroelectric material.

7. The semiconductor device according to claim 4, wherein, The channel conditioning membrane comprises borosilicate glass.

8. The semiconductor device according to claim 4, wherein, The channel conditioning film includes a work function metal film and a dielectric film located between the upper semiconductor substrate and the work function metal film.

9. The semiconductor device according to claim 1, further comprising: A second interlayer insulating film is located on the second surface of the upper semiconductor substrate. The first portion of the upper contact penetrates the second interlayer insulating film.

10. The semiconductor device according to claim 1, further comprising: Source / drain regions, which are adjacent to the upper gate structure in the upper semiconductor substrate. The first portion of the upper contact penetrates the source / drain region.

11. A semiconductor device, comprising: Lower semiconductor substrate; A lower gate structure, wherein the lower gate structure is located on the surface of the lower semiconductor substrate; A lower interlayer insulating film is located on the lower semiconductor substrate, wherein the lower interlayer insulating film covers the lower gate structure; An upper semiconductor substrate, which overlaps with a lower interlayer insulating film, wherein the upper semiconductor substrate includes a first surface facing the lower semiconductor substrate and a second surface opposite to the first surface; An upper gate structure is located on the first surface of the upper semiconductor substrate, and the upper gate structure includes a top surface adjacent to the first surface of the upper semiconductor substrate and a bottom surface opposite to the top surface; An upper interlayer insulating film, the upper interlayer insulating film being located on the upper semiconductor substrate, wherein the upper interlayer insulating film covers the upper gate structure; and An upper contact is located on a side surface of the upper gate structure, wherein the upper contact penetrates the upper semiconductor substrate and the upper interlayer insulating film. Wherein, the width of the upper contact at the same horizontal height as the second surface is smaller than the width of the upper contact at the same horizontal height as the first surface. At least a portion of the side surface of the upper contact contacts the side surface of the upper gate structure. The side surface of the upper gate structure includes a first concave recess adjacent to the bottom surface of the upper gate structure. The side surface of the upper interlayer insulating film includes a second concave recess adjacent to the bottom surface of the upper gate structure and located below the first concave recess. The upper contact includes a first protrusion that protrudes toward the upper gate structure and fills the first concave recess, and a second protrusion that protrudes toward the upper interlayer insulating film and fills the second concave recess.

12. The semiconductor device of claim 11, further comprising: The lower contact is disposed in the lower interlayer insulating film and connects the lower semiconductor substrate and the upper contact.

13. The semiconductor device according to claim 12, wherein, The width of the lower contact decreases toward the surface of the lower semiconductor substrate.

14. The semiconductor device of claim 12, further comprising: The lower source / drain region is adjacent to the side surface of the lower gate structure in the lower semiconductor substrate; and Upper source / drain region, wherein the upper source / drain region is adjacent to the side surface of the upper gate structure in the upper semiconductor substrate; Wherein, the lower contact is connected to the lower source / drain region, and The upper contact is connected to the upper source / drain region.

15. The semiconductor device according to claim 11, wherein, The upper semiconductor substrate includes an active pattern that protrudes toward the surface of the lower semiconductor substrate and extends in a first direction. The upper gate structure extends in a second direction intersecting the first direction.

16. A semiconductor device, comprising: Lower semiconductor substrate; A conductive pad located on the lower semiconductor substrate; An upper semiconductor substrate, which overlaps with a lower semiconductor substrate, wherein the upper semiconductor substrate includes a first surface facing the lower semiconductor substrate and a second surface opposite to the first surface; An upper gate structure is located on the first surface of the upper semiconductor substrate, wherein the upper gate structure includes an upper gate electrode and insulating structures located on the side surface and bottom surface of the upper gate electrode; An upper interlayer insulating film, wherein the upper interlayer insulating film is located between the first surface of the upper semiconductor substrate and the conductive pad; and An upper contact, which penetrates the upper semiconductor substrate and the upper interlayer insulating film, and is connected to the conductive pad, wherein the upper contact is located on a side surface of the upper gate structure. The side surface of the insulating structure includes a first concave recess adjacent to the bottom surface of the insulating structure. The side surface of the upper interlayer insulating film includes a second concave recess adjacent to the bottom surface of the insulating structure and located below the first concave recess. The upper contact includes a first protrusion that protrudes toward the upper gate structure and fills the first concave recess, and a second protrusion that protrudes toward the upper interlayer insulating film and fills the second concave recess.

17. The semiconductor device according to claim 16, wherein, The width of the upper contact decreases toward the second surface.

Images