Array-type image sensor chips and electronic devices

Abstract

This application discloses an array-type image sensor chip and an electronic device. The array-type image sensor chip includes: a core region, in which a plurality of imaging units are formed, and each imaging unit contains a plurality of pixels arranged in an array; and a control circuit connected to each imaging unit, with at least a portion of the control circuit located within the core region between adjacent imaging units. The array-type image sensor chip fully utilizes the chip area, reducing chip cost.

Description

Technical Field

[0001] This application relates to the field of image sensing technology, specifically to an array-type image sensing chip and an electronic device. Background Technology

[0002] Driven by today's consumer electronics, the imaging quality and production volume of imaging modules are constantly improving. Currently, array-type imaging modules utilize an array of microlenses and their corresponding image sensor chips to capture images of objects. Each microlens corresponds to a sensing area on the image sensor chip, forming an imaging unit. Each imaging unit obtains a different image, and the imaging data are superimposed to create a single image. Array-type imaging modules have a relatively low height and do not require focusing.

[0003] In traditional image sensor chips, pixels are arranged in an array on the sensing area. However, only the pixels in a few sensing areas corresponding to the lens can be used for imaging, while the pixels in other areas do not need to be imaged, which leads to a waste of chip area.

[0004] How to design new image sensing chips for array imaging modes to avoid wasting chip area and further reduce chip costs is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, this application provides an array-type image sensor chip and an electronic device to improve the integration of the image sensor chip used for array-type imaging.

[0006] The present invention provides an array-type image sensing chip, comprising: a core region, wherein a plurality of imaging units are formed in the core region, and a plurality of pixels arranged in an array are formed in each imaging unit; and a control circuit connected to each imaging unit, wherein at least a portion of the control circuit is located in the core region between adjacent imaging units.

[0007] Optionally, the control circuit includes several circuit units, each corresponding to at least one imaging unit, for parallel processing of the sensing data of the corresponding imaging unit.

[0008] Optionally, the plurality of imaging units are arranged along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other, or the first direction and the second direction form an obtuse angle; the pixels in the imaging unit are distributed in a row and column array, and the pixels in the same column in each imaging unit are coupled to the same column signal line, and the pixels in the same row in each imaging unit are coupled to the same row signal line.

[0009] Optionally, the control circuit includes at least a readout circuit, which includes a plurality of readout units, each readout unit corresponding to at least one imaging unit and disposed between imaging units located in the same column, coupled to the column signal line of the corresponding imaging unit.

[0010] Optionally, several row bias units are located outside the core area, with each row bias unit connected to a read unit located in the same row to provide bias for each read unit.

[0011] Optionally, the control circuit further includes an analog-to-digital conversion circuit, which includes a plurality of analog-to-digital conversion units, each of which corresponds to at least one read unit. The analog-to-digital conversion units are connected to the corresponding read units and are arranged along the direction of the column signal lines.

[0012] Optionally, the distance between the analog-to-digital conversion unit and the reading unit is greater than a set threshold.

[0013] Optionally, it may also include: a number of pseudo pixels, disposed in the core region between adjacent imaging units.

[0014] Optionally, the control circuit further includes a row selection circuit located on the periphery of the core region, comprising several row selection units, each row selection unit being connected to several imaging units located in the same row.

[0015] Optionally, it may also include: a plurality of storage units located in a core region between adjacent imaging units; each storage unit is used to store sensing data from one or more imaging units.

[0016] The present invention also provides an electronic device, comprising: an array-type image sensing chip as described in one of the preceding claims.

[0017] The array-type image sensor chip of this application has an array of imaging units and at least a portion of control circuitry formed within its core region. This control circuitry is located between adjacent imaging units, allowing full utilization of the non-imaging area within the core region and reducing the peripheral area of ​​the chip. Compared to traditional image sensor chips, with the same core region area, it effectively reduces the peripheral area, thereby reducing chip size and cost.

[0018] Furthermore, by placing the readout circuit in the core area of ​​the control circuit, the distance between the readout circuit and the pixels in the imaging unit can be reduced, thereby reducing the power consumption of signal transmission; and by setting up readout circuits separately for each imaging unit and adopting distributed processing, the operating frequency of each readout circuit can be reduced.

[0019] Furthermore, storage units can be set up in the core area. In high frame rate scenarios, data can be stored through these storage units, enabling global shutter reading without changing the pixel structure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a traditional image sensor chip;

[0022] Figures 2 to 7 This is a schematic diagram of the structure of an array-type image sensing chip according to an embodiment of the present invention. Detailed Implementation

[0023] As described in the background section, using traditional image sensing chips for array imaging results in wasted chip area and cost.

[0024] Please refer to Figure 1 This is a schematic diagram of the structure of a traditional image sensor chip.

[0025] The image sensing chip 100 includes a core region 10 and a peripheral region 20 located around the core region 10. Pixels 11 are arranged in an array within the core region 10. A control circuit 21 and pins 22 are formed within the peripheral region 20. The control circuit 21 is used to control and read the sensing data of the pixels 11, and the pins 22 serve as the connection terminals for electrical signal transmission between the inside and outside of the chip.

[0026] Pixels 11 are distributed at various locations within the core region 10. However, when the image sensor chip is used in array imaging mode, microlenses are distributed in an array on the core region 10. Only pixels in a portion of the region 12 corresponding to the microlenses can output valid imaging data, while pixels in other locations are invalid pixels. Invalid pixels occupy the core region area of ​​the chip, resulting in wasted chip area and a decrease in chip integration density.

[0027] For array imaging scenarios, the inventors provide a new array-type image sensing chip that makes full use of the chip's effective area and improves chip integration.

[0028] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0029] Please refer to Figure 2 This is a schematic diagram of the structure of an array-type image sensing chip according to an embodiment of the present invention.

[0030] In this embodiment, the array-type image sensing chip 200 includes a core region 210 and a peripheral region 220.

[0031] A plurality of imaging units 211 are formed within the core region 210, and a plurality of pixels are formed within each imaging unit 211; a control circuit 212 is connected to each imaging unit 211, and at least a portion of the control circuit 212 is located within the core region 210 between adjacent imaging units 211.

[0032] Specifically, in this embodiment, an imaging unit 211 consisting of several pixels is formed only at the imaging position of the core region 210, while the non-imaging region is used to form a control circuit 212. Figure 2 The diagram illustrates that, when the non-imaging area within the core region 210 is sufficiently large, all control circuits 212 are formed within the non-imaging area, with pins 221 formed only in the peripheral region 220. This allows for full utilization of the non-imaging area within the core region, reducing the size of the peripheral region 220. Compared to traditional image sensor chips, this effectively reduces the peripheral area while maintaining the same core region area, thereby reducing chip size and cost.

[0033] The control circuit 212 includes a reading circuit for reading sensor data, a data processing circuit for noise reduction, analog-to-digital conversion, and other functions, as well as a storage circuit. The control circuit 212 may include several circuit units 2121, each corresponding to one of the imaging units 211, for reading and processing the sensor data within each imaging unit 211. This allows for parallel processing of the sensor data within each imaging unit 211, improving data processing speed. With the number of pixels in a single imaging unit 211 remaining constant, the imaging resolution can be increased by increasing the number of imaging units 211. Since the sensor data from each imaging unit 211 is processed in parallel, the frame rate does not change with the increase in resolution. Therefore, the frame rate requirement for high-resolution imaging can be reduced, thereby simplifying circuit design.

[0034] Furthermore, the reduced distance between the control circuit 212 and the pixels within the imaging unit 211 lowers the power consumption required for data transmission. Since the number of pixel rows and columns within the imaging unit corresponding to each circuit unit 2121 is relatively small, distributed parallel processing can reduce the operating frequency of each circuit unit 2121, thereby reducing circuit power consumption.

[0035] The imaging resolution determines the number of imaging units 211 and the number of pixels within them. For a core region 210 of the same size, a higher resolution requirement necessitates a smaller non-imaging region. When the non-imaging region is small, some control circuitry can be formed within the non-imaging region, while other control circuitry can be formed within the peripheral region 220. Those skilled in the art can make reasonable arrangements based on the actual situation.

[0036] Based on the concept of the above embodiments, those skilled in the art can form at least part of the control circuitry or other chip structures, such as pseudo-pixels or memory, in the non-imaging area outside the imaging unit 211, according to the area of ​​the non-imaging area within the core region 210, in order to improve chip utilization and reduce costs. Those skilled in the art can also rationally design the correspondence between the control circuitry in the non-imaging area and each imaging unit 211 according to actual needs, so that each circuit unit within the control circuit corresponds to one or more imaging units, thereby achieving distributed processing.

[0037] Please refer to Figure 3 This is a schematic diagram of the structure of an array-type image sensing chip according to another embodiment of the present invention.

[0038] In this embodiment, the array-type image sensing chip 300 includes a core region 310 and a peripheral region 320, with the peripheral region 320 surrounding the core region 310.

[0039] The core region 310 contains a plurality of imaging units 311 arranged in an array. In this embodiment, the imaging units 311 are arranged along a first direction (X direction) and a second direction (Y direction), which are perpendicular to each other, forming a rectangular array. Specifically, the X direction is the row direction and the Y direction is the column direction. The pixels (not shown in the figure) within the imaging units 311 are also distributed in a row-column array. Pixels in the same column within each imaging unit 311 are coupled to the same column signal line 3111, and pixels in the same row within each imaging unit 311 are coupled to the same row signal line 3112. Specifically, imaging units 311 in the same row are connected by row signal lines 3112, and imaging units 311 in the same column are connected by column signal lines 3111.

[0040] A pseudo-pixel region 321 is formed within the peripheral region 320, and a plurality of pseudo-pixels are formed within the pseudo-pixel region 321. The pseudo-pixels can be used to improve the uniformity of pixel pattern distribution within the chip and improve the process uniformity of pixel formation. The pseudo-pixels can also be black reference pixels used for data calibration. The pseudo-pixels can also be other non-imaging pixels with different functions, which are not listed here.

[0041] The array-type image sensor chip 300 also includes a control circuit, part of which is formed within the peripheral region 320 and part of which is formed within the core region 310. The control circuit includes a data reading circuit, a bias circuit, a row selection circuit, and a column selection circuit, etc. These functional circuits cooperate with each other to read the sensing data of each pixel, process it, and then output it.

[0042] In this embodiment, the control circuit includes a readout circuit, which comprises a plurality of readout units 312. Each readout unit 312 corresponds to at least one imaging unit 311 and is disposed between imaging units 311 located in the same column, coupled to the column signal line 3111 of the corresponding imaging unit 311. The readout circuit can be an analog front-end circuit used to read the sensing data of each pixel. In this embodiment, each imaging unit 311 corresponds to one readout unit 312, and the readout units 312 can be synchronized by a clock signal to simultaneously and in parallel read data from multiple imaging units 311, improving efficiency. The readout unit 312 is used to acquire sensing data and perform noise reduction and amplification processing on the data.

[0043] Since data is read row by row and column by column, for ease of wiring layout, each reading unit 312 and its corresponding imaging unit 311 are arranged along the Y direction and along the routing path of the column signal line 3111. Each reading unit 312 is arranged adjacent to its corresponding imaging unit 311 to shorten the distance between the reading unit 312 and the pixel, improve the signal transmission rate, and reduce power consumption during transmission. In other embodiments, if the distance between the imaging units 311 is small, only some circuit units in the reading circuit can be placed in the core area 310. For example, the circuits connecting to the sensing data acquisition parts of each pixel unit can be placed between the imaging units 311, while other noise reduction, amplification, and other circuits can be placed in the peripheral area 310.

[0044] The control circuit may further include a bias circuit, comprising a plurality of row bias units 324 located around the core region. Each row bias unit 324 is connected to a readout unit 312 located in the same row, providing bias current or voltage bias to each readout unit 312. Each bias unit 324 is multiplexed by multiple imaging units 311. In this embodiment, by using multiple bias units 324 to provide bias to readout circuits 312 at different locations, the trace length can be minimized, and signal delay at different locations can be reduced. In other embodiments, a single bias unit 324 can simultaneously provide bias to all readout units 312.

[0045] The control circuit further includes a row selection circuit located in the peripheral region 320 surrounding the core region 310. The row selection circuit includes several row selection units 323, each connected to several imaging units 311 located in the same row. Each row of imaging units 311 corresponds to one row selection unit 323, used for row selection of pixels within the imaging unit 311.

[0046] In this embodiment, the control circuit further includes an analog-to-digital conversion circuit, which comprises a plurality of analog-to-digital conversion units 313, each corresponding to at least one readout unit 312. In this embodiment, the analog-to-digital conversion units 313 are disposed within the peripheral region 320, with each column of readout units 312 corresponding to one analog-to-digital conversion unit 313. Each analog-to-digital conversion unit 313 includes N analog-to-digital converters, the same as the number of pixel columns N in each imaging unit 311. In other embodiments, the number of analog-to-digital converters in each analog-to-digital conversion unit 313 may be less than N, allowing multiple columns of pixels to share a single analog-to-digital converter. In other embodiments, a single analog-to-digital conversion unit 313 may also correspond to multiple columns of imaging units 313. The analog-to-digital conversion unit 313 can be a ramp analog-to-digital converter (ADC), a successive approximation analog-to-digital converter (SAR ADC), a cyclic analog-to-digital converter (Cyclic ADC), a cyclic successive approximation analog-to-digital converter (Cyclic SAR), a pipeline analog-to-digital converter (Pipeline ADC), etc. Those skilled in the art can reasonably select an analog-to-digital conversion circuit with a suitable structure as needed.

[0047] Each analog-to-digital conversion unit 313 is provided with current or voltage bias through an analog-to-digital conversion bias unit 325, which is located in the peripheral region 320 near the analog-to-digital conversion unit 313.

[0048] A column bias circuit 322 is also formed within the peripheral region 320 to provide column bias current for each imaging unit 311.

[0049] In this embodiment, the readout circuit is formed within the core region 310, with each imaging unit 311 corresponding to one readout unit. This fully utilizes the non-imaging area within the core region 310, improving chip area utilization and reducing chip cost. Furthermore, it reduces the distance between the readout unit and the pixel, lowering signal transmission power consumption. Multiple readout units can simultaneously perform data reading operations on each imaging unit, and the distributed processing causes the operating frequency of each readout unit to decrease proportionally, resulting in lower power consumption. Each readout unit only reads data from a single imaging unit, so even if the number of imaging units increases to improve imaging resolution, it will not lead to an increase in frame rate, thus reducing the difficulty of circuit design.

[0050] Please refer to Figure 4 This is a schematic diagram of the structure of an array-type image sensing chip 400 according to another embodiment of the present invention.

[0051] In this embodiment, the reading circuit of the control circuit includes a plurality of reading units 4312, each reading unit 4312 corresponding to a plurality of imaging units 311 located in the same column, and each reading unit 4312 is arranged in the same row, so that the row bias unit 324 in the peripheral area 320 can provide bias for each reading unit 4312.

[0052] In this embodiment, the column bias circuit of the control circuit includes a plurality of column bias units 422, each column bias unit 422 corresponding to a plurality of imaging units 311 in the same column, providing current or voltage bias to the imaging units 311 in the same column. The column bias units 422 and the readout unit 4312 are disposed between adjacent imaging units 311 in the same column, and are arranged along the direction of the column signal lines 3111 of the imaging units 311 in the corresponding column to facilitate wiring.

[0053] Please refer to Figure 5 This is a schematic diagram of the structure of an array-type image sensing chip 500 according to another embodiment of the present invention.

[0054] In this embodiment, Figure 4 Based on the embodiment, a storage unit 510 is also formed within the core region 310. The storage unit 510 can be any one or more of SRAM storage, DRAM storage, or Flash storage.

[0055] The storage unit 510 is relatively large and can be placed in the non-imaging area between adjacent columns of imaging units 311. Each storage unit 510 is used to store sensing data from one or more imaging units 311.

[0056] The storage unit 510 is connected to the reading unit 4312 and is used to store the sensor data output by the imaging unit 311 at various times. By adding the storage unit 510 to the non-imaging area within the core region 310, a global shutter imaging mode can be achieved without increasing the chip area. Sensor data is temporarily stored in the storage unit 510 and then read when needed, achieving flexibility in sensor data output. In the prior art, to achieve a global shutter, it is usually necessary to add a storage structure to each pixel to store the data. However, in this embodiment, by setting the storage unit 510, the pixel structure does not need to be changed, which is easy to implement and improves the chip utilization rate, enabling the chip to support both rolling shutter and global shutter modes.

[0057] Please refer to Figure 6 This is a schematic diagram of the structure of an array-type image sensing chip 600 according to another embodiment of the present invention.

[0058] In this embodiment, the analog-to-digital conversion circuit in the control circuit of the array image sensor chip 600 is also located in the core area 310. Specifically, the analog-to-digital conversion circuit includes several analog-to-digital conversion units 613, which are located in the routing direction of the column signal line 3111 and connected to the reading unit 4312. They are used to perform analog-to-digital conversion on the analog signal read by the reading unit 4312 to output a digital signal.

[0059] In this embodiment, each analog-to-digital conversion unit 613 corresponds to two imaging units. Specifically, it corresponds to two imaging units 311 above the analog-to-digital conversion unit 613, and an analog-to-digital conversion unit 613 is provided between every two imaging units 311 located in the same column.

[0060] In this embodiment, the column bias unit 6422 and the readout circuit 4312 are disposed in the same area between adjacent imaging units 311.

[0061] The storage unit 510 can also be reasonably adjusted in size and position according to the actual size of the non-imaging area and the distribution of other circuit units, so as to fully improve the utilization rate of the non-imaging area in the core area 310 of the chip.

[0062] Preferably, due to the circuit characteristics of the reading unit 4312 and the analog-to-digital conversion unit 613, signal crosstalk is prone to occur between them. When both the reading unit 4312 and the analog-to-digital conversion unit 613 are located within the core region 310, the distance between them needs to be limited to reduce signal crosstalk. The distance between the analog-to-digital conversion unit and the reading unit is greater than a set threshold, which can be adjusted according to actual conditions. In this embodiment, at least one imaging unit 311 is spaced between the reading unit 4312 and the analog-to-digital conversion unit 613.

[0063] In this embodiment, only the bias circuit, row selection circuit, and pseudo-pixel region 321 are retained within the peripheral region 320. Since the bias circuit and row selection circuit can be reused by multiple pixel units or circuit units, their circuit area is relatively small. Placing them within the core region 310 would have limited effect on reducing the chip area, and placing them within the peripheral region 320 facilitates wiring. By placing the control circuits corresponding to each pixel within the non-imaging area of ​​the core region 310, the peripheral region area of ​​the chip can be significantly reduced, data processing efficiency improved, and power consumption reduced.

[0064] In other embodiments, if the area of ​​the non-imaging region between the imaging units 311 is sufficient, other circuit structures or pseudo pixels in the peripheral region can also be disposed within the core region 310.

[0065] Please refer to Figure 7 This is a schematic diagram of the structure of an array-type image sensing chip according to an embodiment of the present invention.

[0066] Figure 7 Only the layout of the imaging unit 711 within the core region 710 of the array image sensing chip is shown.

[0067] In this implementation, the imaging units 711 are arranged along a first direction A-A' and a second direction B-B', with an obtuse angle between A-A' and B-B'. Adjacent imaging units 711 form a minimum unit shape of a triangle. Imaging units 711 in adjacent rows are staggered, and imaging units 711 in adjacent columns are also staggered. The triangle of the minimum unit shape can be an equilateral triangle or an isosceles triangle.

[0068] Compared to the array arrangement where the smallest unit shape is rectangular in the previous embodiment, the array arrangement of the pixel units 711 described above can increase the number of pixel units arranged in the core region 711 while maintaining the same distance between adjacent pixel units. Furthermore, the vertical distance d between pixel units 711 in the same column is doubled, while maintaining the same array spacing. Figure 7The arrangement shown effectively increases the area of ​​the non-imaging region between adjacent pixel units 711 within the same column. Since the readout circuit and analog-to-digital conversion circuit need to be located on the column signal line path, the increased area of ​​the non-imaging region between adjacent pixel units 711 within the same column makes it easier to place readout units and analog-to-digital conversion units, as well as more circuit units, within the non-imaging region. This improves chip area utilization and allows more modules to work together, enhancing the efficiency of sensor data reading and processing.

[0069] Embodiments of the present invention also provide an electronic device, including an array-type image sensing chip as described in the above embodiments. The array-type image sensing chip has an imaging unit array distribution, with at least some control circuitry disposed between pixel units within the core region of the chip. This fully utilizes the chip area, reduces the area of ​​the peripheral region, thereby reducing chip cost, power consumption, and improving data reading efficiency. This, in turn, helps to reduce the cost of the electronic device and improve its imaging capabilities.

[0070] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array-type image sensing chip, characterized in that, include: The core region contains several imaging units, and each imaging unit contains several pixels arranged in an array. A control circuit is connected to each imaging unit, and at least a portion of the control circuit is located in the core region between adjacent imaging units; Several storage units are located in the core area between adjacent imaging units; each storage unit is used to store sensing data from one or more imaging units. The plurality of imaging units are arranged along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other, or the first direction and the second direction form an obtuse angle; the pixels in the imaging unit are distributed in a row and column array, and the pixels in the same column in each imaging unit are coupled to the same column signal line, and the pixels in the same row in each imaging unit are coupled to the same row signal line. The control circuit also includes an analog-to-digital conversion circuit, which includes a plurality of analog-to-digital conversion units, each of which corresponds to at least one read unit. The analog-to-digital conversion units are connected to the corresponding read units and are arranged along the direction of the column signal lines. At least one imaging unit is spaced between the analog-to-digital conversion unit and the reading unit.

2. The array-type image sensing chip according to claim 1, characterized in that, The control circuit includes several circuit units, each corresponding to at least one imaging unit, for parallel processing of the sensing data of the corresponding imaging unit.

3. The array-type image sensing chip according to claim 1, characterized in that, The control circuit includes at least a readout circuit, which includes a plurality of readout units, each readout unit corresponding to at least one imaging unit and disposed between imaging units located in the same column, coupled to the column signal line of the corresponding imaging unit.

4. The array-type image sensing chip according to claim 3, characterized in that, Several row bias units are located on the periphery of the core area. Each row bias unit is connected to a read unit located on the same row, providing bias for each read unit.

5. The array-type image sensing chip according to claim 1, characterized in that, Also includes: Several pseudo-pixels are set in the core area between adjacent imaging units.

6. The array-type image sensing chip according to claim 1, characterized in that, The control circuit also includes a row selection circuit located on the periphery of the core region, comprising several row selection units, each row selection unit being connected to several imaging units located in the same row.

7. An electronic device, characterized in that, include: The array-type image sensing chip as described in any one of claims 1 to 6.

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