Techniques for storing data to enhance repair and detection of data corruption errors

Abstract

Techniques for storing data to enhance repair and detection of data corruption errors are disclosed. Errors often occur when reading data from computer memory. To detect and correct these errors, various types of error correction codes exist. Disclosed is an error correction architecture that creates code words with a data portion and an error correction code portion. The order of the bits is shuffled and the bits are distributed into different code words. Because the data is redistributed, a potential memory error of up to N consecutive bits (e.g., N equals twice the number of code words that are shuffled together) affects at most two bits per shuffled code word. This keeps the error within the error detection capability of the error correction architecture. Furthermore, this can improve error correction and detection without requiring changes to the error correction code generator and checker.

Description

[0001] Governmental Rights

[0002] This invention was made with government support under DOE Contract No. DE-AC52-07NA27344 and Lawrence Livermore National Laboratory Subcontract No. B620719. The government has certain rights in the invention. TECHNICAL FIELD

[0003] The present application relates generally to storing data and retrieving data from memory, and more specifically, to correcting and detecting errors in data stored in memory. BACKGROUND

[0004] The use of error-correcting codes is a key part of modern computer systems. Error-correcting codes are used to detect and correct errors when transmitting by adding bits to the data bits, called parity bits. The data bits and parity bits make up a codeword. One class of such error-correcting codes is single error correction double error detection (SECDED), which is widely used in modern computer architectures. SECDED is a common type of error-correcting code that allows for the correction of single-bit errors and the detection of double-bit errors. SECDED is commonly used to protect data stored in memory from errors. While SECDED can typically handle single and double-bit errors, this error-correcting code can completely ignore or even incorrectly correct certain multi-bit (N-bit) errors when the number of errors in a codeword is greater than 2.

[0005] SUMMARY

[0006] A first aspect provides an error-correcting code (ECC) apparatus comprising: a first data mixer configured to mix a plurality of data units to form a plurality of mixed data units; an ECC generator configured to generate a plurality of error-correcting bits, at least one of the plurality of error-correcting bits generated from each of the plurality of mixed data units received from the first data mixer; and an ECC mixer configured to mix the plurality of error-correcting bits to form a plurality of mixed error-correcting bits and thereby form a plurality of mixed codewords, wherein each mixed codeword comprises one of the plurality of data units and at least one of the plurality of mixed error-correcting bits.

[0007] A second aspect provides a memory controller employing error correction code (ECC) comprising a data swizzler configured to generate a plurality of swizzled data units from a plurality of data units; an ECC generator configured to generate a plurality of error correction bits from the plurality of data units; and an ECC swizzler configured to generate a plurality of swizzled error correction bits from the plurality of error correction bits, thereby forming a plurality of swizzled codewords, wherein each swizzled codeword comprises one of the plurality of swizzled data units and at least one swizzled error correction bit of the plurality of swizzled error correction bits.

[0008] A third aspect provides a method comprising swizzling a plurality of data units to generate a plurality of swizzled data units; performing error correction code on the swizzled data units to create a plurality of error correction bits; swizzling the plurality of error correction bits to generate a plurality of swizzled error correction bits; and storing the plurality of data units and the plurality of swizzled error correction bits, wherein the storing creates a plurality of swizzled codewords. BRIEF DESCRIPTION OF DRAWINGS

[0009] The following description is presented in connection with the accompanying drawings:

[0010] Figure 1 A block diagram illustrating an embodiment of a computer system including a memory controller constructed in accordance with the principles of the present disclosure is described;

[0011] Figure 2A A block diagram illustrating an example of a memory controller constructed in accordance with the principles of the present disclosure is described;

[0012] Figure 2B An example of swizzling a burst of data in accordance with the principles of the present disclosure is provided;

[0013] Figure 2C An example of swizzling error correction bits in accordance with the principles of the present disclosure is provided;

[0014] Figure 3 A block diagram illustrating another example of a memory controller constructed in accordance with the principles of the present disclosure is described;

[0015] Figure 4A Another example of swizzling a burst of data in accordance with the principles of the present disclosure is described;

[0016] Figure 4B Another example of swizzling error correction bits in accordance with the principles of the present disclosure is described;

[0017] Figure 5 A flowchart of an example method of swizzling and unswizzling error correction bits of a swizzled codeword performed in accordance with the principles of the present disclosure is described; and

[0018] Figure 6A flowchart of an example method of performing data unit on multiple data units and scrambling of code word error correction bits of a scrambled code word in accordance with the principles of the present disclosure is illustrated. DETAILED DESCRIPTION

[0019] As noted above, ECC is used to detect and correct errors related to data stored in memory, such as DRAM. The error can be a bit error, and in some cases can result in a byte pattern failure. A byte pattern failure can occur, for example, when a control signal to a byte in memory does not function properly, and thus the entire data byte is returned as all "0"s or all "1"s. Other types of errors are also possible. In conventional approaches, such a byte pattern failure results in a double error detection (DED) error notification, error correction data, further corrupting the data, or no detection resulting in no error being reported at all. Accordingly, the present invention provides a method of spreading, organizing, and distributing data (including ECC generated error correction bits) across multiple code words, thereby creating a scrambled code word in a manner that ameliorates the effects of a multi-bit memory failure, such as a byte pattern failure, as described below.

[0020] Generally, the present disclosure relates to multiple error correction architectures that utilize data scrambling across multiple code words to ameliorate the effects of memory failures. "Scrambling" can generally be defined as a reversible exchange of bits between different code words or between different data bytes. The scrambling used herein can be performed prior to generating the corresponding error correction bits. In accordance with the principles of the present disclosure, scrambling is used to rearrange the order of bits and distribute or interleave them across different code words.

[0021] Various types of scrambling can be used, such as vertical, horizontal, or diagonal scrambling. In vertical scrambling, there is an exchange of bits between different data bursts at the same bit position. In horizontal scrambling, there is an exchange of bits within the same data burst, but not between data bursts. In diagonal scrambling, there is an exchange of bits between both data bursts and bit positions. Various implementations of diagonal scrambling are illustrated, for example, as follows.

[0022] Generally, a "burst" refers to a specific amount of data that is sent or received in an intermittent operation. Figure 2B and Figure 4A Examples of different bursts discussed herein are provided. Figure 2B An example of a set of four beats of raw data, with eight bytes per beat, is illustrated. Figure 4A An example of a sixteen beat burst and a length of sixteen bits (2 bytes) is illustrated.

[0023] The improved error detection and correction disclosed herein can be used for various types of ECC. Generally, if the ECC can detect a number of "x" bit errors, the number of bits to be checked will be considered a group of interest, and a data word will be mixed using a group of 8 bits of interest (i.e., 8 / 2 = 4 data words).

[0024] For example, consider an error correction architecture using a SECDED code. If a byte error occurs that affects up to 8 bits in the memory, it is preferable to use mixing so that a byte error in each code word affects at most only two bits. This allows for improved error correction and detection without requiring changes to existing SECDED error correction code generators and checkers.

[0025] Figure 1 A block diagram illustrating one embodiment of a computer system 100 including a memory controller 120 constructed in accordance with the principles of the present disclosure is described. The computer system 100 also has a processor 110 and a DRAM 130 coupled to the memory controller 120. The computer system 100 can include additional components not shown but typically included in a conventional computer system, such as an I / O controller coupled to the memory controller 120.

[0026] The processor 110 can be a conventional processor that writes data to and requests data from the DRAM 130. The processor 110 can be a CPU, a GPU, or both. The processor 110 sends data writes and requests to the DRAM 130 through the memory controller 120. The memory controller 120 is configured to retrieve data units from the DRAM 130 for processing and send data units to the DRAM 130 for storage. The memory controller 120 can include a processor, a clock generator, and a data controller for communicating data units to the DRAM 130. The memory controller 120 can be included on a system on a chip (SOC), such as the NVIDIA® Tegra® line of processors from NVIDIA Corporation of Santa Clara, California, on an IC. The memory controller 120 can also be another type of electronic element or integrated circuit, such as other elements or circuits that lack a central processing unit (CPU) but have a memory interface. Some examples include integrated circuits such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). The processor 110 can be a conventional processor that writes data to and requests data from the DRAM 130. The processor 110 can be a CPU, a GPU, or both. The processor 110 sends data writes and requests to the DRAM 130 through the memory controller 120. The memory controller 120 is configured to retrieve data units from the DRAM 130 for processing and send data units to the DRAM 130 for storage. The memory controller 120 can include a processor, a clock generator, and a data controller for communicating data units to the DRAM 130. The memory controller 120 can be included on a system on a chip (SOC), such as the NVIDIA® Tegra® line of processors from NVIDIA Corporation of Santa Clara, California, on an IC. The memory controller 120 can also be another type of electronic element or integrated circuit, such as other elements or circuits that lack a central processing unit (CPU) but have a memory interface. Some examples include integrated circuits such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).

[0027] A data unit can generally be defined as a contiguous bit of data, such as a byte of data. A scrambled codeword can have its data unit scrambled, error bits scrambled, or both its data unit and error bits scrambled. Additionally, a scrambled codeword can store its data unit (whether scrambled or unscrambled) adjacent to or separate from the associated error correction bits (whether scrambled or unscrambled). A scrambled error correction bit can generally be defined as a set of error correction bits associated with a data unit, where the data unit can or can not have been previously scrambled, at least some of whose constituent bits are scrambled with other error correction bits associated with other data units, which can or can not have been previously scrambled. Memory controller 120 is configured to generate error correction bits in the event of an ECC to enable error correction when communicating data with DRAM 130. The error correction can be SECDED-based error correction. Memory controller 120 is configured to utilize a burst format of the ECC generator to improve handling of byte errors. In one example, memory controller 120 uses scrambling to distribute the 8 ECC bits of a 64 / 8 codeword among 4 data beats. Thus, as will be explained in greater detail below, in this example, no more than 2 bits are stored together in any single byte in DRAM 130 in any ECC calculation. This scrambling by memory controller 120 advantageously allows for detection of byte failures of DRAM 130 by an error correction code, such as a SECDED error correction code. Typically, SECDED codes do not guarantee detection of byte failures.

[0028] Advantageously, by scrambling as disclosed herein, error detection is improved without changing the decoding circuitry. In some embodiments, the scrambling by memory controller 120 (e.g., as disclosed in Figure 2B and Figure 2C Another advantage of the scrambling by memory controller 120 (e.g., as disclosed in

[0029] DRAM 130 includes portion 140 in which is stored at least one set of scrambled codewords received from memory controller 120. The set of scrambled codewords can be scrambled SECDED codewords, such as SECDED 64 / 8 codewords.

[0030] As will be discussed below, in one embodiment, memory controller 120 "scrambles" the error correction code portion (e.g., bits) of a codeword (e.g., a SECDED codeword) to create a scrambled codeword. In one example, the SECDED ECC is arranged in a 4 beat 64 / 8 data_ecc pattern.

[0031] Figure 2AA block diagram of a memory controller 200 constructed in accordance with the principles of the present disclosure is illustrated. For example, the memory controller 200 can be the memory controller 120 of Figure 1 FIG. 1. The memory controller 200 includes an ECC blender architecture 210, which will also be discussed with reference to Figure 2B and Figure 2C . The memory architecture 210, or at least a portion thereof, can be implemented in a processor of the memory controller 200. The memory controller 200 can also include additional components typically included in a memory controller, such as a clock generator.

[0032] In the ECC blender architecture 210, a data unit is received for processing and is passed to a memory for storage. The memory can be a DRAM, such as the DRAM 130, and will be used as an example. The data can be received from a processor, a cache, or other device (e.g., the processor 110 in Figure 1 In the illustrated embodiment, the data is received using multi-pulse on a 64-bit wide data bus, and the blending is performed in parallel. Other data bus widths can be used. The received data is then copied onto two parallel paths. A first copy of the data is sent as one or more data units to the DRAM via a first path 212. Via a second path 214, a coupled first data blender 220 blends the data, e.g., write data, as shown in Figure 2B and then forwards the blended data (i.e., one or more blended data units) to a coupled ECC generator 230.

[0033] The coupled ECC generator 230 creates error correction bits based on the error correction code for the blended data unit received from the first data blender 220. The error correction code can be created in accordance with a SECDED protocol, but other error correction codes can be used. One example of a result of such a protocol is 8 error correction bits for a 64 / 8 code word. In one embodiment, the coupled ECC generator 230 is four generators, or in another use, the same ECC generator 230 can be used four times in sequence.

[0034] The ECC blender 240 then receives the error correction bits from the ECC generator 230 and blends the error correction bits to provide blended error correction bits, which are also based on the blended data unit. From the ECC blender 240, the blended error correction bits are sent to a first region and a second region of the DRAM, respectively.

[0035] When data is read from the DRAM, the mixed error correction bits are sent to the ECC unmixer 250 where the mixed error correction bits are unmixed and sent to the ECC checker 270. Unmixing is the opposite of mixing. The second data mixer 260 receives the stored data units of the mixed codeword, where the data units themselves are not previously mixed in this embodiment, then mixes the data units, and then also sends the mixed data units to the ECC checker 270. The ECC checker 270 can be a SECDED checker. In one embodiment, the coupled ECC checker 270 is four error checkers, or in another use, the same ECC checker 270 is used sequentially four times.

[0036] The ECC checker 270 uses the previously unmixed error correction bits of the multiple mixed codewords and the recently generated mixed data units to generate checked error correction bits. As with a conventional ECC checker, the ECC checker 270 performs on the unmixed error correction bits and the mixed data units, but because of the previous mixing and unmixing, a more accurate result can be generated. The ECC checker 270 then sends the mixed data units to the data unmixer 280 to unmix the data units. The checked error correction bits are sent to remap 290 and from there to an error report, such as to report a SECDED status. The error report can be sent out from the ECC mixer architecture 210 for processing.

[0037] Figure 2B A four-tap burst diagram of original data 280 and mixed data 285 is illustrated. The original data 280 is a data unit of a 64 / 8 codeword. The original data 280 can be write data, and the mixed data 285 can be mixed data generated by the first data mixer 220 from the original data 285. The mixed data 285 represents a diagonal mix of the original data 280. To illustrate the data mix, one tap of the original data 280 is designated as data 282 and is represented as part of the mixed data 285.

[0038] The data mix in this example is a (base + 65) % 256 pattern:

[0039] Data_to_ecc_gen[63:0] = original_data[255, 190,..., 65, 0];

[0040] Data_to_ecc_gen[127:64] = original_data[63, 254,..., 129, 64];

[0041] Data_to_ecc_gen[191:128] = original_data[127, 253,..., 193, 128];

[0042] Data_to_ecc_gen[255:192] = original_data[191, 126,..., 1, 192].

[0043] However, other patterns for mixing can also be employed.

[0044] In the data mixer architecture 210, the data is mixed when generating or checking the error correction bits, although they are still considered part of the mixed codeword, unlike the mixed data of the ECC mixer architecture 310 (to be discussed below with respect to Figure 3 The data units being written to the DRAM can remain unmixed, however. This advantageously allows previously developed DRAM characterization patterns to continue to be used without any changes.

[0045] Furthermore, in the ECC mixer architecture 210, since the implementation of the data mixer architecture 210 does not mix the DQ bits to the DRAM, the error injection bits programmed will match the DQ pins. The hardware will report the error bits mapped into the correct DQ pins, so the location of the injected bits will match the location of the reported bits.

[0046] Figure 2C Examples of mixing of error correction bits occurring in the ECC mixer 240 are provided.

[0047] The mixed ECC can be from using four 64 / 8 codewords and the SECDEC protocol. The original error correction bits 290 and the mixed error correction bits 295 are illustrated. The single tap of the original error correction bits 290 is denoted 292 and identified in the mixed error correction bits 295 to illustrate the mixing. As Figure 2B shown, Figure 2C the mixing in is also diagonal mixing. In the mixer architecture 210, the first data mixer 220 mixes the data units before the ECC generator 230 receives and uses the mixed data units.

[0048] In the ECC mixer 240, the error correction bits of the multiple codewords are mixed among the ECC bits of the multiple codewords to allow the error correction bits to be distributed on different bytes of the DRAM, e.g., bytes corresponding to tap 0, tap 1, tap 2, tap 3 of the codeword error correction bits.

[0049] In a similar pattern to the mixing discussed with respect to Figure 2B each burst starts at its original bit index and then each 9th bit is used once. The bit sequence in each burst becomes a (base + 9) % 32 pattern, e.g.:

[0050] ecc_out[7:0] = original_ecc[31, 22, 13, 4, 27, 18, 9, 0];

[0051] ecc_out[15:8] = original_ecc[7, 30, 21, 12, 3, 26, 17, 8];

[0052] ecc_out[23:16] = original_ecc[15, 6, 29, 20, 11, 2, 25, 16];

[0053] ecc_out[31:24] = original_ecc[23, 14, 5, 28, 19, 10, 1, 24].

[0054] However, other mixing patterns can also be used.

[0055] Figure 3 A block diagram illustrating another example of a memory controller 300 constructed in accordance with the principles of the present disclosure is shown. The memory controller 300 includes an alternative embodiment of a data mixer architecture 310. Generally, in comparison to the data mixer architecture 210, the data mixer architecture 310 mixes data units for storage and mixes error correction bits based on an ECC code, and then stores the respective mixed codewords in an appropriate storage medium, such as a DRAM. Upon retrieval, both the mixed data and the mixed error correction bits are unmixed prior to ECC checking. However, the data units themselves that are used by the ECC generator 230 to generate the error correction bits are not mixed beforehand.

[0056] In the data mixer architecture 310, data units are received from a processor (such as the processor 110, a cache, or other device that generates or stores data). In the illustrated embodiment, the data is 64 bits wide, although other data widths are possible.

[0057] The data is then duplicated along two parallel paths. A first copy of the data is sent through a first path 312 to a data mixer 320 to be mixed and from the data mixer 320 to an appropriate storage device (e.g., a DRAM), in this embodiment the DRAM 130. Through a second path 314, a second copy of the data is sent to a coupled ECC generator 230, which then receives the data and creates an error code from the data, such as in accordance with a SECDED protocol. The error code can be an 8-bit ECC portion of a 64 / 8 codeword. The multiple error correction bits are then forwarded to an ECC mixer 240. The ECC mixer 240 mixes the multiple error correction bits of the mixed codeword. Both the mixed data units and the mixed error correction bits are forwarded to respective portions of a DRAM, such as the DRAM 130.

[0058] After retrieving data from the DRAM, the scrambled error correction bits of the scrambled codeword are then unscrambled in ECC unscrambler 250; the scrambled data units of the scrambled codeword are unscrambled in data unscrambler 330.

[0059] The unscrambled bits and unscrambled data units are checked in ECC checker 270. The unscrambled data units and ECC status are then sent out of data scrambler architecture 310, e.g., to a CPU, GPU, or cache, by ECC checker 270. In data scrambler architecture 310, data can be scrambled to help detect DRAM byte errors. The scrambling of data can follow a 64-bit pattern, e.g., the width of the data bus.

[0060] Figure 4A And Figure 4B Another aspect of data unit and error correction bit scrambling for low power double rate memory device (LPPDR) embodiments of DRAM 130 is illustrated. In Figure 4A And Figure 4B Each burst consists of 16 beats in

[0061] In contrast to 64-bit width and 4-length bursts on high bandwidth memory, LPPDR devices (LPPDR 4, LPPDR 4X, LPPDR 5, etc.) typically have a 16-bit lane width and a burst length of 16, as shown in Figure 2A And Figure 3

[0062] In LPPDR, there is no extra interface or memory bit for reading and writing error correction bits at the same time as data, referred to as “parallel ECC,” as employed in Figure 2A And Figure 3 Thus, “inline ECC” is implemented in various chips using LPDDR, as in In other words, a second memory access to read and write error correction bits is issued on a different address before or after reading and writing data. However, since error correction bits corresponding to ECC are much smaller than data, a 16-bit burst length (BL 16) read from the ECC area can cover many data reads. Typically, a 16-bit BL16 access is the smallest size allowed by DRAM.

[0063] The smallest size of a memory access at the system level is typically referred to as an “atom.” In chips using LPDDR, e.g., chip, the atom is 32 bytes, matching the smallest DRAM access. In this example embodiment, ECC is 4 bytes, so one ECC access can cover up to 8 data accesses.

[0064] ​Aspects of mixing schemes for high bandwidth memory (HBM) (such as...) Figure 2A and Figure 2B Similar to those discussed in [the document], this embodiment uses four SECDED ECC-stirred codewords, containing both stirred data units and stirred error correction bits. The error correction bits of these stirred codewords are striped diagonally in the burst, similar to the HBM embodiments discussed in ECC stirrer architectures 210 and 310. For example, see memory section 410, which shows [the data source]. Figure 4A The raw data 405, the mixed data unit, and the data from... Figure 4B The original ECC 415 was mixed with the error correction bit 420.

[0065] Similarly, with Figure 4B and Figure 4B Similar to SECDED as described in HBM, SECDED includes byte error detection and half-byte error correction. In fact, any consecutive 8-bit errors within a burst can be detected, and any consecutive 4-bit errors within a burst can be corrected. However, compared to... Figure 5 and Figure 2A Unlike HBM implementations, which transmit more than 4 bits per pin, LPDDR chips lack pin correction capability. They can correct any consecutive 4-bit errors on a pin and detect any consecutive 8-bit errors. Similar to... Figure 2A and Figure 6 In the HBM implementation, the data writing process can be maintained, and the data can be interleaved between the ECC encoder and decoder, but the error correction bits should be mixed before being written.

[0066] like Figure 3 and Figure 3 As shown, the layout of four groups of four mixed codewords is displayed, with each row belonging to one codeword. As mentioned above, ​ The ECC access includes enough error correction bits generated by ECC to cover 8 data accesses. ​ The entire ECC atom shown is transferred to and from DRAM, but only one 4-byte group (as shown) is used in conjunction with a single data access.

[0067] ​ This describes a method 500 for accessing data in memory using ECC and mixing the ECC to create multiple error correction bits for multiple SECDED mixed codewords. Method 500, or at least a portion thereof, may be derived from an ECC mixer architecture (e.g., ​ECC mixer architecture 210) is performed. The ECC mixer architecture can be part of a memory controller that is used to store data in memory (e.g., DRAM in method 500). Method 500 begins at step 505.

[0068] In step 510, bytes of the data unit are mixed. The mixing of the data unit can be, for example, between data bursts containing the data unit, and can be performed by a data mixer (e.g., first data mixer 220). The mixing can be vertical, horizontal, or diagonal.

[0069] In step 520, error correction bit generation is performed on the bytes of the data unit (such as the burst of mixed data unit) to create a plurality of codewords (e.g., by using SECDED). In one embodiment, there are four codewords, with the data unit and error bits. These can be formed, for example, by ECC generator 230.

[0070] In step 530, error correction bits of the plurality of codewords are mixed, the mixing being based in turn on previously mixed write data. The mixing of the error correction bits of the plurality of codewords creates a plurality of mixed codewords. The mixing of the error correction bits in step 530 can be performed by an ECC mixer (e.g., ECC mixer 240). In one embodiment, the mixing of the error correction bits occurs diagonally between the mixed codewords, such as four mixed codewords. Other types of mixing can also be used.

[0071] In step 540, the mixed error correction bits and the corresponding unmixed data units of the mixed codewords are stored in DRAM, such as DRAM 130. The unmixed data units can be stored, for example, in a first path 212. ​ As an example, the unmixed data units can be transferred to memory by first path 212. In step 550, the mixed error correction bits and corresponding unmixed data units of the plurality of mixed codewords are retrieved from the DRAM. The DRAM can be, for example, DRAM 130.

[0072] In step 560, the error correction bits of the plurality of mixed codewords are unmixed. The error correction bits can be unmixed using an ECC unmixer (e.g., ECC unmixer 250).

[0073] In step 570, the unmixed retrieved data units of the mixed codewords are subsequently mixed. In step 570, the mixing can be performed using a data mixer, such as second data mixer 260.

[0074] In step 580, error correction and / or error detection is performed using the interleaved data units and the de-interleaved ECC bits. Error code check information generated from step 580 can be transferred for further processing. For example, an ECC checker such as the ECC checker 270 disclosed herein can be used in step 580, and the results sent to the remap error bit logic 290.

[0075] The method 500 continues to step 590, where the interleaved data units are de-interleaved. The de-interleaved data can be de-interleaved and transferred for further processing. For example, the data can be de-interleaved by the data de-interleaver 280 and transferred outside the memory controller in response to a read request. The method ends at stop step 595.

[0076] ​ A method 600 is described for accessing data in a memory using ECC and interleaving data units of a plurality of SECDED codewords to create a SECDED interleaved codeword. The method 600, or at least a portion thereof, can be performed by an ECC interleaver architecture, such as the ECC interleaver architecture 310 in ​ The ECC interleaver architecture can be part of a memory controller for storing data in a memory, such as the DRAM in the method 600. The method 600 begins at start step 605.

[0077] In step 610, data of a plurality of data units is interleaved and stored. This can be performed by the data interleaver 320. The interleaving can be vertical, horizontal, or diagonal.

[0078] In step 620, error correction bits are generated from data units that are not interleaved. The ECC generator, such as the ECC generator 230 of the ECC interleaver architecture 310, can generate the error correction bits.

[0079] In step 630, the error correction bits are interleaved. The interleaving can be one of the various types of interleaving described herein. The ECC interleaver, such as the ECC interleaver of the ECC interleaver architecture 310, can perform the interleaving.

[0080] In step 640, the interleaved error correction bits generated from the non-interleaved data units and the interleaved data units of the interleaved codeword are stored in a DRAM. The DRAM can be a memory, such as the DRAM 130.

[0081] In step 650, the dis-galted data units of the dis-galted error correction bits and dis-galted codewords generated from the un-galted data are retrieved from the DRAM. In step 660, the dis-galted data units of the retrieved dis-galted codewords are de-galted. A data de-galter (e.g., data de-galter 330) can be used to de-galt the dis-galted data units.

[0082] In step 670, the retrieved error correction bits of the dis-galted codewords are de-galted. De-galter can be performed using an ECC de-galter (e.g., ECC de-galter 250) in the ​

[0083] In step 680, error correction and / or error detection is performed using the de-galted data units and the de-galted ECC bits of the codewords. An ECC checker (e.g., ECC checker 270) can perform the error correction and / or detection.

[0084] In step 690, the de-galted data units are forwarded. For example, the de-galted data units can be transferred outside the memory controller in response to a read request. After this step, the method 600 proceeds to stop step 695 and ends.

[0085] A portion of the devices, systems, or methods described above can be embodied in or performed by various digital data processors or computers, whether part of a general purpose computer system or part of an integrated circuit or chip. The software that enables the computer or data processor to perform the steps described above can be stored on or downloaded from computer-readable media. Such instructions are depicted in this document by reference to means for carrying out the functions described above, which are part of the systems described above. These instructions can be read and executed by a computer or data processor to perform the functions described above. The instructions can be combined on a computer-readable medium with other instructions, which when executed by the computer or data processor, cause the computer or data processor to perform various example methods of the present disclosure. The instructions can provide proper functionality for the autonomous vehicle and other systems described above and enable a processor or digital data processor to implement parts of the present disclosure. The software that enables the computer or data processor to perform the steps described above can be stored on or downloaded from computer-readable media.

[0086] Portions of the disclosure can be directed to computer storage products with a non-transitory computer-readable medium having stored thereon program code means for performing various computer-implemented operations, including a portion of a device, apparatus, or steps of a method described herein. Non-transitory, as used in this document, is intended to cover all computer-readable media excluding transitory, propagating signals. Examples of non-transitory computer-readable media include, but are not limited to: magnetic media, such as diskettes, hard disks, and magnetic tape; optical media such as compact disks, DVDs, and holographic media; magneto-optical media such as optical disks and floptical disks; and hardware devices that are specially configured to store and execute program code, such as application specific integrated circuits, programmable logic devices, and hard-wired devices. Examples of program code include both machine code produced by a compiler and higher level code, such as assembly language code, that is executed by the computer using an interpreter.

[0087] ​Those skilled in the art having the benefit of the teachings within this application will appreciate that other and further additions, deletions, substitutions, and modifications can be made to the described embodiments.

Claims

1. An error correcting code (ECC) apparatus comprising: a first data mixer configured to exchange bits among a plurality of data units to form a plurality of mixed data units, wherein the exchange of bits includes exchanging bits among different data units at a same bit position; an ECC generator configured to generate a plurality of error correction bits, at least one of the plurality of error correction bits resulting from the plurality of mixed data units received from the first data mixer; and an ECC mixer configured to exchange bits among the plurality of error correction bits to form a plurality of mixed error correction bits, and thereby form a plurality of mixed codewords, wherein each mixed codeword includes one of the plurality of data units and at least one of the plurality of mixed error correction bits.

2. The ECC apparatus of claim 1, wherein the ECC mixer is configured to mix the plurality of error correction bits as a (base+9) % 32 pattern.

3. The ECC apparatus of claim 1, wherein the first data mixer is configured to mix the data units as a (base+65) % 256 pattern.

4. The ECC apparatus of claim 1, further comprising: a first dynamic random access memory (DRAM) region for storing the plurality of data units of the plurality of mixed codewords; and at least a second DRAM region for storing the plurality of mixed error correction bits of the plurality of mixed codewords.

5. The ECC apparatus of claim 4, further comprising a second data mixer configured to mix the plurality of data units of the plurality of mixed codewords, wherein the plurality of data units are retrieved from the first DRAM region.

6. The ECC apparatus of claim 5, further comprising an ECC unmixer configured to unmix the plurality of mixed error correction bits of the plurality of mixed codewords to generate a plurality of unmixed error correction bits.

7. The ECC apparatus of claim 6, further comprising an ECC detector configured to check for and / or detect a single error condition and / or a double bit error condition from use of the plurality of mixed data units of the second data mixer and the plurality of unmixed error correction bits of the ECC unmixer.

8. The ECC apparatus of claim 1, wherein the plurality of mixed codewords is four mixed codewords.

9. The ECC apparatus of claim 1, wherein the error correcting code is a SECDED error correcting code.

10. A memory controller employing error correcting code (ECC) comprising: a data mixer configured to generate a plurality of mixed data units from a plurality of data units; an ECC generator configured to generate a plurality of error correction bits from the plurality of data units; and an ECC mixer configured to exchange bits among the plurality of error correction bits to form a plurality of mixed error correction bits, and thereby form a plurality of mixed codewords, wherein each mixed codeword includes one of the plurality of data units and at least one of the plurality of mixed error correction bits. an ECC blender configured to generate a plurality of blended error correction bits from the plurality of error correction bits by swapping bits between the plurality of error correction bits, wherein the swapping of bits includes swapping bits between different error correction bits at the same position, thereby forming a plurality of blended codewords, wherein each blended codeword includes one of a plurality of blended data units and at least one blended error correction bit of the plurality of blended error correction bits.

11. The memory controller of claim 10, wherein the ECC blender is configured to blend the plurality of error correction bits as a (base+9) % 32 pattern.

12. The memory controller of claim 10, wherein the data blender is configured to blend the plurality of data units as a (base+65) % 256 pattern.

13. The memory controller of claim 10, further comprising a data unblender configured to unblend the plurality of blended data units stored in a first dynamic random access memory (DRAM) region to generate a plurality of unblended data units.

14. The memory controller of claim 13, further comprising an ECC unblender configured to unblend the plurality of blended error correction bits stored in a second DRAM region to generate a plurality of unblended error correction bits.

15. The memory controller of claim 14, further comprising an ECC detector configured to correct a single error condition and / or detect a double bit error condition using the plurality of unblended data units and the plurality of unblended error correction bits when one of the error conditions exists.

16. A method of data storage, comprising: blending a plurality of data units to generate a plurality of blended data units; performing an error correction code on the blended data units to create a plurality of error correction bits; swapping bits between the plurality of error correction bits to generate a plurality of blended error correction bits, wherein the swapping of bits includes swapping bits between different error correction bits at the same position; storing the plurality of data units and the plurality of blended error correction bits, wherein the storing creates a plurality of blended codewords.

17. The method of claim 16, further comprising unblending the plurality of blended error correction bits of the plurality of blended codewords to generate a plurality of unblended error correction bits, wherein the plurality of blended error correction bits are stored in and retrieved from a dynamic random access memory (DRAM).

18. The method of claim 17, further comprising blending the plurality of data units of the plurality of blended codewords to generate a plurality of blended data units, wherein the plurality of data units are stored in and retrieved from the DRAM.

19. The method of claim 18, further comprising performing error correction and / or error detection on the plurality of blended data units and the plurality of unblended ECC bits.

20. The method of claim 19, further comprising de-agglomerating the agglomerated data units to generate a plurality of de-agglomerated data units, and transmitting the plurality of de-agglomerated data units in response to a read request of a memory.

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