Neuronal circuits

Abstract

A self-synchronizing (or self-oscillating) modulator in signal processing is described which, similar to a ΣΔ modulator, has particular application in the design of neural networks based on such modulators. A system of multiple self-synchronizing modulators and supporting structures can be configured to perform computations similar to those of an analog computer (e.g., a neural network) at lower power and smaller size than digital implementations. Such a system constructed using the present method does not require a sequential solution, but converges to a solution in a single step; unlike typical prior art, such a system therefore does not require a clock, and operates asynchronously in a manner similar to a conventional analog computer. The self-synchronizing modulator can be used as a neuron in a neural network, which receives a product-sum signal and generates an output stream representing the product-sum similar to the output stream of a ΣΔ modulator, and potentially also includes an activation function and an offset.

Description

[0001] This application claims priority to Provisional Application No. 62 / 817,395, filed on March 12, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates generally to sigma delta (ΣΔ) modulators, and more particularly to the use of sigma delta modulators as self-clocking circuits. In particular, the present invention relates to self-clocking modulators as simulated neurons. Background Art

[0003] Digital computers are configurable and can therefore be programmed to perform neural network calculations. The ability to integrate thousands of multipliers and adders (MACs for multipliers and accumulators) on a digital chip can enable cost-effective implementations of speech recognition, handwriting analysis, etc.

[0004] Digital computers operate synchronously, that is, the state variables of a digital computer advance from time to time under the control of a clock, which is a digital signal shared by all elements of the computer to ensure that the state variables advance in lockstep.

[0005] In this synchronous environment, the execution of an algorithm on state variables results in the creation of a desired output, which typically requires multiple clock cycles to complete. Thus, digital computers typically proceed through a finite sequence of clock cycles to achieve the programmed goals determined by the algorithm.

[0006] One of the most time-consuming and difficult aspects of creating a digital computer is configuring the distribution of a clock signal to all of the components of the computer that require it. Routing the clock to all of the elements of a digital computer that must remain in lockstep with each other consumes considerable power. In the known art, such clock design is supported by tools created specifically for this purpose; for example, clock "trees" are used to maintain time synchronization, clock "gating" is used to save power, and timing analysis after chip construction is a critical step in the successful manufacture of silicon chips that require clock signals.

[0007] In contrast, analog computers operate asynchronously; their state variables are the voltages and currents in the network. A simulated network—which has a configuration designed to provide a desired solution to a problem—converges to a result determined by that configuration because the network is constrained by Kirchhoff's current law so that its only consistent state is a simulation of the problem to be solved.

[0008] In an analog computer, there is usually no clock or anything resembling a clock, nor are there any intermediate states in the progression toward a solution. A solution in an analog computer occurs in a single event; while an analog computer can have a transient response, that transient response is from an initial state to a final solution.

[0009] Neural networks are a computing paradigm. Neural networks are interesting because they can solve problems in a manner similar to artificial intelligence (AI). Neural networks that implement AI can be trained, that is, can be adjusted so that the network solves problems.

[0010] The neural network computing paradigm can be encoded into an algorithm that executes on a digital computer, or it can be embedded in an analog computer. Analog computer implementations of neural networks generally have some advantages over digital implementations, at least one of which is the absence of a clock. Analog implementations are also generally faster and consume less power.

[0011] However, analog computers may not be easily programmable. In addition, some automated construction tools, such as the Verilog hardware description language and placement and routing tools, that are available for digital circuit design are not available for analog computers.

[0012] It would be desirable to be able to combine some aspects of analog computer implementations (eg, low power and absence of clocks) with the programmability of digital neural networks. Summary of the invention

[0013] This application describes the use of self-synchronizing modulators as devices for simulating neurons used in neural networks.

[0014] One embodiment describes a neuron circuit for use in a neural network, the neuron circuit comprising: a weighting circuit configured to receive a plurality of input signals and generate a product-sum signal by weighting each of the input signals and adding the weighted input signals together; and a self-synchronizing circuit configured to receive the product-sum signal and generate a quantized output signal representing the product-sum signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram of a sigma delta modulator known in the art.

[0016] Figure 2 is a diagram of a self-synchronizing modulator according to one embodiment.

[0017] Figure 3 is a diagram of a self-synchronizing modulator according to another embodiment.

[0018] Figure 4is a diagram of neurons that may be used in a neural network, according to one embodiment.

[0019] Figure 5 is a diagram of neurons that may be used in a neural network according to another embodiment.

[0020] Figure 6 According to one embodiment, Figure 5 The neuron shown in FIG. 5 is a schematic diagram of an implementation of a neuron similar to that of FIG. DETAILED DESCRIPTION

[0021] Described herein is the use of self-clocked (or self-oscillating) modulators in signal processing, similar to sigma delta (ΣΔ) modulators, particularly in the design of neural networks based on such modulators. Systems of multiple self-synchronizing modulators and supporting structures can be configured to perform computations similar to those of analog computers, such as neural networks, at low power and small size compared to digital implementations. Such systems constructed using the present method do not require sequential solutions, but converge on a solution in one step; unlike typical prior art, it therefore does not require a clock and operates asynchronously in a manner similar to conventional analog computers. The description herein uses neural networks as examples, but the present method is not limited to such use cases.

[0022] In the present method, a self-synchronous modulator can be used as a neuron in a neural network; it receives a sum-of-products signal and generates an output stream representing the sum-of-products similar to the output stream of a ΣΔ modulator, potentially also including an activation function and an offset.

[0023] ΣΔ modulators are characterized by a set of discrete output quantities expressed on as few as one bit, where a signal is applied to the discrete outputs. ΣΔ modulators are sometimes called "noise shaping" devices because the output sequence of discrete quantities can be thought of as having noise added to the signal. Noise in this analysis is the amount that must be added to the analog quantity to make the output occupy one of the discrete levels. (ΣΔ modulators are sometimes called delta-sigma (ΔΣ) modulators; in some places, they may also be called delta (Δ) modulators, although in many places, such as the United States, delta modulators are considered to have a slightly different function.)

[0024] For example, a single bit ΣΔ modulator accepts a nominal continuous input in the range -1 to 1, and outputs a quantized signal that can be represented as two states, -1 or 1. The number of times -1 or 1 occurs is such that the average of the output represents the value of the input signal. In this example, if the input signal is 0, the output is:

[0025] -1 1 -1 1 -1 1.

[0026] It will be seen that this is a sequence of quantized values ​​whose average is equal to the input signal, i.e. 0. However, since there is no 0 output, "noise" of either 1 or -1 is added to the input to produce each output value.

[0027] This “noise shaping function” of a ΣΔ modulator can also be seen in another example. If the single bit ΣΔ modulator above is used to encode an input of 0.5, the output sequence may be:

[0028] -1 1 1 1 -1 1 1 1 -1 1 1 1 etc.

[0029] It will be seen that the sequence has an average value of 0.5, i.e. 3 / 4 of the range from -1 to 1 is 0.5 and equal to the input. Furthermore, "noise" has been added to the input in sequence, i.e. values ​​of -1.5, 0.5, 0.5, 0.5, etc. are added in sequence to the input value of 0.5 to obtain a discrete output sequence from the ΣΔ modulator.

[0030] Considering the ΣΔ modulator in this way, i.e. as a device that adds noise to a continuous signal in a way that generates a sequence of discrete outputs, the frequency domain characteristics of the noise can be analyzed. Such analysis is known in the art.

[0031] Those skilled in the art often refer to the "order" of noise shape in the frequency domain. A first order ΣΔ modulator or "first order noise shaper" has a noise that increases by 6 decibels (db) per octave (or equivalently, 20 db per decade or something of that order). A second order noise shaper has a region where the noise increases by 12 db per octave, etc. Some forms of ΣΔ modulators have zeros in the noise, i.e., they have a noise spectrum that nominally goes to zero at a particular frequency.

[0032] In addition to the quantization in amplitude required for the discrete output amplitudes of the ΣΔ modulator, there is also an implicit quantization in time. Elements of the quantized output change at discrete and generally predictable times. In the prior art, as in a typical digital system, the quantization in time of the ΣΔ modulator is achieved by using a clock signal, a digital event at the specific time at which the ΣΔ modulator switches between discrete output levels.

[0033] Those skilled in the art will appreciate that systems using ΣΔ modulators can have physically fewer interconnects, since the sigma delta encoded signal can be transmitted using only one wire. Furthermore, certain mathematical operations are convenient in the ΣΔ signal domain; in particular, multiplications require few resources and summations can be easily implemented. These observations provide motivation for using ΣΔ devices as elements of neural networks.

[0034] In the prior art, ΣΔ modulators usually require a clock. In this method, the ΣΔ modulator operates as a neuron in a digital neural network without a clock. The programmability of the digital neural network is maintained, and the low power and smaller size of the analog neural network are achieved using signals on a single line, and no clock is required.

[0035] Figure 1 1 is a diagram of a prior art ΣΔ modulator 100. Differential element 102 compares input signal Ain with a quantized feedback signal from the Q output of quantizer 104; quantizer 104 may be, for example, a D-type flip-flop (DFF). Filter 106 operates on the output of differential element 102 and drives to the D input of quantizer 104.

[0036] Each clock edge provided by the clock signal Clk will cause the quantizer 104 to update the Q output to a high level if the input at D is high and to a low level if the input at D is low. Therefore, since the filter 106 is typically an integrator with a 1 / s characteristic as part of the transfer function, the average value of the Q output of the quantizer 104 must be equal to the input signal Ain.

[0037] Figure 2 is a diagram of a self-synchronizing modulator 200 according to one embodiment of the present method. Figure 1 In the quantizer 104 of the ΣΔ modulator 100 in FIG. 1 , the amplifier 204 has high gain but limited output; for example, the Texas Instruments OPA699 voltage-limiting amplifier is considered to have these characteristics. In the present method, the amplifier 204 has a transfer characteristic similar to the following:

[0038] Out = min(max(In*G), 1), -1) (Equation 1)

[0039] where G is much larger than 1. This indicates that, although the amplifier 204 has a high gain, the output Q of the modulator 200 is limited to 1 and -1.

[0040] If the filter 206 has a low-pass characteristic, that is, the gain remains finite at direct current (DC) but the phase margin is insufficient to remain stable, the system will oscillate and the output Q will be observed to be at -1 or 1 (the limits of equation 1). Therefore, the modulator 200 is essentially quantized due to the high gain, jumping between the upper and lower limits of the power supply. However, because the differential element 202 drives the filter 206 using the difference between Q and Ain, the modulator 200 has the same desired characteristics as a ΣΔ modulator, without an explicit clock. Specifically, the output Q is a sequence of discrete outputs, one of -1 or 1, whose timing is determined by the stability (or more accurately, lack of stability) characteristics of the loop in the modulator 200.

[0041] Those skilled in the art will recognize how the phase margin of a circuit, as taught by, for example, the Bode stability criterion, determines its stability, and will be able to determine whether a given circuit of this type is stable or unstable.

[0042] Figure 3 A self-synchronizing modulator 300 according to another embodiment of the present method is shown. In the modulator 300, the lack of stability is not caused by the stability criteria of the loop, but by the presence of hysteresis around the high gain amplifier 304.

[0043] as Figure 2 Modulator 300 has a differential element 302 that compares the input signal Ain with the quantized feedback Q output, a low pass filter 306, and a high gain amplifier 304. However, there is an adder 308 that adds a Q-based component to the filtered differential output of the differential element 302. A second amplifier 310 in the loop provides the Q-based component to the adder 308; the amplifier 310 multiplies the Q output by a gain k.

[0044] The gain k of amplifier 310 is finite but small; for example, the gain k can be as small as 0.0001. This is enough to prevent the loop from converging to a stable solution regardless of the phase margin, and thus the output Q will oscillate between the limits of 1 and -1, and again create a ΣΔ modulator-like output sequence.

[0045] Note that Figure 2 and Figure 3 In circuits 200 and 300, the oscillations between upper and lower limits (here 1 and -1) are not necessarily regular and are not constrained to a particular frequency, but rather the circuits operate at a duty cycle that produces an average output value such that the input to filter 206 or 306, respectively, is 0. How much time the circuit spends at each output value again depends on the input.

[0046] Figure 4 is a diagram of a neuron 400 that may be used in a neural network according to one embodiment of the present method, which illustrates how a self-synchronizing modulator may be used within a neural network. Neuron 400 includes a self-synchronizing modulator 412 as described above; for example, self-synchronizing modulator 412 may be Figure 2 The circuit 200 or Figure 3 Circuit 300, or some circuit similar to circuits such as those discussed elsewhere in this document.

[0047] Respectively Figure 2 The self-synchronizing modulator 200 and Figure 3As with the self-synchronizing modulator 300 of FIG. 1 , there is no clock. The output signal is discrete and can be expressed on a single line, as compared to digital systems that require more than one line to express digital quantities other than a single bit thereon.

[0048] If the neurons are used for analog addition of weighted signals as shown, positive and negative quantities are easily represented. Figure 4 Three inputs A1, A2 and A3 are shown, but any number of inputs Ai are possible; these are assumed to be digital values ​​(perhaps as a result of the previous self-synchronizing circuit); in this context, they are conceptually 1 or -1, and can be represented as -1 volt and +1 volt.

[0049] Impedance elements R1, R2, and R3 are adjustable impedances that provide weights to the values ​​of inputs A1 to A3. In one embodiment, the values ​​of impedance elements R1 to R3 can be programmed by signals on W1, W2, and W3 buses, respectively. (For any number of inputs Ai, there are typically an equal number of impedances Ri and control buses Wi.)

[0050] In the illustrated embodiment, the least significant bit (LSB or zeroth bit) of the bus is used to change the sign of the input signals A1, A2, and A3 to the exclusive OR (XOR) gates X1, X2, and X3 when necessary, and the bits in the signal other than the LSB are used to change the impedance value. (Again, assume that each input signal A1, A2, and A3 is 1 or -1; in some cases, the weights to be applied to these inputs may be negative, thus requiring a sign change.) The only analog signal in neuron 400 is the input to self-synchronous modulator 412, which is the analog sum of the product of the Ai signal and the Wi signal.

[0051] The portion of circuit 400 that includes impedance elements R1, R2 and R3, XOR gates X1, X2 and X3, and control buses W1, W2 and W3 (for a certain number n of input values, these can be generalized as Rn, Xn and Wn) includes a weighting circuit because, as is known in the art, each input signal is given a weight by its associated resistor and the weighted inputs are then connected to a common point, i.e., summed to become a product sum signal.

[0052] Figure 5is a diagram of a neuron 500 that can be used in a neural network according to another embodiment. The self-synchronous modulator portion 512 of the neuron 500 now includes three inverters U1, U2 and U3, capacitors C1 and C2, and a feedback resistor R4. The threshold voltage of inverter U1, i.e., the point at which inverter U1 switches its output, defines a zero voltage level. Nominally, the threshold voltage of inverter U1 will be half the voltage of the power supply. The first inverter U1 receives a product-sum signal from a weighted circuit portion of the neuron 500, which also includes impedance elements R1, R2 and R3, XOR gates X1, X2 and X3, and control buses W1, W2 and W3. The first inverter U1 also receives capacitive feedback from capacitor C1, resistive feedback from resistor R1, and capacitive grounding from capacitor C2. The second inverter U2 produces a second inverted signal, and the third inverter U3 produces a quantized output signal.

[0053] Capacitor C2 is an integrating capacitor in the first order ΣΔ modulator; one end of capacitor C2 is connected to all weighted inputs from resistors R1, R2 and R3 at point 514 and thus receives the sum of the weighted inputs. The other end of capacitor C2 is connected to ground, providing capacitive grounding.

[0054] Without feedback capacitor C1, self-synchronous modulator 512 is almost unstable, but may not actually be unstable due to the variability of the inverter. To ensure instability, capacitor C1 provides positive capacitive feedback and hysteresis, pulling the input of inverter U1 high when the output of inverter U2 goes high, and thereby ensuring instability.

[0055] The output signal Y is a digital signal suitable for application to the input of the next neuron layer. Due to the resistive feedback through resistor R4, the average value of the output signal Y maintains the value at point 514 (also the input to inverter U1) near the threshold voltage of inverter U1.

[0056] Based on the teachings herein, one skilled in the art will note that if the power supply for inverter U1 is wired separately from the other inverters, then that power supply will be used to adjust the threshold of the circuit, thereby achieving the offset typically required in neural networks. This can be considered a slightly more practical implementation using a unipolar power supply, with the two logic levels represented as, for example, 0 volts and 1 volt. In this case, Figure 5 The self-synchronizing modulator 402 in can be modified to include Figure 6 Offset shown.

[0057] Figure 6 is similar to Figure 5 Schematic diagram of an implementation of neuron 600 of neuron 500 shown in FIG. Figure 6 The first inverter 616 ( Figure 5 A separate power supply B of U1 in circuit 500 of FIG. 5 acts as an offset. The offset is believed to help the circuit converge to a solution in AI applications. (The offset can be provided in other ways; for example, signal A3 and resistor R3 can be controlled to provide an offset, but such modifications to the input signal and weighted impedance to provide an offset are believed to be uncommon in AI applications.)

[0058] In neuron 600, transistor M3 and transistor M4 form a second inverter 618 (equivalent to Figure 5 Inverter U2 in FIG. 1 ), while transistor M5 and transistor M6 form a third inverter 620 (equivalent to Figure 5 The capacitor C2 also receives the sum of the weighted input signals from the XOR gates X1, X2 and X3. Feedback is also provided from the node between the second inverter 618 and the third inverter 620 through the capacitor C1.

[0059] Neuron 600 also illustrates how an activation function may be implemented. Activation circuit 622 includes transistors M7 and M8 and resistors R4A and R4B. Figure 5 Compared to the feedback resistor R4 in the circuit 500 of FIG. 5 , in the neuron 600, feedback is provided by resistors R4A and R4B. The node between resistors R4A and R4B is connected to the input of the first inverter 616 and the product-sum signal, and the gates of transistors M7 and M8 are connected to the output of the second inverter 618 and the input of the third inverter 620.

[0060] If resistor R4A and resistor R4B have the same value, they perform the same Figure 5 4A and R4B have the same function as resistor R4 in FIG. However, if resistor R4A and resistor R4B have different values, the feedback from transistor M7 can be different from the feedback from transistor M8; one transistor can even provide positive feedback while the other provides negative feedback. Thus, resistors R4A and R4B can provide nonlinear feedback and define the nonlinear activation function of neuron 600 as needed for neuron 600 to work properly in an AI application.

[0061] like Figure 6As shown, transistors M1, M3, M5, and M7 are P-type metal oxide semiconductor field effect transistors (P-type MOSFETs), while transistors M2, M4, M6, and M8 are N-type metal oxide semiconductor field effect transistors (N-type MOSFETs). Those skilled in the art will appreciate that other arrangements and / or other numbers of transistors may be used to achieve the same or similar results as neuron 600.

[0062] According to the teachings herein, it will be clear to those skilled in the art that according to the present method, in particular according to Figure 6 The circuit of the embodiment configuration shown can be made into a unit suitable for use with existing digital location and routing systems. This benefit exists because all input and output signals are digital signals. The programmable resistor and associated XOR gate may be one layout unit, while the self-synchronous modulator is another layout unit. The B voltage can be globally routed to a common voltage.

[0063] Alternatively, it will be apparent to those skilled in the art from the teachings herein that an AI compiler corresponding to known Verilog fine-grained processing or RAM compiler methods can be applied to the present method so that any arbitrary analog AI neural network can be created programmatically.

[0064] By combining these features, a neural network can be constructed according to the present method that reduces both the number of components and the amount of power consumed. Those skilled in the art will appreciate that a neural network of any complexity can be constructed according to these principles, and other circuits can be constructed similarly.

[0065] The disclosed system has been described above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art from this disclosure. Certain aspects of the described methods and apparatus may be readily implemented using configurations other than those described in the above embodiments or in combination with elements other than or in addition to the above elements.

[0066] For example, as is well known to those skilled in the art, various options will be apparent to those skilled in the art. In addition, the illustrations of transistors and associated feedback loops, resistors, etc. are exemplary; those skilled in the art will be able to select the appropriate number of transistors and related components suitable for a particular application.

[0067] The present disclosure is intended to cover the above-described and other variations on the embodiments, with the present disclosure being limited only by the following claims.

Claims

1. A neuron circuit for use in a neural network, the neuron circuit comprising: a weighting circuit configured to receive a plurality of input signals and to generate a sum-of-products signal by weighting each of the input signals and adding the weighted input signals together; as well as a self-synchronizing circuit configured to receive the product-sum signal and to generate a quantized output signal representative of the product-sum signal, Wherein, the self-synchronization circuit further includes: a difference element configured to determine a difference between the product-sum signal and the quantized output signal; a filter configured to filter the difference between the product-sum signal and the quantized output signal; a high gain amplifier configured to amplify the filtered difference between the product-sum signal and the quantized output signal, thereby generating the quantized output signal, or Wherein, the self-synchronization circuit further includes: a difference element configured to determine a difference between the product-sum signal and the quantized output signal; a filter configured to filter the difference between the product-sum signal and the quantized output signal; an adder configured to add the filtered difference between the product-sum signal and the quantized output signal to the amplified quantized output signal; a first amplifier configured to amplify a sum of the filtered differences between the product-sum signal and the quantized output signal, thereby generating the quantized output signal; and a second amplifier configured to amplify the quantized output signal, or Wherein, the self-synchronization circuit further includes: a fourth inverter configured to invert the sum of the product-sum signal, the capacitive feedback, the resistive feedback, and the capacitive ground, thereby generating a first inverted signal; a fifth inverter configured to invert the first inverted signal to thereby generate a second inverted signal; a third capacitor coupled at a first terminal to the second inverted signal and at a second terminal to the product-sum signal, thereby generating the capacitive feedback; a sixth inverter configured to invert the second inverted signal, thereby generating the quantized output signal; a resistor coupled at a first terminal to the quantized output signal and at a second terminal to the product-sum signal, thereby generating the resistive feedback; and a fourth capacitor coupled at a first terminal to the product-sum signal and at a second terminal to ground, thereby generating the capacitive ground, or Wherein, the self-synchronization circuit further includes: a first inverter configured to invert the sum of the product-sum signal, the capacitive feedback, the resistive feedback, and the capacitive ground, thereby generating a first inverted signal; a second inverter configured to invert the first inverted signal to thereby generate a second inverted signal; a first capacitor coupled at a first terminal to the second inverted signal and at a second terminal to the product-sum signal, thereby generating the capacitive feedback; a third inverter configured to invert the second inverted signal, thereby generating the quantized output signal; a second capacitor coupled to the product-sum signal at a first end and to ground at a second end, thereby generating the capacitive ground; and An activation circuit comprising: a first transistor having a source connected to a power supply, a gate connected to an output port of the second inverter, and a drain; a first resistor having a first resistance having a first end connected to the drain of the first transistor and a second end connected to the input port of the first inverter; a second transistor having a source connected to ground, a gate connected to the output port of the second inverter, and a drain; and A second resistor has a second resistance and has a first end connected to the drain of the second transistor and a second end connected to the input port of the first inverter, whereby the activation circuit enables the neuron circuit to have a nonlinear activation function.

2. The neuron circuit according to claim 1, wherein: The first amplifier is a high gain, limited output amplifier.

3. The neuron circuit according to claim 1, wherein: Each of the first inverter, the second inverter, and the third inverter includes: a first transistor having a source connected to the power supply section, a gate connected to the input port, and a drain connected to the output port; and A second transistor has a drain connected to the drain of the first transistor and the output port, a gate connected to the input port, and a source connected to the ground.

4. The neuron circuit according to claim 3, wherein: The first transistor of the activation circuit and each inverter is a P-type metal oxide semiconductor field effect transistor, and the second transistor of the activation circuit and each inverter is an N-type metal oxide semiconductor field effect transistor.

5. The neuron circuit according to claim 1, wherein: The first inverter is connected to a first power supply section, and the second and third inverters and the activation circuit are connected to a second power supply section.

6. The neuron circuit according to claim 1, wherein: The weighting circuit further includes a plurality of impedance elements, each impedance element having a first end and a second end, the first end being configured to receive a different input signal among the plurality of input signals, the second ends of the plurality of impedance elements being connected together.

7. The neuron circuit according to claim 6, wherein: Each of the impedance elements has an impedance that can be adjusted by a control signal.

8. The neuron circuit according to claim 7, wherein: The weighting circuit further includes: a plurality of XOR gates, each XOR gate having a first input port configured to receive a different one of the plurality of input signals and a second input port configured to receive a control signal; A plurality of impedance elements, each impedance element having a first end and a second end, the first end being connected to an output port of a different XOR gate among the XOR gates, and the second ends of the plurality of impedance elements being connected together.

9. The neuron circuit according to claim 8, wherein: The control signal instructs the XOR gate to invert the input signal received at a first input port of the XOR gate or not to invert the input signal received at the first input port of the XOR gate.

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