An improved electronic synaptic circuit and neural network circuit based on ferroelectric transistors

Abstract

The present application relates to a neural network circuit, including a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit includes at least a switch unit, an input unit and a weight calculation unit. The present application also relates to an electronic system and an electronic device including the aforementioned neural network circuit.

Description

Technical Field

[0001] The present application relates to the field of neural network circuit design, and in particular to an electronic synapse circuit and a neural network circuit based on ferroelectric transistors. Background Art

[0002] With the rapid development of information technology industries such as artificial intelligence and big data, people's social production and daily life have higher and higher requirements for computer processing speed and performance. The amount of data that computers need to process is growing exponentially, which has brought unprecedented pressure on data storage and computing. The most commonly used computer architecture at present is the traditional von Neumann architecture, which has the characteristics of storage and computing separation. Data needs to be frequently migrated between storage units and computing units, which not only greatly reduces the computing speed, but also greatly increases the power consumption of computing.

[0003] In order to solve the problems of the von Neumann architecture, people have proposed an architectural approach to neuromorphic computing based on bionics. By imitating the connection between neurons and synapses in the brain, neuroscience theoretical modeling is completed to solve complex computing problems that cannot be processed at high speed in traditional architectures. The LIF neuron model is one of the most basic models commonly used in neuromorphic computing architectures. Its essence abstracts neurons into capacitors and converts the way neurons communicate into action potentials and pulses. In the LIF neuron model, the potential of the electrical signal input to the neuron and the stability of the final output pulse are both core factors that can improve the stability and processing speed of the neuron model.

[0004] As an emerging computing paradigm, if the behavior of neurons or synapses is simulated at the physical level through hardware circuits, neuromorphic computing with low power consumption and high computing performance can be achieved. Therefore, choosing a reasonable computing method and designing and building hardware circuits are also important issues in realizing neuromorphic computing. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present application proposes a neural network, comprising a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit at least comprises a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and configured to control the connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of the control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and configured to receive the input signal from the presynaptic neuron circuit under the control of the first and second feedback signals from the postsynaptic neuron circuit; a weight calculation unit, coupled between the switch unit and the ground and coupled to the input unit, the weight calculation unit at least comprises a ferroelectric transistor, and the ferroelectric transistor is configured to receive the input signal and the second feedback signal from the input unit to update the channel resistance of the ferroelectric transistor.

[0006] In particular, the postsynaptic neuron circuit includes a comparator, whose positive input terminal is coupled to the switch unit of the electronic synapse circuit, the negative input terminal of the comparator is configured to receive a preset constant signal, and the output terminal of the comparator is coupled to the input unit of the electronic synapse circuit; a resistor, which is coupled between the positive input terminal of the comparator and a power supply; a capacitor, which is coupled between the positive input terminal of the comparator and ground; when the switch unit connects the postsynaptic neuron circuit to the electronic synapse circuit and the ferroelectric transistor is turned on, the voltage at the positive input terminal of the comparator drops, and when the voltage drops below the preset constant signal, the comparator is configured to output the first and second feedback signals.

[0007] Particularly, the switch unit comprises a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the positive input terminal of the comparator, and a second electrode of which is coupled to the first electrode of the ferroelectric transistor.

[0008] In particular, the input unit includes a second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is configured to receive the input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a third transistor, which is of a type complementary to the second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; and a fourth transistor, which is of the same type as the second transistor, whose control electrode is configured to receive the control signal, whose first electrode is coupled to the second electrode of the ferroelectric transistor, and whose second electrode is configured to receive the second feedback signal.

[0009] In particular, the control electrode of the ferroelectric transistor is configured to receive the input signal, and the second electrode of the ferroelectric transistor is configured to receive the second feedback signal; the control signal and the input signal have the same period, the effective level of the input signal gradually decreases from a first preset amplitude in the first half of the effective level pulse time, and the effective level of the input signal gradually decreases from a second preset amplitude in the second half of the effective level pulse time, wherein the second preset amplitude is greater than the first preset amplitude.

[0010] Particularly, the effective level amplitude of the first feedback signal is greater than the second preset amplitude.

[0011] Particularly, the effective level amplitude of the second feedback signal is greater than the first preset amplitude and less than the second preset amplitude.

[0012] The present application proposes an electronic synaptic circuit, configured to receive input and control signals from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit at least includes a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control the connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of the control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive the input signal from the presynaptic neuron circuit under the control of the first and second feedback signals from the postsynaptic neuron circuit; a weight calculation unit, coupled between the switch unit and the ground, and coupled to the input unit, the weight calculation unit at least includes a ferroelectric transistor, the ferroelectric transistor is configured to receive the input signal and the second feedback signal from the input unit to update the channel resistance of the ferroelectric transistor.

[0013] Particularly, the switch unit of the electronic synapse circuit comprises a first transistor, whose control electrode is configured to receive the control signal, whose first electrode is coupled to the input terminal of the post-synaptic neuron, and whose second electrode is coupled to the first electrode of the ferroelectric transistor.

[0014] In particular, the input unit of the electronic synapse circuit includes a second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is configured to receive the input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a third transistor, which has a type complementary to the second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; and a fourth transistor, which has the same type as the second transistor, whose control electrode is configured to receive the control signal, whose first electrode is coupled to the second electrode of the ferroelectric transistor, and whose second electrode is configured to receive the second feedback signal.

[0015] In particular, as in the aforementioned electronic synapse circuit, the control electrode of the ferroelectric transistor is configured to receive the input signal, and the second electrode of the ferroelectric transistor is configured to receive the second feedback signal; the control signal and the second input signal have the same period; the effective level of the input signal gradually decreases from a first preset amplitude in the first half of the effective level pulse time, and the effective level of the first input signal gradually decreases from a second preset amplitude in the second half of the effective level pulse time, wherein the second preset amplitude is greater than the first preset amplitude.

[0016] Particularly, in the aforementioned electronic synapse circuit, the effective level amplitude of the first feedback signal is greater than the second preset amplitude.

[0017] Particularly, in the aforementioned electronic synapse circuit, the effective level amplitude of the second feedback signal is greater than the first preset amplitude and less than the second preset amplitude.

[0018] The present application also proposes an electronic system, comprising the neural network as described above.

[0019] The present application also proposes an electronic device, comprising the neural network as described above.

[0020] By adopting the scheme of the present application, on the one hand, since the scheme simulates neurons based on the physical structure of the circuit, the advantages of low power consumption and high computing performance can be obtained; on the other hand, the signal transmission of the neuromorphic circuit is optimized by using the STDP mechanism, which can further shorten the time consumed in circuit processing. The use of ferroelectric transistors in circuit design can further reduce the power consumption of the circuit and improve the processing speed through its non-volatile characteristics and other features. The electronic synaptic circuit provided by the present application uses fewer transistors, and its application in neural networks can greatly reduce the chip area. The new neural network structure proposed in this scheme also has a positive significance for promoting the development of neuromorphic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0022] Figure 1 Shown is a schematic diagram of a neural network model according to an embodiment of the present application;

[0023] Figure 2 Shown is a schematic diagram of a characteristic curve of the STDP mechanism of an electronic synapse;

[0024] Figure 3A Shown is a schematic diagram of an electronic synaptic circuit and a portion of a postsynaptic neuron circuit according to an embodiment of the present application;

[0025] Figure 3B Shown Figure 3A The working timing diagram of the circuit shown;

[0026] Figure 4 Shown is a curve showing the change of normalized conductance of an electronic synaptic circuit over time according to one embodiment of the present application. DETAILED DESCRIPTION

[0027] In the specific description of the following embodiments, reference will be made to the attached drawings that constitute a part of the present application. The attached drawings show specific embodiments that can implement the present application by way of example. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present application. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present application. Therefore, the following specific description is not restrictive, and the scope of the present application is limited by the attached claims.

[0028] The technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0029] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0030] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor.

[0031] In the following detailed description, the effective level can be a high level or a low level according to different circuits. In the following embodiments, for ease of understanding, the high level is described as the effective level and the low level is described as the ineffective level.

[0032] In the following detailed description, for ease of understanding, a level with a potential of 0 is described as a low level, and hereinafter, the ground potential is the same as the potential of the low level.

[0033] Traditional computer architecture divides the device into computing units and storage units. To complete a calculation, the computing unit needs to be called to calculate the data to be processed, and then the calculation result is stored in the storage unit. When faced with large data and more complex calculation processes, traditional computer architecture needs to split the calculation process into multiple simple calculations and repeat the above steps many times. Before the final calculation result is obtained, multiple intermediate values ​​will be generated and stored in the storage unit, and these intermediate values ​​will be called to complete the calculation of the final result.

[0034] The artificial neural network (hereinafter referred to as neural network) proposed in this application can effectively simplify complex computing processes and avoid the problems caused by storage and computing separation.

[0035] Figure 1 Schematic diagram of a neural network model according to an embodiment of the present application. A neural network includes multiple nodes, also called neurons, and two neurons can be connected through electronic synapses. The synapse transmits electrical signals from the electronic presynaptic neuron to the postsynaptic neuron, and the transmission path depends on the weight of the electronic synapse between neurons. The higher the weight, the tighter the connection between the two neurons.

[0036] like Figure 1As shown, according to one embodiment of the present application, a neuron in a neural network can be connected to multiple neurons, and two neurons are connected and transmit signals through electronic synapses. The calculations to be completed can be converted into multiple loop calculations in the neural network, and a single calculation process can be converted into a process of transmitting signals in the neural network starting from the initial neuron set by the user, passing through multiple neurons and electronic synapses, and finally transmitting to the target neuron set by the user. The neural network adjusts the weights between neurons based on a preset learning mechanism, thereby realizing the calculation process of different problems.

[0037] Each electronic synapse can receive signals from at least one neuron (referred to as a presynaptic neuron with respect to the synapse), and / or can send signals to at least one neuron (referred to as a postsynaptic neuron with respect to the synapse).

[0038] Figure 2 The figure shows a characteristic curve of the STDP learning mechanism of an electronic synapse. The time Δt on the horizontal axis represents the time difference between the moment when the postsynaptic neuron emits a signal and the moment when the presynaptic neuron emits a signal, and the ΔW on the vertical axis represents the rate of change of the weight of the electronic synapse. Figure 2 It can be seen that for this type of electronic synapse, when Δt is positive, the rate of change of the weight of the electronic synapse will decrease as Δt increases.

[0039] In order to prepare an electronic synapse having the above STDP learning mechanism characteristic curve, the present application provides an electronic synapse circuit. In particular, the electronic synapse circuit includes a ferroelectric transistor (FeFET).

[0040] With the development of semiconductor device technology, some new devices with adjustable resistance and non-volatile characteristics have been proposed, including resistive memory, phase change memory, ferroelectric transistor (FeFET), etc. Among them, FeFET has the advantages of low power consumption and high operating speed, so it has attracted widespread attention from the scientific research community and the industry.

[0041] FeFET is a new type of transistor that adds a layer of ferroelectric material between the gate and gate oxide layer of the traditional MOSFET. By changing the amplitude and duration of the voltage applied to the FeFET gate, the amount of charge induced on the gate oxide layer can be modulated, thereby changing the threshold voltage and channel resistance of the FeFET. When a specific voltage is applied to the gate source of the FeFET, the electric dipole formed in the crystal structure of the ferroelectric material will be consistent with the direction of the electric field. Even if the gate voltage is removed, the above-mentioned conduction characteristics will not change. Even after the electric field is removed, the electric dipole formed in the crystal structure of the ferroelectric material will maintain this polarization state, thereby keeping the threshold voltage and channel resistance of the FeFET unchanged until the gate-source voltage changes to set the threshold voltage and channel resistance again.

[0042] Figure 3A Shown is a schematic diagram of an electronic synapse circuit and a portion of a postsynaptic neuron circuit according to an embodiment of the present application. Figure 3B Shown Figure 3A The working timing diagram of the circuit shown.

[0043] like Figure 3A As shown, the electronic synapse circuit 20 is coupled to its postsynaptic neuron circuit 30, and the electronic synapse circuit 20 is also coupled to a presynaptic neuron circuit (not shown). According to one embodiment, the presynaptic neuron circuit may have a circuit structure similar to that of the postsynaptic neuron circuit.

[0044] According to one embodiment, each neuron circuit can transmit at least four signals when transmitting a signal, including IP_1 and CL_1, which can be provided to the rear neuron circuit as an input signal and a control signal through the rear synapse; these four signals also include FB_1 and FB_2, which can be provided to the front synapse as a feedback signal, and the front synapse is connected between the neuron circuit and the front neuron circuit. The so-called "front" or "back" here refers to the signal transmission path of the user input, and the one that is relatively closer to the initial neuron circuit becomes "front", and the one that is relatively farther away from the initial neuron circuit becomes "back".

[0045] For a specific electronic synaptic circuit, CL_1 is the control signal provided by the presynaptic neuron circuit, which determines the connection state between the electronic synaptic circuit and the postsynaptic neuron circuit. IP_1 is the input signal provided by the presynaptic neuron circuit, which determines the updated value of the weight of the electronic synaptic circuit. Feedback signals FB_1 and FB_2 are provided by the postsynaptic neuron circuit, which determine the timing of modifying the current weight of the electronic synaptic circuit to the updated value. The amplitude of FB_2 also determines the updated value of the weight of the electronic synaptic circuit.

[0046] According to one embodiment, Figure 3A As shown, the electronic synapse circuit 20 may include at least a switch unit 201 , an input unit 202 and a weight calculation unit 203 .

[0047] According to one embodiment, the switch unit 201 may include at least, for example, an NMOS transistor M21, whose gate may be configured to receive a control signal CL_1 from a presynaptic neuron circuit. Figure 3B As shown, CL_1 includes a plurality of high-level long pulses. When CL_1 is at a high level, the electronic synapse circuit 20 is started to operate, and the electrical connection with the post-synaptic neuron circuit 30 is turned on.

[0048] According to one embodiment, the input unit 202 may include at least NMOS transistors M23 and M25 , and a PMOS transistor M24 , for example.

[0049] According to one embodiment, the drain of M23 may be configured to receive an input signal IP_1 from a presynaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive a feedback signal FB_1 from a postsynaptic neuron circuit.

[0050] According to one embodiment, the source of M24 may be coupled to the source of M23 and the weight calculation unit 203 , the drain thereof may be grounded, and the gate thereof may be configured to receive a feedback signal FB_1 from the post-synaptic neuron circuit.

[0051] According to one embodiment, the source of M25 may be configured to receive a feedback signal FB_2 from a post-synaptic neuron circuit, the drain may be coupled to the weight calculation unit 203 , and the gate may be configured to receive a control signal CL_1 from a pre-synaptic neuron circuit.

[0052] According to one embodiment, the weight calculation unit 203 may include at least a FeFET transistor M22. According to one embodiment, the gate of M22 may be coupled to the source of M23 and the source of M24, the source of M22 may be coupled to the drain of M25, and the drain of M22 may be coupled to the source of M21.

[0053] like Figure 3AAs shown, a neuron circuit, such as a post-synaptic neuron circuit 30, may include at least a comparator 301, a resistor 302, and a capacitor 303. The positive input terminal of the comparator 301 may be coupled to the electronic synaptic circuit 20 (e.g., may be coupled to the drain of the transistor M21), and may also be coupled to a power supply through the resistor 302. The negative input terminal of the comparator 301 is configured to receive a preset reference voltage Vth. Once the voltage Vout at the positive input terminal of the comparator 301 is lower than the voltage Vth at the negative input terminal, the neuron will output an output signal Y (including FB_1 and FB_2, and CL_1' and IP_1' provided to the neurons behind it).

[0054] According to one embodiment of the present application, the post-synaptic neuron circuit 30 may further include a signal processing unit 304, which is configured to process the output signal Y to output feedback signals FB_1 and FB_2, ensure that the output feedback signal FB_2 is sent out simultaneously with FB_1, have the same effective level duration, and make the amplitude of FB_1 smaller than the amplitude of FB_2, and the high level amplitude of FB_2 is controlled within a range that meets the circuit design requirements.

[0055] According to an embodiment of the present application, device parameters such as gate length, doping concentration and gate insulation layer thickness of M21, M22, M23, M24 and M25 are not restricted and can be adjusted according to actual needs.

[0056] According to one embodiment, Figure 3B As shown, when Vout is higher than Vth, the postsynaptic neuron circuit will not output signal Y, so FB_1 and FB_2 are also low levels. In this case, transistor M23 in input unit 202 is disconnected, transistor M24 is turned on, and if CL_1 is high, M25 is turned on, and the drain of M25 receives the low level of FB_2, which is equivalent to the gate and source of FeFET transistor M22 being grounded. In this case, the threshold voltage and channel resistance of FeFET transistor M22 remain unchanged. According to one embodiment, M22 can still be turned on when the gate-source voltage is 0.

[0057] When CL_1 reaches a high level, the charge in capacitor 303 is discharged through the path where M22 is located in the electronic synaptic circuit. When Vout drops below Vth, the post-synaptic neuron circuit 30 transmits a signal Y, and FB_1 and FB_2 jump to a high level.

[0058] According to one embodiment, a neuron circuit has multiple preceding electronic synapse circuits coupled to it. When any of these electronic synapse circuits is able to reduce Vout to a level below Vth first, the neuron circuit will emit a signal Y, and all preceding electronic synapse circuits coupled to it will receive high levels of FB_1 and FB_2.

[0059] However, if Vout cannot be reduced to a level lower than Vth after the discharge during a high level pulse of CL_1, and other preceding electronic synapse circuits have not achieved this goal, the power supply will continue to charge capacitor 303 after the high level of CL_1, and discharge the charge in capacitor 303 again when the next high level of CL_1 comes. After several discharges or integrations, the goal of reducing Vout to a level lower than Vth may be achieved.

[0060] During the period when CL_1 is at a high level, M21 and M25 are turned on. When FB_1 and FB_2 are at a high level, M24 is turned off, M23 is turned on, M23 provides IP_1 to the gate of M22, and M25 provides FB_2 to the source of M22, thereby changing the threshold voltage and channel resistance of M22 and updating the weight of the electronic synapse circuit. Of course, as mentioned above, the arrival of FB_1 and FB_2 at a high level may be caused by the electronic synapse circuit itself, or by other electronic synapse circuits coupled to the neuron circuit 30. However, no matter which electronic synapse circuit triggers it, the neuron circuit 30 will emit FB_1 and FB_2, so that the weights of all the previous electronic synapse circuits coupled to it will change.

[0061] According to the embodiment of the present application, since the time when each electronic synaptic circuit receives the input signal IP_1 provided by the presynaptic neuron may be different, the threshold voltage and channel resistance change values ​​of M22 in each electronic synaptic circuit are different, and the weights of each electronic synaptic circuit after the change may also be different, or the threshold voltage and channel resistance of the FeFET transistor may be set to different values. However, no matter which electronic synaptic circuit triggers it, the neuron circuit 30 will emit FB_1 and FB_2, so that the weights of all the previous electronic synaptic circuits coupled to it may change.

[0062] When the control signal CL_1 remains at a high level or comes again, the electronic synapse circuit 20 after the weight value is updated will discharge the charge in the capacitor 303 with the updated channel resistance.

[0063] To achieve Figure 2 The electronic synapse properties shown, according to one embodiment, are for Figure 3A The circuit shown, Figure 3BAs shown, in each clock cycle, the duration of the high level Vhh of CL_1 completely overlaps with the pulse time period of the high level of IP_1, or in other words, the cycles of CL_1 and IP_1 are the same. According to one embodiment, the maximum high levels of CL_1 and IP_1 may be different. According to different embodiments, the maximum high level of CL_1 may be greater than the maximum high level of IP_1, or may be less than or equal to the maximum high level of IP_1.

[0064] According to one embodiment, during the first half of the high level pulse period, the amplitude of the high level of IP_1 gradually decreases from the first preset amplitude V1 over time, and its slope can ensure that the electronic synapse has the same Figure 2 The characteristic curve of the synapse in the third quadrant is basically the same as the characteristic curve of the synapse in the third quadrant; in the second half of the IP_1 high level pulse time period, the amplitude of the IP_1 high level pulse first jumps from a low level to a second preset amplitude V2 and gradually decreases over time, and its slope can ensure that the electronic synapse has the same Figure 2 The characteristic curve of the synapse in the first quadrant is substantially the same as the characteristic curve of the synapse in the first quadrant. According to one embodiment, V1 is less than V2.

[0065] According to different embodiments, the first half time and the second half time herein may be the same or different time periods.

[0066] According to one embodiment, in order to meet the conduction rule of M23 and M25, the high level pulse amplitude of FB_1, i.e., Vhh, should be greater than the maximum value of the amplitude of the high level pulse of IP_1, i.e., the second preset amplitude V2, so that M23 can be turned on; the high level pulse amplitude of FB_2, i.e., V3, should be greater than the first preset amplitude V1 of IP_1 and less than the minimum value of IP_1 in the second half of the high level pulse time period, so as to ensure that the same Figure 2 The synaptic property curves shown are essentially the same as the electronic synaptic properties.

[0067] Figure 4 FIG. 4 is a curve showing the change of the normalized conductance of an electronic synaptic circuit over time according to an embodiment of the present application. Figure 4 As shown, Δt on the horizontal axis is the time difference between the moment when the postsynaptic neuron transmits the signal Y and the preset moment (the preset moment is the moment when the two segments before and after the IP_1 high-level pulse time period are connected, or the moment when the two pulses before and after the IP_1 high-level pulse time period are switched) (Δt can also be calculated relative to other moments, but the resulting change curve is different from Figure 4 There will be a difference, it cannot be achieved Figure 2 The mechanism of the characteristic curve shown in FIG. 1 ). The ΔW / W on the vertical axis represents the percentage change in the conductivity of M22 in the electronic synaptic circuit. To make the curve more intuitive, the conductivity change curve is normalized with respect to Δt.

[0068] If the high levels of FB_1 and FB_2 fall in the second half of the high level pulse time period of IP_1, Δt is positive. At this stage, IP_1 is positive and gradually decreases from the second preset amplitude V2. The conductivity of M22 (and the corresponding weight change rate of the electronic synapse) will decrease as Δt increases (the weight change rate of the electronic synapse is positively correlated with the conductivity of M22). If the high levels of FB_1 and FB_2 fall in the first half of the high level pulse time period of IP_1, Δt is negative. At this stage, IP_1 is positive and gradually decreases from the first preset amplitude V1. The conductivity of M22 and the corresponding weight change rate of the electronic synapse will decrease as Δt increases. The magnitude of the change in the conductivity of M22 is affected by the maximum amplitude of the high level of IP_1.

[0069] Of course, different input and control signals can also be used according to different STDP mechanism curves of electronic synapses.

[0070] The scheme of this application utilizes the memory and non-volatile characteristics of FeFET and applies them to electronic synapses. By adjusting the voltage value applied to the FeFET gate to set the threshold voltage and channel resistance of the FeFET, the specific weights of the synapse can be set, which can simplify the circuit design to a certain extent while realizing the functions of multiple components. At the same time, due to its advantages of low power consumption and high operating speed, the power consumption of circuits and equipment can be further reduced and the operating efficiency can be improved. By using it in the network design of neuromorphic computing, neuromorphic computing with low power consumption and high computing performance can be realized.

[0071] During the calculation and optimization process, the circuit does not need to store the calculated weights and intermediate values ​​of other input signals, nor does it need to call the intermediate values ​​again before the next calculation, which reduces the number of times the circuit is used, improves the calculation speed, and reduces circuit power consumption.

[0072] The electronic synaptic circuit provided in the present application uses fewer transistors and can greatly reduce the chip area when applied to neural networks.

[0073] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A neural network circuit, characterized in that include: a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and to receive feedback signals from a postsynaptic neuron circuit; Wherein, the electronic synapse circuit at least comprises: a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive an input signal from the presynaptic neuron circuit under the control of a first feedback signal and a second feedback signal from the postsynaptic neuron circuit; A weight calculation unit, coupled between the switch unit and the ground and coupled to the input unit, the weight calculation unit at least comprising a ferroelectric transistor, the ferroelectric transistor being configured to receive the input signal and the second feedback signal from the input unit to update the channel resistance of the ferroelectric transistor; When the switch unit connects the postsynaptic neuron circuit to the electronic synapse circuit and the ferroelectric transistor is turned on, when the voltage at the connection point between the postsynaptic neuron circuit and the electronic synapse circuit drops below a preset reference voltage, the postsynaptic neuron circuit is configured to output the first feedback signal and the second feedback signal.

2. The neural network circuit as claimed in claim 1, characterized in that The postsynaptic neuron circuit comprises at least: A comparator, whose positive input terminal is coupled to the switch unit of the electronic synapse circuit, the voltage at the connection point between the post-synaptic neuron circuit and the electronic synapse circuit is the voltage of the positive input terminal of the comparator, the negative input terminal of the comparator is configured to receive the preset reference voltage, and the output terminal of the comparator is coupled to the input unit of the electronic synapse circuit; a resistor coupled between the positive input terminal of the comparator and a power supply; A capacitor is coupled between the positive input terminal of the comparator and ground.

3. The neural network circuit as claimed in claim 2, characterized in that The switch unit at least includes a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the positive input terminal of the comparator, and a second electrode of which is coupled to the first electrode of the ferroelectric transistor.

4. The neural network circuit as claimed in claim 3, characterized in that The input unit at least includes: a second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is configured to receive the input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a third transistor, which is of a complementary type to the second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; A fourth transistor, which is of the same type as the second transistor, has a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.

5. A neural network circuit as described in any one of claims 1 to 4, characterized in that The control electrode of the ferroelectric transistor is configured to receive the input signal, and the second electrode of the ferroelectric transistor is configured to receive the second feedback signal; The control signal and the input signal have the same period; The effective level of the input signal gradually decreases from the first preset amplitude in the first half of its pulse time; The effective level of the input signal gradually decreases from a second preset amplitude in the second half of its pulse time, wherein the second preset amplitude is greater than the first preset amplitude.

6. The neural network circuit as claimed in claim 5, characterized in that The effective level amplitude of the first feedback signal is greater than the second preset amplitude.

7. The neural network circuit as claimed in claim 5, characterized in that The effective level amplitude of the second feedback signal is greater than the first preset amplitude and less than the second preset amplitude.

8. An electronic synaptic circuit configured to receive input and control signals from a presynaptic neuron circuit and to receive feedback signals from a postsynaptic neuron circuit; It is characterized in that The electronic synapse circuit comprises at least: a switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive an input signal from the pre-synaptic neuron circuit under the control of a first feedback signal and a second feedback signal from the post-synaptic neuron circuit; A weight calculation unit is coupled between the switch unit and the ground and coupled to the input unit, wherein the weight calculation unit comprises at least a ferroelectric transistor, and the ferroelectric transistor is configured to receive the input signal and the second feedback signal from the input unit to update the channel resistance of the ferroelectric transistor.

9. The electronic synapse circuit of claim 8, characterized in that The switch unit at least includes a first transistor, a control electrode of which is configured to receive the control signal, a first electrode of which is coupled to the input terminal of the post-synaptic neuron, and a second electrode of which is coupled to the first electrode of the ferroelectric transistor.

10. The electronic synapse circuit of claim 9, characterized in that The input unit at least includes: a second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is configured to receive the input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a third transistor, which is of a complementary type to the second transistor, whose control electrode is configured to receive the first feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; A fourth transistor, which is of the same type as the second transistor, has a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.

11. The electronic synapse circuit according to any one of claims 8 to 10, characterized in that The control electrode of the ferroelectric transistor is configured to receive the input signal, and the second electrode of the ferroelectric transistor is configured to receive the second feedback signal; The control signal and the input signal have the same period; The effective level of the input signal gradually decreases from the first preset amplitude in the first half of its pulse time; The effective level of the input signal gradually decreases from a second preset amplitude in the second half of its pulse time, wherein the second preset amplitude is greater than the first preset amplitude.

12. The electronic synapse circuit of claim 11, wherein The effective level amplitude of the first feedback signal is greater than the second preset amplitude.

13. The electronic synapse circuit of claim 11, wherein The effective level amplitude of the second feedback signal is greater than the first preset amplitude and less than the second preset amplitude.

14. An electronic system, characterized in that Comprising a neural network circuit as described in any one of claims 1-7.

15. An electronic device, characterized in that Comprising a neural network circuit as described in any one of claims 1-7.

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