Shift register unit and driving method thereof, gate driving circuit and display device

Abstract

A shift register unit and a driving method thereof, a gate driving circuit and a display device, wherein the shift register unit comprises an input circuit, an output circuit, a first node noise reduction circuit and a noise reduction reset circuit. The input circuit writes an input signal to a first node in response to an input signal to control the level of the first node. The output circuit receives a clock signal and outputs the clock signal to an output end under the control of the level of the first node. The first node noise reduction circuit is connected to the first node, the first noise reduction node and the second noise reduction node, and is configured to perform noise reduction on the first node under the control of the level of the first noise reduction node or the level of the second noise reduction node. The noise reduction reset circuit is connected to the first noise reduction node and the second noise reduction node, and is configured to reset the first noise reduction node and the second noise reduction node in response to a first reset signal. The shift register unit can completely release the charges of the first noise reduction node and the second noise reduction node to avoid affecting the signal output of the output end.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] In the field of display technology, for example, the pixel array of a liquid crystal display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith. The driving of the gate lines can be achieved by a gate drive circuit. For example, the gate drive circuit can be implemented by a bound integrated drive circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate-driver On Array) to drive the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide a switching state voltage signal for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel unit of the corresponding row in the pixel array, so as to form the grayscale voltage required for each grayscale of the display image in each pixel unit, and then display a frame of image. At present, more and more display panels use GOA technology to drive the gate lines. GOA technology helps to achieve a narrow frame and can reduce production costs. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a shift register unit, including an input circuit, an output circuit, a first node noise reduction circuit and a noise reduction reset circuit; wherein the input circuit is connected to the first node, and is configured to write the input signal to the first node in response to the input signal to control the level of the first node; the output circuit is connected to the first node and the output end, and is configured to receive a clock signal and output the clock signal to the output end under the control of the level of the first node; the first node noise reduction circuit is respectively connected to the first node, the first noise reduction node and the second noise reduction node, and is configured to perform noise reduction on the first node under the control of the level of the first noise reduction node or the level of the second noise reduction node; the noise reduction reset circuit is connected to the first noise reduction node and the second noise reduction node, and is configured to reset the first noise reduction node and the second noise reduction node in response to the first reset signal.

[0004] For example, the shift register unit provided by at least one embodiment of the present disclosure also includes a first noise reduction circuit, a second noise reduction circuit, a first control circuit and a second control circuit; wherein the first noise reduction circuit is respectively connected to the first node, the first noise reduction node and the first control node, and is configured to control the level of the first noise reduction node under the control of the level of the first node and the level of the first control node; the second noise reduction circuit is respectively connected to the first node, the second noise reduction node and the second control node, and is configured to control the level of the second noise reduction node under the control of the level of the first node and the level of the second control node; the first control circuit is connected to the first node and the first control node, and is configured to control the level of the first control node under the control of the level of the first node; the second control circuit is connected to the first node and the second control node, and is configured to control the level of the second control node under the control of the level of the first node.

[0005] For example, the shift register unit provided in at least one embodiment of the present disclosure further includes an output reset circuit, wherein the output reset circuit is connected to the output end and is configured to reset the output end in response to the first reset signal.

[0006] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output reset circuit is also connected to the first node and is configured to reset the first node in response to the first reset signal.

[0007] For example, the shift register unit provided by at least one embodiment of the present disclosure further includes a first node reset circuit, wherein the first node reset circuit is connected to the first node and configured to reset the first node in response to a second reset signal.

[0008] For example, the shift register unit provided by at least one embodiment of the present disclosure also includes an output noise reduction circuit, wherein the output noise reduction circuit is respectively connected to the first noise reduction node, the second noise reduction node and the output end, and is configured to perform noise reduction on the output end under the control of the level of the first noise reduction node or the level of the second noise reduction node.

[0009] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the noise reduction reset circuit includes a first transistor and a second transistor; the gate of the first transistor is connected to the first reset end to receive the first reset signal, the first electrode of the first transistor is connected to the first noise reduction node, and the second electrode of the first transistor is connected to the first voltage end; the gate of the second transistor is connected to the first reset end to receive the first reset signal, the first electrode of the second transistor is connected to the second noise reduction node, and the second electrode of the second transistor is connected to the first voltage end.

[0010] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the input circuit includes a third transistor; the gate of the third transistor is connected to the first electrode and to the input end to receive the input signal, and the second electrode of the third transistor is connected to the first node.

[0011] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output circuit includes a fourth transistor and a first capacitor; the gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the clock signal end to receive the clock signal, and the second electrode of the fourth transistor is connected to the output end; the first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the output end.

[0012] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the first node noise reduction circuit includes a fifth transistor and a sixth transistor; the gate of the fifth transistor is connected to the first noise reduction node, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the first voltage end; the gate of the sixth transistor is connected to the second noise reduction node, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the first voltage end.

[0013] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the first noise reduction circuit includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected to the first control node, the first electrode of the seventh transistor is connected to the second voltage terminal, the second electrode of the seventh transistor is connected to the first noise reduction node, the gate of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the first noise reduction node, and the second electrode of the eighth transistor is connected to the first voltage terminal; the first control circuit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor is connected to the first electrode and to the second voltage terminal, the second electrode of the ninth transistor is connected to the first control node, the gate of the tenth transistor is connected to the first node, the first electrode of the tenth transistor is connected to the first control node, and the second electrode of the tenth transistor is connected to the first voltage terminal.

[0014] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the second noise reduction circuit includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second control node, the first electrode of the eleventh transistor is connected to the third voltage terminal, the second electrode of the eleventh transistor is connected to the second noise reduction node, the gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the second noise reduction node, and the second electrode of the twelfth transistor is connected to the first voltage terminal; the second control circuit includes a thirteenth transistor and a fourteenth transistor, the gate of the thirteenth transistor is connected to the first electrode and to the third voltage terminal, the second electrode of the thirteenth transistor is connected to the second control node, the gate of the fourteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second control node, and the second electrode of the fourteenth transistor is connected to the first voltage terminal.

[0015] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output reset circuit includes a fifteenth transistor; the gate of the fifteenth transistor is connected to the first reset terminal to receive the first reset signal, the first electrode of the fifteenth transistor is connected to the output terminal, and the second electrode of the fifteenth transistor is connected to the first voltage terminal.

[0016] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output reset circuit includes a sixteenth transistor; the gate of the sixteenth transistor is connected to the first reset terminal to receive the first reset signal, the first electrode of the sixteenth transistor is connected to the first node, and the second electrode of the sixteenth transistor is connected to the first voltage terminal.

[0017] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the first node reset circuit includes a seventeenth transistor; the gate of the seventeenth transistor is connected to the second reset terminal to receive the second reset signal, the first electrode of the seventeenth transistor is connected to the first node, and the second electrode of the seventeenth transistor is connected to the first voltage terminal.

[0018] For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output noise reduction circuit includes an eighteenth transistor and a nineteenth transistor; the gate of the eighteenth transistor is connected to the first noise reduction node, the first electrode of the eighteenth transistor is connected to the output end, and the second electrode of the eighteenth transistor is connected to the first voltage end; the gate of the nineteenth transistor is connected to the second noise reduction node, the first electrode of the nineteenth transistor is connected to the output end, and the second electrode of the nineteenth transistor is connected to the first voltage end.

[0019] At least one embodiment of the present disclosure also provides a driving method for a shift register unit as described in any embodiment of the present disclosure, comprising: in a noise reduction reset stage, the noise reduction reset circuit resets the first noise reduction node and the second noise reduction node in response to the first reset signal; in an input stage, the input circuit writes the input signal to the first node in response to the input signal; and in an output stage, the output circuit outputs the clock signal to the output end under the control of the level of the first node.

[0020] At least one embodiment of the present disclosure further provides a gate driving circuit, comprising the shift register unit described in any embodiment of the present disclosure.

[0021] At least one embodiment of the present disclosure further provides a display device, comprising the gate driving circuit described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0023] Figure 1 A schematic block diagram of a shift register unit provided for some embodiments of the present disclosure;

[0024] Figure 2 A schematic block diagram of another shift register unit provided for some embodiments of the present disclosure;

[0025] Figure 3 A schematic block diagram of another shift register unit provided for some embodiments of the present disclosure;

[0026] Figure 4 Schematic block diagram of another shift register unit provided for some embodiments of the present disclosure

[0027] Figure 5 for Figure 3 A circuit diagram of a specific implementation example of the shift register unit shown in

[0028] Figure 6 for Figure 4 A circuit diagram of a specific implementation example of the shift register unit shown in ;

[0029] Figure 7 and Figure 8 A signal timing diagram of a shift register unit provided in some embodiments of the present disclosure;

[0030] Fig. 9 A schematic block diagram of a gate driving circuit provided for some embodiments of the present disclosure; and

[0031] Fig.10 A schematic block diagram of a display device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] In the process of designing a shift register unit for a gate drive circuit, in order to avoid performance drift caused by long-term conduction of transistors in the shift register unit, for example, two groups of noise reduction control circuits can be used to alternately control each noise reduction circuit in the shift register unit to reduce noise at each node (such as a pull-up node) and output end in the shift register unit. For example, the two groups of noise reduction control circuits receive alternating DC high-level signals and DC low-level signals, respectively, and the signals received by the two groups of noise reduction control circuits are mutually inverted signals. For example, in one cycle, the first group of noise reduction control circuits receives a high-level signal, the second group of noise reduction control circuits receives a low-level signal, and each noise reduction circuit in the shift register unit works under the control of the first group of noise reduction control circuits; in the next cycle, the first group of noise reduction control circuits receives a low-level signal, the second group of noise reduction control circuits receives a high-level signal, and each noise reduction circuit in the shift register unit works under the control of the second group of noise reduction control circuits.

[0035] In order not to affect the normal display of the picture, the switching period of the two sets of noise reduction control circuits is usually set to an integer multiple of the display picture refresh period, and the switching time point is set in the blanking stage of the display, that is, the stage after the previous frame of the display ends or before the next frame of the display begins.

[0036] However, during the switching process of the two groups of noise reduction control circuits, for example, when the DC level signal received by the first group of noise reduction control circuits changes from a high level to a low level (for example, the level signal changes from a positive voltage to a negative voltage), since the transistors in the first group of noise reduction control circuits are in an off state in response to the low level signal, the charge in the first group of noise reduction control circuits cannot be directly and quickly released through the transistors, but can only be slowly released through the transistors in the form of leakage current. Therefore, when the clock signal corresponding to the next frame of the display screen arrives, the charge in the first group of noise reduction control circuits may not be completely released, which causes the first group of noise reduction control circuits to continue to affect the noise reduction circuits in the shift register unit. Under the action of the two groups of noise reduction control circuits, the noise reduction circuits in the shift register unit increase the discharge current of each node (for example, the pull-up node), thereby doubling the charge of each node. For example, when an input signal is written to charge the pull-up node, the pull-up node cannot be fully charged when the clock signal arrives due to the influence of, for example, the pull-up node noise reduction circuit on the pull-up node producing a doubled discharge current, resulting in a low level of the pull-up node. Further, under the control of the level of the pull-up node, the amplitude of the signal output from the output end is low, and the output signal is even further attenuated to no output, resulting in abnormal display of the image or poor screen scanning.

[0037] At least one embodiment of the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit can completely release the charge in the corresponding noise reduction control circuit switched to an invalid level (e.g., a low level) during the switching process of two groups of noise reduction control circuits, thereby avoiding affecting the amplitude of the output signal, ensuring the normal display of the picture, and further improving the stability and reliability of the product including the shift register unit.

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0039] At least one embodiment of the present disclosure provides a shift register unit, a plurality of shift register units are cascaded to form a gate drive circuit to sequentially output a plurality of scan signals, and the shift register unit includes an input circuit, an output circuit, a first node noise reduction circuit, and a noise reduction reset circuit. The input circuit is connected to the first node and configured to write the input signal to the first node in response to the input signal to control the level of the first node. The output circuit is connected to the first node and the output end, configured to receive a clock signal and output the clock signal to the output end under the control of the level of the first node. The first node noise reduction circuit is respectively connected to the first node, the first noise reduction node, and the second noise reduction node, and is configured to perform noise reduction on the first node under the control of the level of the first noise reduction node or the level of the second noise reduction node. The noise reduction reset circuit is connected to the first noise reduction node and the second noise reduction node, and is configured to reset the first noise reduction node and the second noise reduction node in response to the first reset signal.

[0040] Figure 1 A schematic block diagram of a shift register unit provided in some embodiments of the present disclosure. Figure 1 As shown, the shift register unit 10 includes an input circuit 100 , an output circuit 200 , a first node noise reduction circuit 300 and a noise reduction reset circuit 400 .

[0041] The input circuit 100 is connected to the first node PU and is configured to write the input signal to the first node PU in response to the input signal to control the level of the first node PU. For example, the input circuit 100 electrically connects the first node PU to the input terminal INT under the control of the input signal, so that the high level of the input signal can charge the first node PU, that is, pull up the first node PU, so that the level of the first node PU is increased to control the output circuit 200 to be turned on. Of course, the embodiments of the present disclosure are not limited to this method. For example, the input circuit 100 can also be connected to a high voltage terminal provided separately, and is configured to electrically connect the first node PU to the high voltage terminal under the control of the input signal provided by the input terminal INT, so that the high level signal output by the high voltage terminal can charge the first node PU. In some other embodiments, the low level of the input signal can also discharge the first node PU, so that the level of the first node PU is reduced to control the output circuit 200 to be turned on. The change mode of the level of the first node PU (i.e., increase or decrease) can be determined according to the specific implementation mode of the output circuit 200.

[0042] The output circuit 200 is connected to the first node PU and the output terminal OP1, and is configured to receive a clock signal and output the clock signal to the output terminal OP1 under the control of the level of the first node PU. For example, the output circuit 200 is turned on under the control of the level of the first node PU, so that the clock signal terminal CLK providing the clock signal is electrically connected to the output terminal OP1, so that the output circuit 200 can output the clock signal to the output terminal OP1 after receiving the clock signal. For example, the output terminal OP1 can be a scan signal output terminal, which is used to provide a scan signal to a pixel circuit (pixel row) to drive, for example, a gate line of a display panel connected to the scan signal output terminal.

[0043] The first node noise reduction circuit 300 is connected to the first node PU, the first noise reduction node PD1, and the second noise reduction node PD2, respectively, and is configured to perform noise reduction on the first node PU under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2. For example, the first node noise reduction circuit 300 is connected to the first node PU, the first noise reduction node PD1, the second noise reduction node PD2, and a first voltage terminal VSS (e.g., a low voltage terminal) provided separately, and is configured to electrically connect the first node PU and the first voltage terminal VSS under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, reset the level of the first node PU to the voltage provided by the first voltage terminal VSS, avoid noise caused by the level of the first node PU during non-operation, and thus perform noise reduction (e.g., pull-down) on the first node PU.

[0044] For example, by controlling the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2, the first noise reduction node PD1 and the second noise reduction node PD2 can be alternately at a valid level (for example, a high level), so that the first node noise reduction circuit 300 alternately responds to the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 to perform noise reduction on the first node PU.

[0045] For example, in the process of the first node noise reduction circuit 300 being alternately controlled by the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2, when the high-level signal is switched to the low-level signal, because the charge at the noise reduction node cannot be released quickly, there is residual charge, resulting in the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 acting on the first node noise reduction circuit 300 at the same time, thereby doubling the discharge current of the first node PU by the first node noise reduction circuit 300, reducing the charge of the first node PU, so that the first node PU cannot be fully charged, thereby affecting the amplitude of, for example, the scanning signal output by the output terminal OP1.

[0046] In order to ensure the stability of the output signal, Figure 1 As shown, the noise reduction reset circuit 400 is connected to the first noise reduction node PD1 and the second noise reduction node PD2, and is configured to reset the first noise reduction node PD1 and the second noise reduction node PD2 in response to a first reset signal. For example, the noise reduction reset circuit 400 is connected to the first noise reduction node PD1, the second noise reduction node PD2, the first reset terminal RST1, and a first voltage terminal VSS (e.g., a low voltage terminal) provided separately, and is configured to electrically connect the first noise reduction node PD1 and the second noise reduction node PD2 to the first voltage terminal VSS respectively in response to the first reset signal provided by the first reset terminal RST1, thereby resetting the first noise reduction node PD1 and the second noise reduction node PD2.

[0047] For example, in the process of switching from a high-level signal to a low-level signal, the charges at the first noise reduction node PD1 and the second noise reduction node PD2 can be quickly released through the first voltage terminal VSS during the process of being reset by the noise reduction reset circuit 400, thereby avoiding the residual charges at the first noise reduction node PD1 or the second noise reduction node PD2 during the switching process. The additional impact on the first node noise reduction circuit 300 is avoided, thereby ensuring that the first node noise reduction circuit 300 only performs noise reduction on the first node PU under the control of the level of any one of the first noise reduction node PD1 and the second noise reduction node PD2.

[0048] For example, before the input signal is written to the input terminal INT, the first reset terminal RST1 can apply a first reset signal to the noise reduction reset circuit 400 to reset the first noise reduction node PD1 and the second noise reduction node PD2, thereby preventing the residual charge of the first noise reduction node PD1 or the second noise reduction node PD2 from affecting the charging of the first node PU, ensuring the stability of the amplitude of the output of the output terminal OP1, such as the scanning signal, so that the display device including the shift register unit 10 can display the picture normally, thereby improving the stability and reliability of the display device.

[0049] Figure 2 A schematic block diagram of another shift register unit provided in some embodiments of the present disclosure. Figure 2 As shown, in this embodiment, the shift register unit 20 further includes a first noise reduction circuit 510, a second noise reduction circuit 520, a first control circuit 610 and a second control circuit 620, and other structures are similar to Figure 1 The shift register unit 10 shown in FIG. 1 is substantially the same.

[0050] The first noise reduction circuit 510 is connected to the first node PU, the first noise reduction node PD1 and the first control node PD_CN1, respectively, and is configured to control the level of the first noise reduction node PD1 under the control of the level of the first node PU and the level of the first control node PD_CN1. For example, the first noise reduction circuit 510 is connected to the first voltage terminal VSS, the second voltage terminal VDD1, the first node PU, the first control node PD_CN1 and the first noise reduction node PD1, and is configured to electrically connect the first noise reduction node PD1 and the first voltage terminal VSS under the control of the level of the first node PU, thereby controlling (for example, pulling down) the level of the first noise reduction node PD1 to be at a low level. At the same time, the first noise reduction circuit 510 can electrically connect the first noise reduction node PD1 and the second voltage terminal VDD1 under the control of the level of the first control node PD_CN1, so as to charge the first noise reduction node PD1 when the second voltage terminal VDD1 provides a high level signal, so as to make it at a high level.

[0051] The second noise reduction circuit 520 is connected to the first node PU, the second noise reduction node PD2 and the second control node PD_CN2, respectively, and is configured to control the level of the second noise reduction node PD2 under the control of the level of the first node PU and the level of the second control node PD_CN2. For example, the second noise reduction circuit 520 is connected to the first voltage terminal VSS, the third voltage terminal VDD2, the first node PU, the second control node PD_CN2 and the second noise reduction node PD2, and is configured to electrically connect the second noise reduction node PD2 and the first voltage terminal VSS under the control of the level of the first node PU, thereby controlling (for example, pulling down) the level of the second noise reduction node PD2 to be at a low level. At the same time, the second noise reduction circuit 520 can electrically connect the second noise reduction node PD2 and the third voltage terminal VDD2 under the control of the level of the second control node PD_CN2, so that when the third voltage terminal VDD2 provides a high level signal, the second noise reduction node PD2 is charged to be at a high level.

[0052] The first control circuit 610 is connected to the first node PU and the first control node PD_CN1, and is configured to control the level of the first control node PD_CN1 under the control of the level of the first node PU. For example, the first control circuit 610 is connected to the first voltage terminal VSS, the second voltage terminal VDD1, the first node PU and the first control node PD_CN1, and is configured to electrically connect the first control node PD_CN1 and the first voltage terminal VSS under the control of the level of the first node PU, thereby pulling down the level of the first control node PD_CN1 to make it at a low level. At the same time, the first control circuit 610 can make the first control node PD_CN1 at a high level when the second voltage terminal VDD1 provides a high level signal.

[0053] The second control circuit 620 is connected to the first node PU and the second control node PD_CN2, and is configured to control the level of the second control node PD_CN2 under the control of the level of the first node PU. For example, the second control circuit 620 is connected to the first voltage terminal VSS, the third voltage terminal VDD2, the first node PU and the second control node PD_CN2, and is configured to electrically connect the second control node PD_CN2 and the first voltage terminal VSS under the control of the level of the first node PU, thereby pulling down the level of the second control node PD_CN2 to make it at a low level. At the same time, the second control circuit 620 can make the second control node PD_CN2 at a high level when the third voltage terminal VDD2 provides a high level signal.

[0054] For example, the second voltage terminal VDD1 and the third voltage terminal VDD2 are configured to alternately provide a DC high-level signal, and through the first noise reduction circuit 510, the second noise reduction circuit 520, the first control circuit 610 and the second control circuit 620, the first noise reduction node PD1 and the second noise reduction node PD2 are alternately high-level, thereby controlling the first node noise reduction circuit 300 to perform noise reduction on the first node PU. For example, when the second voltage terminal VDD1 provides a high-level signal, the third voltage terminal VDD2 provides a low-level signal, and under the action of the first noise reduction circuit 510 and the first control circuit 610, the first noise reduction node PD1 is at a high level; when the third voltage terminal VDD2 provides a high-level signal, the second voltage terminal VDD1 provides a low-level signal, and under the action of the second noise reduction circuit 520 and the second control circuit 620, the second noise reduction node PD2 is at a high level. In this way, the performance drift caused by the long-term conduction of the transistors in the shift register unit 20 can be avoided.

[0055] For example, in the process of the second voltage terminal VDD1 and the third voltage terminal VDD2 alternately providing a DC high-level signal, the noise reduction reset circuit 400 respectively resets the first noise reduction node PD1 and the second noise reduction node PD2 in response to the first reset signal, thereby preventing the charge in the circuit from remaining in the first noise reduction node PD1 or the second noise reduction node PD2 due to the inability to quickly release the charge through, for example, the first control circuit 610 or the second control circuit 620 during the process of the level signal provided by the second voltage terminal VDD1 or the third voltage terminal VDD2 switching from a high level to a low level. Furthermore, it is ensured that when the input signal is written to the first node PU, the first node noise reduction circuit 300 only performs noise reduction on the first node PU under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, thereby avoiding excessive discharge current of the first node PU during the charging process, thereby ensuring the normal output of the output terminal signal.

[0056] Figure 3 A schematic block diagram of another shift register unit provided in some embodiments of the present disclosure. Figure 3 As shown, the shift register unit 30 in this embodiment further includes an output reset circuit 700, a first node reset circuit 800 and an output noise reduction circuit 900, and other structures are similar to those of Figure 2 The shift register unit 20 shown in FIG. 1 is substantially the same.

[0057] The output reset circuit 700 is connected to the output terminal OP1, and is configured to reset the output terminal OP1 in response to a first reset signal. For example, the output reset circuit is connected to the output terminal OP1, the first reset terminal RST1, and the first voltage terminal VSS, and is configured to electrically connect the output terminal OP1 and the first voltage terminal VSS under the control of the first reset signal provided by the first reset terminal RST1, thereby resetting the output terminal OP1, for example, making the voltage of the output terminal OP1 equal to the voltage of the first voltage terminal VSS.

[0058] For example, the output reset circuit 700 may be further connected to the first node PU and configured to reset the first node PU in response to a first reset signal. For example, the output reset circuit 700 may be further connected to the first node PU and configured to electrically connect the first node PU and the first voltage terminal VSS under the control of the first reset signal provided by the first reset terminal RST1, thereby resetting the first node PU, for example, making the voltage of the first node PU equal to the voltage of the first voltage terminal VSS. For example, the output reset circuit 700 may reset the first node PU before and after a frame of image scanning begins, or may reset the first node PU only before or after a frame of image scanning begins.

[0059] The first node reset circuit 800 is connected to the first node PU and is configured to reset the first node PU in response to the second reset signal. For example, the first node reset circuit 800 is connected to the first node PU, the second reset terminal RST2 and the first voltage terminal VSS, and is configured to electrically connect the first node PU and the first voltage terminal VSS under the control of the second reset signal provided by the second reset terminal RST2, thereby resetting the first node PU, for example, making the voltage of the first node PU equal to the voltage of the first voltage terminal VSS. For example, the first node reset circuit 800 resets the first node PU after the output of the shift register unit 30 ends.

[0060] The output noise reduction circuit 900 is connected to the first noise reduction node PD1, the second noise reduction node PD2 and the output terminal OP1 respectively, and is configured to perform noise reduction on the output terminal OP1 under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2. For example, the output noise reduction circuit 900 is connected to the first voltage terminal VSS, the output terminal OP1, the first noise reduction node PD1 and the second noise reduction node PD2, and is configured to electrically connect the output terminal OP1 to the first voltage terminal VSS under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, for example, to make the voltage of the output terminal OP1 equal to the voltage of the first voltage terminal VSS, thereby performing noise reduction (for example, pulling down) on the output terminal OP1.

[0061] Figure 4A schematic block diagram of another shift register unit provided in some embodiments of the present disclosure. Figure 3 The shift register unit 30 shown in FIG. Figure 4 In the illustrated embodiment, the output circuit 200 of the shift register unit 40 is not only connected to the output terminal OP1 (e.g., the scan signal output terminal), but also connected to the second output terminal OP2 (e.g., the shift signal output terminal) to improve the driving capability of the shift register unit 40. For example, the scan signal output terminal (e.g., the output terminal OP1) is used to provide a scan signal for a pixel circuit (pixel row), and the shift signal output terminal (e.g., the second output terminal OP2) is used to provide an input signal for other cascaded shift register units.

[0062] For example, the output circuit 200 is further configured to receive a clock signal and output the clock signal to the second output terminal OP2 under the control of the level of the first node PU. For example, the output circuit 200 is turned on under the control of the level of the first node PU, so that the clock signal terminal CLK is electrically connected to the second output terminal OP2, so that the output circuit 200 can output the clock signal to the second output terminal OP2 after receiving the clock signal.

[0063] Accordingly, the output noise reduction circuit 900 may also be configured to perform noise reduction on the second output terminal OP2 under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2. For example, the output noise reduction circuit 900 is also connected to the second output terminal OP2, and is configured to electrically connect the second output terminal OP2 to the first voltage terminal VSS under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, for example, to make the voltage of the second output terminal OP2 equal to the voltage of the first voltage terminal VSS, thereby performing noise reduction (for example, pulling down) on the second output terminal OP2.

[0064] Figure 5 for Figure 3 A circuit diagram of a specific implementation example of a shift register unit is shown in FIG. In the following description, each transistor is an N-type transistor as an example, but this does not constitute a limitation on the embodiments of the present disclosure. Figure 5 As shown, the shift register unit 30 includes first to nineteenth transistors M1 - M19 and a first capacitor C1 .

[0065] The noise reduction reset circuit 400 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is configured to be connected to the first reset terminal RST1 to receive a first reset signal, the first electrode of the first transistor M1 is configured to be connected to the first noise reduction node PD1, and the second electrode of the first transistor M1 is configured to be connected to the first voltage terminal VSS. The gate of the second transistor M2 is configured to be connected to the first reset terminal RST1 to receive the first reset signal, the first electrode of the second transistor M2 is configured to be connected to the second noise reduction node PD2, and the second electrode of the second transistor M2 is configured to be connected to the first voltage terminal VSS.

[0066] For example, when the first reset signal of the first reset terminal RST1 is at a high level, the first transistor M1 and the second transistor M2 are turned on, and the first noise reduction node PD1 and the second noise reduction node PD2 are electrically connected to the first voltage terminal VSS, thereby resetting the first noise reduction node PD1 and the second noise reduction node PD2.

[0067] The input circuit 100 includes a third transistor M3, a gate of the third transistor M3 is connected to the first electrode and is configured to be connected to the input terminal INT to receive an input signal, and a second electrode of the third transistor M3 is configured to be connected to the first node PU. When the input signal of the input terminal INT is at a high level, the third transistor M3 is turned on, and the input signal charges the first node PU to make it at a high level.

[0068] The output circuit 200 includes a fourth transistor M4 and a first capacitor C1. The gate of the fourth transistor M4 is configured to be connected to the first node PU, the first electrode of the fourth transistor M4 is configured to be connected to the clock signal terminal CLK to receive the clock signal, and the second electrode of the fourth transistor M4 is configured to be connected to the output terminal OP1. The first electrode of the first capacitor C1 is configured to be connected to the first node PU, and the second electrode of the first capacitor C1 is configured to be connected to the output terminal OP1. When the first node PU is at a high level, the fourth transistor M4 is turned on, so that the clock signal of the clock signal terminal CLK can be received, and a scanning signal, for example, can be output through the output terminal OP1.

[0069] The first node noise reduction circuit 300 includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is configured to be connected to the first noise reduction node PD1, the first electrode of the fifth transistor M5 is configured to be connected to the first node PU, and the second electrode of the fifth transistor M5 is configured to be connected to the first voltage terminal VSS. The gate of the sixth transistor M6 is configured to be connected to the second noise reduction node PD2, the first electrode of the sixth transistor M6 is configured to be connected to the first node PU, and the second electrode of the sixth transistor M6 is configured to be connected to the first voltage terminal VSS. When the level of the first noise reduction node PD1 is high, the fifth transistor M5 is turned on; when the level of the second noise reduction node PD2 is high, the sixth transistor M6 is turned on. When either the first noise reduction node PD1 or the second noise reduction node PD2 is high, the fifth transistor M5 or the sixth transistor M6 is turned on, electrically connecting the first node PU to the first voltage terminal VSS, so that the first node PU can be pulled down to a low level for noise reduction.

[0070] The first noise reduction circuit 510 includes a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is configured to be connected to the first control node PD_CN1, the first electrode of the seventh transistor M7 is configured to be connected to the second voltage terminal VDD1, and the second electrode of the seventh transistor M7 is configured to be connected to the first noise reduction node PD1. The gate of the eighth transistor M8 is configured to be connected to the first node PU, the first electrode of the eighth transistor M8 is configured to be connected to the first noise reduction node PD1, and the second electrode of the eighth transistor M8 is configured to be connected to the first voltage terminal VSS.

[0071] For example, when the first control node PD_CN1 is at a high level, the seventh transistor M7 is turned on, so that the first noise reduction node PD1 is electrically connected to the second voltage terminal VDD1, so that when the second voltage terminal VDD1 provides a high level signal, the first noise reduction node PD1 is charged to be at a high level. When the first node PU is at a high level, the eighth transistor M8 is turned on, so that the first noise reduction node PD1 is electrically connected to the first voltage terminal VSS, so that the first noise reduction node PD1 can be pulled down to a low level.

[0072] For example, when the first transistor M1 is turned on in response to the high level of the first reset signal to reset the first noise reduction node PD1, in order to ensure that the first voltage terminal VSS can pull the first noise reduction node PD1 down to a low level, it is necessary to set the parameters of the first transistor M1 and the seventh transistor M7 (such as the on-resistance, that is, the resistance between the drain and the source of the transistor). For example, the on-resistance of the first transistor M1 can be set to be smaller than the on-resistance of the seventh transistor M7, so that even when the seventh transistor M7 is turned on, the first voltage terminal VSS can pull the voltage of the first noise reduction node PD1 down to a voltage approximately equal to the first voltage terminal VSS, so as to achieve the effect of resetting the first noise reduction node PD1.

[0073] The first control circuit 610 includes a ninth transistor M9 and a tenth transistor M10. The gate of the ninth transistor M9 is connected to the first electrode and is configured to be connected to the second voltage terminal VDD1, and the second electrode of the ninth transistor M9 is configured to be connected to the first control node PD_CN1. The gate of the tenth transistor M10 is configured to be connected to the first node PU, the first electrode of the tenth transistor M10 is configured to be connected to the first control node PD_CN1, and the second electrode of the tenth transistor M10 is configured to be connected to the first voltage terminal VSS.

[0074] For example, when the second voltage terminal VDD1 provides a high level signal, the ninth transistor M9 is turned on, so that the first control node PD_CN1 is electrically connected to the second voltage terminal VDD1, thereby charging the first control node PD_CN1 to make it at a high level. When the first node PU is at a high level, the tenth transistor M10 is turned on, so that the first control node PD_CN1 is electrically connected to the first voltage terminal VSS, so that the first control node PD_CN1 can be pulled down to a low level.

[0075] The second noise reduction circuit 520 includes an eleventh transistor M11 and a twelfth transistor M12. The gate of the eleventh transistor M11 is configured to be connected to the second control node PD_CN2, the first electrode of the eleventh transistor M11 is configured to be connected to the third voltage terminal VDD2, and the second electrode of the eleventh transistor M11 is configured to be connected to the second noise reduction node PD2. The gate of the twelfth transistor M12 is configured to be connected to the first node PU, the first electrode of the twelfth transistor M12 is configured to be connected to the second noise reduction node PD2, and the second electrode of the twelfth transistor M12 is configured to be connected to the first voltage terminal VSS.

[0076] For example, when the second control node PD_CN2 is at a high level, the eleventh transistor M11 is turned on, so that the second noise reduction node PD2 is electrically connected to the third voltage terminal VDD2, so that when the third voltage terminal VDD2 provides a high level signal, the second noise reduction node PD2 is charged to be at a high level. When the first node PU is at a high level, the twelfth transistor M12 is turned on, so that the second noise reduction node PD2 is electrically connected to the first voltage terminal VSS, so that the second noise reduction node PD2 can be pulled down to a low level.

[0077] For example, when the second transistor M2 is turned on in response to the high level of the first reset signal to reset the second noise reduction node PD2, in order to ensure that the first voltage terminal VSS can pull the second noise reduction node PD2 down to a low level, it is necessary to set the parameters of the second transistor M2 and the eleventh transistor M11 (such as the on-resistance, that is, the resistance between the drain and the source of the transistor). For example, the on-resistance of the second transistor M2 can be set to be smaller than the on-resistance of the eleventh transistor M11, so that even when the eleventh transistor M11 is turned on, the first voltage terminal VSS can pull the voltage of the second noise reduction node PD2 down to a voltage approximately equal to the first voltage terminal VSS, so as to achieve the effect of resetting the second noise reduction node PD2.

[0078] The second control circuit 620 includes a thirteenth transistor M13 and a fourteenth transistor M14. The gate of the thirteenth transistor M13 is connected to the first electrode and is configured to be connected to the third voltage terminal VDD2, and the second electrode of the thirteenth transistor M13 is configured to be connected to the second control node PD_CN2. The gate of the fourteenth transistor M14 is configured to be connected to the first node PU, the first electrode of the fourteenth transistor M14 is configured to be connected to the second control node PD_CN2, and the second electrode of the fourteenth transistor M14 is configured to be connected to the first voltage terminal VSS.

[0079] For example, when the third voltage terminal VDD2 provides a high level signal, the thirteenth transistor M13 is turned on, so that the second control node PD_CN2 is electrically connected to the third voltage terminal VDD2, thereby charging the second control node PD_CN2 to make it at a high level. When the first node PU is at a high level, the fourteenth transistor M14 is turned on, so that the second control node PD_CN2 is electrically connected to the first voltage terminal VSS, so that the second control node PD_CN2 can be pulled down to a low level.

[0080] The output reset circuit 700 includes a fifteenth transistor M15. The gate of the fifteenth transistor M15 is configured to be connected to the first reset terminal RST1 to receive the first reset signal, the first electrode of the fifteenth transistor M15 is configured to be connected to the output terminal OP1, and the second electrode of the fifteenth transistor M15 is configured to be connected to the first voltage terminal VSS. When the first reset signal of the first reset terminal RST1 is at a high level, the fifteenth transistor M15 is turned on, and the output terminal OP1 is electrically connected to the first voltage terminal VSS, thereby resetting the output terminal OP1.

[0081] The output reset circuit 700 may further include a sixteenth transistor M16. The gate of the sixteenth transistor M16 is configured to be connected to the first reset terminal RST1 to receive the first reset signal, the first electrode of the sixteenth transistor M16 is configured to be connected to the first node PU, and the second electrode of the sixteenth transistor M16 is configured to be connected to the first voltage terminal VSS. When the first reset signal of the first reset terminal RST1 is at a high level, the sixteenth transistor M16 is turned on, electrically connecting the first node PU to the first voltage terminal VSS, thereby resetting the first node PU.

[0082] The first node reset circuit 800 includes a seventeenth transistor M17. The gate of the seventeenth transistor M17 is configured to be connected to the second reset terminal RST2 to receive the second reset signal, the first electrode of the seventeenth transistor M17 is configured to be connected to the first node PU, and the second electrode of the seventeenth transistor M17 is configured to be connected to the first voltage terminal VSS. When the second reset signal at the second reset terminal RST2 is at a high level, the seventeenth transistor M17 is turned on, electrically connecting the first node PU to the first voltage terminal VSS, thereby resetting the first node PU.

[0083] The output noise reduction circuit 900 includes an eighteenth transistor M18 and a nineteenth transistor M19. The gate of the eighteenth transistor M18 is configured to be connected to the first noise reduction node PD1, the first electrode of the eighteenth transistor M18 is configured to be connected to the output terminal OP1, and the second electrode of the eighteenth transistor M18 is configured to be connected to the first voltage terminal VSS. The gate of the nineteenth transistor M19 is configured to be connected to the second noise reduction node PD2, the first electrode of the nineteenth transistor M19 is configured to be connected to the output terminal OP1, and the second electrode of the nineteenth transistor M19 is configured to be connected to the first voltage terminal VSS. When the level of the first noise reduction node PD1 is high, the eighteenth transistor M18 is turned on; when the level of the second noise reduction node PD2 is high, the nineteenth transistor M19 is turned on. When either the first noise reduction node PD1 or the second noise reduction node PD2 is at a high level, the eighteenth transistor M18 or the nineteenth transistor M19 is turned on to electrically connect the output terminal OP1 to the first voltage terminal VSS, so that the scan signal of the output terminal OP1 can be pulled down to a low level for noise reduction.

[0084] Figure 6 for Figure 4 A circuit diagram of a specific implementation example of the shift register unit shown in FIG. Figure 6 As shown, when the output circuit 200 is connected to the second output terminal OP2, the output circuit 200 may further include a twentieth transistor M20, and accordingly, the output noise reduction circuit 900 may further include a twenty-first transistor M21 and a twenty-second transistor M22.

[0085] For example, the gate of the twentieth transistor M20 is configured to be connected to the first node PU, the first electrode of the twentieth transistor M20 is configured to be connected to the clock signal terminal CLK to receive the clock signal, and the second electrode of the twentieth transistor M20 is configured to be connected to the second output terminal OP2. When the first node PU is at a high level, the twentieth transistor M20 is turned on, so that the clock signal of the clock signal terminal CLK can be received and output through the second output terminal OP2.

[0086] The gate of the twenty-first transistor M21 is configured to be connected to the first noise reduction node PD1, the first electrode of the twenty-first transistor M21 is configured to be connected to the second output terminal OP2, and the second electrode of the twenty-first transistor M21 is configured to be connected to the first voltage terminal VSS. The gate of the twenty-second transistor M22 is configured to be connected to the second noise reduction node PD2, the first electrode of the twenty-second transistor M22 is configured to be connected to the second output terminal OP2, and the second electrode of the twenty-second transistor M22 is configured to be connected to the first voltage terminal VSS. When the level of the first noise reduction node PD1 is high, the twenty-first transistor M21 is turned on; when the level of the second noise reduction node PD2 is high, the twenty-second transistor M22 is turned on. When either the first noise reduction node PD1 or the second noise reduction node PD2 is high, the twenty-first transistor M21 or the twenty-second transistor M22 is turned on, electrically connecting the second output terminal OP2 to the first voltage terminal VSS, so that the output signal of the second output terminal OP2 can be pulled down to a low level for noise reduction.

[0087] It should be noted that in each embodiment of the present disclosure, the first capacitor C1 can be a capacitor device manufactured by a process, for example, the capacitor device is realized by making a special capacitor electrode, and the various electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc., and the first capacitor C1 can also be a parasitic capacitor between transistors, which can be realized by the transistor itself and other devices and circuits.

[0088] It should be noted that in the description of the various embodiments of the present disclosure, the first node PU, the first noise reduction node PD1, the second noise reduction node PD2, the first control node PD_CN1 and the second control node PD_CN2 do not represent actual components, but represent the meeting points of related electrical connections in the circuit diagram.

[0089] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are all described by taking thin film transistors as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate (i.e., the source and the drain), one of the poles is directly described as the first pole and the other pole is directly described as the second pole.

[0090] In addition, the transistors in the embodiments of the present disclosure are all described by taking N-type transistors as an example. In this case, the first electrode of the transistor is the drain electrode and the second electrode is the source electrode. It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the shift register unit 10 / 20 / 30 / 40 provided in the embodiments of the present disclosure may also adopt P-type transistors. In this case, the first electrode of the transistor is the source electrode and the second electrode is the drain electrode. It is only necessary to connect the electrodes of the selected type of transistors with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and make the corresponding voltage terminals provide the corresponding high voltage or low voltage. When an N-type transistor is used, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0091] In the embodiments of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the term "pull-up" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (for example, turn-on); "pull-down" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode decreases, thereby realizing the operation of the corresponding transistor (for example, turn-on). For another example, when each circuit is implemented as a P-type transistor, the term "pull-up" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode decreases, thereby realizing the operation of the corresponding transistor (for example, turn-on); "pull-down" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (for example, turn-on).

[0092] Figure 7 and Figure 8 A signal timing diagram of a shift register unit provided in some embodiments of the present disclosure. For example, Figure 7 As shown, the second voltage terminal VDD1 and the third voltage terminal VDD2 are configured to alternately provide DC high level signals. For example, the second voltage terminal VDD1 and the third voltage terminal VDD2 respectively provide alternating DC high level signals and DC low level signals, and the signals provided by the second voltage terminal VDD1 and the third voltage terminal VDD2 are inverted signals to each other.

[0093] The following is only Figure 8 As an example, the second voltage terminal VDD1 provides a DC high level signal, and the third voltage terminal VDD2 provides a DC low level signal. Figure 5 The working principle of the shift register unit 30 shown in the figure is described; the second voltage terminal VDD1 provides a DC low level signal, and the third voltage terminal VDD2 provides a DC high level signal. The one-frame display timing is similar to this, and will not be repeated. Here, each transistor is an N-type transistor as an example for description, but the embodiments of the present disclosure are not limited to this.

[0094] It should be noted that in Figure 8 In the figure and the following description, RST1, VDD1, VDD2, PD1, PD2, CLK, INT, PU, ​​OP1, etc. are used to indicate both the corresponding signal terminals or nodes and the levels of the corresponding signals or nodes.

[0095] exist Figure 8 In the first to sixth stages 1-6 shown, the shift register unit 30 can respectively perform the following operations.

[0096] In the first stage 1, the second voltage signal VDD1 is switched from a DC low level signal to a DC high level signal, the third voltage signal VDD2 is switched from a DC high level signal to a DC low level signal, the ninth transistor M9 is turned on, and the thirteenth transistor M13 is turned off. The input terminal INT provides a low level signal, the third transistor M3 is turned off, the first node PU (due to being reset) is at a low level, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12 and the fourteenth transistor M14 are turned off. The first control node PD_CN1 is pulled up to a high level by the ninth transistor M9, the seventh transistor M7 is turned on, and the first noise reduction node PD1 is pulled up to a high level. The fifth transistor M5 and the eighteenth transistor M18 are turned on, thereby respectively reducing the noise of the first node PU and the output terminal OP1.

[0097] Since the thirteenth transistor M13 is turned off, the charge of the second noise reduction node PD2 can only leak away slowly through the thirteenth transistor M13 and cannot be released quickly. Therefore, although the level of the second noise reduction node PD2 decreases slightly due to the charge release, it is still in a high level state.

[0098] In the second stage 2, the first reset terminal RST1 provides a high-level signal, the first transistor M1 and the second transistor M2 are turned on, and the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 are pulled down to a low level, so that the charge of the second noise reduction node PD2 is leaked through the second transistor M2 and released quickly. Further, when the input terminal INT provides a high-level input signal in the subsequent stage, the residual charge of the second noise reduction node PD2 can be prevented from affecting the charging of the first node PU, so that the first node PU is fully charged, ensuring that when the high-level clock signal provided by the clock signal terminal CLK in the subsequent stage comes, the amplitude of the scanning signal output by the output terminal OP1 can remain stable, so that the display device including the shift register unit 30 can display the picture normally, thereby improving the stability and reliability of the display device.

[0099] In the third stage 3, the first reset terminal RST1 provides a low level signal, and the level of the first noise reduction node PD1 is pulled up to a high level again under the action of the high level second voltage signal VDD1. Therefore, under the control of the high level of the first noise reduction node PD1, the fifth transistor M5 and the eighteenth transistor M18 are turned on, thereby continuing to reduce noise on the first node PU and the output terminal OP1 respectively.

[0100] In the fourth stage 4, the input terminal INT provides a high-level input signal, the third transistor M3 is turned on, the first node PU is charged to a high level, and the fourth transistor M4 is turned on. The fourth transistor M4 outputs the clock signal of the clock signal terminal CLK to the output terminal OP1; and the clock signal is still at a low level in this stage. The eighth transistor M8 and the tenth transistor M10 are turned on under the action of the high level of the first node PU. Due to the series voltage division of the ninth transistor M9 and the tenth transistor M10, the first control node PD_CN1 is pulled down to a low level. The seventh transistor M7 is turned off, and the first noise reduction node PD1 is pulled down to a low level by the turned-on eighth transistor M8.

[0101] In the fifth stage 5, the clock signal of the clock signal terminal CLK becomes high level, and the potential of the first node PU is further increased due to the coupling effect (bootstrap effect) of the level of the output terminal OP1 through the first capacitor C1, so that the fourth transistor M4 is fully turned on, and the high level of the clock signal is output to the output terminal OP1 as, for example, a scanning signal. The first noise reduction node PD1 and the second noise reduction node PD2 remain at a low level, and the eighteenth transistor M18 and the nineteenth transistor M19 remain turned off, which will not affect the output.

[0102] In the sixth stage 6, the clock signal of the clock signal terminal CLK becomes low level, the potential of the first node PU is reduced due to coupling, but is still high level, the fourth transistor M4 remains turned on, and the low level of the clock signal is output to the output terminal OP1, so that the output terminal OP1 outputs a low level scan signal.

[0103] In the subsequent stage, the second reset terminal RST2 provides a high level signal ( Figure 8 The first control node PD_CN1 is pulled up to a high level by the ninth transistor M9, and the seventh transistor M7 is turned on, pulling up the first noise reduction node PD1 to a high level. The fifth transistor M5 and the eighteenth transistor M18 are turned on, thereby continuously reducing noise on the first node PU and the output terminal OP1, respectively.

[0104] At least one embodiment of the present disclosure further provides a gate driving circuit, which includes the shift register unit described in any embodiment of the present disclosure.

[0105] Fig. 9 A schematic block diagram of a gate drive circuit provided in some embodiments of the present disclosure. Fig. 9As shown, the gate drive circuit 50 includes a plurality of cascaded shift register units (SRn, SRn+1, SRn+2, SRn+3, etc.). The number of the plurality of shift register units is not limited and can be determined according to actual needs. For example, the shift register unit adopts the shift register unit 10 / 20 / 30 / 40 described in any embodiment of the present disclosure. For example, in the gate drive circuit 50, some or all of the shift register units can adopt the shift register unit 10 / 20 / 30 / 40 described in any embodiment of the present disclosure. The gate drive circuit 50 can be directly integrated on the array substrate of the display device using the same process as the thin film transistor to realize the line-by-line scanning drive function.

[0106] For example, the plurality of shift register units respectively have an input terminal INT, a first reset terminal RST1, a second reset terminal RST2, an output terminal OP1 (eg, a scan signal output terminal) and a second output terminal OP2 (eg, a shift signal output terminal). For simplicity, other signal terminals that should be present are not shown or marked in the figure.

[0107] For example, the first reset terminal RST1 of each stage of the shift register unit receives the first reset signal provided. For example, except for the first stage, the second output terminal OP2 of each stage of the shift register unit is connected to the second reset terminal RST2 of the previous stage of the shift register unit. For example, except for the last stage, the second output terminal OP2 of each stage of the shift register unit is connected to the input terminal INT of the next stage of the shift register unit. For example, the input terminal INT of the first stage of the shift register unit is configured to receive the trigger signal STV1; the second reset terminal RST2 of the last stage of the shift register unit is configured to receive the reset signal provided separately. Of course, the above is the case of forward scanning. When scanning in reverse, the trigger signal STV1 used for the first stage of the shift register unit is replaced by the reset signal, and the reset signal used for the last stage of the shift register unit is replaced by the trigger signal STV1.

[0108] For example, in the case where each level of the shift register unit of the gate driving circuit does not include the second output terminal OP2, except for the first level, the output terminal OP1 of each level of the shift register unit is connected to the second reset terminal RST2 of the previous level of the shift register unit. For example, except for the last level, the output terminal OP1 of each level of the shift register unit is connected to the input terminal INT of the next level of the shift register unit. For example, the input terminal INT of the first level of the shift register unit is configured to receive the trigger signal STV1; the second reset terminal RST2 of the last level of the shift register unit is configured to receive a reset signal provided separately. Of course, the above is the case of forward scanning. When scanning in reverse, the trigger signal STV1 used for the first level of the shift register unit is replaced by the reset signal, and the reset signal used for the last level of the shift register unit is replaced by the trigger signal STV1.

[0109] For example, the gate drive circuit 50 further includes a first system clock CLK1 and a second system clock CLK2, and the clock signals output by the two are, for example, complementary to each other. For example, the odd-numbered shift register units (e.g., SRn and SRn+2) are connected to the first system clock CLK1 to receive the clock signal, and the even-numbered shift register units (e.g., SRn+1 and SRn+3) are connected to the second system clock CLK2 to receive the clock signal, so as to ensure that the output signals of the output terminals OP1 and the second output terminals OP2 of each shift register unit are shifted.

[0110] For example, the gate drive circuit 50 may further include a timing controller, which is configured to provide a first system clock signal and a second system clock signal to each level of the shift register unit, and the timing controller may also be configured to provide a trigger signal STV1. In different examples, more system clocks may be provided, such as 4, 6, etc., according to different configurations.

[0111] It should be noted that in various embodiments of the present disclosure, the cascading method of the shift register units at each level in the gate drive circuit 50 and the connection method with the system clock are not limited, and can be the above-mentioned method or other applicable connection methods, and the embodiments of the present disclosure are not limited to this.

[0112] For example, the gate driving circuit 50 further includes a first voltage line LVSS, a second voltage line LVDD1, a third voltage line LVDD2 and other voltage lines not shown to provide the first voltage, the second voltage, the third voltage and other required voltages to each shift register unit.

[0113] For example, when the gate drive circuit 50 is used to drive a display panel, the gate drive circuit 50 can be arranged on one side of the display panel. For example, the display panel includes multiple rows of gate lines, and the output terminal OP1 of the shift register unit at each level in the gate drive circuit 50 can be configured to be connected with the multiple rows of gate lines in sequence for outputting scanning signals. Of course, the gate drive circuit 50 can also be arranged on both sides of the display panel respectively to realize bilateral driving, and the embodiments of the present disclosure do not limit the arrangement mode of the gate drive circuit 50. For example, the gate drive circuit 50 can be arranged on one side of the display panel for driving the odd-numbered rows of gate lines, and the gate drive circuit 50 can be arranged on the other side of the display panel for driving the even-numbered rows of gate lines.

[0114] At least one embodiment of the present disclosure further provides a display device, which includes the gate driving circuit described in any embodiment of the present disclosure.

[0115] Fig.10 A schematic block diagram of a display device provided in some embodiments of the present disclosure. Fig.10 As shown, the display device 60 includes a gate drive circuit 50, and the gate drive circuit 50 is the gate drive circuit described in any embodiment of the present disclosure. For example, the display device 60 can be a liquid crystal panel, a liquid crystal TV, an OLED panel, an OLED TV, a display, an electronic paper display device, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited to this. The technical effect of the display device 60 can refer to the corresponding description of the shift register unit 10 / 20 / 30 / 40 and the gate drive circuit 50 in the above embodiments, which will not be repeated here.

[0116] For example, in one example, the display device 60 includes a display panel 6000, a gate driver 6010, a timing controller 6020, and a data driver 6030. The display panel 6000 includes a plurality of pixel units P defined by a plurality of gate lines GL and a plurality of data lines DL; the gate driver 6010 is used to drive the plurality of gate lines GL; the data driver 6030 is used to drive the plurality of data lines DL; the timing controller 6020 is used to process image data RGB input from outside the display device 60, provide the processed image data RGB to the data driver 6030, and output a scan control signal GCS and a data control signal DCS to the gate driver 6010 and the data driver 6030 to control the gate driver 6010 and the data driver 6030.

[0117] For example, the gate driver 6010 includes the gate driving circuit 50 provided in any of the above embodiments. The output terminals OP1 of the plurality of shift register units 10 / 20 / 30 / 40 in the gate driving circuit 50 are connected to the plurality of gate lines GL in correspondence. The plurality of gate lines GL are connected to the pixel units P arranged in a plurality of rows in correspondence. The output terminals OP1 of the shift register units 10 / 20 / 30 / 40 at each level in the gate driving circuit 50 sequentially output signals to the plurality of gate lines GL so that the plurality of rows of pixel units P in the display panel 6000 are scanned row by row. For example, the gate driver 6010 can be implemented as a semiconductor chip, or can be integrated in the display panel 6000 to form a GOA circuit.

[0118] For example, the data driver 6030 converts the digital image data RGB input from the timing controller 6020 into data signals according to a plurality of data control signals DCS from the timing controller 6020 using a reference gamma voltage. The data driver 6030 provides the converted data signals to a plurality of data lines DL. For example, the data driver 6030 may be implemented as a semiconductor chip.

[0119] For example, the timing controller 6020 processes the externally input image data RGB to match the size and resolution of the display panel 6000, and then provides the processed image data to the data driver 6030. The timing controller 6020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using a synchronization signal SYNC (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 60. The timing controller 6020 provides the generated scan control signal GCS and data control signal DCS to the gate driver 6010 and the data driver 6030, respectively, for control of the gate driver 6010 and the data driver 6030.

[0120] The display device 60 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, which will not be described in detail here.

[0121] At least one embodiment of the present disclosure further provides a method for driving a shift register unit, which can be used to drive the shift register unit 10 / 20 / 30 / 40 described in any embodiment of the present disclosure.

[0122] For example, in one example, the driving method of the shift register unit 10 / 20 / 30 / 40 includes the following operations:

[0123] In the noise reduction reset stage (i.e., the aforementioned second stage 2), the noise reduction reset circuit 400 resets the first noise reduction node PD1 and the second noise reduction node PD2 in response to the first reset signal;

[0124] In the input stage (ie, the aforementioned fourth stage 4), the input circuit 100 writes the input signal into the first node PU in response to the input signal; and

[0125] In the output stage (ie the aforementioned fifth stage 5), the output circuit 200 outputs the clock signal to the output terminal OP1 under the control of the level of the first node PU.

[0126] It should be noted that for the detailed description of the driving method and the technical effects, reference may be made to the corresponding description of the shift register unit 10 / 20 / 30 / 40 in the embodiments of the present disclosure, which will not be repeated here.

[0127] There are a few points to note:

[0128] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0129] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0130] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A shift register unit, comprising an input circuit, an output circuit, a first node noise reduction circuit and a noise reduction reset circuit; in, The input circuit is connected to the first node and is configured to write the input signal into the first node in response to an input signal to control the level of the first node; The output circuit is connected to the first node and the output terminal, and is configured to receive a clock signal and output the clock signal to the output terminal under the control of the level of the first node; The first node noise reduction circuit is connected to the first node, the first noise reduction node, the second noise reduction node and the first voltage terminal respectively, and is configured to electrically connect the first node and the first voltage terminal under the control of the level of the first noise reduction node or the level of the second noise reduction node to perform noise reduction on the first node; The noise reduction reset circuit is connected to the first noise reduction node, the second noise reduction node and the first voltage terminal, and is configured to electrically connect the first noise reduction node and the second noise reduction node to the first voltage terminal respectively in response to a first reset signal, so as to reset the first noise reduction node and the second noise reduction node; The shift register unit also includes: an output noise reduction circuit, wherein the output noise reduction circuit is connected to the first noise reduction node, the second noise reduction node and the output end respectively, and is configured to perform noise reduction on the output end under the control of the level of the first noise reduction node or the level of the second noise reduction node; and A first node reset circuit, wherein the first node reset circuit is connected to the first node and is configured to reset the first node in response to a second reset signal.

2. The shift register unit according to claim 1, further comprising a first noise reduction circuit, a second noise reduction circuit, a first control circuit and a second control circuit; in, The first noise reduction circuit is connected to the first node, the first noise reduction node and the first control node respectively, and is configured to control the level of the first noise reduction node under the control of the level of the first node and the level of the first control node; The second noise reduction circuit is connected to the first node, the second noise reduction node and the second control node respectively, and is configured to control the level of the second noise reduction node under the control of the level of the first node and the level of the second control node; The first control circuit is connected to the first node and the first control node, and is configured to control the level of the first control node under the control of the level of the first node; The second control circuit is connected to the first node and the second control node, and is configured to control the level of the second control node under the control of the level of the first node.

3. The shift register unit according to claim 1 further comprising an output reset circuit, in, The output reset circuit is connected to the output terminal and is configured to reset the output terminal in response to the first reset signal.

4. The shift register unit according to claim 3, wherein: The output reset circuit is also connected to the first node and configured to reset the first node in response to the first reset signal.

5. The shift register unit according to any one of claims 1 to 4, wherein: The noise reduction reset circuit includes a first transistor and a second transistor; The gate of the first transistor is connected to the first reset terminal to receive the first reset signal, the first electrode of the first transistor is connected to the first noise reduction node, and the second electrode of the first transistor is connected to the first voltage terminal; The gate of the second transistor is connected to the first reset terminal to receive the first reset signal, the first electrode of the second transistor is connected to the second noise reduction node, and the second electrode of the second transistor is connected to the first voltage terminal.

6. The shift register unit according to any one of claims 1 to 4, wherein: The input circuit includes a third transistor; A gate of the third transistor is connected to the first electrode and to the input terminal to receive the input signal, and a second electrode of the third transistor is connected to the first node.

7. The shift register unit according to any one of claims 1 to 4, wherein: The output circuit includes a fourth transistor and a first capacitor; The gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the clock signal terminal to receive the clock signal, and the second electrode of the fourth transistor is connected to the output terminal; A first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to the output end.

8. The shift register unit according to any one of claims 1 to 4, wherein: The first node noise reduction circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is connected to the first noise reduction node, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the first voltage terminal; A gate of the sixth transistor is connected to the second noise reduction node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the first voltage terminal.

9. The shift register unit according to claim 2, wherein: The first noise reduction circuit includes a seventh transistor and an eighth transistor, The gate of the seventh transistor is connected to the first control node, the first electrode of the seventh transistor is connected to the second voltage terminal, and the second electrode of the seventh transistor is connected to the first noise reduction node. The gate of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the first noise reduction node, and the second electrode of the eighth transistor is connected to the first voltage terminal; The first control circuit includes a ninth transistor and a tenth transistor, The gate of the ninth transistor is connected to the first electrode and to the second voltage terminal, and the second electrode of the ninth transistor is connected to the first control node. A gate of the tenth transistor is connected to the first node, a first electrode of the tenth transistor is connected to the first control node, and a second electrode of the tenth transistor is connected to the first voltage terminal.

10. The shift register unit according to claim 2, wherein: The second noise reduction circuit includes an eleventh transistor and a twelfth transistor, The gate of the eleventh transistor is connected to the second control node, the first electrode of the eleventh transistor is connected to the third voltage terminal, and the second electrode of the eleventh transistor is connected to the second noise reduction node. The gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the second noise reduction node, and the second electrode of the twelfth transistor is connected to the first voltage terminal; The second control circuit includes a thirteenth transistor and a fourteenth transistor, The gate of the thirteenth transistor is connected to the first electrode and to the third voltage terminal, and the second electrode of the thirteenth transistor is connected to the second control node. A gate of the fourteenth transistor is connected to the first node, a first electrode of the fourteenth transistor is connected to the second control node, and a second electrode of the fourteenth transistor is connected to the first voltage terminal.

11. The shift register unit according to claim 3 or 4, wherein: The output reset circuit includes a fifteenth transistor; The gate of the fifteenth transistor is connected to the first reset terminal to receive the first reset signal, the first electrode of the fifteenth transistor is connected to the output terminal, and the second electrode of the fifteenth transistor is connected to the first voltage terminal.

12. The shift register unit according to claim 4, wherein: The output reset circuit includes a sixteenth transistor; A gate of the sixteenth transistor is connected to the first reset terminal to receive the first reset signal, a first electrode of the sixteenth transistor is connected to the first node, and a second electrode of the sixteenth transistor is connected to the first voltage terminal.

13. The shift register unit according to claim 1, wherein: The first node reset circuit includes a seventeenth transistor; The gate of the seventeenth transistor is connected to the second reset terminal to receive the second reset signal, the first electrode of the seventeenth transistor is connected to the first node, and the second electrode of the seventeenth transistor is connected to the first voltage terminal.

14. The shift register unit according to claim 1, wherein: The output noise reduction circuit includes an eighteenth transistor and a nineteenth transistor; The gate of the eighteenth transistor is connected to the first noise reduction node, the first electrode of the eighteenth transistor is connected to the output terminal, and the second electrode of the eighteenth transistor is connected to the first voltage terminal; A gate of the nineteenth transistor is connected to the second noise reduction node, a first electrode of the nineteenth transistor is connected to the output end, and a second electrode of the nineteenth transistor is connected to the first voltage end.

15. A method for driving a shift register unit according to any one of claims 1 to 14, comprising: In the noise reduction reset stage, the noise reduction reset circuit resets the first noise reduction node and the second noise reduction node in response to the first reset signal; In the input stage, the input circuit writes the input signal into the first node in response to the input signal; as well as In the output stage, the output circuit outputs the clock signal to the output end under the control of the level of the first node.

16. A gate driving circuit, comprising a plurality of cascaded shift register units according to any one of claims 1 to 14.

17. A display device comprising the gate driving circuit according to claim 16.

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