Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a shift register, and the shift register comprises a plurality of shift register units. The shift register unit comprises an input module, an output module and a voltage stabilizing module. The input module is configured to write voltage into a first node and a second node at least based on an input signal and a first clock signal, and the output module is connected with the first node and the second node; the output module is configured to output a high-level signal based on the voltage of the first node and is also configured to output a low-level signal based on the voltage of the second node; the voltage stabilizing module is at least connected with the first node; in at least part of the time period when the first node is high in potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and the first voltage signal. The shift register unit can be ensured to stably output a high-level enable signal, and the product performance reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Indium Gallium Zinc Oxide (IGZO) is a material used for the channel layer in the new generation of thin film transistor technology, and is a type of metal oxide panel technology. IGZO transistors have the advantages of high mobility and low leakage current, which can better improve display afterimages in applications and reduce costs. Currently, pixel circuits made entirely of metal oxide transistors have become one of the technological development trends, so providing a shift drive circuit that matches them is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a display panel and a display device, so as to provide a shift driving circuit capable of stably outputting a scanning signal, thereby improving the product yield.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, the display panel includes a shift register, the shift register includes a plurality of shift register units; the shift register unit includes an input module, an output module and a voltage stabilizing module;

[0005] The input module is configured to write voltages to the first node and the second node respectively based on at least the input signal and the first clock signal, and the output module is connected to the first node and the second node respectively; the output module is configured to output a high level signal based on the voltage of the first node, and is also configured to output a low level signal based on the voltage of the second node;

[0006] The voltage stabilizing module is connected to at least the first node; during at least a portion of the time when the first node is at a high potential, the voltage stabilizing module is configured to increase the potential of the first node based on the voltage of the first node and the first voltage signal.

[0007] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising a display panel provided by any embodiment of the present invention.

[0008] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: a plurality of cascaded shift register units are provided in the display panel, each transistor in the shift register unit is an n-type transistor, a voltage stabilizing module is added to the shift register unit, and the voltage stabilizing module can pull up the potential of the first node during at least part of the period when the first node is at a high potential, so that the first node is stably maintained at a high potential, thereby ensuring that the shift register unit stably outputs a high-level signal. Then the shift register unit can stably provide a high-level enable signal to the n-type transistor in the pixel circuit, ensuring that the pixel circuit works stably and improving the product performance reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a pixel circuit in the related art;

[0011] Figure 2 A schematic diagram of a shift register unit in the related art;

[0012] Figure 3 for Figure 2 A timing diagram of a shift register unit in an embodiment;

[0013] Figure 4 A simplified schematic diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0015] Figure 6 A timing diagram provided for an embodiment of the present invention;

[0016] Figure 7 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0017] Figure 8 Another timing diagram provided for an embodiment of the present invention;

[0018] Fig. 9 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0019] Fig.10 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0020] Fig.11 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0021] Fig.12 Another timing diagram provided for an embodiment of the present invention;

[0022] Fig.13 Another timing diagram provided for an embodiment of the present invention;

[0023] Fig.14 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0024] Fig.15 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0025] Fig.16 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0026] Fig.17 Another timing diagram provided for an embodiment of the present invention;

[0027] Fig.18 A schematic diagram of a cascade of shift register units provided by an embodiment of the present invention;

[0028] Fig.19 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0029] Fig. 20 Another schematic diagram of cascaded shift register units provided by an embodiment of the present invention;

[0030] Fig.21 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0031] Fig. 22 Another timing diagram provided for an embodiment of the present invention;

[0032] Fig.23 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0033] Fig.24 Another timing diagram provided for an embodiment of the present invention;

[0034] Fig.25 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0035] Fig.26 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0036] Fig. 27 A schematic diagram of a display device provided for the implementation of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0039] Figure 1 FIG. 1 is a schematic diagram of a pixel circuit in the related art. Figure 1 As shown, the pixel circuit includes a driving transistor DT, a data writing transistor T1, a gate reset transistor T2, a light emitting control transistor T3, an electrode reset transistor T4, and a storage capacitor C1. The driving transistor DT is a dual-gate structure, including a top gate and a bottom gate, wherein the top gate is connected to the data writing transistor T1, the gate reset transistor T2, and one plate of the storage capacitor C1, and the bottom gate is connected to the other plate of the storage capacitor C1. The operation of the pixel circuit also requires a first power supply signal ELVDD, a reset signal Vref, a constant voltage signal Vini, a data signal Data, a light emitting control signal EM1, a scan signal G1, a scan signal G2, and a scan signal G3. The pixel circuit is connected to the first electrode of the light emitting device OLED (Organic Light-Emitting Diode), and the second electrode of the light emitting device OLED is connected to the second power supply signal ELVSS, and Coled represents the parasitic capacitance of the light emitting device OLED itself. The active layer of each transistor in the pixel circuit includes a metal oxide, and the transistor is an n-type transistor. The control signals required by the pixel circuit, such as the light emitting control signal EM1, the scanning signal G1, the scanning signal G2, and the scanning signal G3, have an enable level of a high level, so a shift register unit capable of providing a high level enable level is required.

[0040] Figure 2 Schematic diagram of a shift register unit in the related art, such as Figure 2As shown, the shift register unit includes an input module 01 and an output module 02. The output module 02 includes a first output tube T1' and a second output tube T2', a second capacitor C2 and a third capacitor C3. The output end of the input module 01 is connected to the node N1 and the node NB1, the control end of the first output tube T1' is connected to the node N2, the node N2 is connected to the node N1 through the switch tube T3', and the control end of the second output tube T2' is connected to the node NB1. The first end of the first output tube T1' receives a high-level signal VGH, and the second end is connected to the output end OUT of the shift register unit. The first end of the second output tube T2' receives a low-level signal VGL, and the second end is connected to the output end OUT of the shift register unit. The control end of the switch tube T3' receives the high-level signal VGH. The first output tube T1', the second output tube T2', and the switch tube T3' are all n-type transistors. The input module 01 writes signals to the node N1 and the node NB1 respectively under the control of the input signal STV and the clock signal CK'.

[0041] Figure 3 for Figure 2 A timing diagram of the shift register unit in an embodiment. Figure 3 The potential changes at each node are shown in Figure . Figure 3 As shown, during the period when the node N2 is at a high level, the first output tube T1' is turned on and provides a high level signal VGH to the output terminal OUT, and the output terminal OUT outputs a high level signal; during the period when the node NB1 is at a high level, the second output tube T2' is turned on and provides a low level signal VGL to the output terminal OUT, and the output terminal OUT outputs a low level signal. Since the threshold voltage range of the n-type transistor is small, during the period when the node N2 is written at a high level, the node N2 will leak electricity to the node N1 through the switch tube T3', causing the potential of the node N2 to decrease (such as Figure 3 The potential change of the node N2 affects the opening state of the first output tube T1', thereby affecting the output capability of the high-level signal. When the high-level signal is used as an enable signal, it affects the operation of the pixel circuit, resulting in abnormal display.

[0042] In order to solve the problems existing in the related art, an embodiment of the present invention provides a display panel, wherein a voltage stabilizing module is provided in a shift register unit, and the voltage stabilizing module is used to stabilize the potential of the control end of the output module, so that the output module stably outputs a high-level enable signal. In the application, the shift register unit outputs a stable high-level enable signal to drive the n-type transistor in the pixel circuit.

[0043] Figure 4 A simplified schematic diagram of a display panel provided by an embodiment of the present invention. Figure 4As shown, the display panel includes a plurality of pixel circuits 10 arranged in an array, and the pixel circuits 10 are arranged in a pixel circuit row 10H in the horizontal direction. A plurality of cascaded shift register units 20 form a shift register 2, and the output end of the shift register unit 20 is connected to each pixel circuit 10 in the pixel circuit row 10H through a scan line 30. Among them, the pixel circuit 10 includes at least one n-type transistor, and the output end of the shift register unit 20 outputs a high-level enable signal to drive the n-type transistor in the pixel circuit 10. Figure 4 It is shown that the shift register unit 20 is disposed on one side of the pixel circuit row 10H. In other embodiments, the shift register units 20 are disposed on both sides of the pixel circuit row 10H.

[0044] Figure 5 A schematic diagram of a shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the shift register unit includes an input module 21, an output module 22 and a voltage stabilizing module 23. The input module 21 is configured to write voltages to the first node Q1 and the second node Q2 respectively based on at least the input signal STV and the first clock signal CK1, and the output module 22 is connected to the first node Q1 and the second node Q2 respectively; the output module 22 is configured to output a high-level signal based on the voltage of the first node Q1, and is also configured to output a low-level signal based on the voltage of the second node Q2. Optionally, the output module 22 includes a third output tube M3 and a fourth output tube M4, the third output tube M3 provides a high-level signal VGH to the output terminal OUT under the high-level control of the first node Q1, and the fourth output tube M4 provides a low-level signal VGL to the output terminal OUT under the high-level control of the second node Q2. The high-level signal output by the output terminal OUT is used as an enable signal for driving the n-type transistor in the pixel circuit.

[0045] The voltage stabilizing module 23 is connected to at least the first node Q1; during at least a portion of the time when the first node Q1 is at a high potential, the voltage stabilizing module 23 is configured to pull up the potential of the first node Q1 based on the voltage of the first node Q1 and the first voltage signal VG1. The first voltage signal VG1 is a high level signal during at least a portion of the time.

[0046] An embodiment of the present invention provides a display panel, in which a voltage stabilizing module 23 is added to a shift register unit 20. The voltage stabilizing module 23 can raise the potential of the first node Q1 during at least part of the time period when the first node Q1 is at a high potential, so that the first node Q1 is stably maintained at a high potential, thereby ensuring that the shift register unit 20 stably outputs a high-level signal. The shift register unit 20 can stably provide a high-level enable signal to the n-type transistor in the pixel circuit 10, thereby ensuring that the pixel circuit 10 works stably and improving the product performance reliability.

[0047] In some embodiments, at least the transistor connected to the first node Q1 in the output module 22 is an n-type transistor. The n-type transistor is turned on under high-level control and turned off under low-level control. In the embodiment of the present invention, the voltage stabilizing module 23 is set to stably maintain the high potential during the period when the first node Q1 is at a high potential, which can ensure that the n-type transistor in the output module 22 maintains a stable open state, thereby allowing the shift register unit 20 to stably output a high-level signal. Optionally, all transistors in the output module 22 are n-type transistors.

[0048] In some embodiments, all transistors in the shift register unit 20 are n-type transistors. Such an arrangement enables the active layers of each transistor to be made of the same material, which can simplify the film manufacturing process of the display panel and reduce the manufacturing cost. In addition, when at least part of the transistors in the pixel circuit of the display panel are made of n-type transistors, the shift register unit 20 can also match the manufacturing process of the pixel circuit to simplify the manufacturing process of the display panel.

[0049] In the embodiment of the present invention, the active layer of the n-type transistor in the shift register unit 20 includes indium gallium zinc oxide. The indium gallium zinc oxide transistor has the advantages of high mobility and low leakage current, and can improve the circuit performance reliability of the shift register unit 20.

[0050] In some embodiments, Figure 6 A timing diagram provided in an embodiment of the present invention can be used to drive Figure 5 The shift register unit 20 is provided. Figure 6 As shown, the operation of the shift register unit 20 includes a first period t1 and a second period t2; at least in the first period t1 and the second period t2, the first node Q1 is at a high potential. In the first period t1, the voltage of the first node Q1 is V1; in the second period t2, the voltage of the first node Q1 is V2, V2>V1. Figure 6 The timing diagram shows that the potential of the first node Q1 in the second period t2 is higher than that in the first period t1. In this embodiment, the voltage stabilizing module 23 pulls the potential of the first node Q1 higher in the second period t2, so that the first node Q1 can be stably maintained at a high potential, thereby ensuring that the shift register unit 20 stably outputs a high-level signal, and the shift register unit 20 can provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10, ensuring that the pixel circuit 10 works stably and improving the product performance reliability.

[0051] In some embodiments, the operation of the shift register unit 20 includes m first time periods t1 and m second time periods t2, where m is an integer and m≥1; in time sequence, the first time periods t1 and the second time periods t2 are arranged alternately, and the first first time period t1 is earlier than the first second time period t2. Figure 6The embodiment takes m=2 as an example. It can be understood that the number of m is related to the duration of the first node Q1 maintaining a high level. The larger the m, the longer the first node Q1 maintains a high level. The potential writing of the first node Q1 is controlled by the input module 21, that is, the duration of the first node Q1 maintaining a high level is related to the high level duration of the input signal STV. The longer the first node Q1 maintains a high level, the longer the shift register unit 20 outputs a high level. In the embodiment of the present invention, the number of m is set according to the duration of the high level enable level required in the application.

[0052] In some embodiments, in the first time period t1, the input module 21 writes a high potential to the first node Q1 based on the high level signal of the first clock signal CK1, and the voltage stabilizing module 23 writes the low level signal of the first voltage signal VG1 to the third node Q3 in the voltage stabilizing module 23 under the control of the first node Q1. In the second time period t2, the voltage stabilizing module 23 writes the high level signal of the first voltage signal VG1 to the third node Q3 under the control of the first node Q1, and pulls up the potential of the first node Q1 based on the potential change of the third node Q3. In this embodiment, the third node Q3 is set in the voltage stabilizing module 23, a low level is written to the third node Q3 in the first time period t1, a high level is written to the third node Q3 in the second time period t2, and the potential of the first node Q1 is pulled up by the potential change of the third node Q3. Even if there is leakage from the first node Q1 to other nodes, the leakage can be compensated, ensuring that the first node Q1 has a relatively stable high potential, so that the output tube controlled by it can be stably turned on, and then the shift register unit 20 can be ensured to stably output a high level signal. The shift register unit 20 can provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10 , thereby ensuring that the pixel circuit 10 works stably and improving product performance reliability.

[0053] In some embodiments, Figure 7 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, the voltage stabilizing module 23 includes a first transistor T1, a second transistor T2 and a first capacitor C1; the control end of the first transistor T1 is connected to the first node Q1, the control end of the second transistor T2 is connected to the second node Q2, the first end of the first transistor T1 receives the first voltage signal VG1, the second end of the first transistor T1 and the second end of the second transistor T2 are connected to the third node Q3, and the first end of the second transistor T2 receives the second voltage signal VG2. One plate of the first capacitor C1 is connected to the first node Q1, and the other plate is connected to the third node Q3. In addition, the shift register unit 20 also includes a protection transistor M5, the control end of the protection transistor M5 receives the high level signal VGH, the protection transistor M5 is connected between an output end of the input module 21 and the first node Q1, and the protection transistor M5 and the output end of the input module 21 are connected to the fifth node Q5.

[0054] Combination Figure 6 From the schematic timing diagram, in the first time period t1, the voltage stabilizing module 23 writes the low level signal of the first voltage signal VG1 into the third node Q3 under the control of the high potential of the first node Q1. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on and write the low level signal of the first voltage signal VG1 into the third node Q3. In this time period, the third node Q3 is at a low potential, and the plate of the first capacitor C1 connected to the first node Q1 is at a high potential, and the plate connected to the third node Q3 is at a low potential.

[0055] In the second period t2, the voltage stabilizing module 23 writes the high level signal of the first voltage signal VG1 into the third node Q3 under the control of the high potential of the first node Q1. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on and write the high level signal of the first voltage signal VG1 into the third node Q3, so that the third node Q3 is at a high potential. The potential of the third node Q3 jumps from low to high, and the potential of the first node Q1 is pulled up due to the coupling effect of the first capacitor C1.

[0056] In this embodiment, the voltage stabilizing module 23 works under the control of the potential of the first node Q1, and uses the coupling effect of the first capacitor C1 to pull up the potential of the first node Q1, so that the potential of the first node Q1 after being pulled up in the second period t2 will be higher than its potential in the first period t1. It can compensate for the leakage of the first node Q1 to the fifth node Q5 through the protection transistor M5, ensure that the first node Q1 is stably maintained at a high potential, and then the output tube controlled by the first node Q1 can be stably turned on, ensuring that the output end of the shift register unit 20 outputs a stable high-level enable signal.

[0057] In some embodiments, Figure 6As shown, the operation of the shift register unit 20 also includes a reset period t30; during the reset period t30, the first node Q1 is at a low potential, and the second node Q2 is at a high potential. During the reset period t30, the voltage stabilizing module 23 writes the low potential of the second voltage signal VG2 to the third node Q3 based on the control of the second node Q2. In this way, the third node Q3 can be reset. Specifically, in combination Figure 7 From the perspective of FIG. 1 , during the period when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on and write the second voltage signal VG2 to the third node Q3 to reset the third node Q3. Optionally, the second voltage signal VG2 is a low level signal VGL.

[0058] Figure 7 The structure of the output module 22 is also schematically shown, and the output module 22 includes a third output tube M3, a fourth output tube M4, a capacitor C01 and a capacitor C02. The control end of the third output tube M3 is connected to the first node Q1, the first end receives a high-level signal VGH, and the second end is connected to the output end OUT of the output module 22. The control end of the fourth output tube M4 is connected to the second node Q2, the first end receives a low-level signal VGL, and the second end is connected to the output end OUT of the output module 22. During the period when the first node Q1 is at a high level, the first node Q1 controls the third output tube M3 to turn on, and the shift register unit outputs a high-level signal. During the period when the second node Q2 is at a high level, the second node Q2 controls the fourth output tube M4 to turn on, and the shift register unit outputs a low-level signal.

[0059] In some embodiments, the first voltage signal VG1 is the second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 can be a pair of clock signals with the same period. In the first time period t1, the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level; in the second time period t2, the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level. The first clock signal CK1 and the second clock signal CK2 jointly drive the cascaded multiple shift register units 20. In the embodiment of the present invention, setting the first voltage signal VG1 as the second clock signal CK2 can simplify the types of signals required to drive the shift register unit 20, and is also beneficial to reducing the wiring of the display panel and narrowing the border.

[0060] In other embodiments, Figure 8 Another timing diagram provided by the embodiment of the present invention can be used to drive the shift register unit 20 provided by the embodiment of the present invention. Figure 8As shown, the operation of the shift register unit 20 includes a first time period t1 and a second time period t2; at least in the first time period t1 and the second time period t2, the first node Q1 is at a high potential. In the first time period t1, the voltage of the first node Q1 is V1; in the second time period t2, the voltage of the first node Q1 is V2, and V2 > V1. In terms of chronological order, the first time period t1 is earlier than the second time period t2; the length of the first time period t1 is t01, and the length of the second time period t2 is t02, where t02 > t01. That is, the duration of the first time period t1 is less than the duration of the second time period t2, and the potential of the first node Q1 remains at a higher potential for a longer time after being pulled up. The high potential of the first node Q1 controls the output module 22 to output a high-level enable signal, and the longer the first node Q1 is at a higher potential, the better the stability of the high-level signal output by the shift register unit.

[0061] In some embodiments, in the first time period t1, the input module 21 writes a high potential to the first node Q1 based on the high-level signal of the first clock signal CK1, and the voltage stabilization module 23 writes the high level of the input signal STV to the fourth node Q4 in the voltage stabilization module 23 under the control of the high-level signal of the first clock signal CK1, and writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4.

[0062] The second time period t2 includes a first sub-period t21 and a second sub-period t22. In the first sub-period t21, the voltage stabilization module 23 writes the high-level signal of the first voltage signal VG1 to the third node Q3 under the control of the fourth node Q4, raises the potential of the fourth node Q4 based on the potential change of the third node Q3, the voltage of the fourth node Q4 is V3, and there is unidirectional conduction between the fourth node Q4 and the first node Q1, and writes the voltage of the fourth node Q4 to the first node Q1; in the second sub-period t22, the voltage stabilization module 23 writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4, and the voltage stabilization module 23 writes the voltage of the input signal STV to the fourth node Q4 under the high-level control of the first clock signal CK1, the voltage of the fourth node Q4 is V4, and V4 < V3. Since there is unidirectional conduction between the fourth node Q4 and the first node Q1, the first node Q1 will not leak electricity to the fourth node Q4, so that the first node Q1 can maintain a high potential. Figure 8 It can be seen from the timing that in the second time period t2, the first node Q1 remains at a relatively higher potential, and although the fourth node Q4 remains at a high potential, its high potential fluctuates.

[0063] In this embodiment, a third node Q3 and a fourth node Q4 are set in the voltage stabilizing module 23, and a low level is written to the third node Q3 in the first period t1. A high level is written to the third node Q3 in the first sub-segment t21 of the second period t2, and the potential of the fourth node Q4 is pulled up by the potential change of the third node Q3, and then the potential of the first node Q1 is pulled up by the high potential of the fourth node Q4. In the second sub-segment t21, the potential of the fourth node Q4 is pulled down, and the path between the fourth node Q4 and the first node Q1 is cut off. In this way, it can be ensured that the first node Q1 is stably maintained at a relatively higher high potential after the first sub-segment t21, so that the output tube controlled by the first node Q1 can be stably turned on, and the output end of the shift register unit 20 is ensured to output a stable high-level enable signal.

[0064] In some embodiments, Fig. 9 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig. 9 As shown, the voltage stabilizing module 23 includes a first transistor T1, a second transistor T2, a first capacitor C1, a third transistor T3 and a sub-input module 231. The control end of the first transistor T1 is connected to the first node Q1 through the third transistor T3, the control end of the second transistor T2 is connected to the second node Q2, the first end of the first transistor T1 receives the first voltage signal VG1, the second end of the first transistor T1 and the second end of the second transistor T2 are connected to the third node Q3, and the first end of the second transistor T2 receives the second voltage signal VG2. Among them, the first voltage signal VG1 can be the second clock signal CK2, and the second voltage signal VG2 can be a low level signal VGL. The control end of the first transistor T1, one plate of the first capacitor C1 and the control end of the third transistor T3 are connected to the fourth node Q4, the first end of the third transistor T3 is connected to the fourth node Q4, and the second end of the third transistor T3 is connected to the first node Q1. The output end of the sub-input module 231 is connected to the fourth node Q4, and the sub-input module 231 is configured to write a voltage to the fourth node Q4 based on the input signal STV and the first clock signal CK1.

[0065] Combination Figure 8From the timing diagram, in the first time period t1, the sub-input module 231 writes the high level of the input signal STV into the fourth node Q4 in the voltage stabilizing module 23 under the control of the first clock signal CK1. The high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the low level signal of the first voltage signal VG1 into the third node Q3. In the first sub-segment t21 of the second time period t2, the high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the high level signal of the first voltage signal VG1 into the third node Q3. The third node Q3 jumps from a low potential to a high potential. Due to the coupling effect of the first capacitor C1, the potential of the fourth node Q4 is pulled up. The high potential of the fourth node Q4 controls the third transistor T3 to turn on and writes the high potential of the fourth node Q4 into the first node Q1, thereby pulling up the potential of the first node Q1. In addition, Fig. 9 In the embodiment, the control end of the third transistor T3 and the first end of the third transistor T3 are both connected to the fourth node Q4, and the third transistor T3 forms a diode-like structure, so that it has a unidirectional conduction characteristic. In the second sub-segment t21, under the control of the high potential of the fourth node Q4, the low level signal of the first voltage signal VG1 is written into the third node Q3, and the voltage stabilizing module 23 writes the high level of the input signal STV into the fourth node Q4 under the control of the high level signal of the first clock signal CK1. At this time, the potential of the fourth node Q4 is lower than its potential in the first sub-segment t21, but because the third transistor T3 forms a diode-like structure, it can prevent the first node Q1 from discharging to the fourth node Q4, so that the high potential stability of the first node Q1 is better, and the first node Q1 can still maintain a relatively higher high potential in the second sub-segment t22.

[0066] in addition, Fig. 9 In the embodiment, the operation of the shift register unit 20 also includes a reset period t30; during the reset period t30, the first node Q1 is at a low potential and the second node Q2 is at a high potential. During the reset period t30, the voltage stabilizing module 23 writes the low potential of the second voltage signal VG2 to the third node Q3 based on the control of the second node Q2. Specifically, during the period when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on and writes the second voltage signal VG2 to the third node Q3 to reset the third node Q3.

[0067] In some embodiments, Fig.10 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.10As shown, the sub-input module 231 includes a fourth transistor T4 and a fifth transistor T5. The control end of the fourth transistor T4 receives the first clock signal CK1, the first end receives the input signal STV, and the second end is connected to the sixth node Q6. The control end of the fifth transistor T5 receives the third voltage signal VG3, the first end is connected to the sixth node Q6, and the second end is connected to the fourth node Q4. Among them, the third voltage signal VG3 is a high-level signal VGH. In the first period t1, the fourth transistor T4 is turned on under the control of the high level of the first clock signal CK1, and the high level of the input signal STV is written to the sixth node Q6. The fifth transistor T5 is turned on under the control of the third voltage signal VG3, and the high potential of the sixth node Q6 is written to the fourth node Q4. In the first sub-segment t21 of the second period t2, the first clock signal CK1 is at a low level, then the fourth transistor T4 is turned off, and the path for the sub-input module 231 to write the signal to the fourth node Q4 is closed, so that the fourth node Q4 maintains a high potential. In the second sub-section t22 of the second period t2, the first clock signal CK1 is at a high level, the fourth transistor T4 is turned on, and the sub-input module 231 writes the signal provided by the input signal STV into the fourth node Q4.

[0068] In some embodiments, Fig.10 As shown, the voltage stabilizing module 23 further includes a sixth transistor T6, the control end of the sixth transistor T6 is connected to the sixth node Q6, the first end receives the second voltage signal VG2, and the second end is connected to the second node Q2. In the first period t1 and the second period t2 when the first node Q1 is at a high potential, the sixth node Q6 is at a high potential, and the high potential of the sixth node Q6 controls the sixth transistor T6 to turn on and write the low level of the second voltage signal VG2 to the second node Q2, so that the second node Q2 is well maintained at a low level state.

[0069] In other embodiments, Fig.11 A schematic diagram of another shift register unit provided by an embodiment of the present invention, Fig.12 Another timing diagram provided for an embodiment of the present invention, Fig.12 The signal timing provided can be used to drive Fig.11 The shift register unit provided. Fig.11 As shown, the voltage stabilizing module 23 includes a seventh transistor T7 and an eighth transistor T8. The control end of the seventh transistor T7 receives the first clock signal CK1, the first end of the seventh transistor T7 and an output end of the input module 21 are connected to the fifth node Q5, and the second end of the seventh transistor T7 is connected to the first node Q1. The control end of the eighth transistor T8 is connected to the first node Q1, the first end of the eighth transistor T8 receives the first voltage signal VG1, the first voltage signal VG1 is the input signal STV or the first high level signal VGH, and the second end of the eighth transistor T8 is connected to the fifth node Q5.

[0070] Combination Fig.12 From the timing diagram, the operation of the shift register unit 20 includes a first period t1 and a second period t2; the first node Q1 is at a high potential during the first period t1 and the second period t2.

[0071] In the first period t1, the first clock signal CK1 is a high-level signal, the first voltage signal VG1 is a high-level signal, and the voltage stabilizing module 23 writes the high-level signal of the first voltage signal VG1 to the fifth node Q5 under the control of the potential of the first node Q1, and writes the high potential of the fifth node Q5 to the first node Q1 under the control of the high-level signal of the first clock signal CK1. Specifically, the high potential of the first node Q1 controls the eighth transistor T8 to turn on, writes the high-level signal VGH (or the high-level signal of the input signal STV) to the fifth node Q5, and the high-level signal of the first clock signal CK1 controls the seventh transistor T7 to turn on, and writes the high potential of the fifth node Q5 to the first node Q5. In this period, the first node Q1 and the fifth node Q5 are both at high potential.

[0072] In the second period t2, the first clock signal CK1 is a low level signal, and the first voltage signal VG1 is a high level signal. The voltage stabilizing module 23 writes the high level signal of the first voltage signal VG1 to the fifth node Q5 under the control of the potential of the first node Q1, and cuts off the path between the fifth node Q5 and the first node Q1 under the control of the low level signal of the first clock signal CK1. Specifically, the high potential of the first node Q1 controls the eighth transistor T8 to turn on, and writes the high level signal VGH (or the high level signal of the input signal STV) to the fifth node Q5, while the first clock signal CK1 is a low level signal at this time, and the seventh transistor T7 is turned off. In this period, the first node Q1 and the fifth node Q5 are both at a high potential, and the path between the two nodes is cut off, so that the first node Q1 can maintain a high potential, and prevent the first node Q1 from leaking to other nodes to affect the output of the high level signal of the shift register unit.

[0073] In some embodiments, Figure 7 As shown, the input module 21 includes a first submodule 211, a second submodule 212 and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based at least on the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211. In this embodiment, the first submodule 211, the second submodule 212 and the third submodule 213 cooperate to write signals to the first node Q1 and the second node Q2.

[0074] Figure 7The shift register unit 20 further includes a protection transistor M5, wherein an output terminal of the input module 21 is connected to the fifth node Q5, and the protection transistor M5 is connected between the fifth node Q5 and the first node Q1. The first submodule 211 is configured to write a voltage to the fifth node Q5 based on the input signal STV and the first clock signal CK1, and then write a voltage to the first node Q1 through the protection transistor M5.

[0075] In one embodiment, if Figure 7 As shown, the second submodule 212 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The control end of the ninth transistor T9 receives the input signal STV, the first end of the ninth transistor T9 receives the second voltage signal VG2, the second voltage signal VG2 may be a low level signal VGL, the second end of the ninth transistor T9 and the control end of the tenth transistor T10 are connected to the seventh node Q7. The first end of the tenth transistor T10 receives the first clock signal CK1, and the second end is connected to the second node Q2; one plate of the second capacitor C2 receives the first clock signal CK1, and the other plate is connected to the seventh node Q7.

[0076] The first submodule 211 includes an eighteenth transistor T18, the control end of the eighteenth transistor T18 receives the first clock signal CK1, the first end receives the input signal STV, and the second end is connected to the first node Q1. The third submodule 213 includes a nineteenth transistor T19, the control end of the nineteenth transistor T19 is connected to the output end of the first submodule 211 (that is, connected to the fifth node Q5), the first end receives the second voltage signal VG2, and the second end is connected to the second node Q2.

[0077] Fig.13 Another timing diagram provided by the embodiment of the present invention can be used to drive Figure 7 The shift register unit provided in the embodiment. The operation of the input module 21 can be combined with Figure 7 and Fig.13 From the above, the operation of the shift register unit 20 includes a first period t1, a second period t2 and a third period t3 which are arranged in time sequence.

[0078] In the first period t1, the input module 21 is turned on under the control of the high level signal of the first clock signal CK1 and the high level of the input signal STV, and the high level of the input signal STV is written to the first node Q1, and the low level of the second voltage signal VG2 is written to the second node Q2 and the seventh node Q7. Specifically, the high level signal of the first clock signal CK1 controls the eighteenth transistor T18 in the first submodule 211 to turn on, and the high level of the input signal STV is written to the fifth node Q5, and the high level of the fifth node Q5 is written to the first node Q1 through the protection transistor M5. The high level of the fifth node Q5 controls the nineteenth transistor T19 in the third submodule 213 to turn on, and the low level of the second voltage signal VG2 is written to the second node Q2. In addition, the high level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn on, and the low level of the second voltage signal VG2 is written to the seventh node Q7. In this period, the fifth node Q5 and the first node Q1 are at a high potential, and the second node Q2 and the seventh node Q7 are at a low potential.

[0079] In the second period t2, the input module 21 is closed under the control of the low level signal of the first clock signal CK1, the first node Q1 maintains a high potential, and the second node Q2 and the seventh node Q7 maintain a low potential. Specifically, the eighteenth transistor T18 controlled by the low level signal of the first clock signal CK1 is closed, and the fifth node Q5 maintains a high potential. The high level of the fifth node Q5 controls the nineteenth transistor T19 in the third submodule 213 to turn on, and the second node Q2 maintains a low potential. The high level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn on, and the seventh node Q7 maintains a low potential. In combination with the above description of the voltage stabilizing module 23, it can be known that during this period, the first node Q1 maintains a high potential due to the action of the voltage stabilizing module 23.

[0080] In the third period t3, the input module 21 is turned on under the control of the high level signal of the first clock signal CK1, and the low level of the input signal STV is written to the first node Q1, and the potential of the seventh node Q7 is pulled up based on the high level signal of the first clock signal CK1, and the high level of the first clock signal CK1 is written to the second node Q2. Specifically, the high level signal of the first clock signal CK1 controls the eighteenth transistor T18 in the first submodule 211 to turn on, and the low level of the input signal STV is written to the fifth node Q5. The low level of the fifth node Q5 is written to the first node Q1 through the protection transistor M5, so that the first node Q1 is at a low potential. In addition, the low level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn off. In this period, the first clock signal CK1 jumps from a low level to a high potential. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled up, and the seventh node Q7 is at a high potential. The high potential of the seventh node Q7 controls the tenth transistor T10 in the second submodule 212 to turn on, and the high level signal of the first clock signal CK1 is written to the second node Q2. During this period, the first node Q1 is at a low potential, and the second node Q2 is at a high potential.

[0081] in addition, Fig.11 The structure of the input module 21 shown in the embodiment and Figure 7 The structure of the input module 21 is the same as that of the Fig.11 The working process of the input module 21 illustrated in the embodiment can be understood with reference to the above description, and will not be described in detail here.

[0082] In other embodiments, Fig.10 As shown, the input module 21 includes a first submodule 211, a second submodule 212 and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based at least on the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0083] The second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The ninth transistor T9 includes a first sub-transistor T91 and a second sub-transistor T92. The control end of the first sub-transistor T91 and the control end of the second sub-transistor T92 receive the input signal STV, the first end of the first sub-transistor T91 receives the second voltage signal VG2, the second end of the first sub-transistor T91 and the first end of the second sub-transistor T92 are connected to the eighth node Q8, and the second end of the second sub-transistor T92 is connected to the seventh node Q7. The control end of the tenth transistor T10 is connected to the seventh node Q7, the first end receives the first clock signal CK1, and the second end is connected to the second node Q2; one plate of the second capacitor C2 receives the first clock signal CK1, and the other plate is connected to the seventh node Q7. The second submodule 212 also includes an eleventh transistor T11, the control end of the eleventh transistor T11 is connected to the seventh node Q7, the first end receives the third voltage signal VG3, and the second end is connected to the eighth node Q8. The second voltage signal VG2 can be a low level signal VGL, and the third voltage signal VG3 can be a high level signal VGH. Fig.10 It is also shown in FIG. 2 that the first submodule 211 includes an eighteenth transistor T18 and the third submodule 213 includes a nineteenth transistor T19.

[0084] In another embodiment, Fig.14 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.14 As shown, the input module 21 includes a first submodule 211, a second submodule 212 and a third submodule 213. The first submodule 211 includes an eighteenth transistor T18, the third submodule 213 includes a nineteenth transistor T19, and the second submodule 212 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. Fig.14 and Fig.10 The difference of the input module 21 in the embodiment is that: Fig.14 In the embodiment, a first end of the eleventh transistor T11 receives the first clock signal CK1 , and a control end of the eleventh transistor T11 is connected to a second end of the tenth transistor T10 .

[0085] In another embodiment, Fig.15 A schematic diagram of another shift register unit provided by an embodiment of the present invention, Fig.15 and Fig.14 The difference is that Fig.15 In the embodiment, the first end of the eleventh transistor T11 receives the third voltage signal VG3 , and the control end of the eleventh transistor T11 is connected to the seventh node Q7 .

[0086] Above Fig.10 , Fig.14 , Fig.15The working process of the input module 21 in the embodiment can be combined with the above Fig.13 The working process of the second submodule 212 is as follows: Fig.10 Taking the embodiment as an example, in the first period t1, the input signal STV is at a high level to control the first sub-transistor T91 and the second sub-transistor T92 to turn on, the eighth node Q8 and the seventh node Q7 are written at a low level, and the low level of the seventh node Q7 controls the eleventh transistor T11 to turn off. In the second period t2, the eighth node Q8 and the seventh node Q7 maintain a low level. In the third period t3, the input signal STV is at a low level to control the first sub-transistor T91 and the second sub-transistor T92 to turn off, and the first clock signal CK1 jumps from a low level to a high level. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled up, and the high potential of the seventh node Q7 controls the eleventh transistor T11 to turn on and write the high level of the third voltage signal VG3 to the eighth node Q8. In this period, the eighth node Q8 and the seventh node Q7 are both at a high level, and the first sub-transistor T91 and the second sub-transistor T92 are both in a closed state, thereby preventing the leakage of the seventh node Q7 when the ninth transistor T9 is in a negative bias state. This ensures that the tenth transistor T10 is in a stably turned-on state, so that the high-level signal provided by the first clock signal CK1 is stably written into the second node Q2, and the second node Q2 is at a stable high potential.

[0087] In some embodiments, Fig. 9 and Fig.10 As shown, the shift register unit further includes an anti-leakage module 24, which is connected between the second node Q2 and the output module 22, and the anti-leakage module 24 is configured to be closed under the control of the first clock signal CK1. Fig.10 For example, combined with Fig.13 From the timing diagram, in the third period t3, the first clock signal CK1 is at a high level, and the second node Q2 is written with a high potential, then the leakage prevention module 24 is turned on to write the high level of the second node Q2 to the control end of the fourth output tube M4 in the output module 22, thereby causing the shift register unit to output a low level provided by the low level signal VGL. The third period t3 is the period for writing a high level signal to the control end of the fourth output tube M4. In the fourth period t4, the first clock signal CK1 is at a low level, and the leakage prevention module 24 is turned off, thereby causing the leakage current path of the control end of the fourth output tube M4 to be closed, thereby stabilizing the potential of the output end of the fourth output tube M4, and the shift register unit can stably output a low level signal.

[0088] like Fig.10As shown, the leakage prevention module 24 includes a twelfth transistor T12, the control end of the twelfth transistor T12 receives the first clock signal CK1, the first end is connected to the second node Q2, and the second end is connected to a control end of the output module 22, specifically, the second end is connected to the control end of the fourth output tube M4.

[0089] In some embodiments, Fig.16 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig.16 As shown, the input module 21 includes a first submodule 211, a second submodule 212 and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1. The second submodule 212 is configured to write a voltage to the second node Q2 based on at least the output signal of the first submodule 211, the first clock signal CK1 and the second clock signal CK2. The third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0090] like Fig.16 As shown, the second submodule 212 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17 and a third capacitor C3. The control end of the thirteenth transistor T13 is connected to the output end of the first submodule 211, the first end receives the second voltage signal VG2, and the second end is connected to the second end of the fourteenth transistor T14. Optionally, the second voltage signal VG2 is a low level signal VGL. The control end of the fourteenth transistor T14 receives the first clock signal CK1, and the control end of the fifteenth transistor T15 receives the third voltage signal VG3, and optionally, the third voltage signal VG3 is a high level signal VGH. The first end of the fourteenth transistor T14 receives the third voltage signal VG3, and the second end is connected to the first end of the fifteenth transistor T15; the second end of the fifteenth transistor T15 and the control end of the sixteenth transistor T16 are connected to the ninth node Q9. The first end of the sixteenth transistor T16 receives the second clock signal CK2, and the second end is connected to the tenth node Q10. One plate of the third capacitor C3 is connected to the ninth node Q9, and the other plate is connected to the tenth node Q10. The control end of the seventeenth transistor T17 receives the second clock signal CK2, the first end is connected to the tenth node Q10, and the second end is connected to the second node Q2.

[0091] In addition, the first submodule 211 includes an eighteenth transistor T18, the control end of the eighteenth transistor T18 receives the first clock signal CK1, the first end receives the input signal STV, and the second end is connected to the first node Q1. Fig.16The second end of the eighteenth transistor T18 is connected to the fifth node Q5, and the fifth node Q5 is connected to the first node Q1 through the protection transistor M5. The third submodule 213 includes a nineteenth transistor T19, the control end of the nineteenth transistor T19 is connected to the output end of the first submodule 211, the first end receives the second voltage signal VG2, and the second end is connected to the second node Q2.

[0092] Fig.17 Another timing diagram provided by the embodiment of the present invention can be used to drive Fig.16 The shift register unit provided in the embodiment. The working process of the input module 21 can be combined with Fig.16 and Fig.17 to understand. Fig.17 As shown, the operation of the shift register unit 20 includes a first period t1, a second period t2, a third period t3 and a fourth period t4 which are sequentially arranged in time.

[0093] In the first time period t1, the input module 21 is turned on under the control of the high level signal of the first clock signal CK1 to write the high level of the input signal STV to the first node Q1, write the low level of the second voltage signal VG2 to the second node Q2, and write the low level to the ninth node Q9, and cut off the path between the tenth node Q10 and the second node Q2 under the control of the low level of the second clock signal CK2. Specifically, the high level of the first clock signal CK1 controls the eighteenth transistor T18 in the first submodule 211 to turn on, write the high level of the input signal STV to the fifth node Q5, and the fifth node Q5 writes the high level to the first node Q1 through the protection transistor M5. At this time, the output end of the first submodule 211 is at a high level, which controls the nineteenth transistor T19 in the third submodule 213 to turn on, and write the low level of the second voltage signal VG2 to the second node Q2. The high level of the output terminal of the first submodule 211 also controls the thirteenth transistor T13 in the second submodule 212 to turn on, and the first clock signal CK1 controls the fourteenth transistor T14 to turn on. The high level of the third voltage signal VG3 written through the fourteenth transistor T14 will leak through the thirteenth transistor T13, and the fifteenth transistor is turned on under the control of the high level of the third voltage signal VG3, so at this moment, the ninth node Q9 is written with a low potential. The ninth node Q9 is at a low potential, the second clock signal CK2 is at a low level, and the sixteenth transistor T16 and the seventeenth transistor 17 are both turned off. During this period, the first node Q1 is at a high potential, the second node Q2 is at a low potential, the third output terminal M3 in the output module 22 is turned on, and the output terminal OUT outputs a high-level signal.

[0094] In the second period t2, the input module 21 is closed under the control of the low level signal of the first clock signal CK1, the first node Q1 maintains a high potential, the second node Q2 and the ninth node Q9 maintain a low potential, and the path between the tenth node Q10 and the second node Q2 is turned on under the control of the high level of the second clock signal CK2. Specifically, if the first clock signal CK1 is low, the eighteenth transistor T18 and the fourteenth transistor T14 are turned off. The fifth node Q5 and the first node Q1 maintain a high potential. In this period, the second node Q2 and the ninth node Q9 maintain a low potential. And the second clock signal CK2 is high level to control the seventeenth transistor T17 to open, so that the path between the tenth node Q10 and the second node Q2 is turned on. In this period, the first node Q1 is high potential, the second node Q2 is low potential, the third output terminal M3 in the output module 22 is turned on, and the output terminal OUT outputs a high level signal.

[0095] In the third period t3, the input module 21 is turned on under the control of the high level signal of the first clock signal CK1, and the low level of the input signal STV is written to the first node Q1, the high level of the third voltage signal VG3 is written to the ninth node Q9, and the low level of the second clock signal CK2 is written to the tenth node Q10 under the control of the ninth node Q9, and the path between the tenth node Q10 and the second node Q2 is cut off under the control of the low level of the second clock signal CK2, and the second node Q2 maintains a low potential. Specifically, the eighteenth transistor T18 and the fourteenth transistor T14 are turned on under the control of the high level signal of the first clock signal CK1, and the eighteenth transistor T18 is turned on to write the low level of the input signal STV to the fifth node Q5, and the fifth node Q5 writes a low level to the first node Q1 through the protection transistor M5. At the same time, the low level of the fifth node Q5 controls the thirteenth transistor T13 to be turned off, and the fourteenth transistor T14 and the fifteenth transistor T15 are turned on to write the high level of the third voltage signal VG3 to the ninth node Q9. The high level of the ninth node Q9 controls the sixteenth transistor T16 to turn on, writes the low level of the second clock signal CK2 into the tenth node Q10, and the low level of the second clock signal CK2 controls the seventeenth transistor T17 to turn off, and the path between the tenth node Q10 and the second node Q2 is cut off. During this period, the second node Q2 is at a low potential, the first node Q1 is at a low potential, and the output terminal OUT of the output module 22 maintains the output state of the previous period and outputs a high level signal.

[0096] In the fourth period t4, the input module 21 is closed under the control of the low level signal of the first clock signal CK1, the first node Q1 maintains a low potential, the ninth node Q9 maintains a high potential, and the high level of the second clock signal CK2 is written into the tenth node Q10 under the control of the ninth node Q9. Due to the coupling effect of the third capacitor C3, the potential change of the tenth node Q10 couples the potential of the ninth node Q9 to a high level, and the path between the tenth node Q10 and the second node Q2 is connected under the control of the high level of the second clock signal CK2, and the second node Q2 is written into a high potential. In this period, the second node Q2 is at a high potential, the first node Q1 is at a low potential, the fourth output terminal M4 in the output module 22 is opened, and the output terminal OUT outputs a low level signal.

[0097] In some embodiments, Fig.18 A schematic diagram of a cascade of shift register units provided in an embodiment of the present invention is shown in FIG. Fig.18 As shown, the shift register unit 20 includes an input module 21, an output module 22 and a voltage stabilizing module 23, wherein the output terminal OUT of the output module 22 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the i+1-th stage shift register unit 20(i+1), where i is a positive integer. That is, the signal outputted by the output terminal OUT of the output module 22 in the shift register unit 20 is used as the input signal STV received by the input module 21 in the next stage shift register unit 20.

[0098] In other embodiments, Fig.19 A schematic diagram of another shift register unit provided by an embodiment of the present invention, Fig. 20 Another schematic diagram of a cascade connection of shift register units provided by an embodiment of the present invention is as follows: Fig.19 As shown, the shift register unit 20 also includes a level transmission module 25, which is connected to the first node Q1 and the second node Q2 respectively; the level transmission module 25 is configured to output a high-level signal based on the voltage of the first node Q1, and is configured to output a low-level signal based on the voltage of the second node Q2. In the application, the signal output by the output terminal Next of the level transmission module 25 is used for level transmission to the input terminal of the next-stage shift register unit, and the signal output by the output terminal OUT of the output module 22 is used to provide to the scan line to drive the pixel circuit. In this way, the voltage drop of the scan signal output by the shift register unit 20 can be reduced, which is conducive to improving the display uniformity.

[0099] Combination Fig. 20From the above, the output terminal Next of the transmission module 25 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the i+1-th stage shift register unit 20(i+1), where i is a positive integer. That is, the signal outputted by the output terminal Next of the transmission module 25 in the shift register unit 20 is used as the input signal STV received by the input module 21 in the next stage shift register unit 20.

[0100] In some embodiments, Fig.21 A schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig. 22 Another timing diagram provided by the embodiment of the present invention can be used to drive Fig.21 The shift register unit provided. Fig.21 As shown, the shift register unit 20 includes an input module 21, an output module 22, a voltage stabilizing module 23 and a stage transmission module 25. The stage transmission module 25 includes a first output tube M1 and a second output tube M2, wherein the control end of the first output tube M1 is connected to the first node Q1, the first end receives the third voltage signal VG3, and the second end is connected to the output end Next of the stage transmission module 25, and the control end of the second output tube M2 is connected to the second node Q2, the first end receives the second voltage signal VG2, and the second end is connected to the output end Next of the stage transmission module 25. Specifically, the protection transistor M5 is connected between the first node Q1 and the output end of the input module 21, and the control end of the second output tube M2 is connected to the second node Q2 through the twelfth transistor T12. Among them, the third voltage signal VG3 provides a high level signal, and the second voltage signal VG2 provides a low level signal. Fig.21 A capacitor C03 is also shown, one plate of the capacitor C03 is connected to the control end of the second output tube M2, and the other plate receives the second voltage signal VG2.

[0101] The output module 22 includes a third output tube M3 and a fourth output tube M4, wherein the control end of the third output tube M3 is connected to the first node Q1, the first end receives the fourth voltage signal VG4, and the second end is connected to the output end OUT of the output module 22, and the control end of the fourth output tube M4 is connected to the second node Q2, the first end receives the fifth voltage signal VG5, and the second end is connected to the output end OUT of the output module 22. Specifically, the control end of the fourth output tube M4 is connected to the second node Q2 through the twelfth transistor T12. The fourth voltage signal VG4 provides a high level signal, and the fifth voltage signal VG5 provides a low level signal.

[0102] in addition, Fig.21 In the embodiment, the input module 21 and Fig.10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Figure 1 The structure of the voltage stabilizing module 22 in the embodiments is the same and will not be described again.

[0103] In other embodiments, Fig.23 A schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig.24 Another timing diagram provided by the embodiment of the present invention can be used to drive Fig.23 The shift register unit provided. Fig.23 As shown, the shift register unit 20 includes an input module 21 , an output module 22 , a voltage stabilizing module 23 and a stage transmission module 25 . Fig.23 In the embodiment, the input module 21 and Fig.10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Fig.10 The structures of the voltage stabilizing modules 22 in the embodiments are the same.

[0104] In other embodiments, Fig.25 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig.25 As shown, the shift register unit 20 includes an input module 21, an output module 22, a voltage stabilizing module 23, an anti-leakage module 24 and a level transmission module 25. Fig.23 In the embodiment, the input module 21 and Fig.10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Fig.11 The structures of the voltage stabilizing modules 22 in the embodiments are the same.

[0105] In other embodiments, Fig.26 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig.25 As shown, the shift register unit 20 includes an input module 21, an output module 22, an anti-leakage module 24 and a level transfer module 25. Fig.26 Also shown are capacitors C04 and C05.

[0106] In some embodiments, the third voltage signal VG3 and the fourth voltage signal VG5 both provide high level signals, the voltage value of the third voltage signal VG3 is VGH1, the voltage value of the fourth voltage signal VG4 is VGH2, and VGH2≤VGH1. Such a setting can make the potential of the first node Q1 control the third output tube M3 to be turned on more completely, so that the output terminal OUT of the output module 22 outputs a high level enable level more stably.

[0107] In some embodiments, the second voltage signal VG2 and the fifth voltage signal VG5 both provide low-level signals, the voltage value of the second voltage signal VG2 is VGL1, the voltage value of the fifth voltage signal VG5 is VGL2, and VGL2 ≥ VGL1. Such a setting enables the fourth output tube M4 to be completely turned off when the output terminal OUT of the output module 22 is in a negative bias state and outputs a high level, thereby ensuring the stability of the high-level output of the output terminal OUT of the output module 22.

[0108] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig. 27 A schematic diagram of a display device provided for the implementation of the present invention, such as Fig. 27 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device such as a mobile phone, a tablet, a television, a smart wearable product, etc.

Claims

1. A display panel, characterized in that: The display panel includes a shift register, and the shift register includes a plurality of shift register units; the shift register unit includes an input module, an output module and a voltage stabilizing module; The input module is configured to write voltages to the first node and the second node respectively based on at least an input signal and a first clock signal, and the output module is connected to the first node and the second node respectively; the output module is configured to output a high level signal based on the voltage of the first node, and is also configured to output a low level signal based on the voltage of the second node; The voltage stabilizing module is connected to at least the first node; during at least a portion of the time period when the first node is at a high potential, the voltage stabilizing module is configured to increase the potential of the first node based on the voltage of the first node and a first voltage signal.

2. The display panel according to claim 1, characterized in that: The operation of the shift register unit includes a first period and a second period; the first node is at a high potential during the first period and the second period; In the first period, the voltage of the first node is V1; in the second period, the voltage of the first node is V2, V2>V1.

3. The display panel according to claim 2, characterized in that: The operation of the shift register unit includes m first time periods and m second time periods, where m is an integer and m≥1; In time sequence, the first time periods and the second time periods are arranged alternately, and the first first time period is earlier than the first second time period.

4. The display panel according to claim 3, characterized in that: In the first period, the input module writes a high potential to the first node based on a high level signal of the first clock signal, and the voltage stabilizing module writes a low level signal of the first voltage signal to a third node in the voltage stabilizing module under the control of the first node; In the second period, the voltage stabilizing module writes a high level signal of the first voltage signal into the third node under the control of the first node, and raises the potential of the first node based on the potential change of the third node.

5. The display panel according to claim 2, characterized in that: In terms of time sequence, the first period is earlier than the second period; The length of the first time period is t01, the length of the second time period is t02, and t02>t01.

6. The display panel according to claim 5, characterized in that: In the first period, the input module writes a high potential to the first node based on the high level signal of the first clock signal, the voltage stabilizing module writes the high level of the input signal to the fourth node in the voltage stabilizing module under the control of the high level signal of the first clock signal, and writes the low level signal of the first voltage signal to the third node under the control of the high potential of the fourth node; The second period includes a first sub-segment and a second sub-segment; In the first sub-segment, the voltage stabilizing module writes a high-level signal of the first voltage signal into the third node under the control of the fourth node, raises the potential of the fourth node based on the potential change of the third node, the voltage of the fourth node is V3, the fourth node and the first node are unidirectionally conductive, and the voltage of the fourth node is written into the first node; In the second sub-segment, the voltage stabilizing module writes the low level signal of the first voltage signal into the third node under the high potential control of the fourth node, and the voltage stabilizing module writes the voltage of the input signal into the fourth node under the high level signal control of the first clock signal, and the voltage of the fourth node is V4, V4 <V3。 7. The display panel according to claim 1, characterized in that: The operation of the shift register unit includes a first period and a second period; the first node is at a high potential during the first period and the second period; In the first time period, the first clock signal is a high-level signal, the first voltage signal is a high-level signal, the voltage stabilizing module writes the high-level signal of the first voltage signal to the fifth node under the control of the first node, and writes the high potential of the fifth node to the first node under the control of the first clock signal; During the second time period, the first clock signal is a low-level signal and the first voltage signal is a high-level signal. Under the control of the first node, the voltage stabilizing module writes the high-level signal of the first voltage signal into the fifth node, and under the control of the first clock signal, cuts off the path between the fifth node and the first node.

8. The display panel according to claim 1, characterized in that: The voltage stabilizing module includes a first transistor, a second transistor and a first capacitor; The control end of the first transistor is connected to the first node, the control end of the second transistor is connected to the second node, the first end of the first transistor receives the first voltage signal, the second end of the first transistor and the second end of the second transistor are connected to a third node, and the first end of the second transistor receives the second voltage signal; One plate of the first capacitor is connected to the first node, and the other plate is connected to the third node.

9. The display panel according to claim 8, characterized in that: The first voltage signal is a second clock signal.

10. The display panel according to claim 8, characterized in that: The voltage stabilization module also includes a third transistor and a sub-input module; The control end of the first transistor, one plate of the first capacitor and the control end of the third transistor are connected to a fourth node, the first end of the third transistor is connected to the fourth node, and the second end of the third transistor is connected to the first node; The output end of the sub-input module is connected to the fourth node, and the sub-input module is configured to write a voltage to the fourth node based on the input signal and the first clock signal.

11. The display panel according to claim 10, characterized in that: The sub-input module includes a fourth transistor and a fifth transistor; The control end of the fourth transistor receives the first clock signal, the first end receives the input signal, and the second end is connected to the sixth node. The control end of the fifth transistor receives the third voltage signal, the first end is connected to the sixth node, and the second end is connected to the fourth node.

12. The display panel according to claim 11, characterized in that: The voltage stabilizing module further includes a sixth transistor, wherein a control end of the sixth transistor is connected to the sixth node, a first end of the sixth transistor receives the second voltage signal, and a second end of the sixth transistor is connected to the second node.

13. The display panel according to claim 1, characterized in that: The voltage stabilizing module includes a seventh transistor and an eighth transistor; The control end of the seventh transistor receives the first clock signal, the first end of the seventh transistor and an output end of the input module are connected to a fifth node, and the second end of the seventh transistor is connected to the first node; The control end of the eighth transistor is connected to the first node, the first end of the eighth transistor receives the first voltage signal, the first voltage signal is the input signal or a high level signal, and the second end of the eighth transistor is connected to the fifth node.

14. The display panel according to claim 1, characterized in that: The input module includes a first submodule, a second submodule and a third submodule; The first submodule is configured to write a voltage to the first node based on the input signal and the first clock signal; The second submodule is configured to write a high level to the second node based on at least the input signal and the first clock signal; The third submodule is configured to write a low level to the second node based on control of the output signal of the first submodule.

15. The display panel according to claim 14, characterized in that: The second submodule includes a ninth transistor, a tenth transistor and a second capacitor; The control end of the ninth transistor receives the input signal, the first end of the ninth transistor receives the second voltage signal, the second end of the ninth transistor and the control end of the tenth transistor are connected to the seventh node; the first end of the tenth transistor receives the first clock signal, and the second end is connected to the second node; one plate of the second capacitor receives the first clock signal, and the other plate is connected to the seventh node.

16. The display panel according to claim 15, characterized in that: The ninth transistor includes a first sub-transistor and a second sub-transistor, the control end of the first sub-transistor and the control end of the second sub-transistor receive the input signal, the first end of the first sub-transistor receives the second voltage signal, the second end of the first sub-transistor and the first end of the second sub-transistor are connected to the eighth node, and the second end of the second sub-transistor is connected to the seventh node; The second submodule also includes an eleventh transistor, a control end of the eleventh transistor is connected to the seventh node or the second end of the tenth transistor, a first end receives a third voltage signal or the first clock signal, and a second end is connected to the eighth node.

17. The display panel according to claim 1, characterized in that: The shift register unit further includes an anti-leakage module, which is connected between the second node and the output module, and is configured to be closed under the control of the first clock signal.

18. The display panel according to claim 17, characterized in that: The anti-leakage module includes a twelfth transistor, a control end of the twelfth transistor receives the first clock signal, a first end is connected to the second node, and a second end is connected to a control end of the output module.

19. The display panel according to claim 1, characterized in that: The input module includes a first submodule, a second submodule and a third submodule; The first submodule is configured to write a voltage to the first node based on the input signal and the first clock signal; The second submodule is configured to write a voltage to the second node based on at least an output signal of the first submodule, the first clock signal, and a second clock signal; The third submodule is configured to write a low level to the second node based on control of the output signal of the first submodule.

20. The display panel according to claim 19, characterized in that: The second submodule includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The control end of the thirteenth transistor is connected to the output end of the first submodule, the first end receives the second voltage signal, and the second end is connected to the second end of the fourteenth transistor; the control end of the fourteenth transistor receives the first clock signal, the control end of the fifteenth transistor receives the third voltage signal, the first end of the fourteenth transistor receives the third voltage signal, and the second end is connected to the first end of the fifteenth transistor; the second end of the fifteenth transistor and the control end of the sixteenth transistor are connected to the ninth node; The first end of the sixteenth transistor receives the second clock signal, and the second end is connected to the tenth node; The control end of the seventeenth transistor receives the second clock signal, the first end is connected to the tenth node, and the second end is connected to the second node.

21. The display panel according to claim 14 or 19, characterized in that: The first submodule includes an eighteenth transistor, a control end of the eighteenth transistor receives the first clock signal, a first end receives the input signal, and a second end is connected to the first node; And / or, the third submodule includes a nineteenth transistor, a control end of the nineteenth transistor is connected to the output end of the first submodule, a first end receives a second voltage signal, and a second end is connected to the second node.

22. The display panel according to claim 1, characterized in that: The output end of the output module in the i-th stage shift register unit is connected to the input end of the input module in the i+1-th stage shift register unit, where i is a positive integer.

23. The display panel according to claim 1, characterized in that: The shift register unit further includes a level transmission module, the level transmission module is connected to the first node and the second node respectively; the level transmission module is configured to output a high level signal based on the voltage of the first node, and is configured to output a low level signal based on the voltage of the second node; The output end of the stage transmission module in the i-th stage shift register unit is connected to the input end of the input module in the i+1-th stage shift register unit, where i is a positive integer.

24. The display panel according to claim 23, characterized in that: The stage transmission module comprises a first output tube and a second output tube, wherein the control end of the first output tube is connected to the first node, the first end receives a third voltage signal, and the second end is connected to the output end of the stage transmission module; the control end of the second output tube is connected to the second node, the first end receives a second voltage signal, and the second end is connected to the output end of the stage transmission module; The output module includes a third output tube and a fourth output tube, wherein the control end of the third output tube is connected to the first node, the first end receives the fourth voltage signal, and the second end is connected to the output end of the output module, and the control end of the fourth output tube is connected to the second node, the first end receives the fifth voltage signal, and the second end is connected to the output end of the output module; wherein The voltage value of the third voltage signal is VGH1, the voltage value of the fourth voltage signal is VGH2, VGH2≤VGH1; and / or the voltage value of the second voltage signal is VGL1, the voltage value of the fifth voltage signal is VGL2, VGL2≥VGL1.

25. The display panel according to claim 1, characterized in that: At least the transistor connected to the first node in the output module is an n-type transistor.

26. The display panel according to claim 25, characterized in that: All transistors in the shift register unit are n-type transistors.

27. The display panel according to claim 25, characterized in that: The active layer of the n-type transistor includes indium gallium zinc oxide.

28. A display device, characterized in that: A display panel comprising any one of claims 1 to 27.

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