Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a patterned mask layer with an opening on the surface of the substrate; etching the substrate along the opening to form an etching pattern in the substrate; forming a dielectric layer that fills the etching pattern and covers the patterned mask layer; flattening the dielectric layer to expose the surface of the patterned mask layer; removing the patterned mask layer by a wet etching process, wherein the wet etching process reversely etches the dielectric layer while removing the patterned mask layer to form a reverse etching layer on the surface of the dielectric layer. The semiconductor structure formed by the method can improve the isolation performance of the dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor processes often involve filling a material layer in a trench or a through hole. Usually, a chemical vapor deposition process, a physical vapor deposition process, etc. are used to fill the material layer, and then planarization is performed.

[0003] Taking the shallow trench isolation structure as an example, silicon oxide is filled in the trench as a shallow trench isolation structure (STI). The deposition quality of the silicon oxide filled in the trench determines the isolation effect of STI. Usually, chemical vapor deposition (CVD) is used to fill silicon oxide in the trench. However, during the filling process, silicon oxide is prone to form holes inside, affecting the isolation effect.

[0004] The existing technology usually avoids the above problems by controlling the deposition process to avoid the generation of holes in the deposition process of the silicon oxide layer, but this requires high parameter adjustment of the deposition process, resulting in a decrease in the process window and making it difficult to control. Moreover, as the integration of integrated circuits increases, the size of trenches or through holes further decreases, and it becomes increasingly difficult to avoid the appearance of holes.

[0005] How to further improve the isolation effect of the isolation structure is a problem that needs to be solved urgently. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the isolation performance of the dielectric layer.

[0007] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a patterned mask layer with an opening on the surface of the substrate; etching the substrate along the opening to form an etching pattern in the substrate; forming a dielectric layer that fills the etching pattern and covers the patterned mask layer; planarizing the dielectric layer to expose the surface of the patterned mask layer; removing the patterned mask layer by a wet etching process, wherein the wet etching process reversely etches the dielectric layer while etching and removing the patterned mask layer to form a reverse etching layer on the surface of the dielectric layer.

[0008] Optionally, the dielectric layer in the etched pattern has holes, and when the dielectric layer is planarized and the patterned mask layer is etched, part of the holes are exposed on the surface of the dielectric layer; the reverse etching layer fills the exposed holes or at least closes the tops of the holes.

[0009] Optionally, in the wet etching process, the etching ratio of the patterned mask layer and the dielectric layer is greater than 100:1; the etching solution used in the wet etching process has reversible etching properties for the dielectric layer, and the negative etching rate is greater than the positive etching rate.

[0010] Optionally, the material of the patterned mask layer is silicon nitride, the material of the dielectric layer is silicon oxide, the etching solution used in the wet etching process is a phosphoric acid solution, and the phosphoric acid solution contains H2SiO3, and the concentration of H2SiO3 is greater than or equal to a preset value.

[0011] Optionally, the phosphoric acid solution stock solution is pretreated to form an etching solution used in the wet etching process, and the pretreatment method includes: etching a certain amount of silicon nitride layer with the phosphoric acid solution stock solution so that the concentration of H2SiO3 in the solution is greater than or equal to a preset value.

[0012] Optionally, the method of etching a quantitative silicon nitride layer using a phosphoric acid solution further includes: placing multiple wafers formed with silicon nitride layers into a wet etching tank filled with a phosphoric acid solution, and etching for a certain period of time until the concentration of H2SiO3 in the solution is greater than or equal to a preset value.

[0013] The technical solution of the present invention also provides a semiconductor structure, comprising: a substrate; an etching pattern located in the substrate; an isolation layer filled in the etching pattern; the isolation layer comprises a dielectric layer and a reverse etching layer located on the top of the dielectric layer, and the reverse etching layer is formed by reverse etching the dielectric layer through a wet etching process.

[0014] Optionally, the dielectric layer of the isolation layer has holes in it, part of the holes are exposed on the surface of the dielectric layer, and the reverse etching layer fills the holes exposed on the surface of the dielectric layer or at least seals the tops of the holes exposed on the surface of the dielectric layer.

[0015] Optionally, the material of the dielectric layer is silicon oxide, and the material of the reverse etching layer is silicon oxide.

[0016] Optionally, the reverse etching layer has a thickness of 0.1 nm to 0.3 nm.

[0017] The method for forming a semiconductor structure of the present invention uses an etching solution with reverse etching properties for a dielectric layer during the process of etching and removing a patterned mask layer. While removing the patterned mask layer, a reverse etching layer is formed on the surface of the dielectric layer to improve the isolation performance of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1A to 1C A schematic diagram of forming a shallow trench isolation structure in a specific embodiment of the present invention;

[0019] Figures 2 to 6 A schematic structural diagram of a semiconductor structure forming process according to a specific embodiment of the present invention;

[0020] FIG. 7A to FIG. 7D It is a schematic diagram of a formation process of a semiconductor structure according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0021] As described in the background art, the isolation effect of the existing isolation structure needs to be further improved.

[0022] Figures 1A to 1C It is a schematic diagram of forming a shallow trench isolation structure according to a specific embodiment of the present invention.

[0023] Please refer to Figure 1A , using the mask layer 101 as a mask, after etching a groove in the semiconductor layer 100, the groove is filled with a silicon oxide layer 102. Holes 103 are formed in the silicon oxide layer in the groove with a smaller critical dimension, and some of the holes 103 are close to the top of the groove, for example, at the height of the plane where the mask layer 101 is located. The material of the mask layer 101 is usually silicon nitride.

[0024] Please refer to Figure 1B The mask layer 101 is used as a stop layer to planarize the silicon oxide layer 102. During the planarization process, part of the holes above the trench isolation structure may be exposed or closer to the surface of the planarized silicon oxide layer 102.

[0025] Please refer to Figure 1C , remove the mask layer 101. The mask layer 101 is usually removed by a wet etching process. The material of the mask layer 101 is silicon nitride, and the etching solution used in the wet etching process is a phosphoric acid solution. The wet etching process has a high selectivity for silicon nitride, but it will also produce a certain amount of etching for silicon oxide, so that the holes close to the surface of the silicon oxide layer 102 are exposed, resulting in a decrease in the isolation effect of the silicon oxide layer 102.

[0026] In order to solve the above problems, the present invention provides a new semiconductor structure and a method for forming the same, which can reduce holes and improve the isolation effect of the isolation structure.

[0027] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 2 , providing a substrate 200, and forming a patterned mask layer 202 having an opening 201 on the surface of the substrate 200.

[0029] The substrate 200 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc.; according to the actual needs of the device, a suitable semiconductor layer may be selected as the substrate 200, which is not limited here. In this specific implementation, the substrate 200 is a single crystal silicon layer. A doped region or a semiconductor device may also be formed in the substrate 200.

[0030] The material of the patterned mask layer 202 may be a silicon nitride layer or a stack of silicon oxide and silicon nitride, etc. In this specific embodiment, the material of the patterned mask layer 202 is silicon nitride. The method for forming the patterned mask layer 202 includes: depositing a mask material layer on the surface of the substrate 200, forming a photoresist layer on the surface of the mask material layer, patterning the photoresist layer by exposure and development, etching the mask material layer using the patterned photoresist layer as a mask to form an opening 201 exposing the surface of the substrate 200, and then removing the photoresist layer.

[0031] The material of the patterned mask layer 202 is silicon nitride. The opening 201 may be hole-shaped or strip-shaped. In this specific embodiment, the opening 201 is used to define the position and shape of the shallow trench isolation structure subsequently formed in the substrate 200, and the opening 201 is strip-shaped. In other specific embodiments, the opening 201 may also be hole-shaped. Depending on the different etching patterns to be formed, the openings 201 at different positions may have different patterns and sizes.

[0032] Please refer to Figure 3 , the substrate 200 is etched along the opening 201 to form an etched pattern 301 in the substrate 200 .

[0033] The substrate 200 may be etched by a dry etching process to form an etched pattern 301 corresponding to the shape of the opening 201. The dry etching process has anisotropy.

[0034] In this specific implementation, the etched pattern 301 includes an etched pattern with a larger critical dimension and an etched pattern with a smaller critical dimension.

[0035] Please refer to Figure 4 , forming a pattern filled with the etching pattern 301 (please refer to Figure 3 ) and covers the dielectric layer 401 of the patterned mask layer 202.

[0036] The material of the dielectric layer 401 can be an insulating dielectric material such as silicon oxide, nitrogen-doped silicon oxide, etc. The dielectric layer 401 can be deposited on the substrate 200 by using a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, etc. The dielectric layer 401 fills the etched pattern 301 and covers the patterned mask layer 202. In this specific embodiment, the material of the dielectric layer 401 is silicon oxide, and the silicon oxide is formed by a chemical vapor deposition process.

[0037] For an etched pattern with a larger critical dimension, the dielectric layer 401 can completely fill the etched pattern; for an etched pattern with a smaller critical dimension, since the deposition rate at the top of the etched pattern is greater than the deposition rate at the bottom during the vapor deposition process, holes are formed in the dielectric material filled in the etched pattern. In this specific embodiment, holes 402 are formed in the dielectric layer 401 in the etched pattern with a smaller critical dimension. The top of some holes 402 is higher than the surface height of the patterned mask layer 202 or close to the surface height of the patterned mask layer 202.

[0038] Please refer to Figure 5 , the dielectric layer 401 is planarized to expose the surface of the patterned mask layer 202 .

[0039] In this specific implementation, the patterned mask layer 202 may be used as a stop layer, and a chemical polishing process (CMP) may be used to planarize the dielectric layer 401 .

[0040] Since the tops of some holes 402 in the dielectric layer 401 are higher than the surface of the patterned mask layer 202 , after the dielectric layer 401 is planarized, some holes 402 are exposed to the surface of the dielectric layer 401 .

[0041] After the dielectric layer is planarized, part of the holes 402 are exposed on the planarized surface of the dielectric layer 401a, or are close to the surface of the dielectric layer 401a, resulting in poor isolation performance of the dielectric layer 401a.

[0042] Please refer to Figure 6 , the patterned mask layer 202 is removed by a wet etching process (please refer to Figure 5 ), the wet etching process, while etching away the patterned mask layer 202, reverse etches the dielectric layer 401a, forming a reverse etching layer 601 on the surface of the dielectric layer 401a.

[0043] In this specific embodiment, the material of the patterned mask layer 202 is silicon nitride, and the material of the dielectric layer 401a is silicon oxide. The patterned mask layer 202 is etched using an etching solution with a high etching selectivity to the patterned mask layer 202. Preferably, the etching ratio of the patterned mask layer 202 and the dielectric layer 401a is greater than 100:1.

[0044] Furthermore, the wet etching solution has reversible etching properties on the dielectric layer 401a, and the negative etching rate is greater than the positive etching rate, so that in the process of etching and removing the patterned mask layer 202, a reverse etching layer 601 is formed on the surface of the dielectric layer 401a.

[0045] In this specific implementation manner, the etching solution used in the wet etching process is a phosphoric acid solution, and the phosphoric acid solution contains H2SiO3, and the concentration of H2SiO3 is greater than or equal to a preset value.

[0046] The following are the reaction equations for the three chemical reactions involved in the wet etching process using a phosphoric acid solution containing H2SiO3:

[0047]

[0048] (NH4)3PO4→NO↑+NO3 - +H2PO4 - (2)

[0049]

[0050] Reaction equations (1) and (3) are both reversible reactions. The etching rate of H3PO4 on silicon oxide is much lower than that of silicon nitride. However, as the amount of H3PO4 etching silicon nitride increases, a large amount of H2SiO3 is generated in the H3PO4 solution. When the concentration of H2SiO3 reaches a certain threshold, reaction equation (3) will proceed to the left, causing reverse etching of silicon oxide and depositing a reverse etching layer.

[0051] When the patterned mask layer 202 is etched by a phosphoric acid solution having a H2SiO3 content greater than or equal to a preset value, a reverse etching layer 601 is deposited on the surface of the dielectric layer 401a while removing the patterned mask layer 202. The reverse etching layer 601 can fill the holes 402 exposed by the dielectric layer 401a, or at least seal the tops of the holes 402, increase the thickness of the dielectric material above the holes 402 at the top of the dielectric layer 401a, reduce the number of holes in the dielectric layer 401a, and thus improve the isolation performance.

[0052] Since the wet etching solution produces a reversible reaction with the material of the dielectric layer 401a, although the reverse etching rate is greater than the forward etching rate, the etching of the dielectric layer 401a and the growth of the reverse etching layer 601 are both dynamic during the etching process. In some specific embodiments, the dielectric layer 401a at the top of a portion of the hole 402 will also be etched away, exposing the hole 402; and then due to the deposition of the reverse etching layer 402, the hole 402 can be further filled.

[0053] In a specific embodiment, the preset value is 7.5×10- 6 mol / L, that is, the concentration of H2SiO3 in the wet etching solution is greater than or equal to 7.5×10- 6 mol / L.

[0054] The thickness of the reverse etching layer 601 is determined by the wet etching time and the concentration of H2SiO3 in the solution. In some specific embodiments, the thickness of the reverse etching layer 601 is 0.1nm to 0.3nm, which can be adjusted according to the size of the hole. In a specific embodiment, the thickness of the reverse etching layer 601 is 0.2nm.

[0055] In the prior art, when etching silicon nitride using a wet etching process, a phosphoric acid solution with a relatively low H2SiO3 concentration is usually used as an etching solution for wet etching to ensure an etching rate for silicon nitride and avoid reverse etching of silicon oxide.

[0056] In some specific embodiments of the present invention, the phosphoric acid solution used in the prior art can be used as the phosphoric acid solution stock solution, and the phosphoric acid solution stock solution can be pretreated to form the etching solution used in the wet etching process of the present invention. In the phosphoric acid solution stock solution, the concentration of H3PO4 can be 15 mol / L, and the concentration of H2SiO3 is close to 0. As the pretreatment process proceeds, the concentration of H2SiO3 increases.

[0057] In some specific embodiments, a phosphoric acid solution stock solution can be used to etch a quantitative silicon nitride layer so that the concentration of H2SiO3 in the solution is greater than or equal to a preset value. No other solution is added during the pretreatment process, so when the concentration of H2SiO3 is increased, the concentration of H3PO4 is less affected. Specifically, the method of etching a quantitative silicon nitride layer using a phosphoric acid solution stock solution further includes: placing multiple wafers formed with silicon nitride layers into a wet etching tank filled with phosphoric acid solution stock solution, and etching for a certain period of time until the concentration of H2SiO3 in the solution is greater than or equal to a preset value.

[0058] Please refer to Fig. 7AThe phosphoric acid solution 7011 is pre-treated by wet etching tank 701. The phosphoric acid solution 7011 contains a relatively low concentration of H2SiO3. The concentration distribution of the phosphoric acid solution 7011 is uniform through the nozzle 702 at the bottom of the wet etching tank 701.

[0059] Please refer to Figure 7B , multiple wafers 703 with silicon nitride films formed on their surfaces are placed in the wet etching groove 701 to etch the silicon nitride films.

[0060] The etching amount of silicon nitride is controlled according to the requirements of H2SiO3 in the final solution. The etching amount of silicon nitride can be controlled by the number of wafers 703, etching time, and the thickness of the silicon nitride layer on the surface of a single wafer 703.

[0061] In some specific embodiments, the thickness of the silicon nitride layer is greater than or equal to 300nm, the number of wafers is 80 to 120, and the etching time is 50min to 70min. In a specific embodiment, the thickness of the silicon nitride layer is 300nm, the number of wafers 703 is 100, and the etching time is 60min.

[0062] In other specific embodiments, the silicon nitride film may also be formed on other carriers that do not react with the phosphoric acid solution.

[0063] Please refer to Figure 7C After the pretreatment is completed, the wafer 703 (please refer to Figure 7B ) is taken out from the wet etching tank 701, and the pretreated solution in the wet etching tank 701 is used as the etching solution 704, and the concentration of H2SiO3 is greater than or equal to a preset value.

[0064] In other specific embodiments, other methods may be used to increase the concentration of H2SiO3 in the phosphoric acid solution, which is not limited here.

[0065] Please refer to Fig.7D , will form Figure 5 The multiple wafers 705 of the structure are placed in a wet etching tank 701 containing a solution 704 to etch the patterned mask layer 202. The solution 704 has an effect on the dielectric layer 401a (see Figure 5 ) to perform reverse etching to form a reverse etching layer 601 that fills the exposed hole 402 or at least seals the top of the exposed hole 402 (see Figure 6 ).

[0066] During the etching process of the patterned mask layer 202 , each time a certain number of wafers are etched, part of the etching solution 704 is drained and a certain amount of pre-treated new etching solution is added to ensure that the concentrations of H 2 SiO 3 and phosphoric acid in the etching solution 704 are stable.

[0067] In the method for forming the semiconductor structure, an etching solution having reverse etching properties for the dielectric layer is used to form a reverse etching layer on the surface of the dielectric layer while etching away the patterned mask layer, thereby improving the isolation performance of the dielectric layer.

[0068] A specific embodiment of the present invention further provides a semiconductor structure.

[0069] Please refer to Figure 6 , which is a schematic structural diagram of the semiconductor structure.

[0070] The semiconductor structure includes: a substrate 200; an etching pattern located in the substrate 200; an isolation layer filled in the etching pattern, the isolation layer includes a dielectric layer 401a and a reverse etching layer 601 located on the top of the dielectric layer 401a, and the reverse etching layer 601 is formed by reverse etching the dielectric layer 401a through a wet etching process.

[0071] In a specific embodiment, the dielectric layer 401a and the reverse etching layer 601 are made of silicon oxide. The reverse etching layer 601 can be formed by reverse etching the dielectric layer 401a with a phosphoric acid solution containing a relatively high concentration of H2SiO3. The concentration of H2SiO3 is greater than or equal to a preset value, preferably, the preset value is 7.5×10 -6 mol / L, that is, the concentration of H2SiO3 in the wet etching solution is greater than or equal to 7.5×10 -6 mol / L.

[0072] The top of the isolation layer is higher than the surface of the substrate 200. In a specific embodiment, during the process of removing the silicon nitride layer on the surface of the substrate 200, the wet etching solution used can reversely etch the dielectric layer 401a while removing the silicon nitride layer to form the reverse etching layer 601, thereby improving the isolation performance of the isolation layer.

[0073] In this specific embodiment, the dielectric layer 401a is formed by chemical vapor deposition. Due to the process limitations of the chemical vapor deposition process, it is easy to cause holes 402 in the dielectric layer 401a, and some of the holes 402 are exposed on the surface of the dielectric layer 401a. The reverse etching layer 601 fills the holes 402 exposed on the surface of the dielectric layer 401a or at least closes the top of the holes 402 exposed on the surface of the dielectric layer 401a.

[0074] In order to make the reverse etching layer 601 have a good filling and sealing effect on the holes and improve the isolation performance of the isolation layer, the thickness of the reverse etching layer is 0.1nm to 0.3nm.

[0075] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a patterned mask layer having an opening on the surface of the substrate; Etching the substrate along the opening to form an etching pattern in the substrate; forming a dielectric layer that fills the etched pattern and covers the patterned mask layer; planarizing the dielectric layer to expose the surface of the patterned mask layer; The patterned mask layer is removed by a wet etching process, wherein the wet etching process performs reverse etching on the dielectric layer while etching and removing the patterned mask layer, thereby forming a reverse etching layer on the surface of the dielectric layer; The dielectric layer in the etched pattern has holes in it. When the dielectric layer is planarized and the patterned mask layer is etched, part of the holes are exposed on the surface of the dielectric layer; the reverse etching layer fills the exposed holes or at least closes the tops of the holes.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the wet etching process, the etching ratio of the patterned mask layer and the dielectric layer is greater than 100:1; the etching solution used in the wet etching process has reversible etching properties for the dielectric layer, and the negative etching rate is greater than the positive etching rate.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the patterned mask layer is silicon nitride, the material of the dielectric layer is silicon oxide, the etching solution used in the wet etching process is a phosphoric acid solution, and the phosphoric acid solution contains H2SiO3, and the concentration of H2SiO3 is greater than or equal to a preset value.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The phosphoric acid solution stock solution is pretreated to form an etching solution used in the wet etching process. The pretreatment method includes: etching a certain amount of silicon nitride layer with the phosphoric acid solution stock solution so that the concentration of H2SiO3 in the solution is greater than or equal to a preset value.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The method of etching a quantitative silicon nitride layer using a phosphoric acid solution further includes: placing multiple wafers with silicon nitride layers formed thereon into a wet etching tank containing a phosphoric acid solution, and etching for a certain period of time until the concentration of H2SiO3 in the solution is greater than or equal to a preset value.

6. A semiconductor structure, characterized in that: include: substrate; an etched pattern located within the substrate; an isolation layer filled in the etched pattern, wherein a top of the isolation layer is higher than a surface of the substrate; The isolation layer includes a dielectric layer and a reverse etching layer located on the top of the dielectric layer, the reverse etching layer is formed by reverse etching the dielectric layer through a wet etching process, the dielectric layer of the isolation layer has holes in it, some of the holes are exposed on the surface of the dielectric layer, and the reverse etching layer fills the holes exposed on the surface of the dielectric layer or at least closes the tops of the holes exposed on the surface of the dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that: The material of the dielectric layer is silicon oxide, and the material of the reverse etching layer is silicon oxide.

8. The semiconductor structure according to claim 6, characterized in that: The thickness of the reverse etching layer is 0.1nm-0.3nm.

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