Stacked package and package connection system including the same

Abstract

The present invention provides a stacked package and a package connection system including the stacked package. The stacked package includes: a first semiconductor package including a first semiconductor chip; and a second semiconductor package disposed on the first semiconductor package and including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip includes one or more units. The number of the units of the first semiconductor chip is greater than the number of the units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement the functions of an application processor chip.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0028668, filed with the Korean Intellectual Property Office on Mar. 13, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a stacked package (PoP) and a package connection system including the stacked package. Background Art

[0003] With the recent development of intelligent electronic devices, the specifications of components used in such devices are increasing. For example, the specifications of application processors (APs), which are core chips of intelligent electronic devices, are rapidly improving. Accordingly, a main processor unit or the like capable of driving various functions is integrated into a single chip. Summary of the Invention

[0004] One aspect of the present disclosure is that a specific unit of an application processor chip is separated into a semiconductor chip, and the performance of the specific unit is enhanced to distinguish the functions of groups.

[0005] One proposal of the present disclosure is that multiple units performing the functions of a single application processor are dispersed into multiple semiconductor chips, and then the multiple semiconductor chips are arranged in the form of a stacked package (PoP).

[0006] According to one aspect of the present disclosure, a stacked package includes: a first semiconductor package including a first semiconductor chip; and a second semiconductor package disposed on the first semiconductor package and including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement the functions of an application processor chip.

[0007] According to another aspect of the present disclosure, a package connection system includes: a printed circuit board having a first surface and a second surface opposite to the first surface; a stacked package disposed on the first surface of the printed circuit board and having the function of an application processor chip; a memory package disposed on one of the first surface and the second surface of the printed circuit board and having a memory function; and a power management package having a power management function and disposed on the other of the first surface and the second surface of the printed circuit board. The stacked package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first semiconductor chip, and the second semiconductor package is disposed on the first semiconductor package and includes a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement the function of an application processor (AP) chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram schematically showing an example of an electronic device system;

[0010] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0011] Figure 3A and Figure 3B are schematic cross-sectional views showing the states of a fan-in type semiconductor package before and after being packaged;

[0012] Figure 4 is a schematic cross-sectional view showing the packaging process of a fan-in type semiconductor package;

[0013] Figure 5 is a schematic cross-sectional view showing a situation where a fan-in type semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device;

[0014] Figure 6 is a schematic cross-sectional view showing a situation where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device;

[0015] Figure 7is a schematic cross-sectional view showing a fan-out semiconductor package;

[0016] Figure 8 is a schematic cross-sectional view showing a situation where a fan-out semiconductor package is mounted on a main board of an electronic device;

[0017] Figure 9 is a schematic cross-sectional view showing an example of a stacked package (PoP);

[0018] Figure 10 is showing an application to Figure 9 a schematic plan view showing the layout of respective units of a first semiconductor chip and a second semiconductor chip of a stacked package (PoP) in;

[0019] Figure 11 is showing an application to Figure 9 a schematic cross-sectional view showing an example of a first semiconductor package of a stacked package (PoP) in;

[0020] Figure 12 is showing an application to Figure 9 a schematic cross-sectional view showing another example of a first semiconductor package of a stacked package (PoP) in;

[0021] Figure 13 is showing an application to Figure 9 a schematic cross-sectional view showing another example of a first semiconductor package of a stacked package (PoP) in;

[0022] Figure 14 is showing an application to Figure 9 a schematic cross-sectional view showing another example of a first semiconductor package of a stacked package (PoP) in;

[0023] Figure 15 is showing an application to Figure 9 a schematic cross-sectional view showing an example of a second semiconductor package of a stacked package (PoP) in;

[0024] Figure 16 is showing an application to Figure 9 a schematic cross-sectional view showing another example of a second semiconductor package of a stacked package (PoP) in;

[0025] Figure 17 is a schematic cross-sectional view showing an example of a package connection system; and

[0026] Figure 18 is a schematic cross-sectional view showing another example of a package connection system. Detailed Description of the Invention

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0028] Electronic device

[0029] Figure 1 is a schematic block diagram showing an example of an electronic device system.

[0030] Referring to Figure 1 , the electronic device 1000 can accommodate the main board 1010 therein. The main board 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically or electrically connected to the main board 1010. These components can be connected to other components to be described below through various signal lines 1090.

[0031] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processors (e.g., central processing unit (CPU)), graphics processors (e.g., graphics processing unit (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADC), application-specific integrated circuits (ASIC), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 can be combined with each other.

[0032] The network-related components 1030 may include components operating based on protocols such as: Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long-Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High-Speed Packet Access+ (HSPA+), High-Speed Downlink Packet Access+ (HSDPA+), High-Speed Uplink Packet Access+ (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating based on a variety of other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 can be combined with each other together with the above chip-related components 1020.

[0033] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components for various other purposes. In addition, other components 1040 may be combined with each other together with the above-described chip-related components 1020 or network-related components 1030.

[0034] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically or electrically connected to the main board 1010 or may not be physically or electrically connected to the main board 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disc (CD) drive (not shown), a digital versatile disc (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes depending on the type of the electronic device 1000, etc.

[0035] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0036] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0037] Refer to Figure 2 , the semiconductor package may be used for various purposes in various electronic devices 1000 as described above. For example, the main board 1110 may be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the main board 1110. In addition, other components (such as a camera module 1130) that may be physically or electrically connected to the main board 1110 or may not be physically or electrically connected to the main board 1110 may be accommodated in the body 1101. Some of the electronic components 1120 may be chip-related components, for example, the semiconductor package 1121, but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0038] Semiconductor package

[0039] Generally, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device or the like in a packaged state.

[0040] Here, in terms of electrical connection, due to the difference in circuit width between the semiconductor chip and the motherboard of the electronic device, a semiconductor package is required. Specifically, the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip are very small, while the size of the component mounting pads of the motherboard used in the electronic device and the pitch between the component mounting pads of the motherboard are significantly larger than the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the motherboard, and a packaging technology for alleviating the difference in circuit width between the semiconductor chip and the motherboard is required.

[0041] The semiconductor package manufactured by the packaging technology can be classified into a fan-in type semiconductor package and a fan-out type semiconductor package according to its structure and purpose.

[0042] Hereinafter, the fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

[0043] Fan-in semiconductor package

[0044] Figure 3A and Figure 3B are schematic cross-sectional views showing the state of the fan-in type semiconductor package before and after being packaged.

[0045] Figure 4 is a schematic cross-sectional view showing the packaging process of the fan-in type semiconductor package.

[0046] Referring to Figures 3A to 4 , the semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a main body 2221, including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.; connection pads 2222, formed on one surface of the main body 2221 and including a conductive material such as aluminum (Al); and a passivation layer 2223 such as an oxide layer, a nitride layer, etc., formed on one surface of the main body 2221 and covering at least a part of the connection pads 2222. In this case, since the connection pads 2222 may be very small, it may be difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) in the medium size class and the motherboard of the electronic device or the like.

[0047] Therefore, in order to redistribute the connection pads 2222, a connection member 2240 may be formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connection member 2240 may be formed through the following steps: forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, forming via holes 2243h that expose the connection pads 2222, and then forming a wiring pattern 2242 and vias 2243. Then, a passivation layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 etc. may be formed. That is, a fan-in type semiconductor package 2200 including, for example, a semiconductor chip 2220, a connection member 2240, a passivation layer 2250, and an under bump metal layer 2260 may be manufactured through a series of processes.

[0048] As described above, a fan-in type semiconductor package may have a package form in which all connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components installed in a smart phone have been manufactured in the form of a fan-in type semiconductor package. Specifically, many components installed in a smart phone have been developed to achieve fast signal transmission while having a compact size.

[0049] However, in a fan-in type semiconductor package, since all I / O terminals need to be disposed inside the semiconductor chip, the fan-in type semiconductor package has great space limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a compact size. In addition, due to the above disadvantages, it may not be possible to directly mount and use a fan-in type semiconductor package on the main board of an electronic device. The reason is that even if the size of the I / O terminals of the semiconductor chip and the pitch between the I / O terminals of the semiconductor chip are increased through a redistribution process, the size of the I / O terminals of the semiconductor chip and the pitch between the I / O terminals of the semiconductor chip are still not sufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.

[0050] Figure 5 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is mounted on a ball grid array (BGA) substrate and finally mounted on the main board of an electronic device.

[0051] Figure 6 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is embedded in a BGA substrate and finally mounted on the main board of an electronic device.

[0052] Refer to Figure 5, in a fan-in semiconductor package 2200, connection pads 2222 (i.e., I / O terminals) of a semiconductor chip 2220 can be redistributed through a BGA substrate 2301, and in a state where the fan-in semiconductor package 2200 is mounted on the BGA substrate 2301, the fan-in semiconductor package 2200 can be finally mounted on a main board 2500 of an electronic device. In this case, solder balls 2270 etc. can be fixed through an underfill resin 2280 etc., and the outside of the semiconductor chip 2220 can be covered with a molding material 2290 etc. Optionally, referring to Figure 6 , the fan-in semiconductor package 2200 can be embedded in a separate BGA substrate 2302. In a state where the fan-in semiconductor package 2200 is embedded in the BGA substrate 2302, connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 can be redistributed through the BGA substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

[0053] As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a main board of an electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate BGA substrate and then mounted on the main board of the electronic device through a packaging process, or the fan-in semiconductor package can be mounted and used on the main board of the electronic device in a state where the fan-in semiconductor package is embedded in the BGA substrate.

[0054] Fan-out semiconductor package

[0055] Figure 7 is a schematic cross-sectional view showing a fan-out semiconductor package.

[0056] Referring to Figure 7 , in a fan-out semiconductor package 2100, for example, the outside of a semiconductor chip 2120 can be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 can be redistributed to the outside of the semiconductor chip 2120 through a connection member 2140. In this case, a passivation layer 2150 can be further formed on the connection member 2140, and an under-bump metal layer 2160 can be further formed in an opening of the passivation layer 2150. Solder balls 2170 can be further formed on the under-bump metal layer 2160. The semiconductor chip 2120 can be an integrated circuit (IC) including a main body 2121, connection pads 2122, a passivation layer (not shown), etc. The connection member 2140 can include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and vias 2143 that electrically connect the connection pads 2122 and the redistribution layer 2142 to each other.

[0057] As described above, a fan-out type semiconductor package may have a form in which I / O terminals of a semiconductor chip are redistributed through connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. As described above, in a fan-in type semiconductor package, all I / O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the balls need to be reduced, such that a standardized ball layout may not be used in the fan-in type semiconductor package. On the other hand, as described above, a fan-out type semiconductor package has a form in which I / O terminals of a semiconductor chip are redistributed through connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. Therefore, even when the size of the semiconductor chip is reduced, the standardized ball layout may still be used as it is in the fan-out type semiconductor package, such that the fan-out type semiconductor package may be mounted on a main board of an electronic device without using a separate BGA substrate, as described below.

[0058] Figure 8 FIG. is a schematic cross-sectional view showing a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0059] Referring to Figure 8 , the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes a connection member 2140 that is formed on the semiconductor chip 2120 and is capable of redistributing the connection pads 2122 to a fan-out region outside the size of the semiconductor chip 2120, such that the standardized ball layout may be used as it is in the fan-out type semiconductor package 2100. Accordingly, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device without using a separate BGA substrate or the like.

[0060] As described above, since the fan-out type semiconductor package may be mounted on the main board of the electronic device without using a separate BGA substrate, the fan-out type semiconductor package may be implemented with a thickness smaller than that of a fan-in type semiconductor package using a BGA substrate. Therefore, the fan-out type semiconductor package may be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly suitable for mobile products. Therefore, the fan-out type semiconductor package may be implemented in a form more compact than a form of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve problems caused by the occurrence of a warping phenomenon.

[0061] In addition, a fan-out semiconductor package refers to a packaging technology for mounting a semiconductor chip on a main board of an electronic device or the like as described above and protecting the semiconductor chip from the influence of external impacts, and is a concept different from that of a printed circuit board (PCB) such as a BGA substrate (which has specifications, uses, etc. different from those of the fan-out semiconductor package and in which a fan-in semiconductor package is embedded).

[0062] Package-on-Package (PoP)

[0063] Figure 9 is a schematic cross-sectional view showing an example of a stacked package (PoP), and Figure 10 is a schematic plan view showing the layout of each unit of a first semiconductor chip and a second semiconductor chip of the stacked package (PoP) applied to Figure 9 therein.

[0064] Referring to Figure 9 and Figure 10 , a stacked package (PoP) 300 according to an exemplary embodiment includes: a first semiconductor package 100 including a first semiconductor chip 120; and a second semiconductor package 200 including a second semiconductor chip 220, and disposed on the first semiconductor package 100 and electrically connected to the first semiconductor chip 120. The stacked package (PoP) 300 having such a structure can be mounted on a printed circuit board (PCB) such as a main board using a first electrical connection metal member 170. The first semiconductor package 100 and the second semiconductor package 200 can be physically / electrically connected via a second electrical connection metal member 270. The detailed structures of the packages 100 and 200 will be described in detail with reference to the accompanying drawings later.

[0065] The first semiconductor chip 120 may include one or more units A1 to A3, B1 to B4, C1 to C4, D1, and D2, and the second semiconductor chip 220 may include one or more units A4, E1 to E4, and F. The number of units A1 to A3, B1 to B4, C1 to C4, D1, and D2 of the first semiconductor chip 120 may be greater than the number of units A4, E1 to E4, and F of the second semiconductor chip 220. The units A1 to A3, B1 to B4, C1 to C4, D1, and D2 of the first semiconductor chip 120 and the units A4, E1 to E4, and F of the second semiconductor chip 220 may implement the functions of at least one application processor chip. As needed, the units A1 to A3, B1 to B4, C1 to C4, D1, and D2, A4, E1 to E4, and F may be electrically connected to each other.

[0066] For example, as Figure 10As shown, the application processor chip 12 may include core units A1 to A4, interface units B1 to B4, memory units C1 to C4, and general-purpose input / output units D1 and D2. The core units A1 to A4 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processing unit (DSPU) (e.g., a digital signal processor (DSP)), an image signal processing unit (ISPU) (e.g., an image processor, an image signal processor, or an image processing engine), a neural processing unit (NPU) (or a neural processor), etc.

[0067] In the stacked package (PoP) 300, the first semiconductor chip 120 includes most of the units A1 to A3 among the core units A1 to A4, and the second semiconductor chip 220 includes the other unit A4 among the core units A1 to A4. The core units A1 to A3 included in the first semiconductor chip 120 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), and / or a digital signal processing unit (DSPU). The core unit A4 included in the second semiconductor chip 220 may be, for example, an image processing unit (ISPU) and / or a neural processing unit (NPU). As needed, the second semiconductor chip 220 may further include additional units E1 to E4 and F. The additional units E1 to E4 and F may be interface units or input / output units, but are not limited thereto.

[0068] According to the discrete design, the first semiconductor chip 120 may not include the core unit A4 included in the second semiconductor chip 220. For example, the first semiconductor chip 120 may not include the image signal processing unit (ISPU) and / or the neural processing unit (NPU) included in the second semiconductor chip 220. When the second semiconductor chip 220 only includes the image signal processing unit (ISPU) as the core unit A4, the first semiconductor chip 120 may include the neural processing unit (NPU). When the second semiconductor chip 220 only includes the neural processing unit (NPU) as the core unit A4, the first semiconductor chip 120 may include the image signal processing unit (ISPU).

[0069] As described above, when a specific unit A4 included in the application processor chip 12 is separated and implemented as a separate second semiconductor chip 220, the function of the corresponding unit A4 can be enhanced. For example, when the unit A4 separated and included in the second semiconductor chip 220 is an image signal processing unit (ISPU), the camera function (such as resolution) of the mobile device can be enhanced. When the unit A4 separated and included in the second semiconductor chip 220 is a neural processing unit (NPU), the artificial intelligence (AI) function (such as the AI function for speech recognition and / or image recognition) of the mobile device can be enhanced. Both the enhanced camera function and the enhanced AI function can be combined with each other.

[0070] The second semiconductor chip 220 is designed by separating a specific unit A4 and can be smaller in size than the first semiconductor chip 120. For example, when viewed from above (or in a plan view), the size of the first semiconductor chip 120 can be larger than the size of the second semiconductor chip 220. As needed, the second semiconductor chip 220 can use the memory cells C1 to C4 included in the first semiconductor chip 120 without including additional memory cells. For example, at least one of the units A4, E1 to E4, and F included in the second semiconductor chip 220 can be electrically connected to the memory cells C1 to C4 included in the first semiconductor chip 120. As needed, in order to reduce the number of input / output terminals of the stacked package (PoP) 300, the second semiconductor chip 220 may not include or may include a minimum number of input / output units for electrically connecting to a dynamic random access memory (DRAM). Instead, the second semiconductor chip 220 can use a path via the first semiconductor chip 120 to be electrically connected to the DRAM. Thus, the stacked package (PoP) 300 can be designed to be more compact.

[0071] Figure 11 is a schematic cross-sectional view showing an example of a first semiconductor package of the stacked package (PoP) 300 applied to Figure 9

[0072] Refer to Figure 11 ​, the first semiconductor package 100A according to the exemplary embodiment includes: a frame 110 having a through-hole 110H and including one or more wiring layers 112a, 112b, and 112c; a first semiconductor chip 120 disposed in the through-hole 110H of the frame 110 and having a first connection pad 122; a first encapsulant 130 covering at least a part of each of the frame 110 and the first semiconductor chip 120; a backside wiring layer 132 disposed on the upper side of the first encapsulant 130; a backside via 133 passing through the first encapsulant 130 and electrically connecting the backside wiring layer 132 to one or more of the wiring layers 112a, 112b, and 112c to each other; a first connection structure 140 disposed on the lower sides of the frame 110 and the first semiconductor chip 120, including one or more first redistribution layers 142 electrically connected to one or more of the wiring layers 112a, 112b, and 112c and the first connection pad 122; a first passivation layer 150 disposed on the lower side of the first connection structure 140 and having an opening exposing at least a part of one or more first redistribution layers 142; a first under-bump metal 160 disposed in the opening of the first passivation layer 150 to be electrically connected to the exposed first redistribution layer 142; a first electrical connection metal 170 disposed on the lower side of the first passivation layer 150 and electrically connected to the exposed first redistribution layer 142 through the first under-bump metal 160; and a cover layer 180 disposed on the upper side of the first encapsulant 130 and having an opening exposing at least a part of the backside wiring layer 132.

[0073] The frame 110 can further improve the rigidity of the first semiconductor package 100A according to the specific materials of the insulating layers 111a and 111b and can be used to ensure the thickness uniformity of the first encapsulant 130, etc. The frame 110 can have a through-hole 110H penetrating the insulating layers 111a and 111b. The first semiconductor chip 120 is disposed in the through-hole 110H, and if necessary, passive components (not shown) can be disposed together. The through-hole 110H can have a wall surface surrounding the first semiconductor chip 120, but the shape of the through-hole 110H is not limited thereto. In addition to the insulating layers 111a and 111b, the frame 110 can further include wiring layers 112a, 112b, and 112c and wiring vias 113a and 113b, and thus can be used as an electrical connection member providing a vertical electrical connection path. If necessary, another type of electrical connection member such as a metal pillar providing a vertical electrical connection path can be introduced as the frame 110.

[0074] In the example, the frame 110 includes: a first insulating layer 111a; a first wiring layer 112a embedded in the first insulating layer 111a while being in contact with the first connection structure 140; a second wiring layer 112b disposed on a side of the first insulating layer 111a opposite to the side in which the first wiring layer 112a is embedded; a second insulating layer 111b disposed on a side of the first insulating layer 111a opposite to the side in which the first wiring layer 112a is embedded, covering at least a portion of the second wiring layer 112b; and a third wiring layer 112c disposed on a side of the second insulating layer 111b opposite to the side in which the second wiring layer 112b is embedded. The first wiring layer 112a and the second wiring layer 112b, and the second wiring layer 112b and the third wiring layer 112c are electrically connected to a first wiring via 113a penetrating the first insulating layer 111a and a second wiring via 113b penetrating the second insulating layer 111b, respectively. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c can be electrically connected to the first connection pad 122 through the first redistribution layer 142 and the first connection via 143 of the first connection structure 140 according to their functions.

[0075] The materials of the insulating layers 111a and 111b are not limited. For example, an insulating material can be used as the materials of the insulating layers 111a and 111b. The insulating material can be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide resin, a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler (e.g., ABF (Ajinomoto Build-up Film)), etc. Optionally, the insulating material can be a material impregnated with an inorganic filler in a core material such as glass fiber (or glass cloth or glass fabric), e.g., a prepreg, etc.

[0076] The wiring layers 112a, 112b, and 112c can provide a vertical electrical connection path for the first semiconductor package 100A together with the wiring vias 113a and 113b, and can be used to redistribute the first connection pads 122. The materials of the wiring layers 112a, 112b, and 112c can be metals, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The wiring layers 112a, 112b, and 112c can perform various functions according to the design of the corresponding layers. For example, the wiring layers 112a, 112b, and 112c can include a ground (GND) pattern, a power (PWR) pattern, a signal (S') pattern, etc. The signal (S') pattern includes various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern, etc. The ground (GND) pattern and the power (PWR) pattern can be the same as each other. The wiring layers 112a, 112b, and 112c can include various types of via pads. The wiring layers 112a, 112b, and 112c can be formed by known plating processes and can each include a seed layer and a plating layer. For example, not only the third wiring layer 112c (the uppermost wiring layer 112c) but also the first wiring layer 112a and the second wiring layer 112b can each include a seed layer and a plating layer.

[0077] The thickness of each of the wiring layers 112a, 112b, and 112c can be greater than the thickness of the first redistribution layer 142. More specifically, the thickness of the frame 110 can be greater than or equal to the thickness of the first semiconductor chip 120. Since a prepreg or the like can be selected as the material of the insulating layers 111a and 111b to maintain the rigidity of the insulating layers 111a and 111b, each of the wiring layers 112a, 112b, and 112c can also have a relatively large thickness. In addition, since the first connection structure 140 requires a fine circuit and a high-density design, a photosensitive dielectric (PID) or the like is selected as the material of the first insulating layer 141, and the first redistribution layer 142 can also have a relatively small thickness.

[0078] The first wiring layer 112a can be recessed into the first insulating layer 111a. The first wiring layer 112a is recessed into the first insulating layer 111a to form a step between the surface of the first insulating layer 111a that is set to contact the first connection structure 140 and the surface of the first wiring layer 112a that is set to contact the first connection structure 140. In this case, when the first semiconductor chip 120 and the frame 110 are encapsulated by the first encapsulant 130, the leakage of the material of the first encapsulant 130 can be suppressed to prevent the first wiring layer 112a from being contaminated by the material of the first encapsulant 130.

[0079] The wiring vias 113a and 113b electrically connect the wiring layers 112a, 112b, and 112c provided on different layers to form an electrical connection path in the frame 110. The materials of the wiring vias 113a and 113b can be metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The wiring vias 113a and 113b can include vias for signals, vias for power, vias for ground, etc., and the vias for power and the vias for ground can be the same as each other. Each of the wiring vias 113a and 113b can be a filled-type via filled with a metal material or a conformal-type via in which a metal material is formed along the wall surface of the via hole. In addition, each of the wiring vias 113a and 113b can have a tapered shape. The wiring vias 113a and 113b can also be formed by a plating process and can include a seed layer and a plating layer.

[0080] When forming the hole for the first wiring via 113a, some pads of the first wiring layer 112a can be used as a barrier. Therefore, in the process, it is advantageous for the first wiring via 113a to have a tapered shape with a width at the upper side greater than the width at the lower side. In this case, the first wiring via 113a can be integrated with the pad pattern of the second wiring layer 112b. Similarly, when forming the hole for the second wiring via 113b, some pads of the second wiring layer 112b can be used as a barrier. Therefore, in the process, it is advantageous for the second wiring via 113b to have a tapered shape with a width at the upper side greater than the width at the lower side. In this case, the second wiring via 113b can be integrated with the pad pattern of the third wiring layer 112c.

[0081] As needed, metal (not shown) can be provided on the wall surface of the penetrating portion 110H of the frame 110 to shield electromagnetic interference or for heat dissipation. A metal layer (not shown) can surround the first semiconductor chip 120.

[0082] The first semiconductor chip 120 may be an integrated circuit (IC) in a bare state without additional bumps or wiring layers formed thereon, but is not limited thereto. As needed, the first semiconductor chip 120 may be a packaged integrated circuit. The first semiconductor chip 120 may be an IC formed based on an active wafer. In this case, the base material of the main body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed on the main body 121. The first connection pad 122 may electrically connect the first semiconductor chip 120 to other components. The material of the first connection pad 122 may be a metal such as aluminum (Al), but is not limited thereto. The passivation layer 123 may be provided on the main body 121 to expose the first connection pad 122, and the passivation layer 123 may be an oxide layer, a nitride layer, etc. Optionally, the passivation layer 123 may be a double layer of an oxide layer and a nitride layer. The first semiconductor chip 120 has an active surface and an inactive surface. The first connection pad 122 is provided on the active surface, and the inactive surface is the back surface opposite to the active surface. In some cases, connection pads may also be provided on the back surface so that both surfaces may be active surfaces. As an example, when the passivation layer 123 is provided on the active surface of the first semiconductor chip 120, the positional relationship of the active surface of the first semiconductor chip 120 is determined based on the lowermost surface of the passivation layer 123.

[0083] The first encapsulant 130 covers at least a part of the frame 110 and the first semiconductor chip 120 and fills at least a part of the through-hole 110H. The first encapsulant 130 includes an insulating material such as a non-photosensitive dielectric. More specifically, the insulating material of the first encapsulant 130 may be a non-photosensitive dielectric including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler immersed in a thermosetting resin or a thermoplastic resin (such as ABF or a non-photosensitive dielectric such as MEC). As needed, a material in which an inorganic filler and / or a core material (such as glass fiber) is immersed in a thermosetting resin or a thermoplastic resin may also be used as the insulating material. Therefore, voids or undulations can be prevented, and warpage can be more easily controlled. As needed, a photosensitive encapsulant (PIE) may be used as the insulating material.

[0084] The backside wiring layer 132 is disposed on the first encapsulant 130 to provide a backside circuit to the first semiconductor package 100A together with the backside vias 133. The backside wiring layer 132 may also include a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The backside wiring layer 132 may perform various functions according to the design. For example, the backside wiring layer 132 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S') pattern, etc. The signal (S') pattern includes various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same as each other. The backside wiring layer 132 may be formed by a known plating process and may include a seed layer and a plating layer.

[0085] The backside vias 133 penetrate the first encapsulant 130 and electrically connect the backside wiring layer 132 to the third wiring layer 112c (the uppermost wiring layer 112c). The backside vias 133 may also include a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The backside vias 133 may be filled vias filled with a metal material or conformal vias formed along the wall surface of the via hole. The backside vias 133 may have a tapered shape in the same direction as the wiring vias 113a and 113b. The backside vias 133 may also include vias for signals, vias for power, vias for ground, etc., and the vias for power and the vias for ground may be the same as each other. The backside vias 133 may also be formed by a known plating process and may include a seed layer and a plating layer.

[0086] The first connection structure 140 may redistribute the first connection pads 122 of the first semiconductor chip 120. Dozens to hundreds of first connection pads 122 having various functions may be redistributed by the first connection structure 140 and physically connected and / or electrically connected by the first electrical connection metal members 170 according to their functions. The first connection structure 140 includes: a first insulating layer 141; a first redistribution layer 142 disposed on the bottom surface of the first insulating layer 141; and a first connection via 143 penetrating the first insulating layer 141 and electrically connected to the first redistribution layer 142. The first insulating layer 141, the first redistribution layer 142, and the first connection via 143 may include more layers or fewer layers than the number of layers shown in the figure. For example, the number of layers may vary according to the design.

[0087] The material of the first insulating layer 141 may be an insulating material such as photosensitive dielectric (PID). In this case, fine pitch can be introduced through photo vias, which is advantageous in terms of fine circuits and high-density designs and allows dozens to millions of connection pads 122 of the first semiconductor chip 120 to be effectively redistributed. The boundary between the first insulating layers 141 may be distinct or may not be easily distinguishable.

[0088] The first redistribution layer 142 may redistribute the first connection pads 122 of the first semiconductor chip 120 to electrically connect the first connection pads 122 to the first electrical connection metal pieces 170. The material of the first redistribution layer 142 may also be a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The first redistribution layer 142 may also perform various functions according to the design. For example, the first redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S') pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same as each other. The first redistribution layer 142 may include various types of via pads, electrical connection metal pads, etc. The first redistribution layer 142 may be formed by a plating process and may include a seed layer and a plating layer.

[0089] The first connection via 143 electrically connects the first redistribution layers 142 provided on different layers to each other, and electrically connects the first connection pads 122 of the first semiconductor chip 120 and the first wiring layer 112a of the frame 110 to the first redistribution layer 142. When the first semiconductor chip 120 is a die, the first connection via 143 may be in physical contact with the first connection pads 122. The material of the first redistribution layer 142 may also be a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The first connection via 143 may include vias for signals, vias for power, vias for ground, etc., and the vias for power and the vias for ground may be the same as each other. The first connection via 143 may also be a filled-type via filled with a metal material or a conformal-type via in which a metal material is formed along the wall surface of the via hole. In addition, the first connection via 143 may have a tapered shape in a direction opposite to the directions of the wiring vias 113a and 113b. The first connection via 143 may also be formed by a plating process and may include a seed layer and a plating layer.

[0090] The first passivation layer 150 is further configured to protect the first connection structure 140 from external physical and chemical damages, etc. The first passivation layer 150 may include a thermosetting resin. For example, the first passivation layer 150 may be ABF, but is not limited thereto. The first passivation layer 150 has openings that expose at least a portion of the lowermost first redistribution layer 142 of the first redistribution layer 142. There may be dozens to hundreds of thousands of openings, and the first passivation layer 150 may be provided with a greater or lesser number of openings. Each of the openings may include a plurality of holes. As needed, surface-mounted components such as capacitors may be disposed in the openings on the bottom surface of the first passivation layer 150 to electrically connect the surface-mounted components to the first redistribution layer 142. Thus, the surface-mounted components may also be electrically connected to the first semiconductor chip 120.

[0091] According to an exemplary embodiment, the first under-bump metal 160 may also be further configured to improve the connection reliability of the first electrical connection metal 170 and improve the board-level reliability of the first semiconductor package 100A. There may be dozens to millions of the first under-bump metals 160, and a greater or lesser number of the first under-bump metals 160 may be provided. Each first under-bump metal 160 may be disposed in the opening of the first passivation layer 150 to be electrically connected to the exposed lowermost first redistribution layer 142. The first under-bump metal 160 may be formed of a metal by a known metallization method, but is not limited thereto.

[0092] The first electrical connection metal 170 is further configured to physically connect and / or electrically connect the first semiconductor package 100A to an external component. For example, the first semiconductor package 100A may be mounted on the main board of an electronic device through the first electrical connection metal 170. The first electrical connection metal 170 may be disposed on the lower side of the first passivation layer 150 and may be electrically connected to the first under-bump metal 160. Each first electrical connection metal 170 may include a low melting point metal, such as tin (Sn) or an Sn-containing alloy. More specifically, each first electrical connection metal 170 may be formed of solder or the like, but is merely an example, and its material is not limited thereto.

[0093] The first electrical connection metal part 170 can be a pad, a solder ball, a pin, etc. The first electrical connection metal part 170 can be formed into a multi-layer structure or a single-layer structure. When the first electrical connection metal part 170 is formed into a multi-layer structure, the first electrical connection metal part 170 can include copper (Cu) pillars and solder. When the first electrical connection metal part 170 is formed into a single-layer structure, the first electrical connection metal part 170 can include tin-silver solder or copper (Cu). However, these are only examples, and the structure and material of the first electrical connection metal part 170 are not limited thereto. The quantity, pitch, arrangement form, etc. of the first electrical connection metal part 170 are not restricted, but can be fully modified by those skilled in the art according to the design. For example, dozens to hundreds of thousands of first electrical connection metal parts 170 can be set according to the quantity of the first connection pads 122, and more or fewer first electrical connection metal parts 170 can be set.

[0094] At least one of the first electrical connection metal parts 170 is disposed in the fan-out region. The term "fan-out region" refers to a region other than the region where the first semiconductor chip 120 is disposed. Compared with a fan-in type package, a fan-out type package can have improved reliability, can allow for the implementation of multiple input / output (I / O) terminals, and can facilitate three-dimensional (3D) interconnection. In addition, compared with a ball grid array (BGA) package, a land grid array (LGA) package, etc., a fan-out type package can be manufactured to have a small thickness and can have an advantage in terms of price competitiveness.

[0095] The cover layer 180 is additionally configured to protect the backside wiring layer 132 from external physical and chemical damage, etc. The cover layer 180 can include a thermosetting resin. For example, the cover layer 180 can be ABF, but is not limited thereto. The cover layer 180 has openings that expose at least a part of the backside wiring layer 132. There can be dozens to hundreds of thousands of openings, and the cover layer 180 can be provided with more or fewer openings. Each of the openings can include a plurality of holes.

[0096] Figure 12 is a schematic cross-sectional view showing another example of the first semiconductor package applied to Figure 9 the stacked package (PoP) in

[0097] Refer to Figure 12, the semiconductor package 100B according to another exemplary embodiment includes: a frame 110 having a structure different from that of the frame 110 of the first semiconductor package 100A described above. More specifically, the frame 110 includes: a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b respectively disposed on two surfaces of the first insulating layer 111a; a second insulating layer 111b and a third insulating layer 111c respectively disposed on two surfaces of the first insulating layer 111a to cover the first wiring layer 112a and the second wiring layer 112b respectively; a third wiring layer 112c disposed on a side of the second insulating layer 111b opposite to the side where the first wiring layer 112a is embedded; a fourth wiring layer 112d disposed on a side of the third insulating layer 111c opposite to the side where the second wiring layer 112b is embedded; a first wiring via 113a penetrating the first insulating layer 111a and electrically connecting the first wiring layer 112a and the second wiring layer 112b to each other; a second wiring via 113b penetrating the second insulating layer 111b and electrically connecting the first wiring layer 112a and the third wiring layer 112c to each other; and a third wiring via 113c penetrating the third insulating layer 111c and electrically connecting the second wiring layer 112b and the fourth wiring layer 112d to each other. Since the frame 110 includes a larger number of wiring layers 112a, 112b, 112c, and 112d, the first connection structure 140 can be further simplified.

[0098] The thickness of the first insulating layer 111a may be greater than the thicknesses of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may have a relatively large thickness to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of wiring layers 112c and 112d. From a similar perspective, the average diameter and height of the first wiring via 113a penetrating the first insulating layer 111a may be greater than the average diameter and height of each of the second wiring via 113b penetrating the second insulating layer 111b and the third wiring via 113c penetrating the third insulating layer 111c. The first wiring via 113a may have an hourglass shape or a cylindrical shape, and the second wiring via 113b and the third wiring via 113c may have a tapered shape in opposite directions. The thickness of each of the wiring layers 112a, 112b, 112c, and 112d may be greater than the thickness of the first redistribution layer 142.

[0099] Other descriptions are substantially the same as the detailed description of the first semiconductor package 100A according to the exemplary embodiment and will be omitted here.

[0100] Figure 13 is a schematic cross-sectional view showing another example of the first semiconductor package applied to Figure 9 the stacked package (PoP) in

[0101] Reference Figure 13 Referring to Figure 13 , a first semiconductor package 100C according to another exemplary embodiment includes a first semiconductor chip 120 disposed in the above-described first semiconductor package 100A in a face-up direction (instead of a face-down direction). Accordingly, a first connection structure 140 and a first passivation layer 150 are disposed on the upper side (instead of the lower side) of the first semiconductor package 100C. In addition, a backside wiring layer 132, backside vias 133, and a cover layer 180 are disposed on the lower side (instead of the upper side) of the first semiconductor package 100C. A first under-bump metal 160 is connected to the backside wiring layer 132, which is disposed and exposed in an opening formed in the cover layer 180. A first electrical connection metal 170 is disposed on the lower side of the cover layer 180 to be electrically connected to the exposed backside wiring layer 132 through the first under-bump metal 160. In such a structure, the electrical connection path between the first semiconductor chip 120 and the above-described second semiconductor chip 220 can be significantly shortened to achieve improved performance.

[0102] Other descriptions are substantially the same as the detailed description of the first semiconductor package 100A according to the exemplary embodiment and will be omitted herein.

[0103] Figure 14 is a schematic cross-sectional view showing another example of a first semiconductor package applied to Figure 9 a stacked package (PoP).

[0104] Reference Figure 14 Referring to Figure 14 , a first semiconductor package 100D according to another exemplary embodiment includes a first semiconductor chip 120 disposed in the above-described first semiconductor package 100B in a face-up direction (instead of a face-down direction). Accordingly, a first connection structure 140 and a first passivation layer 150 are also disposed on the upper side (instead of the lower side) of the first semiconductor package 100D. In addition, a backside wiring layer 132, backside vias 133, and a cover layer 180 are disposed on the lower side (instead of the upper side) of the first semiconductor package 100D. A first under-bump metal 160 is connected to the backside wiring layer 132, which is disposed and exposed in an opening formed in the cover layer 180. A first electrical connection metal 170 is disposed on the lower side of the cover layer 180 to be electrically connected to the exposed backside wiring layer 132 through the first under-bump metal 160. In such a structure, the electrical connection path between the first semiconductor chip 120 and the above-described second semiconductor chip 220 can be significantly shortened to achieve improved performance.

[0105] Other descriptions are substantially the same as the detailed descriptions of the first semiconductor packages 100A and 100B according to the exemplary embodiment and will be omitted herein.

[0106] Figure 15is a schematic cross-sectional view showing an example of a second semiconductor package applied to a Figure 9 stacked package (PoP) in

[0107] Referring to Figure 15 , a second semiconductor package 200A according to an example embodiment includes: a second semiconductor chip 220 having second connection pads 222; a second encapsulant 230 covering at least a portion of the second semiconductor chip 220; a second connection structure 240 disposed on a lower side of the second semiconductor chip 220 and including one or more second redistribution layers 242 electrically connected to the second connection pads 222; a second passivation layer 250 disposed on a lower side of the second connection structure 240 and having an opening exposing at least a portion of the one or more second redistribution layers 242; a second under-bump metal 260 disposed in the opening of the second passivation layer 250 to electrically connect to the exposed second redistribution layer 242; and a second electrical connection metal 270 disposed on a lower side of the second passivation layer 250 and electrically connected to the exposed second redistribution layer 242 through the second under-bump metal 260.

[0108] The second semiconductor chip 220 may be an integrated circuit (IC) in which hundreds to millions or more devices are integrated in a single chip. The integrated circuit constituting the second semiconductor chip 220 may include, for example, a separate chip formed by separating some units from an application processor chip as described above, but is not limited thereto. The second semiconductor chip 220 may be an integrated circuit in a bare state without forming additional bumps or wiring layers, but is not limited thereto. If necessary, the second semiconductor chip 220 may be a packaged integrated circuit. The integrated circuit may be formed based on an active wafer. In this case, the base material of the main body 221 of the second semiconductor chip 220 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed on the main body 221. The second connection pads 222 may electrically connect the second semiconductor chip 220 to other components. The material of the second connection pads 222 may be a metal such as copper (Cu), aluminum (Al), etc., but is not limited thereto. A passivation layer 223 may be disposed on the main body 221 to expose the second connection pads 222, and may be an oxide layer, a nitride layer, etc. Optionally, the passivation layer 223 may be a double layer of an oxide layer and a nitride layer. The second semiconductor chip 220 has an active surface and an inactive surface, and the second connection pads 222 are disposed on the active surface, and the inactive surface is the back surface opposite to the active surface. In some cases, connection pads may also be disposed on the back surface so that both surfaces may be active surfaces. As an example, when the passivation layer 223 is disposed on the active surface of the second semiconductor chip 220, the positional relationship of the active surface of the second semiconductor chip 220 is determined based on the lowermost surface of the passivation layer 223.

[0109] The second encapsulant 230 covers a part of the second semiconductor chip 220. The second encapsulant 230 may include an insulating material. The insulating material may be a non-photosensitive dielectric. More specifically, the insulating material may be a non-photosensitive dielectric including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin having a reinforcing material such as an inorganic filler immersed in a thermosetting resin or a thermoplastic resin (specifically, ABF or a non-photosensitive dielectric such as an epoxy molding compound (EMC)). Optionally, a material in which an inorganic filler and / or a core material such as glass fiber is immersed in a thermosetting resin or a thermoplastic resin may also be used as the insulating material. Accordingly, voids or undulations can be prevented, and warpage can be more easily controlled. As needed, PIE may be used as the insulating material.

[0110] The second connection structure 240 may redistribute the second connection pads 222 of the second semiconductor chip 220. Dozens to hundreds of second connection pads 222 having various functions may be redistributed through the second connection structure 240 and may be physically and / or electrically connected through the second electrical connection metal members 270 according to their functions. The second connection structure 240 includes: a second insulating layer 241; a second redistribution layer 242 provided on the bottom surface of the second insulating layer 241; and second connection vias 243 penetrating the second insulating layer 241 and connected to the second redistribution layer 242. The second insulating layer 241, the second redistribution layer 242, and the second connection vias 243 may include more layers or fewer layers than the number of layers shown in the drawings. For example, the number of layers may vary according to the design.

[0111] The material of the second insulating layer 241 may be an insulating material such as a photosensitive dielectric (PID). In this case, fine pitches can be introduced through photo vias, which is advantageous in terms of fine circuits and high-density designs, and allows dozens to millions of second connection pads 222 of the second semiconductor chip 220 to be effectively redistributed. The boundaries between the second insulating layers 241 may be distinct, or may not be easily distinct.

[0112] The second redistribution layer 242 can redistribute the second connection pads 222 of the second semiconductor chip 220 to electrically connect the second connection pads 222 to the second electrical connection metal parts 270. The material of the second redistribution layer 242 can also be a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The second redistribution layer 242 can also perform various functions according to the design. For example, the second redistribution layer 242 can include a ground (GND) pattern, a power (PWR) pattern, a signal (S') pattern, etc. The ground (GND) pattern and the power (PWR) pattern can be the same as each other. The second redistribution layer 242 can include various types of via pads, electrical connection metal pads, etc. The second redistribution layer 242 can be formed by a plating process and can include a seed layer and a plating layer.

[0113] The second connection vias 243 electrically connect the second redistribution layers 242 provided on different layers to each other. In addition, the second connection vias 243 electrically connect the second connection pads 222 of the second semiconductor chip 220 to the second redistribution layer 242. When the second semiconductor chip 220 is a die, the second connection vias 243 can be in physical contact with the second connection pads 222. The material of the second connection vias 243 can also be a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The second connection vias 243 can include vias for signals, vias for power, vias for ground, etc., and the vias for power and the vias for ground can be the same as each other. The second connection vias 243 can also be filled-type vias filled with a metal material or conformal-type vias formed along the wall surface of the via holes. In addition, the second connection vias 243 can have a tapered shape that tapers in the direction from the second connection structure 240 to the second semiconductor chip 220. The second connection vias 243 can also be formed by a plating process and can include a seed layer and a plating layer.

[0114] The second passivation layer 250 may be additionally configured to protect the second connection structure 240 from external physical and chemical damage, etc. The second passivation layer 250 may include a thermosetting resin. For example, the second passivation layer 250 may be ABF, but is not limited thereto. The second passivation layer 250 has openings that expose at least a portion of the lowermost second redistribution layer 242 of the second redistribution layer 242. There may be dozens to hundreds of thousands of openings, and the second passivation layer 250 may be provided with a greater or lesser number of openings. Each of the openings may include a plurality of holes. As needed, surface-mounted components such as capacitors may be disposed in the openings on the bottom surface of the second passivation layer 250 to electrically connect the surface-mounted components to the second redistribution layer 242. Thus, the surface-mounted components may be electrically connected to the second semiconductor chip 220.

[0115] The second under-bump metal 260 may also be additionally configured to improve the connection reliability of the second electrical connection metal 270 and improve the board-level reliability of the second semiconductor package 200A. There may be dozens to millions of second under-bump metals 260, and a greater or lesser number of second under-bump metals 260 may be provided. Each second under-bump metal 260 may be disposed in the opening of the second passivation layer 250 to be electrically connected to the exposed lowermost second redistribution layer 242. The second under-bump metal 260 may be formed of a metal by a known metallization method, but is not limited thereto.

[0116] The second electrical connection metal 270 is also additionally configured to physically connect and / or electrically connect the second semiconductor package 200A to the above-described first semiconductor package 100 (100A to 100D). The second electrical connection metal 270 may be disposed on the lower side of the second passivation layer 250 and may be electrically connected to the second under-bump metal 260. Each second electrical connection metal 270 may include a low melting point metal such as tin (Sn) or an Sn-containing alloy. More specifically, each second electrical connection metal 270 may be formed using solder or the like, but is merely an example, and its material is not limited thereto.

[0117] The second electrical connection metal member 270 may be a pad, a solder ball, a pin, etc. The second electrical connection metal member 270 may be formed as a multi-layer structure or a single-layer structure. When the second electrical connection metal member 270 is formed as a multi-layer structure, the second electrical connection metal member 270 may include copper (Cu) pillars and solder. When the second electrical connection metal member 270 is formed as a single-layer structure, the second electrical connection metal member 270 may include tin-silver solder or copper (Cu). However, these are only examples, and the structure and material of the second electrical connection metal member 270 are not limited thereto. The number, pitch, arrangement form, etc. of the second electrical connection metal members 270 are not restricted and can be fully modified by those skilled in the art according to the design. For example, dozens to tens of thousands of second electrical connection metal members 270 may be provided according to the number of the second connection pads 222, and more or fewer second electrical connection metal members 270 may be provided.

[0118] At least one of the second electrical connection metal members 270 is disposed in the fan-out region. The term "fan-out region" refers to a region other than the region where the second semiconductor chip 220 is disposed. Compared with a fan-in type package, a fan-out type package may have improved reliability, may allow for the implementation of multiple input / output (I / O) terminals, and may facilitate three-dimensional (3D) interconnection. In addition, compared with a ball grid array (BGA) package, a land grid array (LGA) package, etc., a fan-out type package can be manufactured to have a small thickness and may have an advantage in terms of price competitiveness.

[0119] Figure 16 is a schematic cross-sectional view showing another example of the second semiconductor package applied to Figure 9 the stacked package (PoP) in

[0120] Referring to Figure 16 , the second semiconductor package 200B according to an exemplary embodiment includes a second connection structure 240 provided in the form of an organic interposer. In this case, the second semiconductor chip 220 may be disposed on the second connection structure 240 using surface mount technology (SMT). For example, metal bumps 220P formed by plating a metal such as copper (Cu) may be disposed on the second connection pads 222 of the second semiconductor chip 220. The metal bumps 220P may be connected to pad patterns protruding from the surface of the second redistribution layer 242 of the second connection structure 240 through a third electrical connection metal member 220B such as solder paste. For example, the second semiconductor chip 220 may be physically separated from the second connection structure 240. In addition, underfill resin 220S fills the space between the second semiconductor chip 220 and the second connection structure 240 to embed the third electrical connection metal member 220B, etc., and more firmly fix the second semiconductor chip 220.

[0121] The second connection structure 240 can redistribute the second connection pads 222 of the second semiconductor chip 220. Dozens to hundreds of second connection pads 222 with various functions can be redistributed through the second connection structure 240 and can be physically and / or electrically connected according to their functions through the second electrical connection metal parts 270. The second connection structure 240 includes: a second insulating layer 241; a second redistribution layer 242 disposed on the upper surface of the second insulating layer 241; and second connection vias 243 penetrating the second insulating layer 241 and connected to the second redistribution layer 242. The second insulating layer 241, the second redistribution layer 242, and the second connection vias 243 may include more layers or fewer layers than the number of layers shown in the drawings. For example, the number of layers may vary according to the design.

[0122] The material of the second insulating layer 241 may be an insulating material such as photosensitive dielectric (PID). In this case, fine pitch can be introduced through photo vias, which is advantageous for fine circuits and high-density designs, and allows dozens to millions of second connection pads 222 of the second semiconductor chip 220 to be effectively redistributed. The boundaries between the second insulating layers 241 may be distinct, or may not be easily distinct.

[0123] The second redistribution layer 242 can redistribute the second connection pads 222 of the second semiconductor chip 220 to electrically connect the second connection pads 222 to the second electrical connection metal parts 270. The material of the second redistribution layer 242 may also be a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys. The second redistribution layer 242 can also perform various functions according to the design. For example, the second redistribution layer 242 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S') pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same as each other. The second redistribution layer 242 may include various types of via pads, electrical connection metal pads, etc. The second redistribution layer 242 can be formed by a plating process and may include a seed layer and a plating layer.

[0124] The second connection via 243 electrically connects the second redistribution layers 242 provided on different layers to each other. In addition, the second connection via 243 electrically connects the second connection pads 222 of the second semiconductor chip 220 to the second redistribution layer 242. When the second semiconductor chip 220 is a die, the second connection via 243 may physically contact the second connection pads 222. The material of the second connection via 243 may also be a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second connection via 243 may include vias for signals, vias for power, vias for ground, etc., and the vias for power and the vias for ground may be the same as each other. The second connection via 243 may also be a filled via filled with a metal material or a conformal via in which a metal material is formed along the wall surface of the via hole. In addition, the second connection via 243 may have a tapered shape that tapers in the direction from the second semiconductor chip 220 to the second connection structure 240. The second connection via 243 may also be formed by a plating process and may include a seed layer and a plating layer.

[0125] The second under-bump metal 260 may be additionally configured to improve the connection reliability of the second electrical connection metal 270 and improve the board-level reliability of the second semiconductor package 200B. There may be dozens to millions of second under-bump metals 260, and more or fewer second under-bump metals 260 may be provided. Each second under-bump metal 260 may be embedded in the lowermost second insulating layer 241. Thus, a passivation layer for covering the lowermost second redistribution layer 242 may be omitted. The second under-bump metal 260 may be formed using a metal by a known metallization method, but is not limited thereto.

[0126] Other descriptions are substantially the same as the detailed description of the second semiconductor package 200A according to another exemplary embodiment and will be omitted here.

[0127] Figure 17 is a schematic cross-sectional view showing an example of a package connection system.

[0128] Refer to Figure 17, the package connection system 500A according to the exemplary embodiment includes: a printed circuit board (PCB) 400 having a first surface and a second surface opposite the first surface; a stacked package (PoP) 300A disposed on the first surface of the PCB 400 and having the function of an application processor chip; a memory package 310 disposed on the second surface of the PCB 400 and having a storage function; a power management package 320 disposed on the first surface of the PCB 400 and having a power management function; and a first passive component 330 and a second passive component 340 disposed on the first surface and / or the second surface of the PCB 400. The memory package 310 is disposed on the second surface of the PCB 400 in such a manner that at least a part of the memory package 310 overlaps with the stacked package (PoP) 300A when viewed from above (or in a plan view). The power management package 320 is disposed on the first surface of the PCB 400 in parallel with the stacked package (PoP) 300A. Due to this layout, an improvement in signal integrity between the stacked package (PoP) 300A and the memory package 310 can be ensured.

[0129] The stacked package (PoP) 300A has a structure in which a first semiconductor package 100A and a second semiconductor package 200A are stacked, but is not limited thereto. The first semiconductor packages 100B, 100C, and 100D and the second semiconductor package 200B can be stacked in various combinations and applied to the package connection system 500A.

[0130] The memory package 310 can be an embedded multi-chip package (eMCP) including a dynamic random access memory (DRAM), a flash memory, and a controller CTR. The power management package 320 can be a wafer-level package (WLP) or a panel-level package (PLP) including a power management integrated circuit (PMIC). Each of the packages 310 and 320 can be a fan-in type package or a fan-out type package.

[0131] The first passive component 330 and the second passive component 340 can independently be a capacitor, an inductor, a magnetic bead, etc. The sizes, thicknesses, etc. of the first passive component 330 and the second passive component 340 can be the same or different. Examples of the capacitor can be a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), etc., but are not limited thereto. Examples of the inductor can be a power inductor, etc., but are not limited thereto.

[0132] Figure 18 is a schematic cross-sectional view showing another example of the package connection system.

[0133] Referring to Figure 18, according to another exemplary embodiment, the package connection system 500B includes a memory package 310 disposed on a first surface of a printed circuit board (PCB) 400 in parallel with a stacked package (PoP) 300A. A power management package 320 is disposed on a second surface of the PCB 400 in such a manner that at least a portion of the power management package 320 overlaps with the stacked package (PoP) 300A and / or the memory package 310 when viewed from above (or in a plan view). Due to this layout, the package connection system 500B can be applied to high-end systems.

[0134] Other descriptions are substantially the same as the detailed description of the package connection system 500A according to another exemplary embodiment and will be omitted herein.

[0135] As described above, a specific unit of an application processor chip can be separated into a semiconductor chip, and the performance of the specific unit can be enhanced to distinguish the functions of the group.

[0136] In the present disclosure, terms such as "lower side", "lower part", "lower surface", etc. with respect to the cross-section of the drawings have been used to indicate the direction towards the mounting surface of the electronic component package, and terms such as "upper side", "upper part", "upper surface", etc. have been used to indicate the direction opposite to the direction indicated by terms such as "lower side", "lower part", "lower surface", etc. However, these directions are only defined for convenience of explanation, and the claims are not particularly limited by the directions defined as above.

[0137] The meaning of "connecting" a component to another component in the specification includes indirect connection through an adhesive layer and direct connection between two components. In addition, "electrically connected" means including physical connection and physical disconnection. It can be understood that when an element is referred to as "first" and "second", the element is not limited thereby. These terms can be used only for the purpose of distinguishing an element from other elements and may not limit the order or importance of the element. In some cases, without departing from the scope of the claims set forth herein, the first element may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0138] The term "exemplary embodiment" used herein does not always refer to the same exemplary embodiment and is provided to emphasize specific features or characteristics different from those of another exemplary embodiment. However, the exemplary embodiments provided herein are considered capable of being implemented by combining with each other in whole or in part. For example, unless a contrary or contradictory description is provided therein, an element described in a specific exemplary embodiment can be understood as being related to the description of another exemplary embodiment even if it is not described in another exemplary embodiment.

[0139] The terms used herein are for the purpose of describing exemplary embodiments only and are not intended to limit the present disclosure. In this context, unless otherwise required for interpretation, the singular forms also include the plural forms based on a specific context.

[0140] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. A stacked package, comprising: a first semiconductor package including a first semiconductor chip; and a second semiconductor package disposed on the first semiconductor package, including a second semiconductor chip electrically connected to the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip includes one or more units, the number of the units of the first semiconductor chip is greater than the number of the units of the second semiconductor chip, the one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement the functions of an application processor chip, wherein the first semiconductor chip includes at least one of a central processing unit, a graphics processing unit, and a digital signal processing unit, and the second semiconductor chip includes at least one of an image signal processing unit and a neural processing unit.

2. The stacked package according to claim 1, wherein, when the second semiconductor chip includes one of the image signal processing unit and the neural processing unit, the first semiconductor chip further includes the other of the image signal processing unit and the neural processing unit not included in the second semiconductor chip.

3. The stacked package according to claim 1, wherein, the first semiconductor chip further includes a memory unit, and at least one of the units of the second semiconductor chip is electrically connected to the memory unit of the first semiconductor chip.

4. The stacked package according to claim 1, wherein, in a plan view, the area of the first semiconductor chip is greater than the area of the second semiconductor chip.

5. The stacked package according to claim 1, wherein, the first semiconductor package includes: a frame having a through portion and including one or more wiring layers; the first semiconductor chip disposed in the through portion and having a first connection pad; a first encapsulant covering at least a portion of each of the frame and the first semiconductor chip; and a first connection structure disposed on the frame and the first semiconductor chip, including one or more first redistribution layers electrically connected to the first connection pad, and the one or more wiring layers of the frame are electrically connected to the first connection pad through the one or more first redistribution layers of the first connection structure.

6. The stacked package according to claim 5, wherein, the first semiconductor package further includes: a backside wiring layer disposed on a side of the first encapsulant opposite to the side where the first connection structure is disposed; and a backside via penetrating the first encapsulant and electrically connecting the backside wiring layer and the one or more wiring layers of the frame to each other, the second semiconductor package is disposed on the backside wiring layer and is electrically connected to the backside wiring layer through an electrically connecting metal member, and the first semiconductor chip is disposed in a face-down direction such that the surface having the first connection pad faces the first connection structure.

7. The stacked package according to claim 5, wherein, the first semiconductor package further includes: a backside wiring layer disposed on a side of the first encapsulant opposite to the side provided with the first connection structure; backside vias penetrating the first encapsulant and electrically connecting the backside wiring layer and the one or more wiring layers of the frame to each other, the second semiconductor package is disposed on the first connection structure and electrically connected to the one or more first redistribution layers of the first connection structure through an electrically connecting metal member, and the first semiconductor chip is disposed in a face-up direction such that the surface provided with the first connection pads faces the first connection structure.

8. The stacked package according to claim 5, wherein, the frame includes: a first insulating layer; a first wiring layer embedded in the first insulating layer while being in contact with the first connection structure; a second wiring layer disposed on a side of the first insulating layer opposite to the side in which the first wiring layer is embedded; a second insulating layer disposed on a side of the first insulating layer opposite to the side in which the first wiring layer is embedded, covering at least a portion of the second wiring layer; and a third wiring layer disposed on a side of the second insulating layer opposite to the side in which the second wiring layer is embedded, and a surface of the first insulating layer provided to be in contact with the first connection structure has a step with respect to a surface of the first wiring layer provided to be in contact with the first connection structure.

9. The stacked package according to claim 5, wherein, the frame includes: a first insulating layer; a first wiring layer and a second wiring layer respectively disposed on two surfaces of the first insulating layer; a second insulating layer and a third insulating layer respectively disposed on two surfaces of the first insulating layer, covering at least a portion of the first wiring layer and at least a portion of the second wiring layer; a third wiring layer disposed on a side of the second insulating layer opposite to the side in which the first wiring layer is embedded; and a fourth wiring layer disposed on a side of the third insulating layer opposite to the side in which the second wiring layer is embedded, and the thickness of the first insulating layer is greater than the thickness of each of the second insulating layer and the third insulating layer.

10. The stacked package according to claim 1, wherein, the second semiconductor package includes: a second connection structure including one or more second redistribution layers; a second semiconductor chip disposed on the second connection structure and electrically connected to the one or more second redistribution layers; and a second encapsulant disposed on the second connection structure, covering at least a portion of the second semiconductor chip.

11. A package connection system, comprising: a printed circuit board having a first surface and a second surface opposite to the first surface; a stacked package disposed on the first surface of the printed circuit board, having the function of an application processor chip; a memory package disposed on one of the first surface and the second surface of the printed circuit board, having a memory function; and A power management package, having a power management function, and is disposed on the other of the first surface and the second surface of the printed circuit board, wherein the stacked package includes a first semiconductor package and a second semiconductor package, the first semiconductor package includes a first semiconductor chip, and the second semiconductor package is disposed on the first semiconductor package and includes a second semiconductor chip electrically connected to the first semiconductor chip, each of the first semiconductor chip and the second semiconductor chip includes one or more units, the number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip, and the one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement the functions of an application processor chip.

12. The package connection system according to claim 11, wherein, the memory package is disposed on the second surface of the printed circuit board such that at least a part of the memory package overlaps with the stacked package in a plan view, and the power management package is disposed on the first surface of the printed circuit board in parallel with the stacked package.

13. The package connection system according to claim 11, wherein, the memory package is disposed on the first surface of the printed circuit board in parallel with the stacked package, and the power management package is disposed on the second surface of the printed circuit board to overlap at least a part of at least one of the stacked package and the memory package in a plan view.

14. The package connection system according to claim 11, wherein, the memory package includes a dynamic random access memory, a flash memory, and a controller, and the power management package includes a power management integrated circuit.

15. The package connection system according to claim 11, the package connection system further includes: one or more passive components, disposed on at least one of the first surface and the second surface of the printed circuit board.

16. The package connection system according to claim 11, wherein, in a plan view, the stacked package overlaps with one of the memory package and the power management package.

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