Data copy method, direct memory access controller and computer system

Abstract

The present invention provides a data copy method, a direct memory access controller and a computer system. The data copy method of an embodiment of the present invention comprises a DMA controller reading the target data from a storage space corresponding to a source physical address of the target data through an ACP; the storage space corresponding to the source physical address comprises a first buffer; the DMA controller stores the target data to a storage space corresponding to a destination physical address of the target data through the ACP; the storage space corresponding to the destination physical address comprises a second buffer. The embodiment of the present invention can reduce the CPU occupancy rate.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a data copying method, a direct memory access controller and a computer system. Background Art

[0002] The computer system allocates a buffer for each running process. Each process accesses its own buffer during operation and reads or writes data from its own buffer.

[0003] However, the same data may be accessed by different processes. In this case, the computer system needs to copy the data stored in the buffer of one process to the buffer of another process, so that the other process can obtain the data by accessing its own buffer. Specifically, the central processing unit (CPU) performs the above copy operation.

[0004] Since copying data between the buffers of any two processes requires the participation of the CPU, as the computer system implements more and more functions and the interactions between processes become more and more frequent, the above-mentioned copying of data causes a high CPU occupancy rate, thereby affecting the working performance of the computer system. Summary of the invention

[0005] The invention provides a data copying method, a direct memory access controller and a computer system to improve the working performance of the computer.

[0006] In a first aspect, an embodiment of the present invention provides a data copy method, comprising:

[0007] A direct memory access DMA controller reads the target data from a storage space corresponding to a source physical address of the target data through an acceleration consistency interface ACP; the storage space corresponding to the source physical address includes a first buffer;

[0008] The DMA controller stores the target data in a storage space corresponding to a destination physical address of the target data through the ACP; the storage space corresponding to the destination physical address includes a second buffer zone.

[0009] According to the first aspect, in a first possible implementation manner of the first aspect, the DMA controller reads the target data from a storage space corresponding to a source physical address of the target data through an ACP, including:

[0010] The DMA controller sends the source virtual address of the target data to a memory management unit MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to the cache controller through the ACP;

[0011] The DMA controller receives the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the storage space of the source physical address read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the input / output IO device or storage device corresponding to the first buffer.

[0012] According to the first possible implementation manner of the first aspect, in a second possible implementation manner, the DMA controller stores the target data in a storage space corresponding to a destination physical address of the target data through the ACP, including:

[0013] The DMA controller sends the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the storage space of the destination physical address in the second buffer, or to write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second cache area.

[0014] According to the second possible implementation manner of the first aspect, in a third possible implementation manner, before the DMA controller sends the source virtual address of the target data to the MMU, the method further includes:

[0015] The DMA controller receives configuration information of a transmission channel sent by a central processing unit (CPU); the configuration information includes: the source virtual address and the destination virtual address; the transmission channel is a data transmission channel in the DMA controller corresponding to the target data;

[0016] The DMA controller configures the source address of the transmission channel as the source virtual address;

[0017] The DMA controller configures the destination address of the transmission channel as the destination virtual address.

[0018] In a second aspect, an embodiment of the present invention provides a direct memory access DMA controller, comprising:

[0019] A reading module, configured to read the target data from a storage space corresponding to a source physical address of the target data through an acceleration consistency interface ACP; the storage space corresponding to the source physical address includes a first buffer;

[0020] A writing module is used to store the target data into a storage space corresponding to a destination physical address of the target data through the ACP; the storage space corresponding to the destination physical address includes a second buffer zone.

[0021] According to the second aspect, in a first possible implementation manner of the second aspect, the DMA controller further includes:

[0022] A sending module, configured to send the source virtual address of the target data to a memory management unit MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to a cache controller through the ACP;

[0023] A receiving module, used for receiving the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the storage space of the source physical address read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the input / output IO device or storage device corresponding to the first buffer.

[0024] According to the first possible implementation method of the second aspect, in the second possible implementation method, the sending module is also used to send the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the storage space of the destination physical address in the second buffer, or, to write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second cache area.

[0025] According to the second possible implementation manner of the second aspect, in a third possible implementation manner, the receiving module is further used to receive configuration information of a transmission channel sent by a central processing unit CPU before the sending module sends the source virtual address of the target data to the MMU; the configuration information includes: the source virtual address and the destination virtual address; the transmission channel is a data transmission channel in the DMA controller corresponding to the target data;

[0026] The DMA controller further includes:

[0027] A configuration module is used to configure the source address of the transmission channel as the source virtual address, and configure the destination address of the transmission channel as the destination virtual address.

[0028] In the third aspect, an embodiment of the present invention also provides a computer system, comprising: a direct memory access DMA controller, an acceleration consistency interface ACP and a buffer memory; the DMA controller is connected to the buffer memory through the ACP; the buffer memory includes a first buffer zone and a second buffer zone; the DMA controller is any one of the DMA controllers described above.

[0029] In the data copy method provided by the embodiment of the present invention, a DMA controller reads the target data from the storage space corresponding to the source physical address of the target data in the first buffer through the ACP, and then stores the target data in the storage space corresponding to the target physical address of the target data in the second buffer through the ACP, thereby completing the copying of data between the first buffer and the second buffer without the need for the CPU to execute the data copy, thereby reducing the CPU occupancy rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A schematic diagram of a computer system to which a data copying method of the present invention is applied;

[0032] Figure 2 This is a flow chart of a data copy method according to a first embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a computer system to which another data copying method of the present invention is applied;

[0034] Figure 4 A flowchart of a data copy method provided in Embodiment 2 of the present invention;

[0035] Figure 5 A flowchart of a data copy method provided in Embodiment 3 of the present invention;

[0036] Figure 6 A schematic diagram of the structure of a DMA controller provided in Embodiment 4 of the present invention;

[0037] Figure 7 A schematic diagram of the structure of a computer system provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Figure 1 FIG. 1 is a schematic diagram of a computer system to which a data copying method of the present invention is applied. Figure 1 As shown, the computer system 100 includes a central processing unit (CPU) 101, a direct memory access (DMA) controller 102, an input output (IO) device 103 and a storage device 104. The storage device 104 may include a dual data rate synchronous dynamic random access memory (DDR) 105, a random access memory (RAM) 106, etc. The CPU 101 includes a kernel 107 and a cache memory (CACHE) 108. The cache memory 108 may include at least two buffers 109. The DMA controller 102 may communicate with the buffers 109 in the cache memory 108 of the CPU. The CPU 101 may access the above storage device 104 and IO device 103 through a bus 110. The DMA controller 102 may communicate with the buffer 109 in the cache memory 108 via an accelerator coherency port (ACP) 111 . Figure 2 FIG. 1 is a flow chart of a data copy method according to Embodiment 1 of the present invention. Figure 2 As shown, the data copy method may include:

[0040] S201. A DMA controller reads target data from a storage space corresponding to a source physical address of the target data through an ACP; the storage space corresponding to the source physical address includes a first buffer zone.

[0041] S202. The DMA controller stores the target data into a storage space corresponding to a destination physical address of the target data through the ACP; the storage space corresponding to the destination physical address includes a second buffer zone.

[0042] Specifically, the first buffer may be a buffer corresponding to the first process; the second buffer may be a buffer corresponding to the second process. The source physical address of the target data may be an address storing the target data in the storage space corresponding to the source physical address. The storage space corresponding to the source physical address includes the first buffer, and the source physical address of the target data may be an address storing the target data in the first buffer. The destination physical address of the target data may be an address to be stored in the storage space corresponding to the destination physical address. The storage space corresponding to the destination physical address may include the second buffer, and the destination physical address of the target data may be an address to be stored in the second buffer.

[0043] The target data may include at least one data. If the target data includes one data, the source physical address of the target data and the destination physical address of the target data may each include an address. If the target data includes at least two data, the source physical address of the target data may include at least two addresses, which are storage addresses corresponding to each of the at least two data. The physical address of the target data may also include at least two addresses, which are addresses to be stored corresponding to each of the at least two data.

[0044] For example, if the data in the buffer of process 1 needs to be accessed by process 2, then the data in the buffer of process 1 needs to be copied to the buffer of process 2. The data to be copied in the buffer of process 1 is the target data, and the source physical address of the target data can be the address corresponding to the storage space storing the target data in the buffer of process 1. The destination physical address of the target data can be the address corresponding to the storage space corresponding to the target data in the buffer of process 2.

[0045] If a piece of data in the buffer of process 1 needs to be copied to the buffer of process 2, then the piece of data in the buffer of process 1 is the target data. If the target data is stored in the storage space corresponding to address 0000 in the buffer of process 1, then the source physical address of the target data is address 0000. If the data is copied to the storage space corresponding to address 2000 in the buffer of process 2, then the destination physical address of the target data is address 2000.

[0046] If there are 17 data in the buffer of process 1 that need to be copied to the buffer of process 2, then the 17 data in the buffer of process 1 are the target data. If the 17 target data are stored in the storage space corresponding to addresses 0000 to 0011 in the buffer of process 1, then the source physical address of the target data is address 0000 to 0011. If the 17 data are copied to the storage space corresponding to addresses 2000 to 2011 in the buffer of process 2, then the destination physical address of the target data is address 2000 to 2011.

[0047] Since the codes of each process running in the computer system are known before data copying, the addresses of the buffers corresponding to each process are known when data is copied between the buffers corresponding to each process. The source physical address of the target data and the destination physical address of the target data can be determined based on the known addresses of the buffers corresponding to each process.

[0048] In the above S201, the DMA controller reads the target data from the storage space corresponding to the source physical address of the target data through the ACP. For example, it can be: the DMA controller sends a read data request message including the source physical address of the target data to the cache controller through the ACP, so that the cache controller reads the target data from the storage space corresponding to the source physical address and returns the target data to the DMA controller through the ACP.

[0049] The above-mentioned S202, in which the DMA controller stores the target data in the storage space corresponding to the destination physical address of the target data through the ACP, may be: the DMA controller sends a write data request message including the target data and the destination physical address of the target data to the cache controller through the ACP, so that the cache controller stores the target data in the storage space corresponding to the destination physical address of the target data.

[0050] In the data copy method provided by the embodiment of the present invention, a DMA controller reads the target data from the storage space corresponding to the source physical address of the target data in the first buffer through the ACP, and then stores the target data in the storage space corresponding to the target physical address of the target data in the second buffer through the ACP, thereby completing the copying of data between the first buffer and the second buffer without the need for the CPU to execute the data copy, thereby reducing the CPU occupancy rate.

[0051] Embodiment 2

[0052] Embodiment 2 of the present invention also provides a data copy method. Figure 3 FIG. 1 is a schematic diagram of a computer system to which another data copying method of the present invention is applied. Figure 3The computer system 100 shown in the above Figure 1 Based on the DMA controller 102, it can also include a memory management unit (Memory Management Unit, MMU for short) 301. The DMA controller 102 can be connected to the MMU 301, and the MMU 301 can communicate with the buffer 109 in the cache memory 108 through the ACP 111. The CACHE 108 can also include a cache controller 302 to control the reading and writing of the buffer 109 in the CACHE 108.

[0053] Figure 4 This is a flow chart of a data copy method provided in Embodiment 2 of the present invention. Figure 4 As shown, the method is based on the above-mentioned embodiment 1, wherein the DMA controller in S201 reads the target data from the storage space corresponding to the source physical address of the target data through the ACP, and may include:

[0054] S401, the DMA controller sends the source virtual address of the target data to the MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to the cache controller through the ACP.

[0055] S402, the DMA controller receives the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the storage space of the source physical address read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the IO device or storage device corresponding to the first buffer.

[0056] Specifically, after the cache controller receives the source physical address of the target data sent by the DMA controller through the MMU and ACP in sequence, it will determine whether the source physical address hits in the first buffer. The cache controller determines whether the source physical address hits in the first buffer by determining whether there is storage space for the source physical address in the first buffer; if there is storage space for the source physical address in the first buffer, it is a hit, otherwise, it is a miss. If the source physical address hits in the first buffer, the cache controller reads the target data from the storage space of the source physical address in the first buffer. If the source physical address misses in the first buffer, the cache controller reads the target data from the storage space of the source physical address in the IO device or storage device corresponding to the first buffer.

[0057] It should be noted that before the MMU sends the source physical address to the cache controller through the ACP, it is also necessary to determine whether the cache attribute information of the source physical address is a cacheable attribute (cacheable) or a non-cacheable attribute (non-cacheable) based on the source physical address. If the cache attribute information of the source physical address is a cacheable attribute, the MMU sends the source physical address to the cache controller through the ACP. If the cache attribute information of the source physical address is a non-cacheable attribute, the MMU can directly send the source physical address to the IO device or storage device corresponding to the first buffer.

[0058] Optionally, in the above S202, the DMA controller storing the target data into a storage space corresponding to a destination physical address of the target data through the ACP may include:

[0059] S403, the DMA controller sends the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the storage space of the destination physical address in the second buffer, or write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second cache area.

[0060] Specifically, after receiving the target physical address sent by the DMA controller through the MMU and ACP in sequence, the cache controller will determine whether the target physical address hits in the second buffer. The cache controller determines whether the target physical address hits in the second buffer by determining whether there is storage space for the target physical address in the second buffer; if there is storage space for the target physical address in the second buffer, it is a hit; otherwise, it is a miss. If the target physical address hits in the second buffer, the cache controller may write the target data into the storage space of the target physical address in the second buffer; if the target physical address misses in the second buffer, the cache controller may write the target data into the storage space of the target physical address in the IO device or storage device corresponding to the second cache area.

[0061] It should be noted that before the MMU sends the destination physical address to the cache controller through the ACP, it is also necessary to determine whether the cache attribute information of the destination physical address is a cacheable attribute or a non-cacheable attribute based on the destination physical address. If the cache attribute information of the destination physical address is a cacheable attribute, the MMU sends the target data and the destination physical address to the cache controller through the ACP. If the cache attribute information of the destination physical address is a non-cacheable attribute, the MMU can directly send the target data and the destination physical address to the IO device or storage device corresponding to the second buffer.

[0062] The cache attribute information of the source physical address and the destination physical address may be configured by a core of a CPU.

[0063] Optionally, the MMU may determine that the physical address corresponding to the source virtual address is the source physical address based on the source virtual address and the correspondence between the source virtual address and the physical address. The MMU may determine that the physical address corresponding to the destination virtual address is the destination physical address based on the destination virtual address and the correspondence between the destination virtual address and the physical address. If the target data includes at least one data, at least one address in the source virtual address may be continuous; at least one address in the source virtual address has a physical address, therefore, the source physical address may also include at least one address, and at least one address of the source physical address may be discontinuous.

[0064] The at least one address in the destination virtual address may also be continuous. At least one address in the destination virtual address has a physical address, so the destination physical address may also include at least one address, and at least one address of the destination physical address may be discontinuous.

[0065] If the target data includes at least one data, the DMA controller can convert at least one continuous address in the source virtual address of the target data into a source physical address including at least one discontinuous address through the MMU; the DMA controller can also convert at least one continuous address in the destination virtual address of the target data into a destination physical address including at least one discontinuous address through the MMU. That is to say, in this embodiment, the DMA controller can realize data copying between storage spaces of discontinuous or fragmented physical addresses through the MMU and ACP in sequence according to the continuous virtual addresses.

[0066] Optionally, before the DMA controller sends the source virtual address of the target data to the MMU in S401, the method may further include:

[0067] S401a, the DMA controller receives the configuration information of the transmission channel sent by the CPU; the configuration information includes the source virtual address and the destination virtual address.

[0068] S401b: The DMA controller configures the source address of the transmission channel as the source virtual address.

[0069] S401c: The DMA controller configures the destination address of the transmission channel as a destination virtual address.

[0070] Specifically, the target data may include at least one data, and each data may have a corresponding source address and a destination address. The source virtual address of the target data may include at least one address, and the destination virtual address of the target data may also include at least one address. In the DMA controller, each data in the target data has a transmission channel, so the transmission channel in the DMA controller corresponding to the target data may include at least one channel. The DMA controller may, for example, configure the source address of each channel in the at least one channel as the source address corresponding to each data in at least one address of the source virtual address according to at least one address of the source virtual address. The DMA controller may, for example, configure the destination address of each channel as the destination address corresponding to each data in at least one address of the destination virtual address according to at least one address of the destination virtual address. The different channels are respectively used to transmit different data in the target data, and different channels in the at least one channel have different source addresses and different destination addresses.

[0071] Optionally, the configuration information may also include the number of transmission data bytes, transmission bit width, burst length, etc. of each channel in the transmission channel.

[0072] The DMA controller also configures the number of transmission bytes, transmission bit width and burst length of each channel in at least one channel of the transmission channel according to the number of transmission data bytes, transmission bit width and burst length of each channel in the transmission channel in the configuration information.

[0073] It should be noted that the process of configuring the channel according to the configuration information sent by the CPU by the DMA controller can be performed when the DMA controller is not started. That is to say, after the DMA controller completes the configuration of the channel according to the parameters in the configuration information sent by the CPU, it is necessary to start the DMA controller so that when each process running in the computer system needs to copy the target data, the CPU sends a work instruction to the DMA controller, so that the DMA controller sends the source virtual address to the MMU, and then sends the converted source physical address to the first buffer through the ACP to read the target data.

[0074] In the data copying method of the second embodiment of the present invention, the DMA controller can realize data copying between discontinuous, i.e., fragmented physical address storage spaces through the MMU and ACP in sequence according to the continuous virtual addresses. At the same time, during the data copying process of the DMA controller, whether reading data or storing data, it needs to pass through the buffer, thereby realizing cache-consistent memory access, without the need for the CPU to frequently execute call instructions, further reducing the CPU occupancy rate, ensuring the performance of the computer system, and reducing power consumption.

[0075] Furthermore, the processes running in the computer system may be running in user mode or kernel mode. If the process that needs to perform data interaction runs in kernel mode, the source address and destination address configured by the CPU for the DMA controller for the process running in kernel mode are both the source physical address and the destination physical address, so that the DMA controller executes data copying through ACP; but if the process that needs to perform data interaction runs in user mode, the source address and destination address configured by the CPU for the transmission channel of the DMA controller for the process running in user mode are both the source virtual address and the destination virtual address. At this time, the DMA controller cannot move or copy the target data according to the source virtual address and the destination virtual address, but needs to send the source virtual address and the destination virtual address to the MMU, which is converted into the source physical address and the destination physical address by the MMU, and then the data is copied through the ACP.

[0076] Embodiment 3

[0077] Embodiment 3 of the present invention also provides a data copy method. Figure 5 This is a flow chart of a data copy method provided in Embodiment 3 of the present invention. Figure 5 As shown, the data copy method may include:

[0078] S501. A DMA controller receives configuration information of a transmission channel sent by a CPU core, where the configuration information includes a source virtual address of target data and a destination virtual address of the target data. The transmission channel is a data transmission channel in the DMA controller corresponding to the target data.

[0079] S502: The DMA controller configures the source address of the transmission channel as the source virtual address, and configures the destination address of the transmission channel as the destination virtual address.

[0080] The configuration information may also include the number of transmitted data bytes, the bit width of the transmitted data, and the burst length of the transmission channel. Therefore, the DMA controller also configures the number of transmitted data bytes, the bit width of the transmitted data, and the burst length of the transmission channel to the number of transmitted data bytes, the bit width of the transmitted data, and the burst length in the configuration information.

[0081] It should be noted that, after the DMA controller completes the configuration of the transmission channel according to the above S502, it starts to receive the data copy instruction sent by the CPU.

[0082] S503 . The DMA controller determines the source virtual address according to the source address of the transmission channel, and sends the source virtual address to the MMU.

[0083] S504 , the MMU converts the received source virtual address into a source physical address, and determines that the cache attribute of the storage space of the source physical address is a cacheable attribute, and then the MMU sends the source physical address to the cache controller of the CPU through the ACP.

[0084] S505: The cache controller determines whether the source physical address hits in the first buffer.

[0085] If yes, continue to execute S406; if no, execute S407.

[0086] S506: If the cache controller determines that the source physical address hits the first buffer, the cache controller reads the target data from the storage space of the source physical address in the first buffer.

[0087] S507: If the cache controller determines that the source physical address does not hit in the first buffer, the cache controller reads the target data from the storage space of the source physical address in the IO device or memory corresponding to the first buffer.

[0088] S508 , the cache controller transmits the target data to the DMA controller via the ACP and the MMU in sequence.

[0089] S509 , the DMA controller determines the destination virtual address according to the destination address of the transmission channel, and sends the target data and the destination virtual address to the MMU.

[0090] S510 , the MMU converts the destination virtual address into a destination physical address, and determines that the destination physical address is cacheable, and then the MMU sends the destination physical address and the target data to the cache controller through the ACP.

[0091] S511: The cache controller determines whether the source physical address hits in the second buffer.

[0092] If yes, continue to execute S512; if no, execute S513.

[0093] S512: If the cache controller determines that the source physical address hits the second buffer, the cache controller writes the target data into the storage space of the destination physical address in the second buffer.

[0094] S513: If the cache controller determines that the source physical address does not hit in the second buffer, the cache controller writes the target data into the storage space of the destination physical address in the IO device or memory corresponding to the second buffer.

[0095] In the data copy method provided by an embodiment of the present invention, a DMA controller in a computer system reads the target data from a storage space corresponding to a source physical address of the target data in a first buffer through an ACP, and then stores the target data in a storage space corresponding to a target physical address of the target data in a second buffer through an ACP, thereby completing the copying of data between the first buffer and the second buffer without the need for the CPU to call a corresponding function to copy the data, thereby reducing the CPU occupancy rate and improving the working performance of the computer system.

[0096] Embodiment 4

[0097] Embodiment 4 of the present invention further provides a DMA controller. Figure 6 This is a schematic diagram of the structure of the DMA controller provided in the fourth embodiment of the present invention. Figure 6 As shown, the DMA controller 600 may include:

[0098] The reading module 601 is used to read the target data from the storage space corresponding to the source physical address of the target data through the ACP; the storage space corresponding to the source physical address includes a first buffer zone.

[0099] The writing module 602 is used to store the target data into a storage space corresponding to a destination physical address of the target data through the ACP; the storage space corresponding to the destination physical address includes a second buffer.

[0100] Optionally, the DMA controller 600 further includes:

[0101] The sending module is used to send the source virtual address of the target data to the MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to the cache controller through the ACP.

[0102] A receiving module is used to receive the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the storage space of the source physical address read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the IO device or storage device corresponding to the first buffer.

[0103] Optionally, the sending module is also used to send the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the storage space of the destination physical address in the second buffer, or to write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second cache area.

[0104] Optionally, the receiving module is also used to receive configuration information of the transmission channel sent by the CPU before the sending module sends the source virtual address of the target data to the MMU; the configuration information includes: the source virtual address and the destination virtual address; the transmission channel is the data transmission channel in the DMA controller corresponding to the target data.

[0105] The DMA controller 600 further includes:

[0106] The configuration module is used to configure the source address of the transmission channel as the source virtual address, and configure the destination address of the transmission channel as the destination virtual address.

[0107] The DMA controller provided in the fourth embodiment of the present invention can execute the data copy method of any one of the above embodiments one to three. Its specific implementation process and beneficial effects are similar to those of the above embodiments and will not be repeated here.

[0108] Embodiment 5

[0109] Embodiment 5 of the present invention further provides a computer system. Figure 7 This is a schematic diagram of the structure of a computer system provided in Embodiment 5 of the present invention. Figure 7 As shown, the computer system 700 may include: a DMA controller 701, an ACP 702 and a buffer memory 703; the DMA controller 701 is connected to the buffer memory 703 through the ACP 702; the buffer memory 703 includes a first buffer 704 and a second buffer 705;

[0110] The DMA controller 701 may be the DMA controller of the fourth embodiment, and may be used to execute the data copy method described in any one of the first to third embodiments.

[0111] The DMA controller in the computer system provided in the fifth embodiment of the present invention can execute the data copy method described in any one of the first to third embodiments above. Its implementation process and beneficial effects are similar to those in the first to third embodiments above, and will not be repeated here.

[0112] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data copy method, characterized in that: include: The direct memory access DMA controller reads the target data from the first storage space corresponding to the source physical address in the first buffer through the acceleration consistency interface ACP, wherein the ACP is used to achieve cache consistency; The DMA controller stores the target data in a second storage space corresponding to a destination physical address in a second buffer through the ACP, wherein the first buffer and the second buffer are located in the same processor.

2. The method according to claim 1, characterized in that: The DMA controller reads the target data from a first storage space corresponding to a source physical address through an ACP, including: The DMA controller sends a source virtual address to a memory management unit MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to the cache controller through the ACP; The DMA controller receives the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the first storage space read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the input / output IO device or storage device corresponding to the first buffer.

3. The method according to claim 2, characterized in that The DMA controller stores the target data in a second storage space corresponding to the destination physical address through the ACP, including: The DMA controller sends the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the second storage space in the second buffer, or, to write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second buffer.

4. The method according to claim 3, characterized in that Before the DMA controller sends the source virtual address of the target data to the MMU, the method further includes: The DMA controller receives configuration information of a transmission channel sent by a central processing unit (CPU); the configuration information includes the source virtual address and the destination virtual address; the transmission channel is a data transmission channel in the DMA controller corresponding to the target data; The DMA controller configures the source address of the transmission channel as the source virtual address; The DMA controller configures the destination address of the transmission channel as the destination virtual address.

5. A direct memory access DMA controller, characterized in that: include: A reading module, configured to read target data from a first storage space corresponding to a source physical address in a first buffer through an acceleration consistency interface ACP; A writing module is used to store the target data into a second storage space corresponding to the physical address in a second buffer through the ACP, wherein the first buffer and the second buffer are located in the same processor.

6. The DMA controller according to claim 5, characterized in that: The DMA controller further includes: A sending module, used for sending a source virtual address to a memory management unit MMU, so that the MMU converts the source virtual address into the source physical address, and sends the source physical address to a cache controller through the ACP; A receiving module, used for receiving the target data returned by the cache controller through the ACP and the MMU in sequence; the target data is the data stored in the first storage space read by the cache controller from the first buffer; or the target data is the data stored in the storage space of the source physical address read by the cache controller from the input / output IO device or storage device corresponding to the first buffer.

7. The DMA controller according to claim 6, characterized in that: The sending module is also used to send the target data and the destination virtual address of the target data to the MMU, so that the MMU converts the destination virtual address into the destination physical address, and sends the target data and the destination physical address to the cache controller through the ACP; the target data and the destination physical address are used to enable the cache controller to write the target data into the second storage space in the second buffer, or to write the target data into the storage space of the destination physical address in the IO device or storage device corresponding to the second buffer.

8. The DMA controller according to claim 7, characterized in that: The receiving module is further configured to receive configuration information of a transmission channel sent by a central processing unit (CPU) before the sending module sends the source virtual address of the target data to the MMU; the configuration information includes: the source virtual address and the destination virtual address; the transmission channel is a data transmission channel in the DMA controller corresponding to the target data; The DMA controller further includes: A configuration module is used to configure the source address of the transmission channel as the source virtual address, and configure the destination address of the transmission channel as the destination virtual address.

9. A computer system, characterized in that: include: Direct memory access DMA controller, acceleration consistency interface ACP and buffer memory; The DMA controller is connected to the buffer memory through the ACP; the buffer memory includes a first buffer zone and a second buffer zone; The DMA controller is the DMA controller described in any one of claims 5 to 8 above.

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