An ESD device structure and design method thereof

Abstract

The present invention discloses an ESD device structure and design method thereof. The device comprises a TVS chip, a small capacitor-guided rectifier chip, a gold wire, and a copper alloy frame. The TVS chip and the small capacitor-guided rectifier chip are bonded to the center of the copper alloy frame, and a gold wire is connected between the TVS chip, the small capacitor-guided rectifier chip, and the copper alloy frame. The ESD device structure and design method thereof are connected in parallel to a circuit during use. When the circuit is operating normally, the device is in an off state and does not affect circuit operation. When an abnormal overvoltage occurs in the circuit and reaches its breakdown voltage, the device rapidly changes from a high-resistance state to a low-resistance state, providing a low-impedance conduction path for transient current.

Description

Technical Field

[0001] The present invention relates to the technical field of design and manufacturing of electronic components, and in particular to an ESD device structure and a design method thereof. Background Art

[0002] A new type of protection device combines a TVS diode element and a small-capacitance rectifier chip to provide overvoltage protection. This design also reduces capacitance, minimizing the intermodulation distortion caused by typical solid-state protection solutions. It has a low capacitance value and is primarily used to protect electrostatically sensitive devices in power supply, data transmission, and other circuits. Existing ESD devices have high capacitance, and the device structure has a significant impact on 100M or 1G Ethernet. To this end, we propose an ESD device structure and design method. Summary of the Invention

[0003] The object of the present invention is to provide an ESD device structure and a design method thereof to solve the problems raised in the above background technology.

[0004] To achieve the above objectives, the present invention provides the following technical solutions: an ESD device structure and a design method thereof, comprising a TVS chip, a small capacitor-guided rectifier chip, a gold wire, and a copper alloy frame sheet, characterized in that the TVS chip and the small capacitor-guided rectifier chip are bonded to the center of the copper alloy frame sheet, and a gold wire is connected between the TVS chip, the small capacitor-guided rectifier chip, and the copper alloy frame sheet.

[0005] Preferably, the design method is as follows:

[0006] Design and manufacturing of TVS chips: The structure of the TVS chip is a new punch-through device structure. First, a P-type high epitaxial layer is epitaxially grown on an N substrate. Then, a P-well is formed on the epitaxial layer by implantation adjustment. Then, an N region is formed on the well by diffusion. Under reverse bias, the depletion layer extends to the N substrate region, forming an N+P-P+N+ four-layer structure. Through process control, the base region width is thinned to reduce the PN junction breakdown voltage, thereby achieving avalanche breakdown characteristics.

[0007] Chip design and manufacturing of small-capacitance rectifiers: Small-capacitance rectifiers primarily balance the effects of capacitance and current by balancing junction area and substrate resistivity. Voltage and capacitance are controlled by the precision of the diffusion junction depth and the depth of the N-type high-resistance epitaxial growth. Capacitance is further reduced through a heavy metal platinum diffusion process.

[0008] Bonding the TVS chip and small capacitor-guided rectifier chip to the copper alloy frame: Bond one TVS chip and a group of four small capacitor-guided rectifier chips to the center area of ​​the copper alloy frame using conductive adhesive. Bond a group of two small capacitor-guided rectifier chips to the left and right areas of the copper alloy frame using conductive adhesive.

[0009] The TVS chip and the small capacitor-guided rectifier chip are connected to the copper alloy frame piece circuit by using gold wire ball bonding process.

[0010] Preferably, the TVS chip, the small capacitor-guided rectifier chip and the copper alloy frame sheet are connected to each other by gold wires using a gold wire ball bonding process.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: The ESD device structure and its design method are connected in parallel in the circuit during use. When the circuit is working normally, it is in the cut-off state and does not affect the operation of the circuit. When the circuit has an abnormal overvoltage and reaches its breakdown voltage, it quickly changes from a high-resistance state to a low-resistance state, providing a low-impedance conduction path for the instantaneous current, and at the same time clamping the abnormal high voltage within a safe level, thereby protecting the protected IC or circuit. When the abnormal overvoltage disappears, it returns to a high-resistance state, and the circuit works normally. The copper alloy frame piece adopts a three-partition design, which can realize the series structure of the TVS chip and the small capacitor-guided rectifier chip used in parallel, so as to achieve the purpose of reducing capacitance and reducing the impact of the device structure on 100M or Gigabit Ethernet. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the vertical structure of the TVS chip of the present invention;

[0013] Figure 2 This is a schematic diagram of the longitudinal structure of the small capacitor-guided rectifier chip of the present invention;

[0014] Figure 3 Schematic diagram of the internal connection structure of the present invention;

[0015] Figure 4 This is a structural diagram of the TVS chip manufacturing process of the present invention;

[0016] Figure 5 This is a structural diagram of the chip manufacturing process for the small-capacitor-guided rectifier tube of the present invention.

[0017] In the figure: 1. TVS chip; 2. Small capacitor-guided rectifier chip; 3. Gold wire; 4. Copper alloy frame sheet. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] See also Figure 1-5 The present invention provides a technical solution: a structural design and manufacturing technology for an ESD device. The TVS chip uses a novel punch-through process to produce avalanche breakdown characteristics, resulting in a relatively steep 3-4V breakdown characteristic curve, thereby reducing the impact of leakage current on the circuit. The steering diode adopts a parallel redundant design to increase the current surge resistance and reliability of the structure. The frame adopts a three-partition design to achieve a series structure of the TVS chip 1 and the small capacitor steering rectifier chip 2 used in parallel, thereby achieving the purpose of reducing capacitance and reducing the impact of the device structure on 100M or 1000M Ethernet. The manufacturing process mainly includes the following three steps:

[0020] Design and manufacturing of TVS chip 1: The structure of TVS chip is a new punch-through device structure. First, a P-type high epitaxial layer is epitaxially grown on an N substrate. Then, a P well is formed on the epitaxial layer by implantation adjustment. Then, an N region is formed on the well by diffusion. Under reverse bias, the depletion layer extends to the N substrate region, forming an N+P-P+N+ four-layer structure. Through process control, the base region width is formed thin, the PN junction breakdown voltage is reduced, and the avalanche breakdown characteristic is achieved. The longitudinal cross-section structure is shown as follows: Figure 1 , chip manufacturing process such as Figure 4 :

[0021] Design and manufacturing of chip 2 for small capacitor-guided rectifier tube

[0022] Small capacitance guided rectifiers mainly balance the junction area and substrate resistivity to control the influence of capacitance and current. The voltage and capacitance are controlled by the precision of the diffusion junction depth and the depth of the N high resistance epitaxial growth. The capacitance is further reduced by the heavy metal platinum diffusion process. The longitudinal cross-section structure is shown in the figure. Figure 2 , chip manufacturing process such as Figure 5 .

[0023] Bonding the TVS chip 1 and the small capacitor guide rectifier chip 2 to the copper alloy frame 4: Bond one TVS chip and a group of four small capacitor guide rectifier chips to the central area of ​​the copper alloy frame 4 using conductive adhesive. Bond a group of two small capacitor guide rectifier chips to the left and right areas of the copper alloy frame 4 using conductive adhesive.

[0024] The TVS chip 1 , the small capacitor guide rectifier chip 2 and the copper alloy frame sheet 4 are connected to each other through the gold wire 3 using a gold wire ball bonding process.

[0025] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A design method for an ESD device structure, comprising a TVS chip (1), a small capacitor-guided rectifier chip (2), a gold wire (3) and a copper alloy frame sheet (4), characterized in that: The TVS chip (1) and the small capacitor-guided rectifier chip (2) are bonded to the center of the copper alloy frame sheet (4), and a gold wire (3) is connected between the TVS chip (1) and the small capacitor-guided rectifier chip (2) and the copper alloy frame sheet (4); the design method is as follows: Design and manufacturing of TVS chip (1): The structure of TVS chip (1) is a punch-through device structure. First, a P-type high epitaxial layer is grown epitaxially on an N substrate. Then, a P well is formed by injection adjustment on the epitaxial layer. Then, an N region is formed on the well by diffusion, so that the depletion layer extends to the N substrate region under reverse bias, forming an N+P-P+N+ four-layer structure. The base width is formed thin by process control to reduce the PN junction breakdown voltage to achieve avalanche breakdown characteristics. Chip design and manufacturing of small-capacitance-guided rectifiers: Small-capacitance-guided rectifiers primarily balance the junction area and substrate resistivity to control the effects of fast capacitance and current. Voltage and capacitance are controlled by the precision of the diffusion junction depth and the depth of the N-type high-resistance epitaxial growth. The capacitance is further reduced through a heavy metal platinum diffusion process. Bonding of the TVS chip (1) and the small capacitor-guided rectifier chip (2) to the copper alloy frame sheet (4): One TVS chip (1) and a group of four small capacitor-guided rectifier chips (2) are bonded to the central area of ​​the copper alloy frame sheet (4) through conductive adhesive, and two small capacitor-guided rectifier chips (2) are bonded to the left and right areas of the copper alloy frame sheet (4) through conductive adhesive.

2. The method for designing an ESD device structure according to claim 1, wherein: The TVS chip (1), the small capacitor-guided rectifier chip (2), and the copper alloy frame sheet (4) are connected to each other in a circuit by gold wire (3) using a gold wire ball welding process.

Images