Multiprocessor systems

Abstract

A multiprocessor system includes at least a first processor and a second processor, the multiprocessor system comprising: a storage unit storing a first program executed by the first processor and a second program executed by the second processor; a memory unit having a memory usage area for the second processor; and a monitoring unit connected to the storage unit and the memory unit via a communication line, and storing the read second program in the memory unit when the program read from the storage unit is the second program. The multiprocessor system can activate the second processor faster than conventional techniques.

Description

Technical Field

[0001] The present invention relates to a multi-processor system. Background Art

[0002] Patent Document 1 discloses a multiprocessor system comprising at least a first processor and a second processor, characterized by comprising: a read-only memory storing a first program executed by the first processor and a second program executed by the second processor; and a random access memory connected to the first and second processors in an accessible manner, the random access memory having a memory usage area for the first processor, a memory usage area for the second processor, and a memory usage area shared by the first and second processors. The read-only memory contains headers in addition to program segment codes, each header storing corresponding segment size information and information indicating whether transfer is required for each startup mode. The first processor accesses the program for the second processor stored in the read-only memory, and, as a prerequisite for determining whether transfer is required for the second processor, determines, with respect to the startup mode, whether a startup instruction for the normal mode or a startup instruction for the special mode is present, and expands the program corresponding to the determined startup mode into the memory usage area of ​​the second processor.

[0003] Patent Document 1: International Publication No. 2008 / 001671 Summary of the Invention

[0004] An object of the present invention is to provide a multi-processor system that enables a second processor to be activated faster than in the prior art.

[0005] The multi-processor system involved in the first method includes at least a first processor and a second processor, and the multi-processor system has: a storage unit that stores a first program executed by the first processor and a second program executed by the second processor; a memory unit that has a memory usage area for the second processor; and a monitoring unit that is connected to the storage unit and the memory unit via a communication line, and when the program read from the storage unit is the second program, stores the read second program in the memory unit.

[0006] In the multiprocessor system according to a second aspect, in the multiprocessor system according to the first aspect, the first processor and the monitoring unit are connected to the storage unit via the communication line.

[0007] In the multiprocessor system according to a third aspect, in the multiprocessor system according to the second aspect, the communication line is a bus.

[0008] In the multiprocessor system according to a fourth aspect, in the multiprocessor system according to the first aspect, the first processor and the storage unit are connected via the monitoring unit and the communication line.

[0009] In the multiprocessor system according to a fifth aspect, in the multiprocessor system according to the fourth aspect, the storage unit and the monitoring unit, and the monitoring unit and the first processor are connected on a one-to-one basis via the communication line.

[0010] The multi-processor system involved in the 6th mode is a multi-processor system involved in any one of the 1st to 5th modes, and further comprises: an inter-processor interface circuit between the first processor and the second processor; and a reading unit that reads a program stored in the storage unit, the first processor initializes the inter-processor interface circuit, and the reading unit starts reading the second program from the storage unit until the initialization of the inter-processor interface circuit is completed.

[0011] Effects of the Invention

[0012] According to the first aspect, there is an effect that the second processor can be activated faster than in the conventional art.

[0013] According to the second aspect, there is an effect that a multi-processor system can be easily configured.

[0014] According to the third aspect, there is an effect that a multi-processor system can be easily configured using a bus.

[0015] According to the fourth aspect, there is an effect that the monitoring unit can manage program transmission in a centralized manner.

[0016] According to the fifth aspect, there is an effect that the communication speed can be increased compared to the conventional technology.

[0017] According to the sixth aspect, there is an effect that the second processor can be activated faster than in the related art from the start of reading the second program from the storage unit to the completion of initialization of the inter-processor interface circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Embodiments of the present invention will be described in detail with reference to the following drawings.

[0019] Figure 1 is a block diagram of a multiprocessor system according to a first embodiment;

[0020] Figure 2 This is a flow chart of the transfer processing of CPU2 program data and CPU3 program data by CPU1_112 executing the CPU1 program;

[0021] Figure 3 This is a flowchart of a program data storage process for storing CPU2 program data and CPU3 program data in RAM_B108, which is executed by the Snoop controller 180;

[0022] Figure 4 This is a timing diagram of the CPU1_112, DMAC118, and Snoop controller 180 during the CPU2 program data and CPU3 program data transfer processing and program data storage processing;

[0023] Figure 5 FIG. 1 is a diagram showing an example of an area for storing programs in RAM_B 108;

[0024] Figure 6 is a block diagram of a multiprocessor system according to a second embodiment;

[0025] Figure 7 This is a timing chart of the CPU1_112, DMAC118, and Snoop controller 180 during the CPU2 program data and CPU3 program data transfer processing and program data storage processing in the first modification example;

[0026] Figure 8 This is a timing chart of the CPU1_112, DMAC 118, and Snoop controller 180 during the CPU2 program data and CPU3 program data transfer processing and program data storage processing in the second modification.

[0027] Explanation of symbols

[0028] 100-ROM, 101-bus, 103-bus, 108-RAM_B, 112-CPU1, 118-DMAC, 152-CPU2, 180-Snoop controller, 107A, 107B-communication lines. DETAILED DESCRIPTION

[0029] Hereinafter, examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0030] (First embodiment)

[0031] The configuration of the multiprocessor system according to the first embodiment will be described with reference to the drawings.

[0032] Figure 1 A block diagram of a multi-processor system according to the first embodiment is shown in FIG. Figure 1As shown, the multiprocessor system includes a plurality of CPUs (Central Processing Units), for example, at least CPU1_112 and CPU2_152. Specifically, the multiprocessor system comprises: a System-on-a-chip (SoC) 102 including CPU1_112; and an Application Specific Integrated Circuit (ASIC) 104 including CPU2_152 and CPU3_154.

[0033] CPU1_112 and CPU2_152 are examples of the “first processor” and the “second processor” in the technology of the present invention.

[0034] The multiprocessor system includes a ROM (Read Only Memory) 100. The ROM 100 stores CPU1 program data executed by CPU1_112, CPU2 program data executed by CPU2_152, and CPU3 program data executed by CPU3_154. The ROM 100 is, for example, a nonvolatile memory.

[0035] The ROM 100 is an example of a “storage unit” in the technology of the present invention.

[0036] The multiprocessor system includes RAM (Random Access Memory)_A 106 having a memory area used by CPU1_112 and RAM_B 108 having a memory area used by CPU2_152. RAM_A 106 and RAM_B 108 are volatile memories such as DRAM (Dynamic Random Access Memory).

[0037] RAM_B 108 is an example of a “memory unit” in the technology of the present invention.

[0038] SoC 102 includes CPU 1_112, ROM controller (Cont) 114A, DRAM controller (Cont) 116, DMAC (DMA Controller) 118, and inter-processor controller (Cont) 120. These components (112 to 120) are communicatively connected to each other via bus 122. DRAM controller 116 is connected to RAM_A 106.

[0039] The DMAC 118 is an example of a “memory unit” in the technology of the present invention.

[0040] ASIC 104 includes CPU2_152, CPU3_154, DRAM controller (Cont) 156, inter-processor controller (Cont) 158, multiple other controllers (Other1 controller 160A, Other2 controller 160B, Other3 controller 160C, etc.), and Snoop controller 180. DRAM controller 156 is connected to RAM_B 108.

[0041] The Snoop controller 180 is an example of a “monitoring unit” in the technology of the present invention.

[0042] The inter-processor controller 120 and the inter-processor controller 158 are connected via a PCIE (PCI Express (bus interface)) 105 .

[0043] The inter-processor controller 120 and the inter-processor controller 158 are examples of the “inter-processor interface circuit” in the technology of the present invention.

[0044] The CPU 1_112 and the Snoop controller 180 are connected to the ROM 100 via a communication line. Specifically, the Snoop controller 180 is connected to the bus 101 between the ROM 100 and the CPU 1_112 via the bus 103 .

[0045] The details will be described later. When the program data read from the ROM 100 is the CPU2 program data and the CPU3 program data, the Snoop controller 180 stores the read CPU2 program data and the CPU3 program data in the RAM_B 108. Figure 5 As shown, the Snoop controller 180 stores the CPU2 program from a predetermined CPU2 program start address P2A in the RAM_B 108 , and stores the CPU3 program data from a predetermined CPU3 program start address P3A.

[0046] As described above, ROM 100 stores CPU1 program data, CPU2 program data, and CPU3 program data. CPU1 program data is stored in the area between memory locations M1 and M2 of ROM 100, CPU2 program data is stored in the area between memory locations M2 and M3 of ROM 100, and CPU3 program data is stored in the area after memory location M3 of ROM 100.

[0047] The program data stored in ROM 100 is Figure 1The data is read from top to bottom and from left to right on the paper. Regarding the CPU1 program data, CPU2 program data, and CPU3 program data, program data with a higher startup priority is arranged closer to the beginning (where it is easier to read). As a result, the program data of CPU2_152 and CPU3_154 are transferred earlier than in a different arrangement, and CPU2_152 and CPU3_154 are started faster than in a different arrangement.

[0048] Identification data is provided at the beginning and end of each of the CPU2 and CPU3 program data. Specifically, start identification data P2S indicating the beginning of the CPU2 program data is provided at the beginning of the CPU2 program data, and end identification data P2E indicating the end of the CPU2 program data is provided at the end of the CPU2 program data. Start identification data P3S indicating the beginning of the CPU3 program data is provided at the beginning of the CPU3 program data, and end identification data P3E indicating the end of the CPU3 program data is provided at the end of the CPU3 program data. If this identification data is provided in the program data, the Snoop controller 180 can determine the breakpoints between the CPU1 program data and the CPU2 program data, between the CPU2 program data and the CPU3 program data, and between the CPU3 program data and other program data. Alternatively, the Snoop controller 180 can use the addresses stored in each program data instead of the identification data to determine the breakpoints of the program data. Identification data or addresses can also be stored in a non-volatile memory inside or outside the ASIC 104, and the identifiers of the program data can be made variable or set to values ​​other than predetermined values.

[0049] Next, the operation of the first embodiment will be described.

[0050] Figure 2 3 is a flowchart of a process of transferring the CPU2 program data and the CPU3 program data when the CPU1_112 executes the CPU1 program. Figure 3 , which is a flowchart of a program data storage process for storing CPU2 program data and CPU3 program data in RAM_B 108, executed by the Snoop controller 180. Figure 4 ( Figure 4 (A) to (C) of FIG. 10 show timing charts of the CPU1_112, DMAC118, and Snoop controller 180 during the transfer processing of the CPU2 program data and the CPU3 program data and the program data storage processing.

[0051] When the SoC 102 and the ASIC 104 are powered on, the CPU 1_112 and the Snoop controller 180 are also powered on.

[0052] The Snoop controller 180 starts to be powered on. Figure 3 In step 252, it is determined whether the designated start identification data P2S or start identification data P3S ( Figure 4 : time t0 to time t4).

[0053] If the CPU1_112 is powered on and started, then at (time t0 to t1), step 202 (reference Figure 2 ), CPU1_112 sets DMAC118 so that the CPU1 program is transferred from ROM100 to RAM_A106 (see time t1 to t2). In step 204, CPU1_112 determines whether the transfer of the CPU1 program is completed.

[0054] The DMAC 118 configured in step 202 reads the CPU 1 program data from the ROM 100 and stores it in the RAM_A 106 (from time t2 to before time t3). The CPU 1 program data read by the DMAC 118 is transferred via the bus 101, the ROM controller 114A, the bus 122, and the DRAM controller 116, and is stored in the RAM_A 106.

[0055] As described above, the bus 101 is connected to one end of the bus 103, the other end of which is connected to the Snoop controller 180. Therefore, the program data of the CPU 1 is also transmitted to the Snoop controller 180 via the buses 101 and 103. Figure 3 In step 252, it is determined whether the transmitted program data contains the designated start identification data P2S or start identification data P3S. That is, the Snoop controller 180 determines whether the transmitted program data is the CPU2 program data or the CPU3 program data.

[0056] As described above, the CPU 1 program data is also transferred to the Snoop controller 180 from time t2 to time t3, so the determination result of step 252 is negative. In this case, the Snoop controller 180 ignores the transferred program data (it does not exist in RAM_B 108).

[0057] When the DMAC 118 reads the program data from address M1 to M2 and expands it to RAM_A106, it sets the status (transfer status) to "transfer in progress". When the expansion is completed, it switches to "transfer completed" indicating that the transfer of the CPU1 program has been completed. CPU1_112 checks the status of the DMAC 118 and, when it detects that the status is "transfer completed", Figure 2 The determination in step 204 is affirmative (time t3).

[0058] If the determination in step 204 is positive, in step 206, CPU1_112 sets DMAC118 to transfer the program for CPU2 and then transfer the program for CPU3 (time t3 to time t4). In step 208, CPU1_112 initializes PCIE105 (time t4 to time t5). In step 210, CPU1_112 determines whether the transfer of the program for CPU2 is complete (time t5 to time t6).

[0059] The DMAC 118, which is set to transfer the CPU2 program and then the CPU3 program, reads the CPU2 program data from the ROM 100 and expands it to the RAM_A 106. The CPU2 program data read by the DMAC 118 is transferred via the bus 101, the ROM controller 114A, the bus 122, and the DRAM controller 116 and stored in the RAM_A 106.

[0060] The CPU2 program data is also transferred to the Snoop controller 180 via the buses 101 and 103. In this case, the DMAC 118 first reads the start identification data P2S indicating the beginning of the CPU2 program data and transfers it to the Snoop controller 180.

[0061] If the start recognition data P2S is transmitted to the Snoop controller 180, then Figure 3 The result of the determination in step 252 is positive. If the result of the determination in step 252 is positive, then in step 254, the Snoop controller 180 starts to transmit to the designated address. Specifically, the Snoop controller 180 starts from Figure 5 The address P2A of the RAM_B 108 shown sequentially stores the CPU 2 program data (time t4 to time t6).

[0062] Through the above processing, Figure 4 As shown, during the period from time t4 to time t5 when CPU1_112 is initializing PCIE 105, CPU2 program data is transferred to RAM_B 108 via Snoop controller 180 via buses 101, 103, bus 162, and DRAM controller 156, rather than via PCIE 105. Thus, the transfer of CPU2 program data to RAM_B 108 begins until PCIE 105 initialization is complete.

[0063] In the first embodiment, the initialization of the PCIE 105 and the transfer of the CPU2 program data to the RAM_B 108 are started at the same time t4 , and the initialization of the PCIE 105 is completed before the transfer of the CPU2 program data to the RAM_B 108 is completed.

[0064] As mentioned above, in Figure 2 In step 210, CPU1_112 determines whether the transfer of the CPU2 program is completed (from time t5 to time t6).

[0065] When DMAC118 reads the program data from address M2 to M3 and expands it to RAM_B108, it switches the state (transfer state) to the transfer completion of CPU2 program. CPU1_112 checks the state of DMAC118 and detects that the state has switched to the transfer completion of CPU2 program. Figure 2 The determination in step 210 becomes affirmative (time t6).

[0066] In addition, the Snoop controller 180 switches states in the same manner as the DMAC 118. The CPU 1_112 can check the state of the Snoop controller 180 and detect whether the state has switched to indicate the transfer of the CPU 2 program has been completed. Furthermore, the CPU 1_112 can determine whether the CPU 2 program is stored in the RAM_A 106.

[0067] As described above, PCIE 105 is initialized, and the transfer of CPU2 program data to RAM_B 108 is complete. Therefore, in step 212, CPU1_112 releases the reset of CPU2_152 (CPU2_152 startup begins: from time t6 to time t7). Specifically, CPU1_112 notifies CPU2_152 of the reset release. This prevents CPU2_152 from executing the CPU2 program before all of its program data is stored in RAM_B 108. Furthermore, the CPU2 management unit (Other2 controller 160B) is initialized (time t9).

[0068] In step 214, CPU1_112 determines whether the transfer of the CPU3 program has completed (time t7 to time t8). If the transfer of the CPU3 program has completed, CPU1_112 releases the reset of CPU3_154 in step 216. The execution of the CPU3 program in steps 214 and 216 differs from the execution of the CPU2 program in steps 210 and 212, so their description is omitted. Furthermore, the CPU3 management unit (Other3 controller 160C) is initialized (time t10).

[0069] The DMAC 118 transfers the program of CPU 2 from time t4 to time t6 and transfers the program of CPU 3 from time t6 to time t8.

[0070] In the Snoop controller 180, also through Figure 3Step 254 transfers the CPU2 program from time t4 to time t6, and transfers the CPU3 program from time t6 to time t8.

[0071] In step 256, Snoop controller 180 determines whether the specified end identification data P3E is present in the program data transferred via buses 101 and 103. Step 256 is repeated until it is determined that the specified end identification data P3E is present in the program data transferred via buses 101 and 103. If it is determined that the specified end identification data P3E is present in the transferred program data, it is determined that the transfer of the CPU 3 program has ended, and processing ends.

[0072] As described above, in the first embodiment, PCIE 105 initialization and CPU2 program data transfer to RAM_B 108 begin at the same time t4. That is, CPU2 program data transfer to RAM_B 108 is performed independently of PCIE 105 initialization. Thus, in the first embodiment, CPU2 boots up faster than in conventional techniques that transfer CPU2 program data after PCIE initialization.

[0073] In the first embodiment, the snoop controller 180 is connected to the bus 101 between the ROM 100 and the CPU 1_112 via a single bus 103. Since there is only one communication line, the configuration of the multi-processor system is simplified.

[0074] (Second embodiment)

[0075] The configuration of the multiprocessor system according to the second embodiment is substantially the same as that of the multiprocessor system according to the first embodiment. Therefore, the same reference numerals are given to the same parts and their description is omitted. The description will focus on the different parts.

[0076] exist Figure 6 A block diagram of a multi-processor system according to the second embodiment is shown in FIG. Figure 6 As shown, CPU1_112 and ROM100 are connected via Snoop controller 180 and communication lines 107A and 107B. Specifically, ROM100 and Snoop controller 180 are connected via communication line 107A, and Snoop controller 180 and CPU1_112 are connected via communication line 107B, interface (I / F) controller 114B, and bus 122.

[0077] The ROM 100 and the Snoop controller 180 are connected on a one-to-one (Peer-to-Peer) basis, and the Snoop controller 180 and the CPU 1_112 are connected on a one-to-one (Peer-to-Peer) basis.

[0078] The function of the second embodiment is substantially the same as that of the first embodiment, and therefore its description is omitted. Furthermore, in the second embodiment, each program data is transmitted to RAM_A 106 via communication line 107A, Snoop controller 180, communication line 107B, and SoC 102. In particular, CPU2 program data and CPU3 program data are also transmitted to RAM_B 108 via line 107A and ASIC 104 (Snoop controller 180).

[0079] In the second embodiment, the CPU 2 is activated faster than in the conventional technology in which the CPU 2 program data is transferred after the PCIE is initialized.

[0080] The ROM 100 and the Snoop controller 180 are connected on a one-to-one (Peer-to-Peer) basis, and the Snoop controller 180 and the CPU 1_112 are connected on a one-to-one (Peer-to-Peer) basis. This allows for faster communication speeds than when connected via a bus.

[0081] The Snoop controller 180 comprehensively manages the transmission of each program.

[0082] (Variation)

[0083] (First Modification)

[0084] The first modification example will be described. The structure of the first modification example may be any of the structure of the first embodiment and the structure of the second embodiment.

[0085] The effect of the first modification example will be described. Figure 7 ( Figure 7 (A) to (C) of FIG. 1 show timing charts of the CPU1_112, DMAC118, and Snoop controller 180 during the CPU2 program data and CPU3 program data transfer processing and program data storage processing in the first modification example.

[0086] In the first and second embodiments, the CPU 1 activates the CPU 2 when the CPU 2 program is transferred. However, in the first modification, the Snoop controller 180 activates the CPU 2 — 152 when the CPU 2 program is stored in the RAM — B 108 .

[0087] (Second Modification)

[0088] The second modification example will be described. The structure of the second modification example may be either the structure of the first embodiment or the structure of the second embodiment.

[0089] The effect of the second modification example will be described. Figure 8 ( Figure 8 (A) to (C) show timing charts of the CPU1_112, DMAC118, and Snoop controller 180 during the transfer processing of the CPU2 program data and the CPU3 program data and the program data storage processing in the second modification example.

[0090] In the first and second embodiments, the CPU2 program is transferred during the initialization of PCIE 105 (from time t4 to time t5), but in the second variant, the CPU2 program is transferred before PCIE 105 starts initialization (from time T2 to time T3). In this way, in the technology of the present invention, the initialization of PCIE 105 and the transfer of CPU2 program data to RAM_B 108 are performed independently. At least, the transfer of CPU2 program data begins before the initialization of PCIE 105 is completed. As a result, CPU 2 starts faster than in the existing technology that transfers CPU2 program data after PCIE initialization.

[0091] In the second modification, the CPU2 program is transferred (from time T2 to time T3) before the CPU1 program data is transferred (from time T6 to time T7).

[0092] In addition, the structure of the multiprocessor system described in the above example (refer to Figure 1 、 Figure 6 ) is an example, and of course, unnecessary parts can be deleted or new parts can be added without departing from the scope of the present invention.

[0093] Furthermore, the processing flow in the above example (refer to Figures 2 to 4 Reference) is also an example. Of course, unnecessary steps can be deleted, new steps can be added, or the processing order can be changed without departing from the scope of the present invention.

[0094] The above-described embodiments of the present invention are provided for the purpose of illustration and explanation. In addition, the embodiments of the present invention do not fully and exhaustively include the present invention, and do not limit the present invention to the disclosed embodiments. It is obvious that various modifications and variations are self-evident to those skilled in the art to which the present invention belongs. The present embodiment is selected and described in order to most easily explain the principles of the present invention and its application. Thus, other technical personnel in this field can understand the present invention through various modifications optimized for specific uses of the assumed various embodiments. The scope of the present invention is defined by the above claims and their equivalents.

Claims

1. A multi-processor system comprising at least a first processor and a second processor, The multi-processor system comprises: a storage unit connected to the first processor but not directly connected to the second processor, storing a first program executed by the first processor and a second program executed by the second processor; a memory unit that is not directly connected to the first processor but is directly connected to the second processor and has a memory usage area of ​​the second processor; a monitoring unit connected to the storage unit and the memory portion via a communication line connecting the first processor and the second processor, and storing the read second program in the memory portion when the program read from the storage unit is the second program; and an inter-processor interface connecting the first processor and the second processor and configured as a path different from the communication line; The first processor initializes the inter-processor interface. The monitoring unit starts storing the second program read from the storage unit into the memory unit at the same time as the first processor initializes the inter-processor interface. During initialization of the inter-processor interface, the second program is stored in the memory unit via the communication line.

2. The multiprocessor system according to claim 1, wherein: The first processor and the monitoring unit are connected to the storage unit via the communication line.

3. The multiprocessor system according to claim 2, wherein: The communication line is a bus.

4. The multiprocessor system according to claim 1, wherein: The first processor and the storage unit are connected via the monitoring unit and the communication line.

5. The multiprocessor system according to claim 4, wherein: The storage unit and the monitoring unit, and the monitoring unit and the first processor are connected on a one-to-one basis via the communication line.

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