Semiconductor package apparatus and method of manufacturing the same

Abstract

A semiconductor device package includes a carrier, the semiconductor device package comprising: a first conductive element; a second conductive element disposed on a semiconductor disposed on the carrier; and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element has a surface substantially coplanar with the surface of the second conductive element.

Description

Technical Field

[0001] This application generally relates to semiconductor packaging equipment and methods for manufacturing the same. Background Technology

[0002] A semiconductor device package comprises a carrier and one or more semiconductor devices. Some of the semiconductor devices may be stacked within the semiconductor device package. Coplanarity is crucial in bonding or attaching semiconductor devices to another semiconductor device and the carrier. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes: a carrier having a first substantially uneven surface and a second surface above the first substantially uneven surface; a planarization layer disposed on the first substantially uneven surface of the carrier, the planarization layer having a first surface and a second surface opposite to the first surface; and a first semiconductor device disposed on the first surface of the planarization layer, the first semiconductor device having a first surface below the second surface of the carrier.

[0004] In one or more embodiments, a semiconductor device package includes: a carrier having a first surface, a second surface above the first surface, and a third surface above the second surface; a first semiconductor device disposed on the first surface of the carrier, the first semiconductor device having a first surface lower than the third surface of the carrier; a first conductive element disposed on the second surface of the carrier, the first conductive element having a first surface; and a second conductive element disposed on the first surface of the first semiconductor device, the second conductive element having a first surface, wherein the first surface of the first conductive element is substantially the same as the first surface of the second conductive element in elevation.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes: forming a planarization layer on a first surface of a carrier, the carrier having a second surface above the first surface; picking up a first semiconductor device via a first end of a holder, the holder having a second end above the first end; moving the first semiconductor device toward the planarization layer; and stopping the first semiconductor device once the second end of the holder contacts the second surface of the carrier. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this application will be readily understood from the following detailed description. It should be noted that features may not be drawn to scale, and the dimensions of features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A cross-sectional view illustrating a semiconductor device package according to some embodiments of this application.

[0008] Figure 2A illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0009] Figure 2B illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0010] Figure 2C illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0011] Figure 2D illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0012] Figure 2E illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0013] Figure 2F illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0014] Figure 2G illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0015] Figure 2H illustrate Figure 1 An enlarged view of a portion of a semiconductor device package shown in the image.

[0016] Figure 3 A cross-sectional view illustrating a semiconductor device package according to some embodiments of this application.

[0017] Figure 4A , Figure 4B and Figure 4C This application describes a method for manufacturing a semiconductor device package according to some embodiments.

[0018] Figure 4A , Figure 4B , Figure 4C and Figure 4E This application describes a method for manufacturing a semiconductor device package according to some embodiments.

[0019] Figure 4D illustrate Figure 4CAn enlarged view of a portion of a semiconductor device package shown in the image.

[0020] Figure 4A and Figure 4F This application describes a method for manufacturing a semiconductor device package according to some embodiments.

[0021] Figure 5A This illustrates a cross-sectional view of a semiconductor device package according to some comparative embodiments.

[0022] Figure 5B illustrate Figure 5A An enlarged view of a portion of a semiconductor device package shown in the image.

[0023] Figure 6A This illustrates a cross-sectional view of a semiconductor device package according to some comparative embodiments.

[0024] Figure 6B illustrate Figure 6A An enlarged view of a portion of a semiconductor device package shown in the image.

[0025] Figure 6C illustrate Figure 6A An enlarged view of a portion of a semiconductor device package shown in the image.

[0026] Common reference numbers are used throughout the drawings and detailed descriptions to indicate the same or similar elements. Detailed Implementation

[0027] Figure 1 This illustration shows a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present application. The semiconductor device package 1 includes a carrier 11, a semiconductor device 12, and a planarization layer 13.

[0028] The carrier 11 may be or may contain polymeric or nonpolymeric dielectric materials. For example, the carrier 11 may contain a flowable dielectric material in a hardened or semi-hardened state, such as a liquid crystal polymer, a fibrous resin (e.g., a prepreg), an Ajinomoto Buildup Film (ABF), a resin, an epoxy resin material, or other flowable dielectric materials in a hardened or semi-hardened state. In some embodiments, the carrier 11 comprises a single resin layer. In other embodiments, the carrier 11 comprises multiple resin layers; for example, a first sublayer formed of resin and a second sublayer formed of a reinforcing resin (e.g., a resin reinforced with glass fiber or Kevlar fiber). In some embodiments, the carrier 11 comprises a prepreg material that may be in the form of a single layer or multiple layers. In some embodiments, the carrier 11 comprises at least one prepreg material layer and at least one resin layer. The carrier 11 has a surface 112, a surface 113 above or on surface 112, and a surface 111 above or on surfaces 112 and 113.

[0029] A planarization layer 13 is disposed on the surface 112 of the carrier 11. The planarization layer 13 is in direct contact with the surface 112 of the carrier 11. A semiconductor device 12 is disposed on the planarization layer 13. The semiconductor device 12 is in direct contact with the planarization layer 13. A distance H exists between the surface 121 of the semiconductor device 12 and the surface 111 of the carrier 11. A difference in elevation or level H exists between the surface 121 of the semiconductor device 12 and the surface 111 of the carrier 11.

[0030] The planarization layer 13 may include (but is not limited to) bonding materials. Bonding materials are, for example, but not limited to, welding materials, adhesives, or other suitable materials.

[0031] The planarization layer 13 has a surface 131 that is in direct contact with the semiconductor 12 and a surface 132 that is in contact with the surface 112 of the carrier 11. Surface 131 and surface 132 are opposite to each other. Surface 131 of the planarization layer 13 may be parallel to surface 121 of the semiconductor device 12.

[0032] The thickness of the planarization layer 13 can be in the range of about 20 μm to about 100 μm.

[0033] A conductive element 114 may be disposed on the surface 113 of the carrier 11. The connecting element 114 may include conductive bumps, pillars, or conductive pads. The conductive element 114 has a surface 114t. A distance h1 exists between the surface 114t of the conductive element 114 and the surface 111 of the carrier 11. An elevation or horizontal difference h1 exists between the surface 114t of the conductive element 114 and the surface 111 of the carrier 11.

[0034] RDL 115 may be formed in carrier 11. RDL 115 may be electrically connected to an external device. Conductive element 114 may be electrically connected to RDL 115. Conductive element 114 may be in direct contact with RDL 115. Conductive element 114 may be electrically connected to an external device via RDL 115.

[0035] A conductive element 122 may be disposed on a surface 121 of a semiconductor device 12. The connecting element 122 may include conductive bumps, pillars, or pads. The conductive element 122 has a surface 122t. A distance h2 exists between the surface 122t of the conductive element 122 and the surface 111 of the carrier 11. An elevation or horizontal difference h2 exists between the surface 122t of the conductive element 122 and the surface 111 of the carrier 11. The surface 122t of the conductive element 122 may be substantially parallel to the surface 114t of the conductive element 114. The surface 114t of the conductive element 114 is substantially the same in elevation as the surface 122t of the conductive element 122. In other words, the horizontal difference h1 and the horizontal difference h2 are substantially the same.

[0036] Surface 121 may include an active surface. The circuitry of semiconductor device 12 is adjacent to surface 121. Semiconductor device 12 may include (e.g., but not limited to) photonic integrated circuits, optical dies (e.g., photonic dies), radio frequency dies, detectors, or other integrated circuits.

[0037] Surface 112 may include the bottom surface of a cavity or recess formed in the carrier 11.

[0038] Figure 2A Explanation in such Figure 1 The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A". Surface 112 may be substantially uneven (e.g., due to manufacturing variations or tolerances). Surface 112 of the carrier 11 is uneven. Surface 132 of the planarization layer 13 may be uneven and is bonded to surface 112 of the carrier 11. Surface 132 of the planarization layer 13 may conform to surface 112 of the carrier 11. Surface 132 of the planarization layer 13 may conform to surface 112 of the carrier 11.

[0039] Figure 2B Explanation in such Figure 1 The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A". The surface 112 of the carrier 11 is inclined relative to the surface 121 of the semiconductor device 12. The surface 132 of the planarization layer 13 is conformal to the surface 112 of the carrier 11. The surface 132 of the planarization layer 13 is compliant with the surface 112 of the carrier 11. The surface 132 of the planarization layer 13 is inclined relative to the surface 121 of the semiconductor device 12.

[0040] Figure 2C Explanation in such Figure 1 The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A". The surface 112 of the carrier 11 is not flat and is inclined relative to the surface 121 of the semiconductor device 12. The surface 132 of the planarization layer 13 may conform to the surface 112 of the carrier 11. The surface 132 of the planarization layer 13 may conform to the surface 112 of the carrier 11. The surface 132 of the planarization layer 13 may be bonded to the surface 112 of the carrier. The surface 132 of the planarization layer 13 is not flat and is inclined relative to the surface 121 of the semiconductor device 12.

[0041] Figure 2D Explanation in such Figure 1 The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A". The planarization layer 13, disposed between the carrier 11 and the semiconductor device 12, can be formed of different types. The planarization layer 13 may have a trapezoidal shape.

[0042] Figure 2E Explanation in such Figure 1 An enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A" shown in the image. The planarization layer 13 may have a wedge shape.

[0043] Figure 2F Explanation in such Figure 1 The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "A". In some embodiments, the planarization layer 13 does not fill the space between the carrier 11 and the semiconductor device 12. The planarization layer 13 may be deposited within the periphery of the semiconductor device 12. In some embodiments, the planarization layer 13 is deposited at the corners of the semiconductor device 12. In some embodiments, the planarization layer 13 is deposited at the center of the bottom surface of the semiconductor device 12, opposite surface 121. In some embodiments, the planarization layer 13 may be deposited to form a hollow pattern between the carrier 11 and the semiconductor device 12.

[0044] Figure 2G Explanation in such Figure 1 An enlarged view of a portion of the semiconductor device package 1 within the dashed circle "B" shown. The surface 111 of the carrier 11 may be tilted relative to the surface 114t of the conductive element 114 (e.g., due to manufacturing deviations or tolerances). The surface 111 of the carrier 11 may be tilted relative to the surface 121 of the semiconductor device 12.

[0045] Figure 2H Explanation in such Figure 1The image shows an enlarged view of a portion of the semiconductor device package 1 within the dashed circle "B". The carrier 11 is manufactured with a notch having a surface 113. Surface 113 can be formed by a removal operation. Surface 113 may be tilted relative to surface 111 of the carrier 11 (e.g., due to manufacturing deviations or tolerances). Surface 113 of the carrier may be tilted relative to surface 114t of the conductive element 114 (e.g., due to manufacturing deviations or tolerances). Surface 113 of the carrier may be tilted relative to surface 121 of the semiconductor device 12.

[0046] Figure 3 This illustration shows a cross-sectional view of a semiconductor device package 2 according to some embodiments of this application. A semiconductor device 14 is deposited on or above a semiconductor device 12. The semiconductor device 14 is disposed above and across the semiconductor device 12 and the conductive element 114. The semiconductor device 14 has a surface 141. Surface 141 faces surface 121 of the semiconductor device 12 and surface 114t of the conductive element 114. Surface 141 of the semiconductor device 14 may be substantially parallel to surface 121 of the semiconductor device 12. Surface 141 of the semiconductor device 14 may be substantially parallel to surface 111 of the carrier 11.

[0047] Surface 141 may include or constitute at least a portion of an active surface. Semiconductor device 14 may include (e.g., but not limited to) controller dies, processor dies, application-specific integrated circuit (ASIC) dies, microcontroller unit (MCU) dies, RFID, photonic integrated circuits, optical dies (e.g., photonic dies), radio frequency dies, detectors, RFICs, and the like.

[0048] The conductive element 142 may be configured to directly contact the surface 141 of the semiconductor device 14. The semiconductor device 14 is electrically connected to the conductive element 114 via the conductive element 142. The semiconductor device 14 is electrically connected to the semiconductor device 12 via the conductive elements 142 and 122.

[0049] A distance h3 can be defined from the surface 141 of the semiconductor device 14 to the surface 114t of the conductive element 114. A distance h4 can be defined from the surface 141 of the semiconductor device 14 to the surface 122t of the conductive element 122. Distance h3 can be substantially the same as distance h4. The surface 122t of the conductive element 122 can be substantially coplanar with the surface 114t of the conductive element 114. The coplanar surfaces 122t and 114t can be parallel to the surface 141 of the semiconductor device 14.

[0050] Semiconductor device 12, having surface 121 facing semiconductor device 14, is bonded to semiconductor device 14 to form a face-to-face stacked structure. Signal transmission can be performed between semiconductor device 12 and semiconductor device 14 via conductive elements 122 and 142. Lateral or horizontal signal transmission (e.g., other than conductive elements 122, 142) can be minimized or omitted to reduce transmission loss.

[0051] Encapsulation 15 may be formed between semiconductor device 14 and conductive element 114. Encapsulation 15 may be formed between semiconductor device 14 and semiconductor device 12. Encapsulation 15 may encapsulate conductive element 142. Encapsulation 15 may also encapsulate conductive elements 142 and 122.

[0052] Figure 4A , 4B The present application describes methods for manufacturing semiconductor device packages according to some embodiments of the present application.

[0053] refer to Figure 4A A carrier 11 is provided. The carrier 11 has surfaces 112, 113, and 111. Surface 113 is formed on or above surface 112, and surface 111 is formed on or above surface 113. A conductive element 114 is deposited on surface 113. The carrier 11 may be fabricated to include an RDL structure 115.

[0054] Surface 112 can be formed by a removal process. Surface 112 can be formed by an etching operation (e.g., a chemical operation or a plasma etching operation). Surface 112 can be formed by a mechanical removal operation. Surface 112 can be formed by an optical removal operation.

[0055] The conductive element 114 can be formed by, for example but not limited to, implantation techniques. The conductive element 114 may include conductive bumps, pillars, pads, etc.

[0056] refer to Figure 4B A planarization material 13' is deposited on the surface 112 of the carrier 11. A holder 20 picks up the semiconductor device 12. The semiconductor device 12 may have conductive elements 122 on its surface 121. The conductive elements 122 are formed to be in direct contact with the surface 121 of the semiconductor device 12.

[0057] The holder 20 may have a clamp (not shown) connected to a vacuum via a conduit. The clamp of the holder 20 can be used to vacuum pick up the semiconductor device 12. The holder 20 may further include a heat-conducting conduit (not shown) that is thermally connected to a heater. In some embodiments, the holder 20 may include a heater. The holder 20 has a contact head 23.

[0058] refer to Figure 4CThe holder 20 picks up the semiconductor device 12 and moves the semiconductor device 12 toward the surface 112 of the carrier 11. After the contact head 23 of the holder contacts the surface 111 of the carrier 11, the holder 20 stops.

[0059] The carrier 11 may be or may contain polymeric or nonpolymeric dielectric materials. For example, the carrier 11 may contain a flowable dielectric material in a hardened or semi-hardened state, such as a liquid crystal polymer, a fibrous resin (e.g., a prepreg), an Ajinomoto deposited film (ABF), a resin, an epoxy resin material, or other flowable dielectric materials in a hardened or semi-hardened state. In some embodiments, the carrier 11 comprises a single resin layer. In other embodiments, the carrier 11 comprises multiple resin layers; for example, a first sublayer formed of resin and a second sublayer formed of a reinforcing resin (e.g., a resin reinforced with glass fiber or Kevlar fiber). In some embodiments, the carrier 11 comprises a prepreg material that may be in the form of a single layer or multiple layers. In some embodiments, the carrier 11 comprises at least one prepreg material layer and at least one resin layer. The contact head 23 of the retainer 20 is unlikely to damage the carrier 11 during contact with the surface 111 of the carrier 11 because the carrier 11 comprises a relatively flexible or soft material.

[0060] As the semiconductor device 12 moves toward the surface 112 of the carrier 11, the planarization material 13' is compressed by the semiconductor device 12 to form a planarization layer 13. The semiconductor device 12 can be bonded to the surface 112 of the carrier 11 using the planarization layer 13. After the compression process, the planarization material 13' can be cured via a curing operation. The planarization material 13' can be thermally cured from the holder 20. The planarization material 13' can be cured using optical methods, such as UV curing operations, etc.

[0061] By mechanically contacting the contact head 23 with the surface 111 of the carrier 11, the compression of the planarization material 13' can be well controlled. Furthermore, the planarization material 13' is soft or flexible, and the semiconductor device 12 will not crack or be damaged during the compression operation. Simultaneously, the amount of movement of the semiconductor device 12 can be well controlled.

[0062] After the contact head 23 comes into contact with the surface 111 of the carrier 11, the surface 122t of the conductive element 122 can be substantially parallel to the surface 114t of the conductive element 114. The surface 122t of the conductive element 122 is substantially the same as the surface 114t of the conductive element 114 in terms of elevation.

[0063] After the semiconductor device 12 is mounted on the carrier 11, the holder 12 can be removed to form the semiconductor device package 1, as shown in the reference. Figure 1 The explanation and description.

[0064] Figure 4D Explanation as follows Figure 4C The image shows an enlarged view of a portion of the embodiment of the dashed circle "C" shown. In some other embodiments of this application, the contact head 23 may vary. The contact head 23 may have a contact area ( Figure 4D (Not shown in the image), the contact area may coincide with the surface 111 of the carrier 11. The contact head 23 may have a contact area ( Figure 4D (Not shown in the image), the contact area may conform to the surface 111 of the carrier 11. For example, the carrier 11 may have a sloping surface (e.g., caused by manufacturing deviations or tolerances), and the contact head 23 may be formed conformally to the substantially sloping surface 111.

[0065] Figure 4A , Figure 4B , Figure 4C and Figure 4E This application describes a method for manufacturing a semiconductor device package according to some embodiments.

[0066] The above discussion references Figure 4A , Figure 4B and Figure 4C The operations described herein will be omitted for simplicity in the following description.

[0067] refer to Figure 4E Semiconductor device 14, together with conductive element 142, is bonded to conductive element 114 and conductive element 122 on semiconductor device 12, forming semiconductor device package 2'. The junction 143 between conductive element 142 and conductive element 114 may contain solder balls, solder paste, presolder, or other suitable materials. Similarly, the junction 144 between conductive element 142 and conductive element 122 may contain solder balls, solder paste, presolder, or other suitable materials. According to the method described in this application, junction 143 and junction 144 may be formed substantially coplanar.

[0068] Encapsulation 15 can be used to encapsulate conductive element 122 to form as shown in the reference. Figure 3 The semiconductor device package 2 described and illustrated. The encapsulation 15 may be formed to encapsulate the conductive element 142.

[0069] Encapsulation 15 may comprise epoxy resin. Depending on design specifications, encapsulation 15 may comprise capillary underfill (CUF), molding underfill (MUF), or dispensing gel. Encapsulation 15 may comprise molding materials (e.g., epoxy molding materials or other molding materials). Encapsulation 15 may comprise polyimide. Encapsulation 15 may comprise phenolic compounds or materials. Encapsulation 15 may comprise fillers or particles (e.g., silica particles).

[0070] Figure 4A and Figure 4FThis application describes a method for manufacturing a semiconductor device package according to some embodiments. The above discussion refers to... Figure 4A The operations described herein will be omitted for simplicity in the following description.

[0071] refer to Figure 4F The holder 20' is used to pick up the semiconductor device 12 and place the semiconductor device 12 on the carrier 11. The holder 20' is similar to the reference... Figure 4B or Figure 4C The holder 20 described and illustrated differs in that the contact head 23 is omitted in the holder 20' and the holder 20' further includes an alignment element 21. The alignment element 21 may include an optical emitter, such as, but not limited to, a light-emitting diode (LED), a laser emitter, an infrared light source, etc. The alignment element 21 may include a light receiver or a detector.

[0072] A planarization layer 13' is disposed on the surface 112 of the carrier 11. A holder 20' picks up the semiconductor device 12 containing the conductive element 122. The holder 20' then moves the semiconductor device 12 toward the surface 112 of the carrier 11. An alignment element 21 determines the distance between the alignment element 21 and the surface 112 to control the movement of the holder 20'. After the semiconductor device 12 is disposed on the carrier 11, the holder 12' can be removed to form a semiconductor device package 1, as shown in the reference. Figure 1 The explanation and description.

[0073] However, the accuracy of distance determination can be affected by various parameters, such as the flatness, smoothness, or roughness of the surface 112 of the carrier 11. The accuracy of distance determination can also be affected by optical parameters, such as the color, reflectivity (IOR), or brightness of the carrier 11, or other environmental factors. The movement of the holder 20' and the semiconductor device 12 can be controlled through distance determination.

[0074] In some embodiments where the coplanarity of surfaces 112t and 114t is not critical, a reference can be used. Figure 4A and Figure 4F The methods described and illustrated are used to form such semiconductor device packages.

[0075] Figure 5A This application describes semiconductor device packaging according to some comparative embodiments.

[0076] Carrier 55 is bonded to carrier 51. An adhesive or bonding material is formed on carrier 51. Carrier 55 is bonded to carrier 51 via a connecting element, which may include solder balls. Semiconductor device 52 is attached to carrier 51. Semiconductor device 52 is attached to carrier 51 via adhesive material. After attaching semiconductor device 52 to adhesive material, a curing operation may be performed to cure adhesive material to form adhesive layer 53.

[0077] A connection 551 is formed on the carrier 55. The connection element 551 may be formed by, for example, but not limited to, implantation techniques. The connection element 551 may include conductive bumps or pillars. The connection element 551 may include solder balls.

[0078] A connection element 521 is formed on the semiconductor device 52. The connection element 521 may be formed by, for example, but not limited to, implantation techniques. The connection element 521 may include conductive bumps or pillars. The connection element 521 may include solder balls.

[0079] According to the current comparative example, semiconductor device 54 is bonded to semiconductor device 52 and carrier 55, and a reflow operation is performed to form as shown in the example. Figure 5A The semiconductor device package shown in the image.

[0080] Figure 5B Explanation in such Figure 5A The image shows an enlarged view of a portion of the semiconductor device package within the dashed circle "D". The adhesive layer 53 may have an uneven adhesive line thickness (BLT) caused by the properties of the adhesive (e.g., viscosity, temperature, adhesive volume, etc.). This unevenness in the thickness of the adhesive layer 53 may cause tilting of the semiconductor device 52.

[0081] A height difference may exist within connector 521 (e.g., due to manufacturing variations or tolerances). A height difference may exist within connector 551 (e.g., due to manufacturing variations or tolerances). The height difference in connector 521 may cause tilting of semiconductor device 54. The tilting of semiconductor device 54 may adversely affect the reliability of connectors 521 and 551. The tilting of semiconductor device 54 may adversely affect the performance of the semiconductor device package (e.g., breakage or cracking of connectors 521 and 551).

[0082] Manufacturing or producing solder balls with substantially the same diameter can be challenging. Furthermore, controlling the size or height of solder balls after a reflow operation can be challenging. For example, manufacturing or producing conductive posts with substantially the same height can be challenging because deviations or tolerances are highly likely in certain operations (e.g., plating, etching, or other operations).

[0083] In some comparative embodiments where high control is relatively noncritical, deviations or tolerances as discussed above may be ignored or omitted. In other words, in some comparative embodiments where the horizontal bonding plane or surface (e.g., the virtual plane defined by connecting elements 521 and 551, or the virtual plane defined by adhesive layer 53) is relatively noncritical (e.g., due to the relatively large size of the package), deviations or tolerances as discussed above may not significantly affect the performance of the semiconductor device package. However, in some comparative embodiments requiring high control, deviations or tolerances as discussed above may adversely affect the performance of the semiconductor device package.

[0084] Figure 6A This application describes a semiconductor device package according to some comparative embodiments. A carrier 61 is formed having a notch having surfaces 641 and 642. A semiconductor device 621 is attached to surface 641 of the carrier 61. A semiconductor device 622 is attached to surface 642 of the carrier 61. The semiconductor devices 621 and 622 are attached to the carrier 61 by an adhesive material.

[0085] After the semiconductor devices 621 and 622 are attached to the adhesive material, a planarization operation is applied to the semiconductor devices 621 and 622 by applying pressure to the planarization head. During the planarization operation, the adhesive material is compressed by the semiconductor devices 621 and 622. A curing operation can then be performed to cure the adhesive material, thereby forming adhesive layers 631 and 632.

[0086] A connection 651 is formed on the semiconductor device 621. The connection element 651 may be formed by, for example, but not limited to, implantation techniques. The connection element 651 may include conductive bumps or pillars. The connection element 651 may include solder balls.

[0087] A connection element 652 is formed on the semiconductor device 622. The connection element 652 may be formed using, for example, but not limited to, implantation techniques. The connection element 652 may include conductive bumps or pillars. The connection element 652 may include solder balls.

[0088] According to the current comparative example, semiconductor device 65 is bonded to semiconductor devices 621 and 622, and a reflow operation is performed to form as shown in the example. Figure 6A The semiconductor device package shown in the image.

[0089] Figure 6B Explanation in such Figure 6AThis is an enlarged view of a portion of the semiconductor device package within the dashed circle "E" shown. Depth differences may exist within the notch (e.g., due to manufacturing variations or tolerances). Surface 641 may be formed to be substantially different in elevation from surface 642. After a planarization operation is applied to semiconductor devices 621 and 622 using a planarization head, the bottom surface of semiconductor 621 may contact surface 641. However, the top surface of semiconductor device 621 may be higher than the top surface of semiconductor device 622, causing an elevation difference Δh1 between the top surfaces of semiconductor device 621 and semiconductor device 622. If the planarization head continues to apply force to semiconductor device 621, it may cause semiconductor device 621 to crack or be damaged.

[0090] When semiconductor 65 is deposited on or above semiconductor devices 621 and 622, the non-coplanarity of the top surface of semiconductor device 621 and the top surface of semiconductor 622 may cause tilting of semiconductor device 65. Tilting of semiconductor device 65 may adversely affect the performance of semiconductor device package (e.g., breakage or cracking of interconnects in semiconductor device 65 and semiconductor device 621, and breakage or cracking of interconnects in semiconductor device 65 and semiconductor device 622).

[0091] Figure 6C Explanation in such Figure 6A This is an enlarged view of a portion of the semiconductor device package within the dashed circle "E" shown. A thickness difference may exist between semiconductor devices 621 and 622 (e.g., due to manufacturing variations or tolerances). The thickness of semiconductor device 621 may be greater than the thickness of semiconductor device 622. After a planarization operation is applied to semiconductor devices 621 and 622 using a planarization head, the top surface of semiconductor 621 may be coplanar with the surface 611 of carrier 61. However, the top surface of semiconductor device 621 may not be coplanar with the top surface of semiconductor device 622. The top surface of semiconductor device 621 may be higher than the top surface of semiconductor device 622, causing a horizontal difference Δh2 between the top surfaces of semiconductor devices 621 and 622.

[0092] When semiconductor 65 is deposited on or above semiconductor devices 621 and 622, the non-coplanarity of the top surface of semiconductor device 621 and the top surface of semiconductor 622 may cause tilting of semiconductor device 65. Tilting of semiconductor device 65 may adversely affect the performance of semiconductor device packaging.

[0093] As described in the previous embodiments of this application, surfaces 641 and 642 may be substantially inclined. Surfaces 641 and 642 may be substantially uneven. After semiconductor device 621 is deposited on substantially inclined and / or uneven surface 641 and semiconductor device 622 is deposited on substantially inclined and / or uneven surface 642, the substantially inclined and / or uneven surfaces 641 and 642 in the comparative example cause non-coplanarity of the top surface of semiconductor device 621 and the top surface of semiconductor 622, and further cause tilting of semiconductor device 65 above or on top of semiconductor devices 621 and 622. The tilting of semiconductor device 65 may adversely affect the performance of the semiconductor device package.

[0094] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" parallel might refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “basically” vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0095] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar.

[0096] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0097] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple references. In the description of some embodiments, a component provided “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0098] While this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. Those skilled in the art will readily understand that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be differences between the artistic representation in this application and the actual device due to variations in manufacturing processes, etc. Other embodiments of this application may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this application. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this application.

Claims

1. A semiconductor device package comprising: The carrier (11) has a first substantially uneven surface (112) and a second surface (111 / 113) above the first substantially uneven surface (112); A planarization layer (13) is disposed on the first substantially non-planar surface (112) of the carrier (11) and has a first surface (131) and a second surface (132) opposite to the first surface (131); A first semiconductor device (12) is disposed on the first surface (131) of the planarization layer (13) and has a first surface (121) that is lower than the second surface (111 / 113) of the carrier (11); A first conductive element (114) is disposed on the second surface (113) of the carrier (11) and has a first surface (114t); as well as A second conductive element (122) is disposed on the first surface (121) of the first semiconductor device (12) and has a first surface (122t) that is substantially the same in elevation as the first surface (114t) of the first conductive element (114).

2. The semiconductor device package according to claim 1, wherein the first substantially non-flat surface (112) of the carrier (11) is inclined relative to the first surface (121) of the first semiconductor device (12).

3. The semiconductor device package according to claim 1, wherein the second surface (132) of the planarization layer (13) is substantially non-planar and is bonded to the first substantially non-planar surface (112) of the carrier (11).

4. The semiconductor device package according to claim 1, wherein the planarization layer (13) has a trapezoidal or wedge shape.

5. The semiconductor device package according to claim 1, wherein... The second conductive element (122) has a second surface that contacts the first surface of the first semiconductor device (12), and the second surface of the second conductive element (122) is substantially parallel to the first surface (114t) of the first conductive element (114).

6. The semiconductor device package according to claim 1, wherein the first surface (122t) of the second conductive element (122) is lower than the third surface (111) of the carrier (11), wherein the third surface (111) of the carrier (11) is above the second surface (113) of the carrier (11).

7. The semiconductor device package of claim 1, further comprising a second semiconductor device (14) disposed above and across the first semiconductor device (12) and the first conductive element (114), wherein the second semiconductor device (14) has a first surface (141) facing the first surface (121) of the first semiconductor device (12).

8. The semiconductor device package of claim 7, wherein the first surface (141) of the second semiconductor device (14) is substantially parallel to the first surface (121) of the first semiconductor device (12).

9. The semiconductor device package of claim 7, wherein the second semiconductor device (14) is electrically connected to the first conductive element (114) and the second conductive element (122).

10. The semiconductor device package according to claim 1, wherein the first surface (121) of the first semiconductor device (12) is substantially parallel to the second surface (111 / 113) of the carrier (11).

11. A semiconductor device package comprising: The carrier (11) has a first surface (112), a second surface (113) above the first surface (112) and a third surface (111) above the second surface (113); A first semiconductor device (12) is disposed on the first surface (112) of the carrier (11) and has a first surface (121) that is lower than the third surface (111) of the carrier (11); A first conductive element (114) is disposed on the second surface (113) of the carrier (11) and has a first surface (114t); as well as A second conductive element (122) is disposed on the first surface (121) of the first semiconductor device (12) and has a first surface (122t). The first surface (114t) of the first conductive element is substantially the same in elevation as the first surface (122t) of the second conductive element (122).

12. The semiconductor device package of claim 11, wherein the first surface (122t) of the second conductive element (122) is lower than the third surface (111) of the carrier (11).

13. The semiconductor device package of claim 11, further comprising a second semiconductor device (14) disposed on and across the first semiconductor device (12) and the first conductive element (114), wherein the second semiconductor device (14) has a first surface (141) facing the first surface (121) of the first semiconductor device (12).

14. The semiconductor device package of claim 13, wherein the first surface (141) of the second semiconductor device (14) is substantially parallel to the first surface (121) of the first semiconductor device (12).

15. The semiconductor device package according to claim 11, further comprising a planarization layer (13) disposed between the carrier (11) and the first semiconductor device (12).

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