Digital buffer circuit

Abstract

The present invention is entitled "Digital Buffer Circuit." Circuits and techniques for buffering digital signals are disclosed. These circuits and techniques allow the digital buffer circuit to accommodate a range of output voltages while maintaining a delay between input and output suitable for digital communication. The disclosed circuits and techniques utilize a combination of low-voltage switches and high-voltage switches. When the buffer is driving external circuitry (e.g., a communication bus) that is currently operating at a low voltage, the low-voltage switch dominates the buffering process, and when the buffer is driving external circuitry that is currently operating at a high voltage, the high-voltage switch dominates the buffering process. The high-voltage and low-voltage switches automatically self-configure based on operating conditions determined by the voltage level of the output relative to the voltage level of the input.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application No. 16 / 512,991, filed on July 16, 2019, which in turn claims the benefit of U.S. Provisional Patent Application No. 62 / 820,954, filed on March 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to electronic circuits, and more particularly to high-speed digital buffer circuits with a wide output voltage range. Background Art

[0004] In digital serial communication protocols, the maximum delay can occur between a clock edge and a data transition (i.e., a switch). Digital buffer circuits used to convert between two different voltage domains can significantly impact the delay between a clock edge and a data transition. Digital buffer circuits include an output stage with transistors that switch between the high and low rails of the output voltage domain based on data transitions in the input voltage domain. The transistors in the output stage are designed based on the maximum output voltage the digital buffer circuit is expected to experience. However, as the output voltage decreases from this maximum voltage, the switching speed of these transistors decreases. Summary of the Invention

[0005] Thus, in one general aspect, the present disclosure describes a buffer circuit comprising a plurality of stages, each coupled to a high voltage (HV) power supply and a low voltage (LV) power supply. Each of the plurality of stages includes a push-pull circuit. The push-pull circuit includes an HV PMOS transistor that can be controlled to pull the output of the stage up to the HV power supply when the buffer circuit is in an HV operating condition. The push-pull circuit also includes an LV PMOS transistor that can be controlled to pull the output of the stage up to the LV power supply when the buffer circuit is in an LV operating condition. Under the HV operating condition, the LV power supply is decoupled from the HV power supply by an LV NMOS transistor having an HV source terminal coupled to the output of the stage.

[0006] In one possible implementation, the HV operating condition occurs when the LV power supply provides a regulated voltage and the HV power supply provides a voltage higher than the regulated voltage.

[0007] In another possible implementation, the LV operating condition occurs when the HV power supply provides a voltage lower than the regulated voltage and the HV power supply and the LV provide the same voltage.

[0008] In another possible implementation, the LV PMOS of the buffer circuit may be controlled to pull up the output faster than the HV PMOS under LV operating conditions, and the HV PMOS may be controlled to pull up the output as fast as the LV PMOS under HV operating conditions.

[0009] In another possible implementation, under HV operating conditions, the LV power supply provides a regulated voltage, and the HV power supply provides a voltage higher than the regulated voltage, and under LV operating conditions, both the LV power supply and the HV power supply provide a voltage lower than the regulated voltage. For example, the regulated voltage corresponds to the voltage rating of the LV PMOS.

[0010] In another possible implementation, the LV pull-up circuit of each stage includes an LV NMOS transistor coupled to the LV PMOS transistor and the output via an HV source terminal, and the LV NMOS transistor can be controlled (via an LV signal at a gate terminal) to decouple the LV PMOS transistor from the output under HV operating conditions.

[0011] In another possible implementation, the LV NMOS transistor has a threshold voltage lower than 0.7 volts.

[0012] In another possible implementation, the plurality of stages are connected in series, wherein each stage provides successively higher driving power at the output.

[0013] In another general aspect, the present disclosure describes a method for buffering a digital signal. In this method, upon receiving a logic high signal, a low voltage NMOS transistor is controlled to be turned on. The low voltage NMOS transistor is coupled between the output and ground so that when it is turned on, the output is pulled down to ground. Upon receiving a logic low signal, a high voltage PMOS transistor coupled between the high voltage power supply and the output is controlled to be turned on. In addition, a low voltage PMOS transistor coupled between the low voltage power supply and the output is controlled to be turned on. When both the high voltage PMOS transistor and the low voltage PMOS transistor are turned on, the output is pulled up to the high voltage power supply or the low voltage power supply, depending on the voltage of the high voltage power supply and its relationship to the voltage of the low voltage power supply.

[0014] In another general aspect, the present disclosure describes a system comprising a high voltage power supply that provides a high voltage (VDD_HV). The system also includes an internal voltage regulator coupled to the high voltage power supply and providing a low voltage (VDD_LV). When VDD_HV is greater than a regulated voltage, VDD_LV is equal to the regulated voltage, and when VDD_HV is less than the regulated voltage, VDD_LV is equal to VDD_HV. The system further includes a digital buffer circuit. The digital buffer circuit is configured to minimize the delay between an input and an output by, upon receiving a logic high at the input, pulling the output up to VDD_HV using an HV PMOS transistor when VDD_HV is greater than the regulated voltage and pulling the output up to VDD_LV using an LV PMOS transistor when VDD_HV is less than the regulated voltage.

[0015] In one possible implementation, the system includes a bus connected to an output of the digital buffer circuit and a core memory connected to an input of the digital buffer circuit.

[0016] In another possible implementation of the system, VDD_HV is in the range of 1.2 volts to 5.6 volts, and VDD_LV is in the range of 1.2 volts to 2.0 volts, and the regulated voltage is 2 volts.

[0017] The foregoing illustrative summary, as well as other exemplary objects and / or advantages of the present disclosure, and the manner in which they are achieved, are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram of a system including a digital buffer circuit according to an implementation of the present disclosure.

[0019] Figure 2 Exemplary input and output signals of a digital buffer circuit according to an implementation of the present disclosure are shown.

[0020] Figure 3 is a block diagram of a digital buffer circuit according to a specific implementation of the present disclosure.

[0021] Figure 4 This is a schematic diagram of a push-pull circuit.

[0022] Figure 5 is a schematic diagram of a push-pull circuit and a low-voltage pull-up circuit for a digital buffer circuit according to a specific implementation of the present disclosure.

[0023] Figure 6 is a schematic diagram of a digital buffer circuit according to a specific implementation of the present disclosure.

[0024] Like reference numerals designate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION

[0025] The disclosed digital buffer circuit advantageously accommodates a range of output voltages while reducing (or eliminating) corresponding speed variations within that range. In other words, the disclosed digital buffer circuit does not slow down as the output voltage (VDD_HV) decreases (i.e., decreases from its maximum value).

[0026] Figure 1 1 is a block diagram of a system 100 using a digital buffer circuit 110 (i.e., a buffer circuit) according to an embodiment of the present disclosure. The digital buffer circuit 110 relates (i.e., converts) an input digital signal in an input (i.e., internal, core) voltage domain to an output digital signal in an output (i.e., external, bus) voltage domain. The input voltage domain may be defined by a supply (i.e., power supply) voltage between a reference (e.g., ground) voltage and a high rail voltage (VDD_LV), and the output voltage domain may be defined by a supply voltage between a reference (e.g., ground (GND)) voltage and a high rail voltage (VDD_HV). VDD_LV may be fixed by an internal voltage regulator 120 (e.g., a linear regulator, a voltage clamp), even though VDD_HV may vary. The digital buffer circuit 110 allows internal core circuitry operating on VDD_LV to communicate with various external circuitry 140 (e.g., an external bus) operating within a range of possible VDD_HV.

[0027] In one possible implementation, system 100 may include core memory circuitry (i.e., core memory) with digital and mixed-signal integrated circuits (ICs). For this implementation, internal circuitry 130 is core logic including low-voltage devices that cannot tolerate voltages above a maximum voltage less than 2 volts (V) (e.g., 1.1 V). Internal voltage regulator 120 ensures that the internal voltage does not rise above this maximum (low) voltage even when the external voltage (i.e., VDD_HV) rises above this voltage. External circuitry 140 may be a communication bus (i.e., bus). To allow the core logic to communicate with various types of buses (e.g., with different VDD_HVs), digital buffer circuit 110 may be designed to accommodate a range of VDD_HVs. For example, while the input voltage (i.e., VDD_LV) of the digital buffer circuit may be fixed at 1.1 V, the output voltage (i.e., VDD_HV) may vary between 1.1 V and 5.6 V.

[0028] In the present disclosure, relative terms (e.g., low / high) may be used to describe voltages. A low voltage (LV) may be considered to correspond to a voltage in an input voltage domain (e.g., VDD_LV). A high voltage (HV) may be considered to correspond to a voltage in an output voltage domain (e.g., VDD_HV). Since the buffer circuit can be configured to provide a range of output voltages (VDD_HV), the terms low voltage (LV) and high voltage (HV) may also be used to describe the state of VDD_HV in relation to the input voltage (VDD_LV). Table 1 below illustrates the voltage domain relationship for LV operating conditions and HV operating conditions, as well as the relationship to a regulated voltage (VREG), which may be considered to be the boundary between LV and HV.

[0029] Table 1: LV operating conditions and HV operating conditions

[0030] LV operating conditions HV operating conditions Voltage domain relationship VDD_LV≈VDD_HV VDD_LV <VDD_HV Relationship with VREG VDD_LV≈VDD_HV≤VREG VDD_LV≈VREG<VDD_HV

[0031] The terms low voltage (LV) and high voltage (HV) may also be used to describe devices. LV devices, lines and / or terminals may be considered to have voltage ratings (i.e., low voltage ratings) and / or sizes suitable for (safe) operation at a voltage corresponding to an input voltage (e.g., VDD_LV). HV devices, lines and / or terminals may be considered to have voltage ratings (i.e., high voltage ratings) and / or sizes suitable for (safe) operation at a voltage corresponding to a (maximum) output voltage (e.g., VDD_HV). For the exemplary implementation shown in Table 1, the LV devices are rated for VREG (e.g., 2V). Therefore, an internal voltage regulator 120 (see Figure 1 ) ensures that the LV devices are supplied with a regulated voltage VREG (e.g., 2V), which is the maximum voltage suitable for use with the LV devices (i.e., maximum LV). Under LV operating conditions, VDD_HV is less than or equal to VREG (e.g., 2V), and the HV and LV supplies provide the same voltage (VDD_LV = VDD_HV) because the voltage regulator is not activated. Under this operating condition, it is as if only one power supply is being used. However, when VDD_HV is higher than VREG (e.g., 2V), VDD_LV is kept regulated at VREG (e.g., 2V) by the internal voltage regulator. In this case, the HV devices are used and powered by VDD_HV (i.e., a voltage greater than 2V), while the LV devices are powered by VDD_LV (i.e., 2V).

[0032] Compared to LV transistors designed to switch lower voltages / currents, HV transistors designed to switch high voltages / currents can be physically larger (e.g., with larger channel sizes) and may have greater switching capacitance. Consequently, digital buffer circuit 110 may exhibit slow switching speeds, particularly under LV operating conditions. For example, a digital buffer circuit designed to drive external bus 140 at a 5.6V high rail voltage may operate more slowly when used to drive external bus 140 at a 1.1V high rail voltage. For other applications, this speed reduction can be even more severe. For example, an EEPROM process may have core circuitry utilizing 2V (low voltage) transistors, which are buffered to drive a pad periphery having external circuitry utilizing 20V (high voltage) transistors. The disclosed digital buffer circuit advantageously accommodates a range of output voltages while reducing (or eliminating) the corresponding speed variations within that range. In other words, the disclosed digital buffer circuit does not slow down as the output voltage (VDD_HV) decreases (i.e., decreases from its maximum value).

[0033] The switching speed of a digital buffer circuit corresponds to the communication rate (i.e., data rate, speed, and bandwidth) it can support. For example, an external communication bus may utilize a communication protocol with a data rate of 20 megabits per second (Mb / s). Ideally, the digital buffer circuit transmits the signal from its input (IN) to its output (OUT) with little (or no) distortion (e.g., delay) at all data rates. In practice, a digital buffer circuit may be limited by the delay between the input and output signals. This delay may become more significant as the data rate increases and limit the maximum communication rate.

[0034] Figure 2Schematic diagram illustrating exemplary input and output signals of a digital buffer circuit according to a specific embodiment of the present disclosure. The digital buffer circuit (i.e., buffer circuit, buffer) receives an input signal 200 in a voltage domain corresponding to VDD_LV and transmits an output signal 210 in a voltage domain corresponding to VDD_HV. The output signal 210 may be a delayed version of the input signal, having a first delay 220 between the rising edge of the input signal 200 and the rising edge of the output signal 200, and a second delay 230 between the falling edge of the input signal 200 and the falling edge of the output signal 210. The fidelity of digital communication may correspond to the magnitude of the first delay and / or the second delay. Thus, communication protocols (e.g., I3C, SPI) may specify a maximum acceptable delay for communication. Therefore, a digital buffer circuit having a first delay and a second delay that are less than a specified value and as close to zero as possible may provide advantages for high-speed communication. As previously described, the speed of the buffer may correspond to the size of the switching devices and the voltage that drives them. For a certain speed (e.g., 20 Mb / s) and voltage range (e.g., ≥4 V), the buffer's delay is below a specified value (e.g., less than about 10 nanoseconds), so the buffer's speed can be limited by such speed and voltage range.

[0035] Figure 3 A block diagram of one possible implementation of the digital buffer circuit 110 is shown in FIG. The buffer circuit 110 receives an input signal (LV-IN) at an input 310. The input signal (LV-IN) may be a relatively low voltage digital signal having a logic high corresponding to VDD_LV and a logic low corresponding to ground. In other words, the input signal may be in a low voltage (LV) domain and the output signal may be in a high voltage (HV) domain. Figure 3 , the portion of the circuit in the low voltage (LV) domain and the portion of the circuit in the high voltage (HV) domain are indicated by the width of the line representing the signal flow.

[0036] like Figure 3 As shown, the buffer circuit 110 may include a logic subcircuit 320 (ie, logic). The logic includes logic gates, clocks, and timing circuits to enable the switching of the buffer circuit. In some implementations, the buffer circuit receives an enable signal (EN) (see Figure 1). For these specific implementations, logic 320 may enable / disable some or all of the functionality of buffer circuit 110 based on the state of an enable signal (EN) (i.e., logic high, logic low). In addition, the logic may condition the signal at the input to a signal suitable for controlling level shifter sub-circuit 340. For example, the logic may create (e.g., generate) a pair of digital signals including a first signal suitable for driving a P-channel switching device (e.g., with a pull-up voltage) and a second signal suitable for driving an N-channel switching device (e.g., with a push-down voltage). In some embodiments, additional logic circuitry may be applied to the first and second signals to prevent (or reduce) situations in which the first and second signals have logic states that could control the P-channel switching device and the N-channel switching device to conduct simultaneously, which could create an undesirable situation in buffer circuit 110 (e.g., simultaneous pull-up and push-down). In other words, the additional logic circuitry may be used to prevent overlapping states of the buffer.

[0037] like Figure 3 As shown, the buffer circuit 110 may include a level shifter sub-circuit 330 (i.e., a level shifter). The level shifter 330 includes a switching device (e.g., a transistor) and is connected to the power supply of the HV domain. The switching device can be controlled by a logic signal at the output of the logic 320 to connect the output of the level shifter sub-circuit to a logic high (e.g., VDD_HV) in the HV domain or a logic low (e.g., ground) in the HV domain based on the LV digital signal at its input.

[0038] The level shifter 330 may include a level shifter (LS) output circuit (ie, LS output) 340 . Figure 4 A specific implementation of the LS output 340 as a push-pull circuit 400 is schematically shown. The push-pull circuit (i.e., push-pull) 400 may include a P-channel metal oxide semiconductor (i.e., PMOS) transistor 410 coupled to an N-channel metal oxide semiconductor (i.e., NMOS) transistor 420. These transistors are connected in series between a high rail (e.g., VDD_HV) and a low rail (i.e., ground) of the output voltage domain. The PMOS transistor 410 is connected to a first input 412, while the NMOS transistor 420 is connected to a second input 414. The output 415 of the push-pull circuit is a node between the series-connected PMOS and NMOS transistors. In other words, the source terminal of the PMOS transistor may be connected to the power supply voltage VDD_HV, the drain terminal of the PMOS transistor may be connected to the output of the push-pull circuit, and the gate of the PMOS transistor may be connected to the first input of the push-pull circuit. Additionally, the source terminal of the NMOS transistor may be connected to a reference voltage (GND), the drain terminal of the NMOS transistor may be connected to the output of the push-pull circuit, and the gate of the NMOS transistor may be connected to the second input of the push-pull circuit.

[0039] In operation, digital signals can be provided (e.g., via logic 320) at first input 412 and second input 414. When first input 412 is at a logic low level (i.e., a threshold voltage below VDD_HV) and second input 414 is at a logic low level (i.e., below the threshold voltage), the PMOS transistor conducts (i.e., is turned on) and the NMOS transistor does not conduct (i.e., is turned off). In this state, output 415 is pulled up to approximately the high rail voltage VDD_HV, which functions as a logic high for the circuit's output voltage domain (i.e., the HV domain). When first input 412 is at a logic high level (i.e., equal to or above a threshold voltage below VDD_HV) and second input 414 is at a logic high level (i.e., above the threshold voltage), the PMOS transistor does not conduct (i.e., is turned off) and the NMOS transistor conducts (i.e., is turned on). In this state, output 415 is pushed down to ground, which functions as a logic low for the circuit's output voltage domain (i.e., the HV domain).

[0040] The size of the PMOS / NMOS transistors of the push-pull circuit can depend on the current level pulled or sunk during the push-pull operation. For example, as the required current increases, the size of the transistors can also increase. Without sufficient power to drive the gate of each transistor, it can be difficult to quickly switch large transistors. In addition, operating large transistors at a reduced VDD_HV can reduce the switching speed of the large transistors. For these reasons, additional stages can be used for the buffer circuit 110.

[0041] like Figure 3 As shown, the first (HV) stage (i.e., STAGE1) at the output of the level shifter (i.e., LS output 340) may be followed by a second, larger (HV) stage (i.e., STAGE2). The second stage is a driver circuit (i.e., driver 350), which operates in the same manner as LS output 340 (i.e., in a push-pull manner) and includes circuitry configured to drive more power (e.g., current) at the output. Driver 350 reduces the drive requirements of LS output 340 while generating a larger drive signal to control the third, larger (HV) stage (i.e., STAGE3). The third stage is a buffered output 360, which also operates in a push-pull manner to drive output 370 (i.e., HV-OUT). While more or fewer stages can be used, in some implementations, using three stages of increasing size (i.e., STAGE1, STAGE2, STAGE3) can achieve a good balance between low drive strength (i.e., too few stages) and high latency / complexity (i.e., too many stages).

[0042] In summary, Figure 3A specific implementation of buffer circuit 110 includes three stages, each of which performs a push-pull operation, which involves using a switching device controlled by an input voltage to pull up or push down (i.e., pull down) the output voltage. While each stage may function identically, its size (e.g., device size) and strength (e.g., drive strength) may vary. In other words, each stage can sequentially provide high drive power at the output (i.e., to drive the next stage).

[0043] In addition to using multiple stages, the disclosed circuits and techniques also provide push-pull operation of each stage using a combination of HV and LV switching devices, thereby allowing high-speed buffering with high voltage handling capabilities. In other words, the digital buffer circuit is able to operate over a range of output voltages while maintaining high speed. For example, the disclosed circuits and techniques can operate at low output voltages (i.e., relative to the input voltage) or high output voltages (i.e., relative to the input voltage) with little delay variation (i.e., with a significant speed drop) between the input and output signals of the buffer.

[0044] The disclosed circuits and techniques utilize multiple stages. Each stage can include a combination of LV switching devices and HV switching devices, such that the LV devices dominate operation under LV operating conditions, while the HV devices dominate operation under HV operating conditions. For example, a possible LV operating condition might be VDD_LV≈VDD_HV=1.1V, and a possible HV operating condition might be VDD_LV=1.1V and VDD_HV=5.6V. Furthermore, the disclosed circuits and techniques do not require any sensing of voltage domains to determine specific operating conditions or how to apply LV or HV devices for specific operating conditions.

[0045] Figure 5 yes Figure 3 The circuit topology of stage 500 can be used to Figure 3 Each of the multiple stages (eg, STAGE1, STAGE2, and STAGE3) in the digital buffer circuit. Figure 3 The stages in may include switching devices (eg, HV switching devices) of different sizes (eg, increasing from STAGE1 to STAGE3 size). Figure 5 The stage 500 shown includes HV parts / devices and LV parts / devices. The HV circuit parts / devices are shown with thicker lines than the LV circuit parts / devices. In addition, nodes are indicated as HV or LV.

[0046] like Figure 5As shown, stage 500 includes a push-pull circuit portion 510 that is controlled by a first push-pull input 512 and a second push-pull input 514 and is powered by the HV supply voltage VDD_HV. Push-pull circuit portion 510 is coupled to an output 530 of stage 500. In addition, stage 500 includes a low voltage pull-up circuit portion (i.e., LV pull-up) 520 that is also coupled to output 530. The LV pull-up is controlled by a first pull-up input 522 and a second pull-up input 524.

[0047] The push-pull circuit portion 510 includes an LV NMOS transistor fabricated using a process technology (e.g., ONC18EE non-volatile memory technology) that includes features (e.g., a thin oxide layer) that allow an LV signal at the gate terminal (i.e., the push-pull input 514) to control an LV NMOS transistor 513, thereby switching an HV signal at the drain (and source) terminal (i.e., coupled to the output 530). In other words, the HV drain terminal 515 of the LV NMOS 513 is capable of withstanding (i.e., tolerant of) a high voltage, while the gate terminal (i.e., the second push-pull input 514) is rated for a low voltage, which allows the LV NMOS transistor to be turned on and off quickly. The LV NMOS 513, having the HV drain terminal 515, is smaller than the HV NMOS (e.g., has a smaller switching capacitance). Thus, LV NMOS 513 with HV drain 515 allows push-pull circuit portion 510 to pull output 530 down to logic low faster than HV NMOS with HV gate. Stage 500 can perform pull-down under any operating condition (see Table 1) using LV NMOS 513 with HV drain 515.

[0048] The push-pull circuit portion 510 also includes a high voltage PMOS transistor (i.e., HV PMOS) 511. Due to the switching relationship between the operation of the PMOS transistor and the HV power supply (VDD_HV), the HV PMOS 511 can be controlled by the HV signal. For example, in order to turn off the HVPMOS, the voltage applied to the gate terminal (i.e., the first push-pull input 512) can be about VDD_HV (i.e., VDD_HV-VT). When the HV power supply voltage is large (i.e., VDD_HV>VDD_LV), the pull-up operation of stage 500 is provided by the HV PMOS 511. Since the HV PMOS is operating under HV conditions, the switching speed is relatively fast. When the HV power supply voltage is small (i.e., VDD_HV≈VDD_LV), the speed of the HV PMOS is slow. Under this operating condition, the pull-up operation can be performed faster by the (auxiliary) LV pull-up 520.

[0049] The voltage pull-up of the output 530 under low-voltage (i.e., VDD_HV≈VDD_LV) operating conditions is performed by the LV pull-up circuit section (i.e., LV pull-up) 520. The LV pull-up includes a low-voltage PMOS transistor 521 (i.e., LV PMOS), which can be controlled by a low-voltage signal at the gate terminal 522 to pull the output 530 of the HV stage to the power rail VDD_LV. Under low-voltage operating conditions, the LV PMOS transistor 521 can switch faster than the HV PMOS transistor. Therefore, even under low-voltage operating conditions, the speed of the pull-up operation is not slowed down.

[0050] The LV pull-up 520 also includes a low-voltage low-threshold NMOS transistor (i.e., low-threshold NMOS) 523, which is controlled by an LV signal at the gate terminal 524 to conduct when the LV PMOS is conducting. The output 530 is pulled up by the low-threshold NMOS and the LV PMOS 521. The low (i.e., compared to 0.7V) threshold of the low-threshold NMOS 523 reduces the voltage drop across the device, causing the output 530 to be pulled closer to VDD_LV. Under LV operating conditions (i.e., VDD_LV≈VDD_HV), the LV PMOS 521 can be conducted faster than the HV PMOS 511. Therefore, the contribution of the HV PMOS 511 to the pull-up of the output 530 is reduced or eliminated.

[0051] The low-voltage low-threshold NMOS transistor 523 (i.e., low-threshold NMOS) includes a HV-tolerant source terminal (i.e., HV source terminal 525), which can be controlled by the voltage between the gate terminal 524 and the HV source terminal 525 to oppose current (i.e., cut off). This low-voltage NMOS transistor with a HV source prevents (and / or reduces) the coupling between the high-voltage rail VDD_HV and the low-voltage rail VDD_LV under high-voltage (i.e., VDD_HV>VDD_LV) operating conditions. Under HV operating conditions (i.e., VDD_LV<VDD_HV), the HV PMOS 511 is driven to conduct to pull the output 530 up to VDD_HV. Roughly simultaneously (i.e., due to no power sensing), the LV PMOS 521 is driven to conduct. The switching speed of the HV PMOS transistor and the switching speed of the LV PMOS transistor are approximately the same under HV conditions. Therefore, the low-voltage low-threshold NMOS transistor 523 is cut off by a negative gate-source voltage. Therefore, this NMOS transistor is used to decouple the LV pull-up 520 circuit section for HV operating conditions.

[0052] The disclosed circuits and techniques describe the use of multiple stages (i.e., HV stages) to increase the speed of each stage while keeping the overall drive capability unchanged. In another aspect, the disclosed circuits and techniques describe a push-pull circuit portion for each stage that utilizes a low voltage NMOS transistor with a high voltage tolerant drain (i.e., an HV tolerant drain) to pull the output voltage down to ground when controlled by a low voltage input signal at its gate. In another aspect, the disclosed circuits and techniques include an LV pull-up circuit portion for pulling the output of the stage up to VDD_LV under LV operating conditions. In another aspect, the disclosed circuits and techniques describe the use of low voltage low threshold NMOS transistors to decouple the LV pull-up circuit portion from the output of the stage under HV operating conditions, and allow the circuit to use HV devices under HV operating conditions and LV switching devices under LV operating conditions without the need for sensing the operating conditions (e.g., active sensing).

[0053] Figure 6 A schematic diagram of a specific implementation of a digital buffer circuit is shown in FIG. The schematic diagram shows the portion of the circuit corresponding to three stages (i.e., STAGE1, STAGE2, and STAGE3). Each stage includes a push-pull circuit (i.e., PP1, PP2, and PP3, respectively) and an LV pull-up circuit (i.e., PU1, PU2, and PU3, respectively). The push-pull circuit of the first stage (i.e., PP1) is not shown in detail because it is part of the level shifter. Each stage includes a push-pull circuit portion and an LV circuit portion, which are arranged according to the Figure 5 The operation is performed as described in the exemplary stages shown in FIG. Figure 6 , HV circuits and devices are indicated by thicker lines than those used for LV circuits and devices. The digital buffer circuit is powered by a low voltage supply (VDD_LV) and a high voltage supply (VDD_HV), which describe the operating conditions of the digital buffer circuit 600 based on their respective values. The digital buffer circuit 600 receives a digital signal at an input (IN) having a logic value corresponding to a first power domain (e.g., VDD_LV) and drives a corresponding output digital signal having a logic value corresponding to a second power domain (e.g., VDD_HV at an output (OUT)).

[0054] Digital buffer circuit 600 includes logic circuitry (i.e., logic) 610. This logic receives a digital enable signal (EN). When disabled, the state of the enable signal (i.e., logic high / low) causes the logic to disable all or part of the operation of the digital buffer circuit. When digital is enabled, logic 610 also receives a digital input signal and, based on the digital input signal, generates control signals for various circuitry within the buffer circuit. For example, the logic can generate a pair of low-voltage signals (i.e., IN_P, IN_PB) corresponding to the input signal for input to level shifter 620. These signals can also control the switching devices of LV pull-up PU1 to be (simultaneously) turned on or off. Additionally, logic 610 can create a pair of signals (i.e., PPUD_LV, NPUD_LV) for controlling the switching devices of the LV pull-up (PU2) of the driver stage (STAGE2) to be (simultaneously) turned on or off. Additionally, logic 610 can create a pair of signals (i.e., PPUD_LV, NPUD_LV) for controlling the switching devices of the LV pull-up (PU3) of the output stage (STAGE3) to be (simultaneously) on or off. Logic 610 can also generate a signal (PDD_LV) for controlling the pull-down switching devices of the push-pull stage (i.e., PP2) of the driver stage (i.e., STAGE2). Logic 610 can also generate a signal (i.e., PDO_LV) for controlling the pull-down switching devices of the push-pull stage (i.e., PP3) of the output stage (i.e., STAGE3). The corresponding signals can be timed based on the input signal so that there is no overlap between the states of the switching devices. Therefore, the logic circuit may include logic gates and timing to perform non-overlapping operations.

[0055] In the specification and / or drawings, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The drawings are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise indicated, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.

[0056] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like.

[0057] Although certain features of the described implementations have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented by way of example only and not limitation, and that various changes in form and detail are possible. Except for mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

Claims

1. A buffer circuit, comprising: a plurality of stages, each of the plurality of stages being coupled to a high voltage HV power supply and a low voltage LV power supply, wherein each stage comprises: a push-pull circuit comprising an HV PMOS transistor controllable to pull the output of the stage up to the HV power supply when the buffer circuit is in a high voltage (HV) operating condition; and an LV pull-up circuit including an LV PMOS transistor controllable to pull up the output of the stage to the LV power supply when the buffer circuit is in a low-voltage (LV) operating condition, wherein in the high-voltage (HV) operating condition, the LV power supply is decoupled from the HV power supply by an LV NMOS transistor having an HV source terminal coupled to the output of the stage.

2. The buffer circuit according to claim 1, wherein: Under the high voltage (HV) operating condition, the LV power supply provides a regulated voltage, and the HV power supply provides a voltage higher than the regulated voltage; and Under the low voltage (LV) operating condition, both the LV power supply and the HV power supply provide a voltage lower than the regulated voltage.

3. The buffer circuit according to claim 1, wherein The push-pull circuit of each stage further comprises: an LV NMOS transistor coupled to the HV PMOS transistor and the output via an HV drain terminal; and The LV NMOS transistor is controllable by an LV signal at a gate terminal to pull the output down to a ground voltage when the buffer circuit is in the high voltage (HV) operating condition or in the low voltage (LV) operating condition.

4. The buffer circuit according to claim 1, wherein The LV pull-up circuit of each stage includes: an LV NMOS transistor coupled to the LV PMOS transistor and the output via an HV source terminal; and The LV NMOS transistor is controllable by an LV signal at a gate terminal to decouple the LVPMOS transistor from the output under high voltage (HV) operating conditions.

5. A method for buffering a digital signal, the method comprising: When receiving a logic high signal, controlling a low voltage NMOS transistor coupled between the output and the ground to be turned on so that the output is pulled down to the ground; as well as When a logic low signal is received, a high-voltage PMOS transistor coupled between a high-voltage power supply and the output is controlled to be turned on, and a low-voltage PMOS transistor coupled between a low-voltage power supply and the output is controlled to be turned on, so that the output is pulled up to the high-voltage power supply or the low-voltage power supply depending on the respective switching speeds of the high-voltage PMOS and the low-voltage PMOS, and the respective switching speeds are determined by the voltage of the high-voltage power supply and the relationship between the voltage of the high-voltage power supply and the voltage of the low-voltage power supply.

6. The method according to claim 5, wherein: When the voltage of the high voltage power supply is greater than the regulated voltage and the voltage of the low voltage power supply is equal to the regulated voltage, the output is pulled up to the high voltage power supply; and When the voltage of the high voltage power supply is less than the regulated voltage and the voltage of the low voltage power supply is equal to the high voltage power supply, the output is pulled up to the low voltage power supply.

7. A system for buffering a digital signal, the system comprising: Provides a high voltage power supply of a high voltage VDD_HV; an internal voltage regulator coupled to the high voltage power supply and providing a low voltage VDD_LV, wherein VDD_LV is equal to the regulated voltage when VDD_HV is greater than the regulated voltage, and VDD_LV is equal to VDD_HV when VDD_HV is less than the regulated voltage; A digital buffer circuit configured to reduce a delay between an input and an output upon receiving a logic high at the input by: When VDD_HV is greater than the regulated voltage, pulling the output up to VDD_HV using a HV PMOS transistor; and When VDD_HV is less than the regulated voltage, the output is pulled up to VDD_LV using the LV PMOS transistor.

8. The system according to claim 7, wherein: The digital buffer circuit is further configured to minimize a delay between the input and the output upon receiving a logic low at the input by: The output is pulled down to ground using a LV NMOS transistor with a high voltage drain.

9. The system of claim 7, wherein: When VDD_HV is less than the regulated voltage, preventing the HV PMOS transistor from pulling up the output by the LV PMOS transistor because the LV PMOS transistor pulls up the output before the HV PMOS can turn on; and When the output is pulled up to VDD_HV and VDD_HV is greater than VDD_LV, the LV PMOS transistor is prevented from pulling up the output by a low voltage low threshold NMOS transistor that decouples the LV PMOS transistor from the output.

10. The system according to claim 7, wherein: The digital buffer circuit includes a plurality of stages connected in series, each stage being similarly configured to minimize delay between input and output, and each stage having successively larger LV PMOS transistors and HV PMOS transistors to drive more power at the output.

11. The system of claim 7, further comprising a level shifter and logic configured to receive an input signal to generate a signal to control the level shifter, the logic including circuitry for preventing overlapping conditions in the level shifter.

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