Display device and method for testing the same

Abstract

A display device and a method for testing the display device are provided. The display device includes: a display panel, including signal lines located in a display area and a peripheral area, the signal lines extending in a column direction and separated; and test lines electrically connected to the signal lines in the peripheral area, extending in a column direction and arranged to be separated. The peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area. The test lines include: a first test line, including a 1-1 test portion arranged on the first peripheral area and a 1-2 test portion arranged on the second peripheral area; and a second test line, including a 2-1 test portion arranged on the second peripheral area. The width of the 1-1 test portion of the first test line is greater than the width of the 1-2 test portion of the first test line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0033704, filed on Mar. 25, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a display device and a method of testing the display device. Background Art

[0003] Typically, a liquid crystal display device may include an array substrate, a gate driving circuit and a data driving circuit, wherein the array substrate is provided with a plurality of gate lines, a plurality of data lines and a plurality of pixels, the gate driving circuit outputs a gate signal to the gate lines, and the data driving circuit outputs a data signal to the data lines.

[0004] Each pixel includes a pixel electrode and a thin film transistor, and the thin film transistor is connected to the gate line, the data line, and the pixel electrode to drive the pixel.

[0005] In the aforementioned liquid crystal display device, various tests may be performed during the manufacturing process. For example, during the manufacturing process of the liquid crystal display device, a data line continuity test may be performed in a contact manner or a non-contact manner to determine whether any data line is disconnected or shorted.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] The device and method constructed according to the exemplary embodiments of the invention can provide a device having high test reliability of a data line during the aforementioned test process.

[0008] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0009] According to one or more exemplary embodiments of the invention, a display device includes: a display panel including a display area and a peripheral area arranged at one side of the display area in a column direction; a plurality of gate lines located on the display area of ​​the display panel, the plurality of gate lines extending in a row direction crossing the column direction; a plurality of data lines insulated from and crossing the plurality of gate lines, the plurality of data lines being located on the display area and the peripheral area, extending in the column direction, and spaced apart from each other along the row direction; and a plurality of test lines electrically connected to the plurality of data lines in the peripheral area, the plurality of test lines being ... The test lines extend in a column direction and are arranged to be separated from each other along a row direction, wherein the peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area, wherein the multiple test lines include: a first test line including a 1-1 test portion arranged on the first peripheral area and a 1-2 test portion arranged on the second peripheral area; and a second test line including a 2-1 test portion arranged on the second peripheral area, and wherein a width of the 1-1 test portion of the first test line in the row direction is greater than a width of the 1-2 test portion of the first test line in the row direction.

[0010] A width of the second test line in the row direction may be greater than a width of the 1-2 test portion of the first test line in the row direction.

[0011] The plurality of test lines may further include a third test line extending in a column direction and separated from the first test line, with the second test line located between the third test line and the first test line, the third test line including: a 3-1 test portion arranged on the first peripheral area; and a 3-2 test portion arranged on the second peripheral area.

[0012] The width of the 3-1 test section of the third test line in the row direction may be greater than the width of the 3-2 test section of the third test line in the row direction, and the width of the second test line in the row direction may be greater than the width of the 3-2 test section of the third test line in the row direction.

[0013] The plurality of test lines may further include a fourth test line extending in a column direction and spaced apart from the second test line, with the third test line located between the fourth test line and the second test line, and the fourth test line includes a 4-1 test portion disposed on the second peripheral area.

[0014] A width of the fourth test line in the row direction may be greater than a width of the 3-2 test portion of the third test line in the row direction.

[0015] The first test line and the third test line may extend longer than the second test line and the fourth test line in the column direction.

[0016] The 2-1 test section of the second test line may be located between the 1-2 test section of the first test line and the 3-2 test section of the third test line, and the 2-1 test section of the second test line may not overlap with the 1-1 test section of the first test line and the 3-1 test section of the third test line in the row direction.

[0017] The second test line may further include a 2-2 test portion disposed on the first peripheral area, and a width of the 2-1 test portion of the second test line in the row direction may be greater than a width of the 2-2 test portion of the second test line in the row direction.

[0018] The 2-2 test section of the second test line may be located between the 1-1 test section of the first test line and the 3-1 test section of the third test line.

[0019] The plurality of test lines may be arranged on the same layer as the plurality of data lines, and the plurality of test lines and the plurality of data lines may be formed by the same process.

[0020] The display device may further include: a pad area to which the printed circuit board is attached, wherein the pad area is located opposite to the peripheral area with respect to the display area.

[0021] According to one or more exemplary embodiments of the invention, a display device includes: a display panel including a display area and a peripheral area disposed at one side of the display area in a row direction; a plurality of data lines located on the display area of ​​the display panel, the plurality of data lines extending in a column direction crossing the row direction; a plurality of gate lines insulated from and crossing the plurality of data lines, the plurality of gate lines being located on the display area and the peripheral area and extending in the row direction and spaced apart from each other in the column direction; and a plurality of gate test lines electrically connected to the plurality of gate lines in the peripheral area, the plurality of gate test lines extending in the row direction. Extending upward and arranged to be separated from each other along the column direction, wherein the peripheral area includes: a first peripheral area; and a second peripheral area, located between the display area and the first peripheral area, wherein the plurality of gate test lines include: first gate test lines, each including a 1-1 test portion arranged on the first peripheral area and a 1-2 test portion arranged on the second peripheral area; and second gate test lines, each including a 2-1 test portion arranged on the second peripheral area, and wherein the width of the 1-1 test portion of the first gate test line in the column direction is greater than the width of the 1-2 test portion of the first gate test line in the column direction.

[0022] A width of the second gate test line in the column direction may be greater than a width of the 1-2 test portion of the first gate test line in the column direction, and each of the second gate test lines may be disposed between adjacent first gate test lines.

[0023] According to one or more exemplary embodiments of the invention, a method for testing a display device includes the following steps: sequentially applying a first electrical signal to a data line by moving a signal applying device along a first direction; while sequentially applying the first electrical signal to the data line, sequentially sensing a first test signal from a first peripheral area by moving a signal sensing device in the first direction; sequentially applying a second electrical signal to the data line by moving the signal applying device along the first direction; while sequentially applying the second electrical signal to the data line, sequentially sensing a second test signal from a second peripheral area by moving the signal sensing device in the first direction; filtering the second test signal received from the signal sensing device to generate a filtered second test signal; and using the first test signal and the filtered second test signal to determine whether there is a short circuit and a break in the data line.

[0024] The plurality of test lines may be electrically connected to the data lines arranged in the display area, and the second peripheral area is located between the display area and the first peripheral area.

[0025] The multiple test lines may include: a first test line, including a 1-1 test portion arranged on a first peripheral area and a 1-2 test portion arranged on a second peripheral area; and a second test line, including a 2-1 test portion arranged on the second peripheral area, and a width of the 1-1 test portion of the first test line in the first direction may be greater than a width of the 1-2 test portion of the first test line in the first direction.

[0026] Each of the second test lines may be disposed between adjacent first test lines.

[0027] An average width of pulses of the second test signal sensed through the 1-2 test section of the first test line may be smaller than an average width of pulses of the first test signal sensed through the 1-1 test section of the first test line.

[0028] An average width of a pulse of the second test signal sensed through the 2-1 test section of the second test line may be greater than an average width of a pulse of the second test signal sensed through the 1-2 test section of the first test line.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0031] Figure 1 is a schematic plan layout diagram of a display device according to an exemplary embodiment;

[0032] Figure 2 yes Figure 1 an enlarged plan view of a portion A of the

[0033] Figure 3 It is along Figure 2 A cross-sectional view taken along the section line III-III' and the section line IV-IV';

[0034] Figure 4 yes Figure 1 An enlarged plan view of the first test area and the second test area shown in FIG.

[0035] Figure 5 is a flowchart illustrating a method of testing a display device according to another exemplary embodiment;

[0036] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a cross-sectional view showing a part of a process of manufacturing a display device;

[0037] Fig.10 is a perspective view showing a process of sensing a first test signal;

[0038] Fig.11 is a perspective view showing a process of sensing a second test signal;

[0039] Fig. 12A , Fig. 12B and Fig. 12C are diagrams showing a first test signal, a second test signal and a third test signal, respectively;

[0040] Fig.13 is an enlarged plan view of a first test area and a second test area according to another exemplary embodiment;

[0041] Fig.14A , Fig. 14B and Fig. 14C are diagrams respectively illustrating a first test signal, a second test signal, and a third test signal according to another exemplary embodiment;

[0042] Fig.15 is a schematic plan layout diagram of a display device according to another exemplary embodiment;

[0043] Fig.16 is an enlarged plan view of a third test area and a fourth test area according to another exemplary embodiment; and

[0044] Fig.17is an enlarged plan view of a first test area and a second test area according to another exemplary embodiment. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring various exemplary embodiments. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0046] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0047] The use of cross hatching and / or shading is usually provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the shown elements and / or any other characteristics, attributes, properties, etc. of the element. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two continuously described processes may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0048] When an element or layer is referred to as being "on", "connected to" or "bonded to" another element or layer, the element or layer may be directly on, connected to or bonded to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system, such as x, y and z axes, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "selecting at least one from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be named as the second element.

[0050] For descriptive purposes, spatially relative terms such as "under," "below," "below," "above," "upper," "on," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another (additional) element as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0051] The terms used herein are for the purpose of describing a particular embodiment, rather than being intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular "one (kind / person)" and "the (described)" may also include plural forms. In addition, when the term "includes" and its variations and / or "comprising" and its variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, assemblies and / or their groups, but one or more other features, integral bodies, steps, operations, elements, assemblies and / or their groups are not excluded from existence or addition. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as degree terms, so, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be identified by those of ordinary skill in the art.

[0052] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments disclosed herein need not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but rather include deviations in shapes caused by, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0053] According to the practice of the art, some exemplary embodiments are described and shown in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by circuits (or optical paths) (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units and / or modules by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed here, and the blocks, units and / or modules can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs certain functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0055] Figure 1 is a schematic plan layout diagram of a display device according to an exemplary embodiment, Figure 2 yes Figure 1 An enlarged plan view of part A of Figure 3 is along Figure 2 The sectional view taken along the section line III-III' and the section line IV-IV', Figure 4 yes Figure 1 An enlarged plan view of the first test area and the second test area is shown in FIG.

[0056] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 , the display device 1 according to the present invention may include an array substrate 10 and a counter substrate 20 facing the array substrate 10. The array substrate 10 may include a first substrate 100, a plurality of gate lines G1, G2, ... and Gn (n is a natural number), a plurality of data lines D1, D2, D3, D4, ... and Dm (m is a natural number) insulated from the plurality of gate lines G1, G2, ... and Gn and crossing the plurality of gate lines G1, G2, ... and Gn, a gate driver 700, a printed circuit board 500, and a data driver 590 disposed on the printed circuit board 500.

[0057] The first substrate 100 may include a display area DA defining a pixel area PX and a non-display area other than the display area DA, and the pixel area PX includes a thin film transistor and a pixel electrode. The non-display area may include a first peripheral area PA1 and a second peripheral area PA2. The first peripheral area PA1 may be located on the upper side of the display area DA in the column direction in the figure, and the second peripheral area PA2 may be located on the lower side of the display area DA in the column direction in the figure and positioned opposite to the first peripheral area PA1, and the display area DA is located between the first peripheral area PA1 and the second peripheral area PA2. Figure 2 As shown in FIG. 1 , the pixel region PX may include a first sub-pixel region PX1 and a second sub-pixel region PX2. The first sub-pixel region PX1 and the second sub-pixel region PX2 may be regions that emit light of the same color.

[0058] The first peripheral area PA1 may be a pad area provided with a plurality of pads (also called "pads") for electrically connecting a data driver 590 to be described later to data lines D1, D2, D3, D4, ... and Dm, and the second peripheral area PA2 may be a test area provided with a plurality of test lines to be described later. That is, the second peripheral area PA2 may be a test area for testing whether the data lines D1 to Dm are open or short-circuited.

[0059] A plurality of gate lines G1, G2, ... and Gn and a plurality of data lines D1, D2, D3, D4, ... and Dm insulated from and crossing the plurality of gate lines G1, G2, ... and Gn may be located on the display area DA of the first substrate 100.

[0060] In the following, for the sake of convenience, the direction along which the multiple gate lines G1, G2, ... and Gn extend is called the row direction (also called the first direction), and the direction along which the multiple data lines D1, D2, D3, D4, ... and Dm extend is called the column direction (also called the second direction).

[0061] A plurality of gate lines G1, G2, ... and Gn may be arranged to be spaced apart from each other in a column direction intersecting the row direction. Each data line D1, D2, D3, D4, ... and Dm may extend along the column direction and may be arranged along the row direction. Each data line D1, D2, D3, D4, ... and Dm may extend to the first peripheral area PA1 and the second peripheral area PA2 and the display area DA.

[0062] The pixel region PX may be located at portions where the plurality of gate lines G1, G2, ..., and Gn cross the plurality of data lines D1, D2, D3, D4, ..., and Dm, respectively. Figure 1 As shown in , each pixel region PX may be disposed at a portion where one of the gate lines G1 , G2 , . . . , and Gn crosses each of the adjacent data lines D1 , D2 , D3 , D4 , . . . , and Dm.

[0063] In the non-display area except the first and second peripheral areas PA1 and PA2, a gate driver 700 for applying a scan control signal to control scan signals of the plurality of gate lines G1, G2, . . . and Gn may be disposed.

[0064] A printed circuit board 500 provided with a data driver 590 for applying data signals and data control signals for controlling the data signals to a plurality of data lines D1, D2, D3, D4, ... and Dm may be attached to the first peripheral area PA1. In this case, a plurality of pads for electrically connecting the data driver 590 to the data lines D1, D2, D3, D4, ... and Dm may be provided on the first peripheral area PA1 of the first substrate 100. The plurality of pads may be formed by forming the data lines D1, D2, D3, D4, ... and Dm in the first peripheral area PA1. The width of the plurality of pads in the row direction is greater than the width of the data lines D1, D2, D3, D4, ... and Dm of the display area DA in the row direction, and thus the attachment to the printed circuit board 500 may be further facilitated.

[0065] In some exemplary embodiments, the data driver 590 may be directly mounted on the first substrate 100 without the printed circuit board 500. In this case, a plurality of pads of the data lines D1, D2, D3, D4, . . . , and Dm may be combined with the data driver 590.

[0066] As mentioned above Figure 1 As described, the display device 1 may include an array substrate 10 , an opposing substrate 20 facing the array substrate 10 , and a liquid crystal layer 300 located between the array substrate 10 and the opposing substrate 20 .

[0067] The array substrate 10 may include a first substrate 100 , a gate insulating layer 110 , a first gate line Gn, data lines D1 and D2 , thin film transistors Ta and Tb as switching elements, a passivation layer 130 , an insulating pattern 150 , pixel electrodes PEa and PEb, a cell gap spacer CS, and a first alignment layer 190 .

[0068] The first substrate 100 may be a transparent insulating substrate. For example, the first substrate 100 may be a glass substrate, a quartz substrate or a transparent resin substrate. The first substrate 100 may include a polymer having high heat resistance. For example, the first substrate 100 may include any one selected from polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate, cellulose acetate propionate (CAP), poly (arylene ether sulfone) and combinations thereof.

[0069] In some exemplary embodiments, the first substrate 100 may have flexibility. That is, the first substrate 100 may be a substrate that can be deformed by rolling, folding, bending, etc.

[0070] As described above, the first substrate 100 may include the display area DA and the non-display area.

[0071] The first gate line Gn may extend on the first substrate 100 in one direction (shown as a horizontal direction in the figure). The first gate line Gn may be located on the display area DA of the first substrate 100, and at least a portion of the first gate line Gn may extend to a non-display area of ​​the first substrate 100. The first gate line Gn may include an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and neodymium, an alloy material containing the above elements as main components, or a composite material containing the above elements as main components. However, the material of the first gate line Gn is not limited thereto.

[0072] The gate insulating layer 110 may be formed on the first substrate 100 to cover the first gate line Gn. The gate insulating layer 110 may be located not only on the display area DA of the first substrate 100 but also on the second peripheral area PA2 of the first substrate 100. In some exemplary embodiments, the gate insulating layer 110 may be made of a material such as silicon oxide (SiO 2 ) or silicon nitride (SiN x ) is made of inorganic insulating material.

[0073] The data lines D1 and D2 may be located on the gate insulating layer 110. That is, the data lines D1 and D2 may be insulated from the first gate line Gn and cross the first gate line Gn. The data lines D1 and D2 may be located on the display area DA of the first substrate 100, and at least a portion of each of the data lines D1 and D2 may extend to the first peripheral area PA1 and the second peripheral area PA2 of the first substrate 100 and may be used as a test line. Corresponding portions of other signal lines (e.g., gate lines or other data lines) may also be used as test lines.

[0074] The data lines D1 and D2 may be made of a metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, or Ba, an alloy thereof, or a metal nitride thereof, but the material thereof is not limited thereto.

[0075] Reference Figure 4 , the data lines D1 and D2 include a 1-1 data line portion D11 and a 2-1 data line portion D21 located in the display area DA and a 1-2 data line portion D12 and a 2-2 data line portion D22 located in the second peripheral area PA2.

[0076] The second peripheral area PA2 may include a 2-1 peripheral area PA21 and a 2-2 peripheral area PA22 between the display area DA and the 2-1 peripheral area PA21.

[0077] The 1-2 data line portion D12 of the first data line D1 may include a 1-2-2 data line portion D12b located in the 2-1 peripheral area PA21 and a 1-2-1 data line portion D12a located in the 2-2 peripheral area PA22 and electrically connecting the 1-1 data line portion D11 and the 1-2-2 data line portion D12b. For example, the 1-2-1 data line portion D12a may physically and directly connect the 1-1 data line portion D11 and the 1-2-2 data line portion D12b.

[0078] The 2-2 data line portion D22 of the second data line D2 may be located in the 2-2 peripheral area PA22 and may be electrically connected to the 2-1 data line portion D21. For example, the 2-2 data line portion D22 may be physically directly connected to the 2-1 data line portion D21.

[0079] That is, the 1-2 data line portion D12 of the first data line D1 may include the same material as that of the 1-1 data line portion D11 and may be formed by the same deposition process, and the 2-2 data line portion D22 of the second data line D2 may include the same material as that of the 2-1 data line portion D21 and may be formed by the same deposition process.

[0080] The 1-2 data line portion D12 and the 2-2 data line portion D22 may be test portions for testing whether the 1-1 data line portion D11 is short-circuited or disconnected and whether the 2-1 data line portion D21 is short-circuited or disconnected, respectively.

[0081] The first thin film transistor Ta may be located on the display area DA of the first substrate 100. The first thin film transistor Ta may include: a first gate electrode GEa connected to the first gate line Gn; a first active pattern APa overlapping the first gate electrode GEa and located on the gate insulating layer 110; a first source electrode SEa connected to the first data line D1, located on the first active pattern APa, and overlapping the first active pattern APa; and a first drain electrode DEa spaced apart from the first source electrode SEa and disposed on the first active pattern APa to overlap the first active pattern APa.

[0082] The second thin film transistor Tb may be located on the display area DA of the first substrate 100. The second thin film transistor Tb may include a second gate electrode GEb connected to the first gate line Gn, a second active pattern APb overlapping the second gate electrode GEb and located on the gate insulating layer 110, a second source electrode SEb connected to the second data line D2, located on the second active pattern APb and overlapping the second active pattern APb, and a second drain electrode DEb spaced apart from the second source electrode SEb and disposed on the second active pattern APb to overlap the second active pattern APb.

[0083] In some exemplary embodiments, the gate electrodes GEa and GEb may be made of the same material as the first gate line Gn, the source electrodes SEa and SEb and the drain electrodes DEa and DEb may be made of the same material as the data lines D1 and D2. The active patterns APa and APb may be made of any one of an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, and an oxide semiconductor.

[0084] The passivation layer 130 may be located on the gate insulating layer 110 to cover the data lines D1 and D2, the source electrodes SEa and SEb, and the drain electrodes DEa and DEb. The passivation layer 130 may cover not only the data line portions D11 and D21 of the data lines D1 and D2 located on the display area DA of the first substrate 100, but also the data line portions D12 and D22 located on the second peripheral area PA2. In some exemplary embodiments, the passivation layer 130 may include an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN x ). In other embodiments, the passivation layer 130 may be omitted.

[0085] The insulating pattern 150 may be located on the display area DA of the first substrate 100 and may cover the thin film transistors Ta and Tb. The insulating pattern 150 may planarize the array substrate 10. The insulating pattern 150 may be located on the passivation layer 130.

[0086] In some exemplary embodiments, the insulating pattern 150 may be made of an organic insulating material, and the organic insulating material may include a photosensitive organic composition. The insulating pattern 150 may be a color filter. The color filter may be made of a photosensitive organic composition containing a pigment for coloring. For example, the color filter may be made of a photosensitive organic composition containing any one of red, green, and blue pigments. That is, the color filter may be any one of a red color filter, a green color filter, and a blue color filter.

[0087] The pixel electrodes PEa and PEb may be disposed on the insulating pattern 150 and may be formed of a transparent and conductive material. The pixel electrodes PEa and PEb may contact the drain electrodes DEa and DEb through the contact holes CH1 and CH2 penetrating the insulating pattern 150 and the passivation layer 130. Therefore, the pixel electrodes PEa and PEb may be electrically connected to the thin film transistors Ta and Tb.

[0088] The cell gap spacer CS may be located on the insulating pattern 150. The cell gap spacer CS may serve to maintain a spacing between the array substrate 10 and the counter substrate 20. In some exemplary embodiments, the cell gap spacer CS may be disposed such that at least a portion of the cell gap spacer CS overlaps the first thin film transistor Ta.

[0089] The first alignment layer 190 may be located on the insulating pattern 150, the cell gap spacer CS, and the pixel electrodes PEa and PEb. That is, the first alignment layer 190 may be formed on the entire surface of the array substrate 10. The first alignment layer 190 may be a film subjected to a uniaxial alignment treatment (e.g., a rubbing treatment or a photo-alignment treatment). At least a portion of a portion of the first alignment layer 190 (the portion being located on the cell gap spacer CS) may contact the counter substrate 20.

[0090] The counter substrate 20 may include a second substrate 200 facing the array substrate 10 , a light blocking member 210 , a cover layer 230 , a common electrode 250 , and a second alignment layer 270 .

[0091] Like the first substrate 100, the second substrate 200 may be a transparent insulating substrate. For example, the first substrate 100 may be a glass substrate, a quartz substrate, or a transparent resin substrate. The second substrate 200 may include a polymer having high heat resistance. In some exemplary embodiments, like the first substrate 100, the second substrate 200 may have flexibility. That is, the second substrate 200 may be a substrate that can be deformed by curling, folding, bending, etc.

[0092] The light blocking member 210 may be located on one surface of the second substrate 200 facing the array substrate 10 , and may be disposed to overlap the first gate line Gn, the data lines D1 and D2 , the thin film transistors Ta and Tb, and the second peripheral area PA2 .

[0093] The cover layer 230 may be formed on the light blocking member 210 and the second substrate 200 to planarize the substrate 20. In some exemplary embodiments, the cover layer 230 may be omitted.

[0094] The common electrode 250 may be formed on the cover layer 230. The common electrode 250 may be formed of a transparent and conductive material.

[0095] The second alignment layer 270 may be formed on the second substrate 200 on which the common electrode 250 is formed. The second alignment layer 270 may be formed on the entire surface of the counter substrate 20 facing the array substrate 10. The second alignment layer 270 may be uniaxially aligned (eg, rubbed or photo-aligned).

[0096] The liquid crystal layer 300 may be disposed between the array substrate 10 and the counter substrate 20, and may be made of a liquid crystal composition including liquid crystal molecules. In some exemplary embodiments, the liquid crystal composition may further include a reactive mesogen polymer in addition to the liquid crystal molecules.

[0097] Reference Figure 4 , the third data line D3 can be located in the row direction of the first data line D1, and the second data line D2 is located between the third data line D3 and the first data line D1, and the fourth data line D4 can be located in the row direction of the second data line D2, and the third data line D3 is located between the fourth data line D4 and the second data line D2.

[0098] The third data line D3 may include a 3-1 data line portion D31 located in the display area DA and a 3-2 data line portion D32 located in the second peripheral area PA2, and the fourth data line D4 may include a 4-1 data line portion D41 located in the display area DA and a 4-2 data line portion D42 located in the second peripheral area PA2. The 3-2 data line portion D32 and the 4-2 data line portion D42 may be test portions for testing whether the third data line D3 is short-circuited or open-circuited and whether the fourth data line D4 is short-circuited or open-circuited, respectively.

[0099] The 3-2 data line portion D32 may include a 3-2-2 data line portion D32b located in the 2-1 peripheral area PA21 and a 3-2-1 data line portion D32a located in the 2-2 peripheral area PA22 and electrically connecting the 3-1 data line portion D31 and the 3-2-2 data line portion D32b. For example, the 3-2-1 data line portion D32a may physically directly connect the 3-1 data line portion D31 and the 3-2-2 data line portion D32b. The 3-2-1 data line portion D32a may be disposed between the 2-2 data line portion D22 of the adjacent second data line D2 and the 4-2 data line portion D42 of the fourth data line D4.

[0100] The 4-2 data line portion D42 of the fourth data line D4 may be located in the 2-2 peripheral area PA22 and may be electrically connected to the 4-1 data line portion D41. For example, the 4-2 data line portion D42 may be physically directly connected to the 4-1 data line portion D41.

[0101] The shape of the third data line D3 is substantially the same as that of the first data line D1, and the shape of the fourth data line D4 is substantially the same as that of the second data line D2. Therefore, hereinafter, description will be made based on the first data line D1 and the second data line D2.

[0102] like Figure 4 As shown in , the 2-2 data line portion D22 of the second data line D2 may not be disposed in the 2-1 peripheral area PA21. That is, the length of the 2-2 data line portion D22 of the second data line D2 in the column direction may be shorter than the length of each of the data line portions D12 and D32 of the first data line D1 and the third data line D3 extending to the 2-1 peripheral area PA21 in the column direction. More specifically, the second data line D2 may not be disposed between the 1-2-2 data line portion D12b of the first data line D1 and the 3-2-2 data line portion D32b of the third data line D3, and may not overlap along the row direction.

[0103] Therefore, as will be described later, the distance between data lines disposed in the 2-1 peripheral area PA21 increases, thereby preventing or suppressing the phenomenon that the probes of the sensing device simultaneously contact adjacent test lines and cause short circuits in the adjacent test lines during the process of testing short circuits and disconnections.

[0104] Each of the 1-1 data line portion D11 of the first data line D1 and the 2-1 data line portion D21 of the second data line D2 has a first width W1 in the row direction, and the 1-2 data line portion D12 of the first data line D1 may include portions having widths W2 and W3 different from each other. The 2-2 data line portion D22 of the second data line D2 has a fourth width W4 along the row direction, and the fourth width W4 may be equal to the first width W1. However, the present invention is not limited thereto, and the fourth width W4 may be greater than or less than the first width W1.

[0105] The 1-2-2 data line portion D12b located in the 2-1 peripheral area PA21 may have a third width W3, and the 1-2-1 data line portion D12a located in the 2-2 peripheral area PA22 and electrically connecting the 1-1 data line portion D11 and the 1-2-2 data line portion D12b may have a second width W2 along the row direction. The third width W3 of the 1-2-2 data line portion D12b in the row direction may be equal to the first width W1 of the 1-1 data line portion D11. However, the present invention is not limited thereto, and the third width W3 may be greater than or less than the first width W1.

[0106] like Figure 4As shown in , the second width W2 of the 1-2-1 data line portion D12a in the row direction may be smaller than the third width W3 of the 1-2-2 data line portion D12b in the row direction. Therefore, the second width W2 of the 1-2-1 data line portion D12a in the row direction may be smaller than the fourth width W4 of the 2-2 data line portion D22 of the second data line D2 in the row direction.

[0107] Therefore, as will be described later, the distance between data lines disposed in the 2-2 peripheral area PA22 increases, thereby preventing or suppressing the phenomenon in which the probes of the sensing device simultaneously contact adjacent test lines and cause short circuits in the adjacent test lines during the process of testing short circuits and disconnections.

[0108] Hereinafter, a method for testing a display device will be described, wherein a test unit of the display device is used to determine whether a data line of the display device is short-circuited / open-circuited. In the following embodiments, the same reference numerals as those in the previous embodiments refer to the same elements or parts, and their descriptions will be omitted or simplified.

[0109] Figure 5 is a flowchart illustrating a method of testing a display device according to another exemplary embodiment, Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a cross-sectional view showing a part of a process for manufacturing a display device, Fig.10 is a perspective view showing a process of sensing a first test signal, Fig.11 is a perspective view showing a process of sensing a second test signal, Fig. 12A , Fig. 12B and Fig. 12C 2 are diagrams showing a first test signal, a second test signal, and a third test signal, respectively.

[0110] Reference Figure 5 and Figure 6 A first metal layer (not shown) is formed on the first substrate 100, and the first metal layer is patterned to form a first gate line Gn and a first gate electrode GEa. Figure 3 As described in the description of , the first gate electrode GEa may be formed on the display area DA of the first substrate 100 .

[0111] Then, refer to Figure 3 , Figure 5 and Figure 7, a gate insulating layer 110 is formed on the first gate line Gn, the first gate electrode GEa, and the first substrate 100. In some exemplary embodiments, the gate insulating layer 110 may be formed by chemical vapor deposition or the like, and may be formed not only on the display area DA of the first substrate 100 but also on the non-display area including the second peripheral area PA2.

[0112] Then, refer to Figure 3 , Figure 5 and Figure 8 , an active layer (not shown) is deposited on the gate insulating layer 110, and the active layer is patterned to form a first active pattern APa overlapping the first gate electrode GEa.

[0113] Then, refer to Figure 3 , Figure 5 and Fig. 9 A second metal layer (not shown) is formed on the first substrate 100 on which the first active pattern APa is formed, and the second metal layer is patterned to form the first data line D1, the first source electrode SEa, and the first drain electrode DEa. Thus, a first thin film transistor Ta including the first gate electrode GEa, the first active pattern APa, the first source electrode SEa, and the first drain electrode DEa is formed on the display area DA of the first substrate 100.

[0114] As mentioned above Figure 3 and Figure 4 As described, the first data line D1 may include a 1-1 data line portion D11 located on the display area DA of the first substrate 100 and a 1-2 data line portion D12 located on the second peripheral area PA2 of the first substrate 100 .

[0115] Then, refer to Figure 5 , Fig.10 and Fig. 12A , a process of testing the open circuit or short circuit of the data lines D1 and D2 can be performed. Figure 4 The test process is performed by using the data lines D1 and D2, the signal applying device 810, and the signal sensing device 830 as described.

[0116] First, the first electrical signal IS1 is sequentially applied to the data lines D1, D2, D3 and D4 while the signal applying device 810 is moved along the row direction, and at the same time, the first test signal OS1 is sequentially sensed from the 1-2-2 data line portion D12b of the data line D1 of the 2-1 peripheral area PA21 and the 3-2-2 data line portion D32b of the data line D3 while the signal sensing device 830 is moved along the row direction (S10), thereby completing the first scan SC1.

[0117] The signal applying device 810 may apply the first electrical signal IS1 by bringing the probe into contact with the upper ends of the data lines D1, D2, D3, and D4 in the column direction. The first electrical signal IS1 may be a voltage signal.

[0118] The signal applying device 810 may sequentially pass or slide the probe from the first data line D1 to the fourth data line D4 in the row direction at the left side in the figure while moving the probe. The probe of the signal applying device 810 may continuously move from the first data line D1 to the fourth data line D4 in the row direction at the left side in the figure. The probe of the signal applying device 810 may move not only in contact with the ends of the data lines D1, D2, D3, and D4, but also in contact with the spaces between the data lines D1, D2, D3, and D4.

[0119] Meanwhile, the signal sensing device 830 may directly contact the probe with the 1-2-2 data line portion D12b of the data line D1 and the 3-2-2 data line portion D32b of the data line D3 in the 2-1 peripheral area PA21 sequentially to sense the first test signal OS1. The first test signal OS1 may be a current signal.

[0120] When the probe of the signal applying device 810 contacts the end of each of the data lines D1, D2, D3 and D4 as conductors, current flows, and when the probe of the signal applying device 810 contacts the space between the data lines D1, D2, D3 and D4 as a non-conductor, current does not flow.

[0121] That is to say, Fig. 12A As shown in , when the probe of the signal applying device 810 sequentially contacts the end of each of the data lines D1, D2, D3 and D4 as conductors, the signal sensing device 830 can generate a first test signal OS1 having a predetermined size, and when the probe sequentially contacts the spaces between the data lines D1, D2, D3 and D4 as non-conductors, the signal sensing device 830 can generate a first test signal OS1 having a size of approximately 0.

[0122] Subsequently, the second electrical signal IS2 is sequentially applied to the data lines D1, D2, D3, and D4 while the signal applying device 810 is moved along the row direction, and at the same time, the second test signal OS2 is sequentially sensed from the 1-2-1 data line portion D12a of the data line D1, the 2-2 data line portion D22 of the data line D2, the 3-2-1 data line portion D32a of the data line D3, and the 4-2 data line portion D42 of the data line D4 in the 2-2 peripheral area PA22 while the signal sensing device 830 is moved along the row direction (S20), thereby completing the second scan SC2. The second electrical signal IS2 may be a voltage signal having the same magnitude as the first electrical signal IS1.

[0123] The signal applying device 810 may sequentially pass or slide the probe from the first data line D1 to the fourth data line D4 in the row direction at the left side in the figure while moving the probe. The probe of the signal applying device 810 may continuously move from the first data line D1 to the fourth data line D4 in the row direction at the left side in the figure. The probe of the signal applying device 810 may move not only in contact with the ends of the data lines D1, D2, D3, and D4, but also in contact with the spaces between the data lines D1, D2, D3, and D4.

[0124] At the same time, the signal sensing device 830 may directly contact the probe with the 1-2-1 data line portion D12a of the data line D1, the 2-2 data line portion D22 of the data line D2, the 3-2-1 data line portion D32a of the data line D3, and the 4-2 data line portion D42 of the data line D4 in sequence to sense the second test signal OS2. The second test signal OS2 may be a current signal.

[0125] When the probe of the signal applying device 810 contacts each of the data lines D1, D2, D3 and D4 as conductors, current flows, and when the probe of the signal applying device 810 contacts the space between the data lines D1, D2, D3 and D4 as a non-conductor, current does not flow.

[0126] That is to say, Fig. 12B As shown in , when the probe of the signal applying device 810 sequentially contacts the end of each of the data lines D1, D2, D3 and D4 as conductors, the signal sensing device 830 can generate a second test signal OS2 having a predetermined size, and when the probe contacts the space between the data lines D1, D2, D3 and D4 as a non-conductor, the signal sensing device 830 can generate a second test signal OS2 having a size of approximately 0.

[0127] In addition, as described above, the width of the 1-2-1 data line portion D12a of the first data line D1 and the width of the 3-2-1 data line portion D32a of the third data line D3 in the row direction may be smaller than the width of the 2-2 data line portion D22 of the second data line D2 and the width of the 4-2 data line portion D42 of the fourth data line D4 in the row direction.

[0128] Therefore, if Fig. 12BAs shown in, the shape of the pulse of the 2-1 test signal OS21 sensed from the 1-2-1 data line portion D12a of the first data line D1 and the 3-2-1 data line portion D32a of the third data line D3 by the probe of the signal sensing device 830 can be different from the shape of the pulse of the 2-2 test signal OS22 sensed from the 2-2 data line portion D22 of the second data line D2 and the 4-2 data line portion D42 of the fourth data line D4.

[0129] The pulse shape of the 2-1 test signal OS21 and the pulse shape of the 2-2 test signal OS22 may have the same pulse amplitude.

[0130] Since the width of the 1-2-1 data line portion D12a of the first data line D1 and the width of the 3-2-1 data line portion D32a of the third data line D3 in the row direction are smaller than the width of the 2-2 data line portion D22 of the second data line D2 and the width of the 4-2 data line portion D42 of the fourth data line D4 in the row direction, the width of the pulse shape of the 2-1 test signal OS21 tends to decrease along the vertical axis, while the pulse shape of the 2-2 test signal OS22 has a substantially constant width along the vertical axis. In other words, the 2-1 test signal OS21 may have a triangular wave shape, and the 2-2 test signal OS22 may have a square wave shape.

[0131] In addition, if Fig. 12A and Fig. 12B As shown in , the number of pulses of the second test signal OS2 is greater than the number of pulses of the first test signal OS1.

[0132] The pulse shape of the 2-1 test signal OS21 can be identified as noise.

[0133] Then, refer to Figure 5 and Fig. 12B , the 2-1 test signal OS21 of the second test signal OS2 from the signal sensing device 830 is filtered (S30). According to an exemplary embodiment, the filtered second test signal OS2' may be generated by filtering the 2-1 test signal OS21 from the second test signal OS2.

[0134] Then, refer to Figure 5 and Fig. 12C , the filtered second test signal OS2' and the first test signal OS1 are used to determine the short circuit or disconnection of the data line (S40). That is, the first test signal OS1 and the filtered second test signal OS2' can be combined with each other to generate a third test signal OS3 to determine the short circuit or disconnection of the data line.

[0135] Even in this embodiment, referring to Figure 4As described above, a display device in which the space between data lines not arranged in the 2-1 peripheral area PA21 (i.e., the space between data lines arranged in the 2-1 peripheral area PA21) is increased may also be used to sense the first test signal OS1 from the 1-2-2 data line portion D12b of the first data line D1 and the 3-2-2 data line portion D32b of the third data line D3, so that the probes of the signal sensing device 830 do not simultaneously touch the adjacent test lines to short-circuit the adjacent test lines, thereby preventing or suppressing noise of the first test signal OS1.

[0136] In addition, as described above, since the width of the 1-2-1 data line portion D12a of the first data line D1 in the row direction is smaller than the width of the 2-2 data line portion D22 of the second data line D2 in the row direction, a display device in which the space between the data lines arranged in the 2-2 peripheral area PA22 is increased is used to sense the second test signal OS2 from the 1-2-1 data line portion D12a of the data line D1, the 2-2 data line portion D22 of the data line D2, the 3-2-1 data line portion D32a of the data line D3, and the 4-2 data line portion D42 of the data line D4, so that the probes of the signal sensing device 830 do not touch the adjacent test lines at the same time to short-circuit the adjacent test lines, thereby preventing noise of the second test signal OS2.

[0137] That is, when the display device according to the exemplary embodiment is used, noise of the first test signal OS1 and the second test signal OS2 can be prevented or at least reduced, respectively, thereby increasing reliability of a short or open test of a data line.

[0138] Hereinafter, other embodiments of the aforementioned display device will be described. In the following embodiments, the same reference numerals as those in the aforementioned embodiments refer to the same elements or parts, and the description thereof will be omitted or simplified.

[0139] Fig.13 is an enlarged plan view of a first test area and a second test area according to another exemplary embodiment, Fig.14A , Fig. 14B and Fig. 14C 2 are diagrams respectively illustrating a first test signal, a second test signal, and a third test signal according to another exemplary embodiment.

[0140] Reference Fig.13 as well as Fig.14A , Fig. 14B and Fig. 14C The display device 2 according to the present embodiment is different from the aforementioned display device 1 in that the second data line D2_1 and the fourth data line D4_1 extend to the 2-1 peripheral area PA21.

[0141] More specifically, the second data line D2_1 and the fourth data line D4_1 of the display device 2 may extend to the 2-1 peripheral area PA21. That is, the second data line D2_1 may further include a 2-3 data line portion D23 disposed in the 2-1 peripheral area PA21, and the fourth data line D4_1 may further include a 4-3 data line portion D43 disposed in the 2-1 peripheral area PA21.

[0142] The 2-3 data line portion D23 of the second data line D2_1 may be disposed between the adjacent 1-2-2 data line portion D12b of the first data line D1 and the 3-2-2 data line portion D32b of the third data line D3, and the 3-2-2 data line portion D32b of the third data line D3 may be disposed between the 2-3 data line portion D23 and the 4-3 data line portion D43.

[0143] Since the 2-3 data line portion D23 of the second data line D2_1 and the 4-3 data line portion D43 of the fourth data line D4_1 have substantially the same shape, a description will be made based on the 2-3 data line portion D23 of the second data line D2_1.

[0144] The 2-3 data line portion D23 may have a sixth width W6 along the row direction. The sixth width W6 of the 2-3 data line portion D23 may be smaller than the fourth width W4 of the 2-2 data line portion D22 of the second data line D2_1 along the row direction, and may be smaller than the third width W3 of the 1-2-2 data line portion D12b of the first data line D1 along the row direction.

[0145] In the present embodiment, since the width of the 2-3 data line portion D23 of the second data line D2_1 in the row direction is smaller than each of the width of the 1-2-2 data line portion D12b of the first data line D1 and the width of the 3-2-2 data line portion D32b of the third data line D3 in the row direction, the distance between the data lines disposed in the 2-1 peripheral area PA21 can be increased. Therefore, the probes of the signal sensing device 830 do not touch the adjacent test lines at the same time to short-circuit the adjacent test lines, thereby preventing noise of the first test signal OS1_1.

[0146] The second and fourth data lines D2_1 and D4_1 extend in the 2-1 peripheral area PA21, and thus shapes of pulses of the first test signal OS1_1 may be different from each other.

[0147] Since the width of the 2-3 data line portion D23 in the row direction and the width of the 4-3 data line portion D43 in the row direction are smaller than the width of the 1-2-2 data line portion D12b of the first data line D1 and the width of the 3-2-2 data line portion D32b of the third data line D3 in the row direction, the first test signal OS1_1 in the 2-3 data line portion D23 and the 4-3 data line portion D43 can be different from the first test signal OS1_1 in the 1-2-2 data line portion D12b of the first data line D1 and the 3-2-2 data line portion D32b of the third data line D3.

[0148] That is to say, referring to Fig.14A , the first test signal OS1_1 may include a 1-2 test signal OS12 corresponding to the 2-3 data line portion D23 and the 4-3 data line portion D43 and a 1-1 test signal OS11 corresponding to the 1-2-2 data line portion D12b and the 3-2-2 data line portion D32b. A pulse shape of the 1-1 test signal OS11 and a pulse shape of the 1-2 test signal OS12 may be different from each other.

[0149] The pulse shape of the 1-1 test signal OS11 and the pulse shape of the 1-2 test signal OS12 may have the same pulse amplitude.

[0150] That is, since the width of the 1-2-2 data line portion D12b of the first data line D1 and the width of the 3-2-2 data line portion D32b of the third data line D3 in the row direction are greater than the width of the 2-3 data line portion D23 of the second data line D2_1 and the width of the 4-3 data line portion D43 of the fourth data line D4_1 in the row direction, the width of the pulse shape of the 1-2 test signal OS12 tends to decrease along the vertical axis, while the pulse shape of the 1-1 test signal OS11 has a basically constant width along the vertical axis.

[0151] In addition, if Fig.14A and Fig. 14B As shown in , the number of pulses of the first test signal OS1_1 is equal to the number of pulses of the second test signal OS2.

[0152] The pulse shape of the 1-2 test signal OS12 (like the pulse shape of the 2-1 test signal OS21 ) may be identified as noise. Therefore, the 1-2 test signal OS12 of the first test signal OS1_1 from the signal sensing device 830 may be filtered.

[0153] Reference Fig. 14C, the filtered first test signal OS1_1 and the filtered second test signal OS2 are used to determine the short circuit or disconnection of the data line. That is, the filtered first test signal OS1_1 and the filtered second test signal OS2 are combined with each other to generate the third test signal OS3 to determine the short circuit or disconnection of the data line.

[0154] Fig.15 is a schematic plan layout diagram of a display device according to another exemplary embodiment, Fig.16 is an enlarged plan view of a third test region and a fourth test region according to another exemplary embodiment.

[0155] Reference Fig.15 and Fig.16 The display device 3 according to the present embodiment is different from the aforementioned display device 1 in that the gate lines G1 to Gn include test lines.

[0156] More specifically, the gate lines G1 to Gn of the display device 3 according to the present embodiment may include test lines.

[0157] Reference Fig.15 , the non-display area may further include a third peripheral area PA3 located at the right side of the display area DA in the row direction. The third peripheral area PA3 may be located opposite to the gate driver 700, and the display area DA is located between the third peripheral area PA3 and the gate driver 700. The gate lines G1 to Gn may extend to the third peripheral area PA3, and the gate lines G1 to Gn located in the third peripheral area PA3 may include gate test lines. The gate test lines may be test lines for determining whether the gate lines G1 to Gn electrically connected to each other are short-circuited or open-circuited.

[0158] The gate lines G1 and G2 include a 1-1 gate line portion G11 and a 2-1 gate line portion G21 located in the display area DA and a 1-2 gate line portion G12 and a 2-2 gate line portion G22 located in the third peripheral area PA3.

[0159] The third peripheral area PA3 may include a 3-1 peripheral area PA31 and a 3-2 peripheral area PA32 between the display area DA and the 3-1 peripheral area PA31.

[0160] The 1-2 gate line portion G12 of the first gate line G1 may include a 1-2-2 gate line portion G12b located in the 3-1 peripheral area PA31 and a 1-2-1 gate line portion G12a located in the 3-2 peripheral area PA32 and electrically connecting the 1-1 gate line portion G11 and the 1-2-2 gate line portion G12b. For example, the 1-2-1 gate line portion G12a may physically directly connect the 1-1 gate line portion G11 and the 1-2-2 gate line portion G12b.

[0161] That is, the 1-2 gate line portion G12 of the first gate line G1 may include the same material as the 1-1 gate line portion G11 and may be formed by the same deposition process. In addition, the 2-2 gate line portion G22 of the second gate line G2 may include the same material as the 2-1 gate line portion G21 and may be formed by the same deposition process.

[0162] The 1-2 gate line portion G12 and the 2-2 gate line portion G22 may be test units for testing whether the 1-1 gate line portion G11 and the 2-1 gate line portion G21 are short-circuited or open-circuited, respectively.

[0163] The third gate line G3 may be located in the column direction of the first gate line G1, and the second gate line G2 may be located between the third gate line G3 and the first gate line G1, and the fourth gate line G4 may be located in the column direction of the second gate line G2, and the third gate line G3 may be located between the fourth gate line G4 and the second gate line G2.

[0164] The third gate line G3 may include a 3-1 gate line portion G31 located in the display area DA and a 3-2 gate line portion G32 located in the third peripheral area PA3, and the fourth gate line G4 may include a 4-1 gate line portion G41 located in the display area DA and a 4-2 gate line portion G42 located in the third peripheral area PA3. The 3-2 gate line portion G32 and the 4-2 gate line portion G42 may be test units for testing whether the third gate line G3 and the fourth gate line G4 are short-circuited or open-circuited, respectively.

[0165] The 3-2 gate line portion G32 may include a 3-2-2 gate line portion G32b located in the 3-1 peripheral area PA31 and a 3-2-1 gate line portion G32a located in the 3-2 peripheral area PA32 and electrically connecting the 3-1 gate line portion G31 and the 3-2-2 gate line portion G32b. For example, the 3-2-1 gate line portion G32a may physically directly connect the 3-1 gate line portion G31 and the 3-2-2 gate line portion G32b. The 3-2-1 gate line portion G32a may be located between the 2-2 gate line portion G22 of the adjacent second gate line G2 and the 4-2 gate line portion G42 of the fourth gate line G4.

[0166] In addition, the 4-2 gate line portion G42 of the fourth gate line G4 may be located in the 3-2 peripheral area PA32 and may be electrically connected to the 4-1 gate line portion G41. For example, the 4-2 gate line portion G42 may be physically directly connected to the 4-1 gate line portion G41.

[0167] The shape of the third gate line G3 is substantially the same as that of the first gate line G1, and the shape of the fourth gate line G4 is substantially the same as that of the second gate line G2. Therefore, the following description will be based on the first gate line G1 and the second gate line G2.

[0168] like Fig.16 As shown in , the 2-2 gate line portion G22 of the second gate line G2 may not be disposed in the 3-1 peripheral area PA31. That is, the length of the 2-2 gate line portion G22 of the second gate line G2 in the row direction may be shorter than the length of each of the gate line portion G12 of the first gate line G1 and the gate line portion G32 of the third gate line G3 extending to the 3-1 peripheral area PA31 in the row direction. More specifically, the second gate line G2 may not be disposed between the 1-2-2 gate line portion G12b and the 3-2-2 gate line portion G32b of the third gate line G3, and may not overlap in the column direction.

[0169] Therefore, as will be described later, the distance between gate lines located in the 3-1 peripheral area PA31 increases so that during testing short circuits and open circuits, the probes of the signal sensing device 830 do not touch adjacent test lines at the same time, thereby preventing or suppressing adjacent test lines from shorting.

[0170] The 1-2 gate line portion G12 of the first gate line G1 may include portions having different widths W7 and W8 from each other along the column direction. The 2-2 gate line portion G22 of the second gate line G2 may have a ninth width W9 along the column direction. The 1-2-2 gate line portion G12b located in the 3-1 peripheral area PA31 may have an eighth width W8 along the column direction, and the 1-2-1 gate line portion G12a located in the 3-2 peripheral area PA32 and electrically connecting the 1-1 gate line portion G11 and the 1-2-2 gate line portion G12b may have a seventh width W7 along the column direction.

[0171] like Fig.16 As shown in , the seventh width W7 of the 1-2-1 gate line portion G12a along the column direction may be smaller than the eighth width W8 of the 1-2-2 gate line portion G12b along the column direction. Therefore, the seventh width W7 of the 1-2-1 gate line portion G12a along the column direction may be smaller than the ninth width W9 of the 2-2 gate line portion G22 of the second gate line G2.

[0172] Therefore, the distance between the gate lines located in the 3-2 peripheral area PA32 increases so that during the short circuit and open circuit test, the probes of the signal sensing device 830 do not touch the adjacent test lines at the same time, thereby preventing the adjacent test lines from being short-circuited.

[0173] Fig.17is an enlarged plan view of a first test area and a second test area according to another exemplary embodiment.

[0174] Reference Fig.17 The display device 4 according to the present embodiment is different from the aforementioned display device 1 in that the data lines D1_1, D2_1, D3_1 and D4_1 further include position test line portions D13, D23, D33 and D43.

[0175] More specifically, the data lines D1_1, D2_1, D3_1, and D4_1 according to the present embodiment may further include position test line portions D13, D23, D33, and D43 located between the data line portions D11, D21, D31, and D41 and the data line portions D12, D22, D32, and D42. The position test line portions D13, D23, D33, and D43 may be pad portions for determining disconnection positions of the data lines, and may be referenced in the data lines. Figure 5 Confirm the aforementioned disconnection.

[0176] That is, although not shown, the probe of the position testing device can contact the position test line portions D13, D23, D33 and D43 of the data lines in which the break is confirmed, and the probe of the signal applying device 810 can contact the upper side of the position test line portions D13, D23, D33 and D43 of the data lines in which the break is confirmed in the column direction.

[0177] The probe of the signal applying device 810 may apply an electrical signal to the end of the data line in which the disconnection is confirmed, while the position testing device moves toward the upper side of the data line in the column direction. The position testing device may receive the electrical signal of the signal applying device 810 in the area where the position testing device is located below the disconnection position in the column direction, but may not receive the electrical signal of the signal applying device 810 in the area where the position testing device is located above the disconnection position, thereby testing the disconnection position.

[0178] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to one of ordinary skill in the art.

Claims

1. A display device, comprising: A display panel including a display area and a peripheral area disposed at one side of the display area in a column direction; A plurality of gate lines are located on the display area of ​​the display panel, and the plurality of gate lines extend in a row direction intersecting the column direction; a plurality of data lines insulated from and crossing the plurality of gate lines, the plurality of data lines being located on the display area and the peripheral area, extending in the column direction, and spaced apart from each other along the row direction; as well as a plurality of test lines electrically connected to the plurality of data lines in the peripheral region, the plurality of test lines extending in the column direction and arranged to be spaced apart from each other along the row direction, The peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area. The plurality of test lines include: a first test line including a 1-1 test section disposed on the first peripheral area and a 1-2 test section disposed on the second peripheral area; and a second test line including a 2-1 test section disposed on the second peripheral area. The width of the 1-1 test portion of the first test line in the row direction is greater than the width of the 1-2 test portion of the first test line in the row direction. wherein the width of the 2-1 test portion of the second test line in the row direction is greater than the width of the 1-2 test portion of the first test line in the row direction, wherein the 1-2 test portion disposed on the second peripheral area is directly connected to a corresponding data line disposed on the display area, and The plurality of test lines are arranged in the same layer, and the 1-1 test section, the 1-2 test section and the 2-1 test section are configured to contact with a probe of a signal sensing device to sense a test signal.

2. The display device according to claim 1, wherein: The plurality of test lines further include a third test line extending in the column direction and separated from the first test line, and the second test line is located between the third test line and the first test line, and the third test line includes: 3-1 a test portion, provided on the first peripheral area; and 3-2 a test portion, provided on the second peripheral area.

3. The display device according to claim 2, wherein: The width of the 3-1 test portion of the third test line in the row direction is greater than the width of the 3-2 test portion of the third test line in the row direction, and The width of the second test line in the row direction is greater than the width of the 3-2 test portion of the third test line in the row direction.

4. The display device according to claim 2, wherein: The plurality of test lines further include a fourth test line extending in the column direction and spaced apart from the second test line, and the third test line is located between the fourth test line and the second test line, and The fourth test line includes a 4-1 test portion disposed on the second peripheral area.

5. The display device according to claim 4, wherein: A width of the fourth test line in the row direction is greater than a width of the 3-2 test portion of the third test line in the row direction.

6. The display device according to claim 4, wherein: The first test line and the third test line extend longer than the second test line and the fourth test line in the column direction.

7. The display device according to claim 6, wherein: The 2-1 test section of the second test line is located between the 1-2 test section of the first test line and the 3-2 test section of the third test line, and The 2-1 test section of the second test line does not overlap with the 1-1 test section of the first test line and the 3-1 test section of the third test line in the row direction.

8. The display device according to claim 4, wherein: The second test line further includes a 2-2 test section disposed on the first peripheral area, and The width of the 2-1 test portion of the second test line in the row direction is greater than the width of the 2-2 test portion of the second test line in the row direction.

9. The display device according to claim 8, wherein: The 2-2 test section of the second test line is located between the 1-1 test section of the first test line and the 3-1 test section of the third test line.

10. The display device according to claim 1, wherein: The plurality of test lines and the plurality of data lines are arranged on the same layer, and Wherein, the plurality of test lines and the plurality of data lines are formed by a same process.

11. The display device according to claim 1, further comprising: a pad area to which a printed circuit board is attached, Wherein, the pad area is positioned relative to the display area and the peripheral area.

12. A display device, comprising: A display panel including a display area and a peripheral area arranged at one side of the display area in a row direction; a plurality of data lines, located on the display area of ​​the display panel, the plurality of data lines extending in a column direction intersecting the row direction; a plurality of gate lines insulated from and crossing the plurality of data lines, the plurality of gate lines being located on the display area and the peripheral area and extending in the row direction and being spaced apart from each other along the column direction; as well as a plurality of gate test lines electrically connected to the plurality of gate lines in the peripheral region, the plurality of gate test lines extending in the row direction and arranged to be spaced apart from each other along the column direction, The peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area and contacting the first peripheral area. The plurality of gate test lines include: first gate test lines, each including a 1-1 test portion disposed on the first peripheral region and a 1-2 test portion disposed on the second peripheral region; and second gate test lines, each including a 2-1 test portion disposed on the second peripheral region, The width of the 1-1 test portion of the first gate test line in the column direction is greater than the width of the 1-2 test portion of the first gate test line in the column direction. wherein the width of the 1-2 test portion of the first gate test line in the column direction is smaller than the width of a gate line electrically connected to the first gate test line among the plurality of gate lines in the column direction, wherein the width of the second gate test line in the column direction is greater than the width of the 1-2 test portion of the first gate test line in the column direction, and The plurality of gate test lines are arranged in the same layer, and the 1-1 test portion, the 1-2 test portion and the 2-1 test portion are configured to contact with a probe of a signal sensing device to sense a test signal.

13. The display device according to claim 12, wherein: Each of the second gate test lines is disposed between adjacent first gate test lines.

14. A method for testing a display device, the method comprising the following steps: sequentially applying a first electrical signal to the data lines by moving the signal applying device along a first direction; sequentially sensing a first test signal from a first peripheral area by moving a signal sensing device in the first direction while sequentially applying the first electrical signal to the data line; sequentially applying a second electrical signal to the data lines by moving the signal applying device along the first direction; sequentially sensing a second test signal from a second peripheral area by moving the signal sensing device in the first direction while sequentially applying the second electrical signal to the data line; filtering the second test signal received from the signal sensing device to generate a filtered second test signal; as well as using the first test signal and the filtered second test signal to determine whether there is a short circuit or a break in the data line, wherein a plurality of test lines are electrically connected to the data lines arranged in the display area, and the second peripheral area is located between the display area and the first peripheral area, The plurality of test lines include: a first test line including a 1-1 test section disposed on the first peripheral area and a 1-2 test section disposed on the second peripheral area; and a second test line including a 2-1 test section disposed on the second peripheral area, and Among them, the width of the 1-1 test section of the first test line in the first direction is greater than the width of the 1-2 test section of the first test line in the first direction, and the width of the 1-2 test section of the first test line in the first direction is less than the width of the 2-1 test section of the second test line in the first direction.

15. The method according to claim 14, wherein: Each of the second test lines is disposed between adjacent first test lines.

16. The method according to claim 15, wherein: An average width of pulses of the second test signal sensed through the 1-2 test section of the first test line is smaller than an average width of pulses of the first test signal sensed through the 1-1 test section of the first test line.

17. The method according to claim 16, wherein: An average width of pulses of the second test signal sensed through the 2-1 test section of the second test line is greater than an average width of pulses of the second test signal sensed through the 1-2 test section of the first test line.

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