Thin film transistor substrate and display device

Abstract

A thin film transistor substrate includes a substrate; a first electrode arranged on the substrate; a bank arranged on the substrate and having an inclined surface inclined at an angle with respect to the substrate; a second electrode arranged on the bank; an active pattern electrically connected to the first electrode and the second electrode, the active pattern being arranged on the inclined surface and including a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region; and a gate electrode overlapping at least a portion of the channel region of the active pattern. In a plan view, the inclined surface extends in a first direction. The first conductive region, the channel region, and the second conductive region are sequentially arranged on the inclined surface along a second direction intersecting the first direction. The present application also discloses a display device including the above-described thin film transistor substrate.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present inventive concept relate to a thin film transistor substrate, a display device having the thin film transistor substrate, and a method of manufacturing the thin film transistor substrate. More particularly, example embodiments of the present inventive concept relate to a thin film transistor substrate having improved space utilization, a display device having a thin film transistor substrate with improved flexibility, and a method of manufacturing the thin film transistor substrate. BACKGROUND

[0002] Recently, display devices having a light weight and a small size have been manufactured. Cathode ray tube (CRT) display devices have been used for several decades due to their performance and competitive prices. However, CRT display devices have disadvantages in terms of their size and portability. Accordingly, flat panel display devices such as plasma display devices, liquid crystal display devices, and organic light emitting display devices have been highly valued due to their small size, light weight, and low power consumption.

[0003] In order to improve the display quality of display devices, efforts have been made to increase the resolution of display devices. However, as the area occupied by one pixel is reduced, the space for placing a thin film transistor is reduced.

[0004] In recent years, research has been actively conducted to develop flexible display devices that can fold a screen to enhance portability and can unfold the screen when the flexible display device is used. There is a demand to make the thickness of the flexible display device thinner than that of conventional display devices to impart and increase flexibility. SUMMARY

[0005] One or more example embodiments of the present inventive concept provide a thin film transistor substrate having a thin film transistor with improved space utilization.

[0006] One or more example embodiments of the present inventive concept also provide a display device having a thin film transistor substrate including a flexible area.

[0007] One or more example embodiments of the present inventive concept also provide a method of manufacturing a thin film transistor substrate.

[0008] According to an exemplary embodiment of the inventive concept, a thin film transistor substrate includes a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, the active pattern being disposed on the inclined surface and including a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. In a plan view, the inclined surface extends in a first direction. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction crossing the first direction.

[0009] In an exemplary embodiment, the channel region of the active pattern can be formed on the inclined surface.

[0010] In an exemplary embodiment, a height difference between the first electrode and the second electrode can be no more than 200 µm (micrometers).

[0011] In an exemplary embodiment, the first conductive region can have a first portion overlapping the first electrode and a second portion connected to the first portion and overlapping a portion of the inclined surface adjacent to the first electrode.

[0012] In an exemplary embodiment, the active pattern can have an S-shape on the inclined surface.

[0013] According to an exemplary embodiment of the inventive concept, a display device includes a substrate, a first bank disposed on the substrate and having a first inclined surface inclined at a first angle with respect to the substrate, a first thin film transistor including a first electrode, a second electrode, a first active pattern, and a gate electrode, and a light emitting structure electrically connected to the first thin film transistor. The first electrode is disposed on the substrate, and the second electrode is disposed on the first bank. The first active pattern is electrically connected to the first electrode and the second electrode and is disposed on the first inclined surface. The first active pattern includes a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region, and the gate electrode overlaps the channel region of the first active pattern.

[0014] In an exemplary embodiment, in a plan view, the first inclined surface can extend in a first direction. The first conductive region, the channel region, and the second conductive region can be sequentially disposed on the first inclined surface along a second direction crossing the first direction. The substrate can include a first reinforcing region and a second reinforcing region and a flexible region bendable and disposed between the first reinforcing region and the second reinforcing region.

[0015] In an exemplary embodiment, a height difference between the first electrode and the second electrode can be no more than 200 µm (micrometers).

[0016] In an exemplary embodiment, the first conductive region can have a first portion overlapping the first electrode and a second portion connected to the first portion and overlapping a portion of the first inclined surface adjacent to the first electrode.

[0017] In an exemplary embodiment, the display device can further include a second bank spaced apart from the first bank in the first direction and a second thin film transistor including a second active pattern. The second bank can include a second inclined surface inclined at a second angle with respect to the substrate. The second active pattern of the second thin film transistor can be disposed on the second inclined surface of the second bank.

[0018] In an exemplary embodiment, the display device can further include a third bank spaced apart from the first bank in a second direction. Each of the first bank, the second bank, and the third bank has an island shape. The substrate can be bendable along the first direction and the second direction.

[0019] In an exemplary embodiment, the display device can further include a second thin film transistor having a second active pattern. The first bank can further include a second inclined surface opposite the first inclined surface. The second active pattern of the second thin film transistor can be disposed on the second inclined surface.

[0020] In an exemplary embodiment, the first bank can have an elastic modulus of 10 GPa or more.

[0021] In an exemplary embodiment, a channel region of the first active pattern can be formed on the inclined surface.

[0022] According to an exemplary embodiment of the inventive concept, a method of manufacturing a thin film transistor substrate includes forming a bank having an inclined surface inclined at a first angle with respect to a substrate; forming an initial active pattern including amorphous silicon on the inclined surface; irradiating the initial active pattern with an excimer laser to form an active pattern including polycrystalline silicon; forming a gate insulating layer on the active pattern; and forming a gate electrode on the gate insulating layer.

[0023] In an exemplary embodiment, a height of the active pattern in a direction perpendicular to the substrate can be no more than 200 µm (micrometers).

[0024] In an exemplary embodiment, the method can further include forming source and drain regions by doping impurities in respective portions of the active pattern. The active pattern can include a channel region between the source and drain regions and can overlap the gate electrode. The channel region of the active pattern can be formed on the inclined surface.

[0025] In an exemplary embodiment, the method can further include forming a first electrode on the substrate and forming a second electrode on the bank. The first electrode can be connected to a source region of the active pattern, and the second electrode can be connected to a drain region of the active pattern. In a plan view, the first electrode and the second electrode can be spaced apart from each other.

[0026] In an exemplary embodiment, the bank can have an elastic modulus of 10 GPa or more.

[0027] According to an exemplary embodiment of the present inventive concept, a thin film transistor substrate includes a substrate; a first electrode disposed on the substrate; a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate; a second electrode disposed on the bank; an active pattern electrically connected to the first electrode and the second electrode, the active pattern being disposed on the inclined surface and including a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region; and a gate electrode overlapping the channel region of the active pattern. In a plan view, the inclined surface extends in a first direction. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction intersecting the first direction.

[0028] The active pattern of the thin film transistor is disposed on the inclined surface of the bank, so that a space in a plan view occupied by a plurality of thin film transistors included in one pixel can be reduced. Accordingly, a size of a pixel of a display apparatus can be reduced, and the display apparatus can have a high resolution, and a display quality of the display apparatus can be improved.

[0029] In addition, the height of the bank can be determined in consideration of a focal length of an excimer laser used for crystallization of the active pattern. In addition, the channel region of the thin film transistor is formed on the inclined surface, thereby preventing deterioration in quality of the thin film transistor that can be caused by poor crystallization quality. In addition, the display device can implement a flexible display device including a flexible area, in which a bank of a suitable shape, size, and configuration can be provided so that the display apparatus can be foldable, bendable, or rollable.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure, including the inventive concept. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other features of the present inventive concept will become more apparent by describing in detail its exemplary embodiments with reference to the attached drawings, in which:

[0032] Figure 1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present inventive concept;

[0033] Figure 2 is a perspective view of a thin film transistor substrate; Figure 1

[0034] Figure 3 is a conceptual cross-sectional view of a thin film transistor substrate; Figure 1

[0035] Figure 4A is a plan view of a display device illustrating an example embodiment according to the inventive concept;

[0036] Figure 4B is a cross-sectional view of a display device; Figure 4A

[0037] Figure 5A is a perspective view of a display device being folded; Figure 4A

[0038] Figure 5B is a cross-sectional view of a display device; Figure 5A

[0039] Figure 6 is a cross-sectional view of the "A" portion; Figure 4B

[0040] Figure 7A is a plan view of a display device illustrating an example embodiment according to the inventive concept;

[0041] Figure 7B is a perspective view of a display device being freely bent; Figure 7A

[0042] Figure 8A is a cross-sectional view of a display device taken along the line I-I' in Figure 7A

[0043] Figure 8B is a cross-sectional view of a display device taken along the line II-II' in Figure 7A

[0044] Figure 9 is a cross-sectional view of a thin film transistor substrate illustrating an example embodiment according to the inventive concept;

[0045] Figure 10 is a cross-sectional view of a thin film transistor substrate illustrating an example embodiment according to the inventive concept;

[0046] Figures 11A to 11E is a cross-sectional view of a method of manufacturing a thin film transistor substrate illustrating an example embodiment according to the inventive concept; and

[0047] Figure 12 ​​​​​​​​​is a block diagram illustrating an electronic device according to an example embodiment. DETAILED DESCRIPTION

[0048] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0049] Figure 1 is a plan view illustrating a thin film transistor substrate according to an example embodiment of the inventive concept.

[0050] Figure 2 is a perspective view illustrating Figure 1 a thin film transistor substrate. Figure 3 is a conceptual cross-sectional view illustrating Figure 1 a thin film transistor substrate.

[0051] Referring to Figures 1 to 3 , the thin film transistor substrate can include a substrate 100, a buffer layer 110, a first conductive layer including a drain electrode DE, a bank BN, a second conductive layer including a source electrode SE, an active pattern ACT, a gate insulating layer 120, and a third conductive layer including a gate electrode GE.

[0052] The substrate 100 can be made of a transparent material or an opaque material. For example, the substrate 100 can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, an alkali lime glass substrate, an alkali-free glass substrate, or the like. Alternatively, the substrate 100 can be made of a flexible resin substrate. An example of the flexible resin substrate that can be made of the substrate 100 can be a polyimide substrate. For example, the substrate 100 can include a polymer resin such as polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyalkyl ester, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 can have a thickness in the range of several micrometers (μm) to several tens of micrometers.

[0053] The buffer layer 110 can be disposed on the substrate 100. The buffer layer 110 can prevent metal atoms or impurities from diffusing from the substrate 100 to structures inside a display device including the thin film transistor substrate.

[0054] The drain electrode DE can be disposed on the buffer layer 110. The drain electrode DE can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0055] The bank BN can be disposed adjacent to the drain electrode DE on the buffer layer 110. In Figure 3In a cross-sectional view, the bank BN can have an inclined surface IS having an angle Θ with respect to the substrate 100. The angle Θ can be greater than 0 degree and less than 90 degrees. For example, in a plan view, the inclined surface IS can extend in the first direction D1 between the drain electrode DE and the source electrode SE. The elastic modulus of the bank BN can be greater than the elastic modulus of the substrate 100. The elastic modulus represents the stiffness of a substance or material. The elastic modulus is generally defined as the slope of the stress-strain curve in the elastic deformation region. The greater the elastic modulus, the smaller the degree of shape change (deformation) due to external stress. That is, since the elastic modulus of the bank BN is greater than the elastic modulus of the substrate 100, the bank BN can be made of a material that is relatively harder (more difficult to deform) than the substrate 100. In some example embodiments, the elastic modulus of the bank BN can be 10 GPa or greater.

[0056] The source electrode SE can be disposed on the bank BN. In a plan view, the source electrode SE and the drain electrode DE can be spaced apart from each other in the first direction D1 and in a second direction D2 perpendicular to the first direction D1. Accordingly, the inclined surface IS of the bank BN can be disposed between the source electrode SE and the drain electrode DE, spacing the source electrode SE and the drain electrode DE in both the first direction D1 and the second direction D2.

[0057] The active pattern ACT can be disposed on the inclined surface IS of the bank BN and extend to at least partially overlap the source electrode SE and the drain electrode DE, respectively. The active pattern ACT can include a semiconductor material such as silicon, germanium, and silicon germanium. For example, the active pattern ACT can include polysilicon. The polysilicon can be formed by crystallizing amorphous silicon by irradiating an excimer laser to the amorphous silicon.

[0058] The active pattern ACT includes a drain region D and a source region S doped with an impurity and a channel region C disposed between the drain region D and the source region S.

[0059] The drain region D, the channel region C, and the source region S of the active pattern ACT can be disposed on the inclined surface IS in the second direction D2.

[0060] The drain region D of the active pattern ACT has a first portion disposed on the buffer layer 110 to at least partially overlap the drain electrode DE and a second portion extending on the inclined surface IS in the first direction D1. The source region S of the active pattern ACT has a first portion disposed on the bank BN to at least partially overlap the source electrode SE and a second portion extending on the inclined surface IS in the first direction D1.

[0061] The gate insulating layer 120 can be disposed on the active pattern ACT. The gate insulating layer 120 can include an inorganic insulating material and / or an organic insulating material. For example, the gate insulating layer 120 can include a silicon compound, a metal oxide, or the like.

[0062] A gate electrode GE can be disposed on the gate insulating layer 120 to overlap the channel region C of the active pattern ACT. The gate electrode GE can extend in the first direction D1.

[0063] The thin film transistor TFT can include a drain electrode DE, a source electrode SE, an active pattern ACT, and a gate electrode GE.

[0064] The channel region C can be disposed between the source region S and the drain region D. The active pattern ACT can extend in the second direction D2 in a zigzag pattern in the first direction D1. For example, the active pattern ACT can have an S-shape on the inclined surface IS. The channel length of the thin film transistor TFT can be adjusted by changing the shape and / or size of the active pattern ACT on the inclined surface IS, thereby adjusting the characteristics of the thin film transistor TFT.

[0065] The drain region D of the active pattern ACT has a first portion disposed on the buffer layer 110 to at least partially overlap the drain electrode DE and a second portion disposed on the inclined surface IS adjacent to the drain electrode DE and connected to the first portion. Here, a transition region in which the inclination of the active pattern ACT rapidly changes is formed between the first portion and the second portion at the end of the inclined surface IS (see the dotted line extending in the second direction D2 in Figure 1 Due to the rapid change in the inclination, this transition portion of the active pattern ACT can have poor crystalline quality. However, since the transition portion, which can exhibit poor crystalline quality, has high conductivity by doping impurities, the degradation of the characteristics of the thin film transistor TFT that can be caused by poor crystalline quality can be minimized.

[0066] That is, the active pattern ACT can be disposed such that the channel region C is formed on the inclined surface IS, thereby preventing the degradation of the quality of the thin film transistor TFT that can cause a crystalline quality problem. Here, the channel region C of the active pattern ACT can be substantially formed on the inclined surface IS, but due to manufacturing errors, a small deviation can occur in the formation of the channel region C. For convenience of description, the portion of the active pattern ACT overlapping the gate electrode GE can be referred to as the channel region C.

[0067] Figure 4A is a plan view illustrating a display device according to an exemplary embodiment of the present inventive concept. Figure 4B is a cross-sectional view of the display device of Figure 4A . Figure 5A is a perspective view illustrating the display device of Figure 4A being folded. Figure 5B is a cross-sectional view of the display device of Figure 5A .

[0068] Referring toFigures 4A to 5B The display device 10 can include a flexible area FA and two reinforced areas RA. The reinforced areas RA are spaced apart from each other in the first direction D1, with the flexible area FA interposed between the reinforced areas RA. The flexible area FA can extend along a second direction D2 perpendicular to the first direction D1.

[0069] Figure 5A and Figure 5B FIG. illustrates a foldable display device in which the display device 10 is folded about a folding axis C parallel to the second direction D2. The display device 10 has a radius of curvature R in the flexible area FA.

[0070] The display device 10 can include a plurality of banks BN formed in the flexible area FA. The plurality of banks BN can be spaced apart from each other in the first direction D1 and extend in the second direction D2.

[0071] A reinforcing layer (not shown) can be formed in the reinforced areas RA to have a fixed shape. In the flexible area FA, a plurality of banks BN are formed instead of the reinforcing layer to impart flexibility, e.g., foldable, bendable, or rollable, in the flexible area FA. Here, the terms "fixed," "foldable," "bendable," "rollable," and the like are understood to describe a relative degree of flexibility between the flexible area FA and the reinforced areas RA. For example, the reinforced areas RA can also impart flexibility to some extent.

[0072] The elastic modulus of the reinforcing layer and the banks BN can be greater than the elastic modulus of the substrate 100 of the display device 10.

[0073] The reinforcing layer can have a large elastic modulus so that the display device 10 can not be easily bent in the reinforced areas RA. However, by utilizing the spaces between adjacent banks BN, the display device 10 can be foldable in the flexible area FA where the banks BN are formed.

[0074] Figure 6 is a cross-sectional view of the "A" portion of FIG. Figure 4B

[0075] Referring to Figure 4B and Figure 6 The display device 10 can include a substrate 100, a buffer layer 110, a first conductive layer, a bank BN, a second conductive layer, an active pattern ACT, a gate insulating layer 120, a third conductive layer, a via insulating layer 130, a light emitting structure 180, a pixel definition layer PDL, and a thin film encapsulation layer TFE.

[0076] ​The substrate 100 can be made of a transparent material or an opaque material. Since the display device 10 includes a flexible area FA having flexibility, the substrate 100 can be made of a flexible resin substrate. The substrate 100 can include a polymer resin such as polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyalkyl ester, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). For example, an example of the flexible resin substrate of which the substrate 100 can be made can be a polyimide substrate. The substrate 100 can have a thickness in a range of several micrometers (μm) to several tens of micrometers.

[0077] A buffer layer 110 can be disposed on the substrate 100. The buffer layer 110 can prevent metal atoms or impurities from diffusing from the substrate 100 into structures inside the display device 10.

[0078] A first conductive layer can be disposed on the buffer layer 110. The first conductive layer can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. The first conductive layer can include a drain electrode DE.

[0079] A bank BN can be disposed adjacent to the drain electrode DE on the buffer layer 110. The bank BN can have an inclined surface IS having an angle with respect to the substrate 100. An elastic modulus of the bank BN can be greater than an elastic modulus of the substrate 100. In some example embodiments, the elastic modulus of the bank BN can be 10 GPa or more.

[0080] A second conductive layer can be disposed on the bank BN. The second conductive layer can include a source electrode SE.

[0081] The first conductive layer and the second conductive layer can be formed by different layers, but the present disclosure is not limited thereto. For example, the first conductive layer and the second conductive layer can be formed by the same layer after the bank BN is formed.

[0082] An active pattern ACT can be disposed on the inclined surface IS of the bank BN and extended to at least partially overlap the source electrode SE and the drain electrode DE, respectively. The active pattern ACT can include a semiconductor material such as silicon, germanium, and silicon germanium. For example, the active pattern ACT can include polysilicon. The polysilicon can be formed by crystallizing amorphous silicon by irradiating an excimer laser to the amorphous silicon.

[0083] A gate insulating layer 120 can be disposed on the active pattern ACT. The gate insulating layer 120 can include an inorganic insulating material and / or an organic insulating material. For example, the gate insulating layer 120 can include a silicon compound, a metal oxide, or the like.

[0084] A third conductive layer can be disposed on the gate insulating layer 120. The third conductive layer can include a gate electrode GE. The gate electrode GE can be disposed on the gate insulating layer 120 to overlap the channel region C of the active pattern ACT.

[0085] The thin film transistor TFT can include a drain electrode DE, a source electrode SE, an active pattern ACT, and a gate electrode GE.

[0086] Referring to Figure 6 , a plurality of banks BN are formed, and the thin film transistor TFT can be formed on the inclined surface IS of the corresponding bank BN. Also, one bank BN can have a plurality of inclined surfaces IS, and the active pattern ACT of the thin film transistor TFT can be disposed on each of the inclined surfaces IS.

[0087] The via insulating layer 130 can be disposed on the gate insulating layer 120 covering the third conductive layer. The via insulating layer 130 can have a single layer structure or a multi-layer structure including at least two insulating films. The via insulating layer 130 can be formed using an organic material. For example, the via insulating layer 130 can include a photoresist, an acryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, or the like. In some example embodiments, the via insulating layer 130 can be formed using an inorganic material such as a silicon compound, a metal, and a metal oxide.

[0088] The light emitting structure 180 can include a first electrode 181, a light emitting layer 182, and a second electrode 183.

[0089] The first electrode 181 can be disposed on the via insulating layer 130. The first electrode 181 can include a reflective material or a transmissive material according to the emission type of the display device 10. For example, the first electrode 181 can be formed using aluminum, an alloy including aluminum, aluminum nitride, silver, an alloy including silver, tungsten, tungsten nitride, copper, an alloy including copper, nickel, an alloy including nickel, chromium, chromium nitride, molybdenum, an alloy including molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, or the like. These can be used alone or in any combination thereof. In an example embodiment, the first electrode 181 can have a single layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0090] A pixel definition layer PDL can be disposed on the via insulating layer 130 on which the first electrode 181 is disposed. The pixel definition layer PDL can be formed using an organic material. For example, the pixel definition layer PDL can include a photoresist, an acryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, or the like. In some example embodiments, an opening exposing a portion of the first electrode 181 can be formed by etching the pixel definition layer PDL. The emission area and the non-emission area of the display device 10 can be defined by the opening of the pixel definition layer PDL. For example, a portion where the opening of the pixel definition layer PDL is located can correspond to the emission area, and the non-emission area can correspond to a portion adjacent to the opening of the pixel definition layer PDL.

[0091] The light emitting layer 182 can be disposed on the first electrode 181 exposed through the opening of the pixel definition layer PDL. Also, the light emitting layer 182 can extend on the sidewall of the opening of the pixel definition layer PDL. In some example embodiments, the light emitting layer 182 can include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), or the like. In some example embodiments, in addition to the organic light emitting layer, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer can be collectively formed to correspond to a plurality of pixels. In some example embodiments, according to the color pixels of the display device 10, a plurality of organic light emitting layers can be formed using light emitting materials for generating light of different colors such as red light, green light, and blue light. In some example embodiments, the organic light emitting layer of the light emitting layer 182 can include a plurality of stacked light emitting materials for generating red light, green light, and blue light to emit white light. Here, the elements of the light emitting layer 182 can be collectively formed to correspond to a plurality of pixels, and each pixel can be divided by a color filter layer (not shown).

[0092] The second electrode 183 can be disposed on the pixel definition layer PDL and the light emitting layer 182. The second electrode 183 can include a transmissive material or a reflective material according to the emission type of the display device 10. For example, the second electrode 183 can be formed using aluminum, an alloy including aluminum, aluminum nitride, silver, an alloy including silver, tungsten, tungsten nitride, copper, an alloy including copper, nickel, an alloy including nickel, chromium, chromium nitride, molybdenum, an alloy including molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, or the like. These can be used alone or in any combination thereof. In example embodiments, the second electrode 183 can also have a single layer structure or can include a multi-layer structure of a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0093] A thin film encapsulation layer TFE can be disposed on the second electrode 183. The thin film encapsulation layer TFE can prevent moisture and oxygen from penetrating into the display device 10 from the outside. The thin film encapsulation layer TFE can include at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer can be alternately stacked with each other. For example, the thin film encapsulation layer TFE can include two inorganic layers and one organic layer disposed between the two inorganic layers, but the present disclosure is not limited thereto. In some example embodiments, instead of or in addition to the thin film encapsulation layer TFE, a sealing substrate for shielding external air and moisture that penetrates into the display device 10 can be provided.

[0094] According to an embodiment, the display device 10 can include a flexible area FA in which the bank BN is disposed. Accordingly, breakage due to bending of the display device 10 can be prevented. In addition, since the active pattern ACT of the thin film transistor TFT is disposed on the inclined surface IS of the bank BN, the size of the thin film transistor TFT in a plan view can be reduced. As a result, the display device 10 can have a pixel design margin and high resolution.

[0095] Figure 7A FIG. 1 is a plan view illustrating a display device according to an example embodiment of the present inventive concept. Figure 7B FIG. 2 is a perspective view illustrating Figure 7A the display device of FIG. 1 being freely bent. Figure 8A FIG. 3 is a cross-sectional view illustrating the display device of FIG. 1 taken along a line I-I' in Figure 7A FIG. 4 is a cross-sectional view illustrating the display device of FIG. 1 taken along a line II-II' in Figure 8B FIG. 5 is a cross-sectional view illustrating the display device of FIG. 1 taken along a line III-III' in Figure 7A FIG. 6 is a cross-sectional view illustrating the display device of FIG. 1 taken along a line IV-IV' in

[0096] Referring to Figures 7A to 8B , the display device 10 is substantially the same as the display device 10 of Figures 4A to 6 except that the flexible area FA is formed on the entire display device 10 without the reinforcing area such that the shape and arrangement of the bank BN are different. Accordingly, a repeated description will be omitted.

[0097] The entire display device 10 can be a flexible area FA such that the display device 10 can be bent in any direction in a plane defined by the first direction D1 and the second direction D2. The display device 10 can include a plurality of banks BN arranged in a matrix form along the first direction D1 and the second direction D2. That is, each of the banks BN has an island shape and can be arranged along the first direction D1 and the second direction D2. For example, the display device 10 can include a first bank BN1, a second bank BN2 spaced apart from the first bank BN1 in the first direction D1, and a third bank BN3 spaced apart from the second bank BN2 in the second direction D2.

[0098] Accordingly, each of the banks BN can have four inclined surfaces IS. An active pattern ACT of a thin film transistor TFT can be formed on each of the inclined surfaces IS. Referring to Figure 8A Thin film transistors TFT1a and TFT1b can be arranged on two inclined surfaces IS of the first bank BN1 in the first direction D1, and thin film transistors TFT2a and TFT2b can be arranged on two inclined surfaces IS of the second bank BN2 in the first direction D1.

[0099] Referring to Figure 8B Thin film transistors TFT2c and TFT2d are arranged on two inclined surfaces IS of the second bank BN2 in the second direction D2, and thin film transistors TFT3c and TFT3d can be arranged on two inclined surfaces IS of the third bank BN3 in the second direction D2.

[0100] That is, a plurality of thin film transistors TFT can be disposed on an inclined surface IS of one bank BN so that a space in a plan view occupied by a plurality of thin film transistors TFT included in one pixel can be reduced. Accordingly, a size of a pixel can be reduced, a high resolution can be implemented, and a display quality can be improved.

[0101] Figure 9 is a cross-sectional view illustrating a thin film transistor substrate according to an exemplary embodiment of the present inventive concept.

[0102] Referring to Figure 9 The thin film transistor substrate is substantially the same as the thin film transistor substrate of Figures 1 to 3 except for a shape of a drain electrode DE. Accordingly, a repeated explanation will be omitted.

[0103] The thin film transistor substrate can include a substrate 100, a buffer layer 110, a first conductive layer including a drain electrode DE, a bank BN, a second conductive layer including a source electrode SE, an active pattern ACT, a gate insulating layer 120, and a third conductive layer including a gate electrode GE.

[0104] The drain electrode DE can be formed between the bank BN and the buffer layer 110. In a plan view, a portion of the drain electrode DE can extend to overlap at least a portion of the source electrode SE.

[0105] Figure 10 is a cross-sectional view illustrating a thin film transistor substrate according to an exemplary embodiment of the present inventive concept.

[0106] Referring to Figure 10 The thin film transistor substrate is substantially the same as the thin film transistor substrate of Figures 1 to 3The thin-film transistor substrate can include a substrate 100, a buffer layer 110, a first conductive layer, a first bank BN1, a second conductive layer, a first active pattern ACT1, a gate insulating layer 120, a third conductive layer, a second bank BN2, a third bank BN3, a fourth conductive layer, a via insulating layer 130, and a fifth conductive layer.

[0107] The thin-film transistor substrate can include a substrate 100, a buffer layer 110, a first conductive layer, a first bank BN1, a second conductive layer, a first active pattern ACT1, a gate insulating layer 120, a third conductive layer, a second bank BN2, a third bank BN3, a fourth conductive layer, a via insulating layer 130, and a fifth conductive layer.

[0108] The first conductive layer can include a first drain electrode DE1. The second conductive layer can include a first source electrode SE1. The third conductive layer can include a first gate electrode GE1, a second drain electrode DE2, and a third drain electrode DE3. The fourth conductive layer can include a second source electrode SE2 and a third source electrode SE3. The fifth conductive layer can include a second gate electrode GE2 and a third gate electrode GE3.

[0109] The first thin-film transistor TFT1 can include a first drain electrode DE1, a first source electrode SE1, a first active pattern ACT1, and a first gate electrode GE1. The first active pattern ACT1 of the first thin-film transistor TFT1 can be disposed on the inclined surface IS of the first bank BN1.

[0110] The second thin-film transistor TFT2 can include a second drain electrode DE2, a second source electrode SE2, a second active pattern ACT2, and a second gate electrode GE2. In a plan view, the second bank BN2 is disposed to overlap the first bank BN1. The second active pattern ACT2 of the second thin-film transistor TFT2 can be disposed on the inclined surface IS of the second bank BN2.

[0111] The third thin-film transistor TFT3 can include a third drain electrode DE3, a third source electrode SE3, a third active pattern ACT3, and a third gate electrode GE3. In a plan view, the third bank BN3 is disposed on the gate insulating layer 120 without overlapping the first bank BN1 or the second bank BN2. The third active pattern ACT3 of the third thin-film transistor TFT3 can be disposed on the inclined surface IS of the third bank BN3.

[0112] According to the present embodiment, the thin-film transistor TFT of the display device 10 can include a plurality of active patterns ACT formed on the inclined surface IS of the bank BN. It should be understood that the configuration of the thin-film transistor TFT and the bank BN can be modified to have various structures and configurations according to the exemplary embodiments shown in FIGS. 1 to 6 without departing from the scope of the present disclosure. Figure 10 The exemplary embodiments shown in FIGS. 1 to 6 can be modified to have various structures and configurations without departing from the scope of the present disclosure.

[0113] Figures 11A to 11E is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to an example embodiment of the present inventive concept.

[0114] Referring to Figure 11A A buffer layer 110 can be formed on the substrate 100. A first conductive layer including a drain electrode DE can be formed on the buffer layer 110.

[0115] Referring to Figure 11B A bank BN can be formed on the buffer layer 110. The bank BN can have an inclined surface IS having an angle θ with respect to the substrate 100. According to another embodiment, the bank BN can be formed on the buffer layer 110 before the drain electrode DE is formed on the buffer layer 110.

[0116] Referring to Figure 11C A second conductive layer including a source electrode SE can be formed on the bank BN, for example, on a flat surface of the bank BN adjacent to an end of the inclined surface IS. An initial active pattern ACTa contacting and covering the drain electrode DE and the source electrode SE can be formed on the inclined surface IS of the bank BN. The initial active pattern ACTa can include amorphous silicon.

[0117] Referring to Figure 11D The initial active pattern ACTa can be crystallized by irradiating an excimer laser using a laser device (not shown) to form an active pattern ACT including crystalline polysilicon. The irradiation of the excimer laser can be performed, for example, by a linear beam scanning method.

[0118] In the case of a general laser device, a focal length of the excimer laser can be set to about 150 μm in a vertical direction. Accordingly, it can be necessary to adjust a height of the active pattern ACT by adjusting a height of the bank BN in relation to the focal length.

[0119] For example, a height t of the initial active pattern ACTa in a direction perpendicular to the substrate 100 can be adjusted so that an entire area of the initial active pattern ACTa is located within the focal length of the excimer laser. The height t can be within about 200 μm (micrometers). For example, considering the inclined surface IS of the bank BN and the focal length of the excimer laser, a height h of the bank BN can be about 150 μm.

[0120] Referring to Figure 11E A gate insulating layer 120 can be formed on the active pattern ACT. A third conductive layer including a gate electrode GE can be formed on the gate insulating layer 120. Thereafter, a source region S, a drain region D, and a channel region C of the active pattern ACT can be formed by doping impurities in portions of the active pattern ACT.

[0121] Figure 12 is a block diagram illustrating an electronic device according to an example embodiment.

[0122] Referring to Figure 12 , the electronic device 500 can include a processor 510, a storage 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 can correspond to the display apparatus 10 of Figures 4A to 5B . In addition, the electronic device 500 can further include a plurality of ports for communication with various peripheral devices including, but not limited to, a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices. In an example embodiment, the electronic device 500 can be implemented as a television. In another example embodiment, the electronic device 500 can be implemented as a smart phone. It should be understood that the electronic device 500 is not limited thereto. For example, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop, a head-mounted display (HMD), etc.

[0123] The processor 510 can execute various computing instructions. The processor 510 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 can be coupled to other components through various communication buses including, but not limited to, an address bus, a control bus, and a data bus. In addition, the processor 510 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The storage 520 can store data for operating the electronic device 500. For example, the storage 520 can include at least one non-volatile storage device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nanofloating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile storage device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 can include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 can include an input device such as a keyboard, a key, a mouse device, a touchpad, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 550 can provide power for operating the electronic device 500.

[0124] The display device 560 can be coupled to the other components of the electronic device 500 through a bus or other communication link. In some example embodiments, the display device 560 can be included in the I / O device 540. As described above, according to the display apparatus 10 disclosed herein, the active pattern of thin film transistors is disposed on the inclined surface of the bank such that the space in a plan view occupied by the thin film transistors can be reduced. Accordingly, the size of the pixels of the display device 560 can be reduced, the display device can have a high resolution, and the display quality of the display device can be improved. In addition, the height of the bank can be set in consideration of the focal length of the excimer laser used to crystallize the active pattern. In addition, the active pattern can be disposed such that the channel region of the thin film transistor is formed on the inclined surface of the bank, thereby preventing deterioration in the quality of the thin film transistor that can be caused by poor crystallization quality. In addition, the display device 560 can embody a flexible display device including a flexible area, wherein a bank of a suitable shape, size, and configuration can be provided such that the display device 560 can be foldable, bendable, or rollable.

[0125] The present disclosure can be applied to an organic light emitting display device and various electronic devices including the same. For example, the present disclosure can be applied to a mobile phone, a smart phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a television, a computer monitor, a notebook, or the like.

[0126] The above is a description of the inventive concept and is not to be construed as limiting the inventive concept. While there have been described herein a few exemplary embodiments of the inventive concept, those skilled in the art will readily appreciate that many modifications and variations of the exemplary embodiments can be made without departing from the novel teachings and advantages of the inventive concept. Accordingly, the inventive concept is intended to embrace all such alterations, modifications, and variations that fall within the scope of the inventive concept. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited functions and not only structural equivalents but also equivalent structures. Thus although specific exemplary embodiments of the inventive concept have been described herein, the present inventive concept is not to be limited to the disclosed embodiments but encompasses modifications and variations which can be made by those skilled in the art within the scope of the inventive concept. The inventive concept is defined by the appended claims and includes both the explicit embodiments described herein as well as equivalent structures.

Claims

1. A thin film transistor substrate comprising: a substrate; a first electrode arranged on the substrate; a bank arranged on the substrate and having an inclined surface inclined at an angle with respect to the substrate; a second electrode arranged on the bank; an active pattern electrically connected to the first electrode and the second electrode, the active pattern being arranged on the inclined surface and including a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region; and a gate electrode overlapping at least a part of the channel region of the active pattern, wherein the inclined surface extends in a first direction in a plan view, wherein the first conductive region, the channel region, and the second conductive region are sequentially arranged on the inclined surface along a second direction intersecting the first direction, and wherein the first electrode and the second electrode are located on different planes. The channel region of the active pattern is formed on the inclined surface.

2. The thin film transistor substrate according to claim 1, wherein A height difference between the first electrode and the second electrode is not more than 200 pm.

3. The thin film transistor substrate according to claim 2, wherein The first conductive region has a first portion overlapping the first electrode and a second portion connected to the first portion and overlapping a portion of the inclined surface adjacent to the first electrode.

4. The thin film transistor substrate according to claim 1, wherein The active pattern has an S-shape on the inclined surface.

5. The thin film transistor substrate according to claim 1, wherein 6. A display device comprising: a substrate; a first bank arranged on the substrate and having a first inclined surface inclined at a first angle with respect to the substrate; a first thin film transistor including a first electrode, a second electrode, a first active pattern, and a gate electrode; and a light emitting structure electrically connected to the first thin film transistor, wherein the first electrode is arranged on the substrate and the second electrode is arranged on the first bank, wherein the first active pattern is electrically connected to the first electrode and the second electrode and is arranged on the first inclined surface, wherein the first active pattern includes a first conductive region and a second conductive region in which impurities are doped and a channel region between the first conductive region and the second conductive region, and the gate electrode overlaps the channel region of the first active pattern, and wherein the first electrode and the second electrode are located on different planes. The first inclined surface extends in a first direction in a plan view, wherein the first conductive region, the channel region, and the second conductive region are sequentially arranged on the first inclined surface along a second direction intersecting the first direction, and 7. The display device of claim 6, wherein, wherein the substrate includes a first reinforcing region and a second reinforcing region and a flexible region bendable and arranged between the first reinforcing region and the second reinforcing region. A height difference between the first electrode and the second electrode is not more than 200 pm. The first conductive region has a first portion overlapping the first electrode and a second portion connected to the first portion and overlapping a portion of the first inclined surface adjacent to the first electrode.

8. The display device of claim 6, wherein, 10. The display device according to claim 6, further comprising:

9. The display device of claim 6, wherein, ​ ​ a second bank spaced apart from the first bank in the first direction; and a second thin film transistor comprising a second active pattern, wherein the second bank comprises a second inclined surface inclined at a second angle with respect to the substrate, and wherein the second active pattern of the second thin film transistor is arranged on the second inclined surface of the second bank.

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