Processing of iterative operations

Abstract

Processing of iterative operations is disclosed. An apparatus has processing circuitry to perform an iterative operation in response to a decoding of an iterative operation instruction by an instruction decoder, the iterative operation including at least two iterations of processing in which an iteration depends on an operand produced in a preceding iteration. Initial information producing circuitry performs an initial portion of the processing of a given iteration to produce initial information. Result producing circuitry performs a remaining portion of the processing of the given iteration to produce a result value using the initial information. For iterations other than a final iteration, forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation. The initial information producing circuitry begins performing an initial portion of the next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration to improve performance.

Description

TECHNICAL FIELD

[0001] The technology of the present application relates to the field of data processing. BACKGROUND

[0002] A data processing apparatus, such as a microprocessor, can have an instruction decoder for decoding program instructions and processing circuitry for performing processing operations in response to the decoding of the program instructions. There can be challenges in designing the processing circuitry logic so that the operations for a given instruction can be completed within timing constraints imposed by a clock frequency that is desired to be supported. SUMMARY

[0003] At least some examples provide an apparatus comprising:

[0004] an instruction decoder for decoding program instructions; and

[0005] processing circuitry for performing, in response to the decoding of an iteration operation instruction by the instruction decoder, an iteration operation comprising a plurality of processing iterations, for which iterations subsequent to a first iteration are dependent on operands produced in a preceding iteration;

[0006] the processing circuitry comprises:

[0007] initial information producing circuitry for performing an initial portion of the processing of a given iteration to produce initial information;

[0008] result producing circuitry for performing a remaining portion of the processing of the given iteration to produce a result value using the initial information determined by the initial information producing circuitry; and

[0009] forwarding circuitry for forwarding, when the given iteration is an iteration other than a final iteration, the result value produced in the given iteration as an operand for a next iteration of the iteration operation; wherein:

[0010] when the result producing circuitry performs the remaining portion of the given iteration other than the final iteration, the initial information producing circuitry is configured to start performing the initial portion of the next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration.

[0011] At least some examples provide an apparatus comprising:

[0012] a module for decoding program instructions; and

[0013] a module for processing for performing, in response to the decoding of an iteration operation instruction by the instruction decoder, an iteration operation comprising a plurality of processing iterations, for which iterations subsequent to a first iteration are dependent on operands produced in a preceding iteration;

[0014] The module for processing comprises:

[0015] The module for producing initial information by performing an initial portion of the processing of a given iteration;

[0016] The module for producing a result value by performing a remaining portion of the processing of the given iteration, using the initial information determined by the initial information producing circuitry; and

[0017] The module for forwarding, for when the given iteration is an iteration other than the final iteration, the result value produced in the given iteration as an operand for a next iteration of the iterative operation; wherein:

[0018] The initial information producing circuitry is configured to start performing an initial portion of a next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration, when the result producing circuitry performs the remaining portion of the given iteration other than the final iteration.

[0019] At least some examples provide a data processing method comprising:

[0020] Decoding an iterative operation instruction using an instruction decoder; and

[0021] In response to the decoding of the iterative operation instruction, performing an iterative operation comprising a plurality of processing iterations, for which iterations other than a first iteration depend on an operand produced in a preceding iteration;

[0022] Wherein the iterative operation is performed using processing circuitry comprising:

[0023] Initial information producing circuitry for performing an initial portion of the processing of a given iteration to produce initial information;

[0024] Result producing circuitry for performing a remaining portion of the processing of the given iteration to produce a result value using the initial information determined by the initial information producing circuitry; and

[0025] Forwarding circuitry for, for when the given iteration is an iteration other than the final iteration, forwarding the result value produced in the given iteration as an operand for a next iteration of the iterative operation; wherein:

[0026] The initial information producing circuitry starts performing an initial portion of a next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration, when the result producing circuitry performs the remaining portion of the given iteration other than the final iteration.

[0027] Further aspects, features, and advantages of the present technology will be apparent from the following description of examples, which are to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 An example of a data processing apparatus is schematically illustrated;

[0029] Figure 2 An example of a floating point reduction operation is illustrated, which is an example of an iterative operation;

[0030] Figure 3 An example of a portion of a floating point adder unit for adding two floating point operands is shown;

[0031] Figure 4 An example timing diagram is shown, which illustrates a method in which there is no overlap in the processing of successive iterations of an iterative operation for comparison;

[0032] Figure 5 A portion of processing circuitry to support an iterative operation is shown, in which an initial portion of the processing of a given iteration can be performed in parallel with completing a remaining portion of a previous iteration;

[0033] Figure 6 A timing diagram is shown, which illustrates an example of an iterative operation performed using processing circuitry of Figure 5

[0034] Figure 7 A floating point reduction unit for performing a floating point reduction operation of Figure 2 is shown; and

[0035] Figure 8 A flowchart to illustrate a method of performing an iterative operation is shown. DETAILED DESCRIPTION

[0036] ​Processing circuitry can perform data processing operations in response to program instructions decoded by an instruction decoder. When designing circuit logic for processing circuitry, there can be a constant design challenge in balancing the desire to support certain relatively complex instructions that can require circuit logic with greater logic depth, but that will therefore incur greater processing delays when signals pass through the circuit logic, and the desire to increase clock frequency as much as possible to provide improved performance. Relatively complex operations that require greater logic depth can be spread across multiple processing cycles, but if a greater number of cycles are used, then processing workloads that rely on this operation can be slowed down. This can be a particular problem for certain iterative operation instructions that require two or more processing iterations, because if each iteration has to be spread over a greater number of cycles, then the corresponding performance impact is incurred multiple times for the same instruction. Another approach to dealing with this design challenge can be to reduce the maximum clock frequency supported, leaving more time for more complex operations to complete within a certain number of clock cycles, but in this case the reduced clock frequency will reduce the performance of other types of operations that would require less logic depth and can complete in time with a faster clock frequency.

[0037] Techniques are discussed below for improving the performance of each iteration of an iterative operation instruction that, when decoded by an instruction decoder, controls processing circuitry to perform an iterative operation that includes two or more processing iterations for which a subsequent iteration, other than a first iteration of the iterative operation, depends on an operand produced in a previous iteration.

[0038] Processing circuitry includes initial information producing circuitry to produce initial information by performing an initial portion of processing for a given iteration of the iterative operation. Result producing circuitry performs a remaining portion of processing for the given iteration to produce a result value using the initial information determined by the initial information producing circuitry. When the given iteration is an iteration other than a final iteration of the iterative operation, forwarding circuitry forwards the result value produced in the given iteration as an operand for a next iteration of the iterative operation.

[0039] For iterative operations in which the results of an earlier iteration are forwarded for use in a subsequent iteration, one might expect that it is not possible to start the next iteration until the results of the previous iteration have been produced. However, contrary to intuition, the inventors have realized that the initial information producing circuitry can start performing the initial part of the processing of the next iteration in parallel with the result producing circuitry completing the remaining part of the current iteration. Because the latency of each iteration can be less than the combined latency of the initial part and the remaining part of the processing, performance is enabled to be improved so that the iterative operation instruction can be executed on processing circuitry that supports a higher clock frequency than would otherwise be possible. This not only provides a performance benefit for the iterative operation instruction itself, but also for other instructions because when the iterative operation instruction supports a higher clock frequency, other instructions can also benefit from that higher clock frequency.

[0040] The latency between the initial information producing circuitry starting the initial part of a given iteration and the initial information producing circuitry starting the initial part of the next iteration can be less than the latency between the initial information producing circuitry starting the initial part of a given iteration and the result producing circuitry completing the remaining part of the given iteration. This means that the processing circuitry is able to operate according to a clock signal having a clock period that is shorter than the combined latency of the initial part and the remaining part. The delay between starting the initial part of a given iteration and starting the initial part of the next iteration can correspond to N clock periods, where N is one or more, but due to the overlap between the initial part of the next iteration and the completion of the remaining part of the current iteration, this means that the total processing of a given iteration (the combination of the initial part and the remaining part) actually has more than N periods to complete so that more aggressive scaling of the clock frequency becomes possible.

[0041] The initial information producing circuitry can perform the initial part of a given iteration in an earlier clock period than a clock period in which the result producing circuitry starts performing the remaining part of the given iteration. Thus, for the first iteration performed for an iterative operation instruction, the initial part of the first iteration can be performed in a setup clock period, and then in the next clock period, the remaining part can be started for the given iteration, where the initial part of the next iteration is performed in parallel with the end of the remaining part of the given iteration.

[0042] This technique can be applied to operations that require two or more clock cycles for the remainder of the processing, i.e., where in the example discussed above, N is equal to 2 or greater. However, this is particularly useful for operations that are slightly deeper in logic depth than can be accommodated in a single clock cycle, as the technique can then allow operations with excessive logic in one cycle to still be processed according to single-cycle-per-iteration utilization of delay scaling, which can be extremely beneficial for performance. In particular, for implementations where N = 1 (i.e., the initial portion of one iteration starts one cycle after the initial portion of the previous iteration), the total number of clock cycles to produce the result can be M + 1 (one setup cycle and M cycles per iteration result production cycle), where M is the number of iterations in the iterative operation.

[0043] The initial portion of the processing of a given iteration can include producing information about the operands to be processed in that iteration. For example, some initial processing of the operands can be needed to determine which logic paths within the result production circuitry are needed, or to produce configuration signals for configuring certain logic elements of the result production circuitry (such as determining the amount of shifting for a shifter, e.g., for partial or full exponent difference for effective alignment).

[0044] One can ask why iterative operations that involve dependencies between iterations (and thus require forwarding of the result of one iteration as an operand of the next iteration) can be implemented with the initial portion of the next iteration executed in parallel with the end of the previous iteration. However, the inventors have recognized that several options can be implemented for parallelization between iterations, despite the forwarding of the operand of the next iteration based on the result of the previous iteration.

[0045] In one example, for subsequent iterations other than the first iteration, the subsequent iteration can depend not only on the forwarded operand that is forwarded by the forwarding circuitry based on the result value from the previous iteration, but also on a second operand that is independent of the result of the previous iteration. In this case, the initial information determined by the initial information production circuitry can include information derived from the second operand. Because the second operand is independent of the result of the previous iteration, the second operand can be obtained before the result of the previous iteration has been produced. The initial information production circuitry can thus start deriving information from the second operand before the remainder of the processing of the previous iteration is completed, so that the logic depth of the remainder of the processing can be shallower, as it does not need to include the logic for determining the initial information from the second operand.

[0046] As an alternative or in addition to deriving initial information from the second independent operand, another approach can be that the initial information can be information derived from early information on the forwarded operand, which can be available before the forwarded operand has been fully determined by the result generation circuitry for the previous iteration. For example, certain partial information on the operand that is forwarded to the next iteration can be obtained early, and thus certain initial information can be derived from early information for the next iteration of the iterative operation, in parallel with the ongoing computation of the full value of the forwarded operand in the previous iteration.

[0047] For example, the forwarded operand can be a floating point operand having a sign, an exponent, and a number of significant bits. Typically, the sign and / or the exponent of the floating point result can be available earlier than the significant bits, as computing the significant bits can require a greater logic depth than computing the exponent or the sign. Thus, the early information returned about the forwarded operand can include information derived from at least one of the sign or the exponent of the forwarded operand. Thus, initial information about the operand to be processed in the next iteration can be pre-computed prior to the full forwarded operand including the significant bits having been computed for the previous iteration, to speed up processing of the next iteration.

[0048] In cases where there is also a second operand that is independent of the result of the previous iteration, the early information about the forwarded operand can be compared with information derived from the second operand to provide additional initial information. For example, the early available exponent of the forwarded operand can be compared with the exponent of the second independent operand to produce at least one bit of the difference in the exponents, which can be useful to speed up the floating point addition in the next iteration.

[0049] The present technology can be particularly useful for iterative operations whose result value for a given iteration includes a rounded floating point value obtained by adding floating point operands. Floating point addition can be relatively slow and require a relatively large logic depth, as the addition of floating point operands can require initial analysis of the exponents of the floating point operands, alignment of the significant bits of the operands based on the difference between the exponents, addition of the aligned significant bits, and rounding to produce the rounded floating point result. Thus, floating point addition can typically present some of the most stringent timing constraints when designing the processing logic of a given processor. In iterative operations that require floating point addition at each iteration, the techniques discussed above can be very useful to speed up performance by reducing the latency per iteration, which is obtained by overlapping the initial information computation with the remaining portion to produce the rounded floating point value in the previous iteration.

[0050] For such iterative operations involving floating point addition, the initial information can include various different types of information about the floating point operands to be added. For example, the initial information can include any one or more of the following:

[0051] • an indication of whether one of the floating-point operands is subnormal;

[0052] • an indication of whether one of the floating-point operands is infinite;

[0053] • an indication of whether one of the floating-point operands is a non-numeric value;

[0054] • at least a portion of an exponent difference indicating a difference between the exponents of the floating-point operands;

[0055] • an indication of whether the fractional part of the number of significant bits of one of the floating-point operands is zero;

[0056] • an indication of whether the floating-point operands are symbolic or non-symbolic.

[0057] All of this information can be used to control floating-point addition. By computing any of this information in parallel with the end of a previous iteration, this reduces the overall logic depth for the remainder, and thus improves performance by enabling higher clock frequencies.

[0058] While the techniques of the present invention can be used for any iterative operation involving floating-point addition, the techniques can be particularly useful for a floating-point reduction operation. For this operation, the iterative operation instruction can identify a scalar floating-point operand and a vector data value containing a plurality of data elements, each data element specifying a floating-point operand. For this instruction, each active iteration of the iterative operation can include adding a first floating-point operand to a second floating-point operand. For a first active iteration of the active iterations, the first floating-point operand is the scalar floating-point operand, and the second floating-point operand is the floating-point operand specified in a first active data element of the vector data value. For subsequent active iterations of the active iterations, the first floating-point operand is the forwarded result of the addition in the previous active iteration, and the second floating-point operand is the floating-point operand specified in a subsequent active data element of the vector data value. Predicate information can be provided to specify which data elements in the vector data value are active data elements. Each iteration takes as its second floating-point operand the corresponding element of the vector, and if that vector is marked as active by the predicate information, this indicates that the corresponding iteration is an active iteration, while iterations for which the predicate information indicates that the corresponding data element of the vector is not active are treated as inactive iterations. For inactive iterations, a flip-flop in the processing logic can have its enable signal de-asserted to prevent it from being updated based on the inactive vector element.

[0059] Processing systems can support vector operations for which multiple lanes of processing can be performed in response to a single instruction (this approach can also be referred to as single instruction multiple data (SIMD) or SIMD), each lane using a respective data element of at least one vector operand. Some SIMD implementations can provide hardware for processing multiple vector lanes in parallel, while other circuit implementations can execute at least some of the vector lanes sequentially or one after another in blocks. Regardless of the approach, using vector processing can improve code density and performance by reducing the burden of fetching and decoding instructions compared to equivalent scalar code for which a separate instruction is needed for each lane of processing.

[0060] One use of such vector instructions can be to perform a number of lanes of floating point processing that accumulate their results into respective elements of a vector, but ultimately can desire to add together all of the elements in the vector to produce a scalar result, in which case the vector reduction operations discussed above can be useful. It can be useful to include a scalar operand in the addition because this represents that the vector reduction instruction can add all of the elements of a vector operand to a scalar result obtained by a previous vector reduction instruction based on a different vector operand, so that by successively executing several vector reduction instructions, elements from multiple vectors can be accumulated together.

[0061] However, because floating point addition is non-associative, it can be important that the addition of the respective vector elements is performed in a predefined order to ensure that the result of adding the elements is predictable / reproducible. Thus, iterations that add each successive element of a vector to a scalar operand or the result of an earlier iteration can need to be performed sequentially. This represents that the performance of a single iteration can be important because any reduction in speed of a single iteration will have an impact on the overall instruction because its latency will occur multiple times. However, because each iteration involves floating point addition, which can be a relatively slow operation compared to other types of processing operations, and thus timing constraints can be relatively strict. The techniques discussed above can be very useful for these vector reduction operations to allow for a smaller logic depth in one cycle because some initial information for the next cycle is computed in parallel with the result for an earlier cycle to improve the performance of the system as a whole and support higher clock frequencies.

[0062] One problem with this vector reduction operation is that for the first active iteration, the scalar float operand is injected as the first float operand, while for subsequent cycles, the first float operand is the forwarded operand forwarded from the result of the preceding active iteration. It is believed that this would require a multiplexer to select when to inject the scalar float operand as the first float operand, and that multiplexer should be placed on the forward loop signal path that provides the forwarded result of the addition in the previous active iteration as the first float operand to be input for the subsequent active iteration. However, in practice, a multiplexer can introduce a relatively large logic depth and this added delay to the forward loop signal path can be enough to make it impractical for the signal path to perform a single iteration of the vector reduction operation in a single cycle when clocked at some higher clock frequencies.

[0063] Instead, as discussed further below, the multiplexer to select when to inject the scalar float can be located outside of the forward loop signal path that provides the forwarded result of the addition in the previous active iteration as the first float operand for the subsequent active iteration. Thus, the forwarded result can simply be input to the next iteration without going through the multiplexer, and the multiplexer is taken off the critical timing path via the forward loop. Instead, the forward loop signal path can include OR circuitry that provides the first float operand to be processed in a given iteration. This OR circuitry can combine a first input with a second input according to a bitwise OR operation. In iterations other than the first active operation, the first input to the OR circuitry can be the forwarded result of the addition performed in the previous active iteration. The second input can include the output of a multiplexer that selects between a scalar operand, an all-zero value, and optionally other values such as the forwarded result from the final iteration of a previous example of executing a vector reduction (iteration operation) instruction. Since the OR circuitry typically has a shallower logic depth than the multiplexer, this improves performance since the latency along the forward loop signal path is shorter, making it practical to perform a single cycle of the float vector reduction operation at higher clock frequencies.

[0064] To be able to use OR circuitry instead of multiplexers on the critical timing path, the result generation circuitry and the multiplexers themselves can simultaneously ensure that in the cycles where both are not intended to provide the value to be used as the first floating-point operand, the result generation circuitry and the multiplexers output zero values, so that when ORed with the output from the other path, the result will be correct. Thus, in the final iteration of the iterative reduction for the first iterative reduction instruction, the processing circuitry can provide a full zero value on the forward loop signal path, which is to be used as the first input to the OR gate for the first active iteration of the subsequent iterative reduction instruction. On the other hand, the multiplexers can select the scalar floating-point operand (or the forwarded result from the final iteration of an earlier iterative reduction instruction) in the first active iteration of a given iterative reduction instruction, and select the full zero value in one or more subsequent active iterations. Thus, in each iteration, either the output of the multiplexers or the output on the forward loop signal path is zero, while the other is non-zero (it is not possible for both outputs to be non-zero at the same time). In this way, the presence of multiplexers on the critical timing path can be avoided, which are replaced with OR circuitry to improve performance and reduce latency.

[0065] Another way to avoid the latency loss of multiplexers on the forward loop signal path can be to inject the scalar floating-point operand into the output of the forwarding circuitry via a signal path having a shorter logic depth than the logic depth of the result generation circuitry used to generate the actual floating-point addition result during the setup processing cycle. Thus, during the setup processing cycle, the output of the forwarding circuitry, which circuitry will provide the floating-point addition result for the given iteration in the subsequent cycle, can instead output the scalar floating-point operand, so that in the subsequent clock cycle, the result generation circuitry can use the scalar floating-point operand as the first floating-point operand for the first iteration of the loop to perform the remaining part of the processing. This approach can remove the OR circuitry and the multiplexers from the critical timing path of the forward loop.

[0066] Floating-point representation

[0067] Floating-point (FP) is a useful way to approximate real numbers using a small number of bits. The IEEE 754-2008 FP standard provides a number of different formats for FP numbers, some of which are binary 64-bit (also known as double precision, or DP), binary 32-bit (also known as single precision, or SP), and binary 16-bit (also known as half precision, or HP). The numbers 64, 32, and 16 represent the number of bits required for each format.

[0068] FP numbers are very similar to the "scientific notation" taught in science classes, where instead of writing -2,000,000, we write -2.0 x 10 6 The parts of this number are the sign (negative in this case), the number of significant digits (2.0), the base of the exponent (10), and the exponent (6). All of these parts are similar in FP numbers, although there are differences; the most important is that each component is stored in binary numbers, and the base of the exponent is always 2.

[0069] More precisely, an FP number is made of a sign bit, some biased exponent bits, and some fraction bits. Some FP formats of interest provide the following bits:

[0070] Symbol Exponent Fraction Exponent Bias DP[63:0] 63 62:52 (11 bits) 51:0 (52 bits) 1023 SP[31:0] 31 30:23 (8 bits) 22:0 (23 bits) 127 HP[15:0] 15 14:10 (5 bits) 9:0 (10 bits) 15

[0071] The sign of a negative number is 1, and the sign of a positive number is 0. Every number (including zero) has a sign.

[0072] The exponent bias indicates that the true exponent is different from the exponent stored in the number. For example, the biased SP exponent is 8 bits long and ranges from 0 to 255. Exponents 0 and 255 are special cases, but all other exponents have a bias of 127, indicating that the true exponent is less than the biased exponent 127. The smallest biased exponent is 1, which corresponds to the true exponent -126. The largest biased exponent is 254, which corresponds to the true exponent 127. HP and DP exponents work in the same way, with the bias indicated in the table above.

[0073] SP exponent 255 (or DP exponent 2047, or HP exponent 31) is reserved for infinity and a special symbol called NaN (not a number). The fraction of an infinity (which can be positive or negative) is zero. Any number with exponent 255 and a non-zero fraction is NaN. Infinity provides a saturation value, so that value actually indicates a situation such as "the number produced by this computation is larger than we can represent in this format." NaN is returned for operations that are not mathematically defined on real numbers, such as dividing by zero or taking the square root of a negative number.

[0074] In any format, exponent zero is reserved for subnormal numbers and zero. Normal numbers represent values: -1 符号 x 1. fraction x 2 ewhere e is the exponent computed from the biased exponent. The "1. fraction" is called the significand, and the 1 is not stored as part of the FP number, but is inferred from the exponent. All exponents except zero and the maximum exponent indicate a significand in the form "1. fraction". The exponent zero indicates a significand in the form "0. fraction", and the true exponent is equal to the 1-bias for the given format. This number is called subnormal (historically such numbers were called denormal, but modern usage tends to the term subnormal). A number with both the exponent and the fraction equal to zero is zero.

[0075] The following table has exemplary numbers in the HP format. The entries are in binary format, and the "_" character is added for readability. Note that the subnormal entry (line 4 in the table, with exponent zero) produces a different significand than the normal entry in the previous line.

[0076] 5-bit exponent 10-bit fraction 11-bit significand Value 0 01111 00_0000_0000 100_0000_0000 1.0X 2 0 ]]> 1 01110 10_0000_0000 110_0000_0000 -1.1 X 2 -1 ]] 0 00001 10_0000_0000 110_0000_0000 1.1 X 2 -14 ]]> 0 00000 10_0000_0000 010_0000_0000 0.1X 2 -14 ]] 1 11111 00_0000_0000 - infinite 0 11111 00_1111_0011 NaN

[0077] Much of the complexity of FP implementation is due to subnormals, so they are usually handled by microcode or software. In contrast to software or microcode implementations, processing circuitry that handles subnormals in hardware can speed up these operations by a factor of 10 to 100.

[0078] Integer, fixed point, floating point

[0079] The FP way of handling signs is called sign-magnitude, and it is different from the way that integers are usually stored in computers (two's complement). In sign-magnitude representation, the positive and negative versions of the same number differ only in the sign bit. A 4-bit sign-magnitude integer (made up of a sign bit and 3 significant bits) will represent plus and minus one as:

[0080] +1 = 0001

[0081] -1 = 1001

[0082] In two's complement representation, an n-bit integer i is represented by a binary n+1-bit value 2 n + i, so a 4-bit two's complement integer will represent plus and minus one as:

[0083] +1 = 0001

[0084] -1 = 1111

[0085] The two's complement format is actually universal for signed integers, because it simplifies computer operations.

[0086] A fixed-point number looks exactly like an integer, but in fact its representation has a value with a certain number of fractional digits. Sensor data is often in fixed-point format, and there is a large body of fixed-point software that has been written before FP was widely adopted. The use of fixed-point numbers is very cumbersome because the programmer has to keep track of the "binary point," the separator between the integer and fractional parts of the number, and also has to shift the number constantly to keep the bits in the right place. FP numbers do not have this difficulty, so it is desirable to be able to convert between fixed-point and FP numbers. Being able to convert means that we can still use fixed-point software and data, but when writing new software we are not limited to fixed-point.

[0087] Rounding of FP numbers

[0088] The IEEE-754 standard requires that most FP operations be computed as if the operation were performed with unlimited range and precision, and then rounded to fit the FP number. If the computation exactly matches the FP number, then that value is always returned, when normally the computation would produce a value that lies between two consecutive floating-point numbers. Rounding is the process of choosing which of the two consecutive numbers should be returned.

[0089] There are a number of ways of rounding, called rounding modes; six of these rounding modes are as follows:

[0090] Mode Definition RNE round to nearest, ties to even round to the nearest value, or if two values are equally near, round to the even value RNA round to nearest, ties to away round to the nearest value, or if two values are equally near, round to the value furthest from zero RZ round toward zero round to the value nearest to zero RP round toward plus infinity round to the value nearest to positive infinity RM round toward minus infinity round to the value nearest to negative infinity RX round toward odd round to the odd value

[0091] This definition does not tell us how to make the choice in any practical way. One common implementation is to do the computation, find the truncated value (i.e., the value that fits the FP format) and all the remaining bits, and then adjust the truncated value if certain conditions are met. All the computation is based on:

[0092] L (lowest) the least significant bit of the lowest truncated value

[0093] G (guard) the next most significant bit (i.e., the first bit not included in the truncation)

[0094] S (sticky) the logical OR of all the remaining bits that are not part of the truncation.

[0095] Given these three values and the truncated value, we can compute the correctly rounded value according to the following table (Table 1):

[0096] Table 1

[0097] Mode change to truncate value RNE increment if (L & G) | (G & S) RNA increment if G RZ none RP increment if positive & (G | S) RM increment if negative & (G | S) RX set L if G | S

[0098] For example, consider multiplying two 4-bit- fraction numbers and then rounding to 4-bit- fraction numbers.

[0099] sigl = 1011 (decimal 11)

[0100] sig2 = 0111 (decimal 7)

[0101] Multiply the earnings

[0102] sig1 x sig2 = 1001 101 (decimal 77)

[0103] L Gss

[0104] The least significant bit of the truncated 4-bit result is labelled L, the next bit G, and S is the logical OR of the remaining bits labelled s (i.e. S = 0 | 1 = 1). To round, we adjust our 4-bit result (1001) according to the rounding mode and calculation in the table above. So for example in the RNA round, G is set, so we return 1001 + 1 = 1010. For the RX round, G | S is true, so we set L to 1 (which is already 1, so no change in that case) and return 1001.

[0105] Example

[0106] Figure 1 An example of a data processing apparatus 2 is schematically illustrated. The data processing apparatus has a processing pipeline 4 comprising a number of pipeline stages. In this example, the pipeline stages comprise: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to produce micro-operations to be processed by the remaining stages of the pipeline; an issue stage 12 for checking whether the operands required by a micro-operation are available in a register file 14, and once the required operands for a given micro-operation are available, issuing the micro-operation for execution; an execution stage 16 for executing the data processing operations corresponding to the micro-operations by processing the operands read from the register file 14 to produce result values; and a write back stage 18 for writing the results of the processing back to the register file 14. It will be appreciated that this is just one example of a possible pipeline architecture, and other systems can have additional stages or differently configured stages. For example, in an out-of-order processor, an additional register renaming stage can be included for mapping architectural registers specified by program instructions or micro-operations to physical register specifiers which identify physical registers in the register file 14.

[0107] The execution stage 16 includes a number of processing units for performing different classes of processing operations. For example, the execution units can include a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logic operations on scalar operands read from a scalar register file 21, a floating point unit 22 for performing operations on floating point values, a branch unit 24 for evaluating the results of a branch operation and adjusting the program counter accordingly to represent the current point of execution, and a load / store unit 28 for performing load / store operations to access data in the memory system 8, 30, 32, 34. In this example, the memory system includes a level one data cache 30, a level one instruction cache 8, a shared level two cache 32, and a main system memory 34. It will be appreciated that this is just one example of a possible memory hierarchy, and that other arrangements of caches can be provided. The particular types of processing units 20-28 shown in the execution stage 16 are just one example, and other implementations can have a different set of processing units or can include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be handled in parallel. It will be appreciated that Figure 1 is a simplified representation of certain elements of a possible processor pipeline architecture, and that the processor can include many other elements not shown for the sake of brevity, such as a branch prediction mechanism or an address translation or memory management mechanism.

[0108] The floating point unit 22 supports processing operations performed on operands represented in floating point notation. The floating point operations can include operations performed on scalar floating point operands stored within scalar registers, or on respective data elements of vector operands stored in vector registers. Some operations can also process both scalar and vector operands.

[0109] One type of floating point operation that can be supported by the floating point unit 22 can be a floating point vector reduction operation; this operation can be controlled by a vector reduction instruction FADDA as shown in Figure 2 The FADDA instruction is an example of an iterative operation instruction as discussed above. The FADDA instruction specifies a scalar destination register Rd, a vector source register Za, a scalar source register Rb, and a predicate register Pg. The scalar source register Rb contains a scalar floating point operand Sc that contains a sign, a number of significant bits, and an exponent as discussed above. Also, each element V of the vector source register Za also contains a floating point operand that again contains a sign, a number of significant bits, and an exponent. The predicate register Pg contains a series of predicate indications, each of which indicates whether the corresponding element of the source vector register Za is valid or invalid. In this example, the vector element V[1] is indicated as invalid because its corresponding predicate flag in position 1 of the predicate register is 0; while the other vector elements of Za are all valid because their predicate flags are 1.

[0110] Figure 2 The lower portion shows the operations to be performed for the FADDA instruction. In the first iteration (iteration 0), the scalar operand Sc in register Rb is added to the first active element V[0] in vector register Za using a floating-point add that includes rounding and normalization to produce iteration 0 result Sc + V[0]. In this example, the next iteration (iteration 1) would normally add the result of iteration 0 to vector element V[l], but since the V[l] element is inactive by the predicate mask, the output of iteration 0 is carried over as the output of iteration 1 without adding in the next vector element V[l]. For Figure 2 The subsequent iterations 2 and 3 shown in the middle portion again use a floating-point add that includes rounding and normalization to add successive active elements V[2], V[3] of the vector one at a time to the result of the previous iteration until a final result is produced; in this example, the final result corresponds to the sum of the scalar operand Sc and the three active elements V[0], V[2], and V[3]. This final result is stored to the destination register Rd. In practice, it can be relatively common to execute several FADDA instructions in succession, where the different source vector as the vector register Za, and the destination register Rd for one FADDA instruction become the source scalar register Rb for the next instruction to add together vector elements across multiple vectors.

[0111] Floating-point adds are not associative, in order to provide a predictable result, the iterations must be performed in an order that corresponds to the order of the vector elements in the source vector, and the iterations cannot be performed in parallel, so that this type of operation is relatively sensitive to any increased latency associated with performing a single iteration of the floating-point add, as any increased latency will occur multiple times, once per iteration. Thus, it can be desirable to provide techniques for reducing the per-iteration latency for this instruction.

[0112] To compare, Figure 3 An example of the processing logic that can be provided within the floating-point unit 22 for supporting this type of floating-point add is shown. Figure 3 The logic for a single iteration is illustrated, and for brevity, forwarding of operands back to another iteration is not shown. In general, the add can involve a first calculation of information about the operands opa, opb to be added using the logic 30. For example, the exponent difference between the exponents of the operands can be calculated, as well as information about whether the exponents / significand sizes have certain special values that indicate that the floating-point operands are subnormal, infinity, NaN, etc. as discussed above. This calculated information can then be used to configure how the add / routing circuitry 32 or special value handling system 34 processes the operands to produce the result.

[0113] Depending on the information calculated for the operands, the addition / rounding circuitry 32 may include near-path logic 36 and far-path logic 38 to handle different types of processing. Floating-point addition can be considered to represent either like-signed addition (LSA) or unlike-signed addition (USA). LSA is performed when an addition operation is performed on two operands of the same signed value, or when a subtraction operation is performed on values ​​of different signs (which are effectively additions). USA, on the other hand, is an addition operation performed on floating-point operands of different signs, or a subtraction operation performed on operands of the same sign. Far-path logic 38 may be designed to handle all LSA operations and those USA operations performed on operands whose exponent difference is greater than 1. Far-path logic 38 may include processing for aligning the significands of the operands based on the exponent difference, adding the aligned significands, and rounding the result. On the other hand, the near path logic 36 may handle USAs where the exponents are the same or differ by only 1, in which case logic may be needed for adjusting the exponent based on the number of leading zeros in the addition result and for handling potential subnormal outputs.

[0114] Thus, in general, floating-point addition may require computing some information about the operands to decide how to process the operands, for example, so that a near path 36 or a far path 38 may be selected; and for configuring other parts of the operation, such as the amount of shift required for alignment in far path 38; or for deciding whether special value handling 34 is required for special floating-point values ​​such as infinities or NaNs.

[0115] like Figure 4 As shown in , if floating-point addition is included in Figure 2 If, in an iterative operation of a vector reduction operation of , then one would expect that in each cycle of the iterative operation, it would be necessary to first calculate information about the operands to be processed in that cycle, and then add the operands based on the calculated information about the operands. The logic 30 for calculating the information about the operands and the subsequent addition circuitry 32 may both require a certain logic depth, so that the minimum clock cycle C1 (and therefore the maximum clock frequency) that can be supported by the processing logic can be constrained based on the combined logic depth of the circuit logic 30, 32.

[0116] Figure 5 Shows an alternative approach. Figure 5 Shown for support Figure 2part of the floating-point unit 22 that handles floating-point vector reduction as shown in the following diagram. The floating-point vector reduction logic includes two stages, stage 0 and stage 1. Stage 1 includes most of the circuit logic for performing floating-point addition (e.g., near / far path logic). For both the near path and far path logic (which are not distinguished in Figure 5 the diagram for simplicity), the addition circuit logic can include: significand processing logic 50 that produces the significand of the result of adding two floating-point operands opa, opb; exponent and sign processing logic 52 that produces the exponent and sign of the result of adding the operands OP A, OPB. These are located in performing stage 1.

[0117] Selection circuitry 54 is provided to select which operand is to be provided as the first floating-point operand opa to the significand processing logic 50 and the exponent / sign processing logic 52. In the initial cycle of the iterative floating-point reduction operation, the value from the scalar register Rb can be selected as the operand opa, while in subsequent cycles, the floating-point result from the previous iteration can be used, which is forwarded on a forwarding path 56 of the forwarding circuitry. On the other hand, the other operand opb can be selected from the respective vector elements of the source vector Za for the FADDA instruction.

[0118] As Figure 5 shown in the diagram, the floating-point unit includes initial information determination circuitry 60, which includes a part 60-0 within stage 0 and a part 60-1 within stage 1. In parallel with the completion of the production of the addition result of the previous iteration by the significand processing logic 50, the initial information production circuitry 60 produces the operands opa, opb to be processed in the next iteration of the FADDA instruction. This makes use of two properties of the FADDA instruction, which are that although one iteration of the iterative operation requires the result produced in the previous iteration, it is still possible to overlap the processing of successive iterations so that successive iterations are performed in part in parallel. First, for the FADDA instruction, the vector elements within the vector register Za can be available from the start of the instruction processing, and do not depend on the addition output in earlier cycles of the operation, and then the stage 0 initial information production circuitry 60-0 can precompute the initial information in parallel with the addition logic 50, 52 that produces the forwarded operand opa to be used for the next loop.

[0119] Further, in general, the exponent and sign processing logic 52 can have a shorter logic depth than the significant processing logic 50. For example, the significant processing logic 50 can require relatively slow operations, such as shifts for alignment and carry-propagating addition; whereas the exponent and sign can be generated based on combinatorial logic or by selecting between the exponent and sign of the input operands, and thus can be available earlier. Thus, early information 58 about the exponent or sign of the value of the operand opa to be used as the operand for the next iteration can be obtained before the full forwarded operand 56 is available. Thus, the level 1 initial information generation circuitry 60-1 can pre-compute information about the operand opa to be used in the next cycle before the full value of opa has been generated. At the same time, this level 1 initial information generation 60-1 can pre-compute information (e.g., all or part of the exponent difference) based on a comparison of the early information for the next iteration's operand opa with the full value known for the next iteration's operand opb.

[0120] By introducing some pre-computation of information about the operands earlier in the cycle, this represents that the logic depth within the addition logic 50, 52 for the next cycle can be shorter, so that it is possible to use a higher clock frequency. Figure 6 A timing diagram showing how this is implemented is shown. As shown in Figure 6 compared to Figure 4 the clock cycle C2 in Figure 6 may be reduced relative to the clock cycle CI in Figure 4 because now the initial part of the processing 70 to generate initial information for the operands for a given iteration overlaps with the completion of the remaining part 72 to generate the result for the previous iteration.

[0121] Thus, in iteration 0, the initial part 70 of the processing is first performed within the set clock cycle to compute initial information about the operands opa[0], opb[0] to be processed in iteration 0; and then in the next clock cycle (cycle 0), the result of processing the input operands opa[0], opb[0] is generated, and this result is forwarded for use as the operand opa[l] for iteration 1. At the same time, in parallel with the end of the remaining part 72 of the processing of iteration 0 to generate the result OP A [1], the initial part 70 of iteration 1 is performed in clock cycle 0 based on the value of opb[l] known in advance and based on the early information 58 returned on the exponent and sign of opa[l]. Similarly, for iterations 2 and 3, the initial part 70 is started before the end of the remaining part of the preceding iteration.

[0122] Thus, this means that the FADDA instruction can be supported on a system that uses a clock signal having a clock period C2 that is shorter than the combined latency L of the initial portion 70 and the subsequent portion 72 of a given iteration of the iterative operation. This enables a more aggressive scaling of the clock frequency to not only improve performance for the FADDA instruction itself, but also for all other instructions supported by the processing circuitry; as the processing circuitry is clocked at a higher clock frequency, then these other operations are also sped up.

[0123] Figure 7 An example of a floating point reduction unit that can be provided within the floating point unit 22 discussed above is shown. As shown on the left hand side of Figure 7 As shown on the left hand side of The scalar operand from Rb and the vector elements el_1 to el_3 of Za other than the first vector element el_0 are saved within internal registers 100, 102 of the floating point reduction unit in the case that the corresponding source registers Rb, Za have been overwritten at the time that the scalar operand and the vector elements el_1 to el_3 of Za other than the first vector element el_0 are required in the following clock cycle at the subsequent iteration of the FADDA operation. The internal register 100 for saving the scalar operand is provided because it is possible that the first valid element of the vector can be one of the elements el_1 to el_3 (if the predicate Pg flags el_0 as invalid), in which case the scalar value will be required in the subsequent iteration.

[0124] The enable logic 103 is provided to provide enable signals that enable the flip-flops in the second execution stage 104 to update based on the values from the first execution stage 106. In iteration X of the FADDA operation, if the predicate for element el_X indicates that element el_X is invalid, then the enable logic 103 de-asserts the flip-flop enable signals to ensure that the output flip-flops 108 of the second execution stage 104 retain their previous values and will not be updated, effectively providing the masking of iterations as shown in the example of Figure 2 By preventing the flip-flop updates, this also saves power for the invalid iterations of the iterative operation. The first execution stage 106 includes a multiplexer 110 that selects which of the elements el_0 to el_3 of the input vector from the register Za to provide as the operand opb in the current iteration. The multiplexer is controlled by an element counter 112 that cycles through the values 0, 1, 2, 3 to select the next element each cycle. The other operand opa of the addition is selected by the selection circuitry 54, which is implemented using a multiplexer 54-0 and an OR gate 54-1, which will be described in more detail below.

[0125] like Figure 5 As shown in FIG, addition logic 50, 52 is provided in the second execution stage 104, and initial information generation circuitry 60 is provided, including a portion 60-1 within the first stage 106 and a portion 60-1 within the second stage 104. In this example, the information about the operands opa, opb for the next iteration calculated in advance by the initial generation circuitry 60 includes an indication of whether the exponent of each operand opa, opb is zero, which is captured in a flip-flop 116. Precalculating whether the exponent is zero can be useful because it allows for early configuration of logic within the floating-point adders 50, 52. For example, it can allow for determining whether a floating-point operand is subnormal, which may require adjusting the exponent from 0 to 1 before processing. By incurring the logic delay associated with determining whether the exponent of one iteration is zero in parallel with the calculation of the floating-point result of the previous iteration, this reduces latency within the second execution stage, making it more practical to fit the logic depth of the floating-point adders 50, 52 within a single clock cycle.

[0126] Figure 7 The diagram illustrates forwarding path 56, which serves as forwarding circuitry to forward the floating-point result generated by the floating-point adder during one iteration back to be used as input for operand opa in the next iteration. While one might assume this would require a multiplexer to select between the forwarded result on forwarding path 56 and the scalar input provided from register Rb, such a multiplexer would introduce significant additional delay. Therefore, to speed up processing, forwarding path 56 provides its input to OR gate 54-1, and the other input to OR gate 54-1 is the output of multiplexer 54-0. Therefore, OR gate 54-1 simply performs a bitwise OR of its two inputs and provides the result as operand opa (including the exponent and fraction) to floating-point adders 50 and 52. OR gates have much shorter logic delays than multiplexers, thus improving performance.

[0127] When an OR gate is used, then if either input is non-zero, the non-zero bit in that input will affect the output of the OR gate 54-1. Therefore, to ensure that only one of the OR gate inputs is non-zero, either the loop forwarding path 56, or the output of the multiplexer 54-0 should generally provide a value of zero. A flip-flop 120 is provided to provide a signal to the floating point adder 60-1, which forces the value provided on the forwarding path 56 to be cleared to zero in the final iteration of processing of a given floating point reduction instruction FADDA. Therefore, this flip-flop 120 asserts in a clock cycle when the element counter 112 is equal to the value "Done", which corresponds to the element position at the most significant end of the vector (e.g., for Figure 2"done" = 3). Thus, in the final iteration of a floating point vector reduction operation, the value on the loop forward path signal line 56 is output as all zeros, indicating that when the floating point reduction unit begins the iteration operation for the next floating point vector reduction instruction, the all zero value on the loop forward path 56 will not interfere with the value output by the multiplexer 54-0 in the first cycle of the next instruction, which value can then be selected based on the scalar value.

[0128] In any cycle other than the first active iteration of the iteration operation, the opa multiplexer 54-0 selects the all zero value 122 to be provided to the or gate 54-1 so that the value will not interfere with the forwarded result on the forward path 56 from the addition in the previous iteration. In the first active iteration for a given floating point vector reduction instruction, the opa multiplexer 54-0 selects one of: (1) the output 124 from the scalar source register Rb itself; (2) the saved scalar operand stored in the internal register 100 of the floating point reduction unit; (3) the floating point operand provided on the instruction to instruction forward path 126, which provides the result 108 from one FADDA instruction as a potential input and as the scalar operand from the next instruction to avoid the delay of writing the result to a register and then reading it out again. Thus, if forwarding between instructions is needed, the value on the internal instruction to instruction forward path 126 can be selected. If forwarding between instructions is not needed (because the previous instruction executed was not another floating point vector reduction instruction, or because the destination register Rd of the previous floating point vector reduction instruction is different than the source register Rb of the current floating point vector reduction instruction), and if the first iteration is active, the value 124 from the original scalar register Rb is selected on the first iteration (corresponding to element el_0); or if the first active iteration is one of the subsequent iterations 1, 2, 3 other than iteration 0, the value from the internal register 100 is selected on the first active iteration, because iteration 0 is marked as inactive by the assert. Once a given active iteration has been processed, for any remaining iterations the opa multiplexer 54-0 selects the all zero value 122 to avoid interference with the iteration to iteration forwarding on the loop signal path 56.

[0129] Thus, because the multiplexer 54-0 is off the critical timing path along the loop 56, performance is thus improved and thus more aggressive scaling of the clock frequency is enabled.

[0130] Figure 7An example is shown in which the output of the multiplexer 54-0 passes through or circuitry 54-1 that combines the forwarded operand from the forwarding path 56 with the scalar output of the multiplexer 54-0. However, another approach is to inject the scalar value of the initial iteration via a special path loaded during the setup clock cycle through light logic, to produce a scalar value with respect to the output of the forwarding circuitry 56; this would also remove the or gate 54-1 completely from the single-cycle forwarding return path 56, in addition to removing the multiplexer 54-0.

[0131] Figure 7 An example is shown in which the initial information computed about the operands for the next cycle is an indication of whether the exponent of either operand opa, opb is zero. This allows the early construction of the number of significant bits. Also, in Figure 7 In this case, the exponent value can be returned early, and for a given iteration, the processing of the exponents by the floating point adders 50, 52 can be skewed with respect to the processing of the significant bits, so that the exponent processing begins before the significant bit processing.

[0132] However, it is possible to determine other initial information on the operands opa, opb for the next iteration in parallel with completing the remaining portion of the processing for producing the floating point addition result in the previous iteration. For example, it is possible to pre-compute the low order bit or set of low order bits of the exponent difference between the exponents of the operands opa, opb, or even to compute the full exponent difference expa - expb and / or expb - expa, ahead of time. In some implementations, it can not be known in advance which of the operands has the larger exponent, so both of the exponent differences expa - expb and expb - expa can be computed in parallel to allow early processing. These exponent differences can be needed to determine the number of bit positions by which the significant bits of the smaller operand should be shifted in order to align with the other significant bits, and the exponent differences can also be used to produce other information such as the rounding status.

[0133] At the same time, the sign of the operands can be pre-computed early, and this can control whether the processing path for handling LSA or USA can be used, for example, this can control the selection between near processing logic and far processing logic as discussed above. In addition, the pre-compute logic 60 can compute information about whether a given floating point operand is infinite or NaN, which can control whether special handling logic for handling such special floating point values is used.

[0134] Another example can pre-compute whether the operand opb is equal to 0 (this can be determined if both the biased exponent and the fraction are simultaneously 0), which can help to speed up the processing because if the operand is known to be 0, the more complex processing signal path involving addition can be omitted. If for a given iteration opb = 0, the flip-flop enable signal for the register 108 can be disabled to prevent the result of the previous iteration from being updated because the previous result + 0 is still the previous result.

[0135] Thus, various information about the operands opa and / or opb can be computed, and by pulling this logic out of the critical path of a single iteration, the processing of the iterations is thus sped up and the use of higher clock frequencies is enabled.

[0136] Figure 8 A flowchart of a method of performing an iterative operation is shown. At step 202, in a setup period, the initial information generation circuitry 60 determines initial information on the operands to be processed in iteration n of the iterative operation, where for the initial setup period, n = 0.

[0137] In a subsequent clock cycle, at step 204, the result generation circuitry 50, 52 generates a result value for iteration n, and in parallel with completing the remainder of the iteration to generate that result, at step 206, the initial information generation circuitry 60 performs the initial part of the processing of the next iteration to determine initial information about the operands to be performed on in the next iteration n + 1.

[0138] At step 208, it can be determined whether iteration n is the last iteration of the iterative operation; if so, at step 210, the final result of iteration n generated at step 204 is output as the result of the instruction. However, if there is still another iteration to be processed, at step 212, the forwarding circuitry 56 forwards the result of iteration n as an input to the next iteration n + 1, and n is incremented. Thus, in the next clock cycle, steps 204, 206 are performed again to perform the initial / remainder of the subsequent iteration n + 2, n + 1.

[0139] Thus, with this technique, the latency associated with computing the initial information can be hidden in the latency shadow of determining the result, to improve performance.

[0140] In this application, the word "configured" is used to mean that an element of a device has a configuration able to perform a defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, a device can have specific hardware which provides the defined operation, or a processor or other processing device which is programmed to perform the function. "Configured" does not imply that an element of the device needs to change in any way in order to provide the defined operation.

[0141] While the illustrative embodiments of the application have been described with reference to the attached figures, it is to be understood that the application is not limited to those precise embodiments and that various changes and modifications can be made by those skilled in the art without departing from the scope and spirit of the application as defined in the following claims.

Claims

1. Apparatus for data processing, comprising: an instruction decoder to decode program instructions; and processing circuitry to perform, in response to decoding by the instruction decoder of an iteration operation instruction, an iteration operation comprising a plurality of processing iterations, for which a subsequent iteration other than a first iteration depends on an operand produced in a preceding iteration; the processing circuitry comprising: initial information producing circuitry to perform an initial portion of processing of a given iteration to produce initial information; result producing circuitry to perform a remaining portion of processing of the given iteration to produce a result value using the initial information determined by initial information producing circuitry; and forwarding circuitry to forward, when the given iteration is other than a final iteration, the result value produced in the given iteration as an operand for a next iteration of the iteration operation; wherein: when the result producing circuitry performs the remaining portion of the given iteration other than the final iteration, the initial information producing circuitry is configured to begin performing the initial portion of the next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration, and wherein a latency between the initial information producing circuitry beginning the initial portion of the given iteration and the initial information producing circuitry beginning the initial portion of the next iteration is less than a latency between the initial information producing circuitry beginning the initial portion of the given iteration and the result producing circuitry completing the remaining portion of the given iteration. the initial information producing circuitry is configured to perform the initial portion of the given iteration in a clock cycle that is earlier than a clock cycle in which the result producing circuitry begins performing the remaining portion of the given iteration.

2. The apparatus of claim 1, wherein, the result producing circuitry is configured to perform the remaining portion of the given iteration in a single clock cycle.

3. The apparatus of claim 1, wherein, a subsequent iteration other than the first iteration depends on:

4. The apparatus of claim 1, wherein, a forwarded operand forwarded by the forwarding circuitry based on a result value from a preceding iteration; and a second operand that is independent of a result of the preceding iteration. the initial information comprises information derived from the second operand.

5. The apparatus of claim 4, wherein, a subsequent iteration other than the first iteration depends on a forwarded operand forwarded by the forwarding circuitry based on a result value from a preceding iteration, and the initial information comprises information derived from early information about the forwarded operand that is available before the forwarded operand is fully determined by the result producing circuitry for the preceding iteration.

6. The apparatus of claim 1, wherein, the forwarded operand is a floating point operand having a sign, an exponent, and a number of significant bits; and 7. The apparatus of claim 6, wherein, the early information comprises information derived from at least one of the sign and the exponent of the forwarded operand. the iteration operation instruction identifies a scalar floating point operand and a vector data value comprising a plurality of data elements each specifying a floating point operand; 8. The apparatus of claim 1, wherein, each valid iteration of the iteration operation comprises adding a first floating point operand to a second floating point operand; the iteration operation instruction identifies a scalar floating point operand and a vector data value comprising a plurality of data elements each specifying a floating point operand; each valid iteration of the iteration operation comprises adding a first floating point operand to a second floating point operand; for a first valid iteration of the iterative operation, the first floating point operand is the scalar floating point operand and the second floating point operand is a floating point operand specified in a first valid data element of the vector data value; and for a subsequent valid iteration of the iterative operation, the first floating point operand is a forwarded result of the addition in a previous valid iteration and the second floating point operand is a floating point operand specified in a subsequent valid data element of the vector data value.

9. The apparatus of claim 8, wherein, the processing circuitry is configured to determine which iterations are valid iterations based on predicate information specifying which data elements of the vector data value are valid data elements.

10. The apparatus of claim 8, wherein, the forwarding circuitry comprises a forwarding loop signal path to provide the forwarded result of the addition in the previous valid iteration as the first floating point operand for the subsequent valid iteration; the apparatus comprises a multiplexer to select when to inject the scalar floating point operand as the first floating point operand; the multiplexer is external to the forwarding loop signal path.

11. The apparatus of claim 10, wherein, the forwarding loop signal path comprises or circuitry to provide a first floating point operand to be processed in a given iteration; the or circuitry is configured to combine a first input with a second input according to a bitwise OR operation; in iterations other than the first valid iteration, the first input comprises a forwarded result of an addition performed by the result producing circuitry in the previous valid iteration; and the second input comprises an output of the multiplexer.

12. The apparatus of claim 11, wherein, in a final iteration of the iterative operation for the first iteration operation instruction, the processing circuitry is configured to provide a full zero value on the forwarding loop signal path, the full zero value to be used as a first input to an OR gate for a first valid iteration of a subsequent iteration operation instruction.

13. The apparatus of claim 11, wherein, the multiplexer is configured to select the scalar floating point operand in the first valid iteration or a forwarded result in an earlier iteration operation instruction and to select a full zero value in one or more subsequent valid iterations.

14. An apparatus for data processing, comprising: an instruction decoder to decode program instructions; and processing circuitry to, in response to a decoding of an iteration operation instruction by the instruction decoder, perform an iterative operation comprising a plurality of processing iterations, for the plurality of processing iterations, a subsequent iteration other than a first iteration dependent on an operand produced in a previous iteration; the processing circuitry comprises: initial information producing circuitry to perform an initial portion of processing of a given iteration to produce initial information; result producing circuitry to perform a remaining portion of processing of the given iteration to produce a result value using the initial information determined by initial information producing circuitry; and forwarding circuitry to, when the given iteration is an iteration other than a final iteration, forward the result value produced in the given iteration as an operand for a next iteration of the iterative operation; wherein: while the result producing circuitry is executing the remainder of the given iteration other than the final iteration, the initial information producing circuitry is configured to begin executing the initial portion of the next iteration in parallel with the result producing circuitry completing the remainder of the current iteration, and wherein the processing circuitry is capable of operating in accordance with a clock signal having a clock period that is shorter than a combined latency of the initial portion and the remainder.

15. An apparatus for data processing, comprising: an instruction decoder to decode program instructions; and processing circuitry to perform, in response to a decoding of an iteration operation instruction by the instruction decoder, an iteration operation comprising a plurality of processing iterations for which a subsequent iteration other than a first iteration depends on an operand produced in a preceding iteration; the processing circuitry comprising: initial information producing circuitry to perform an initial portion of processing of a given iteration to produce initial information; result producing circuitry to perform a remainder of processing of the given iteration to produce a result value using the initial information determined by initial information producing circuitry; and forwarding circuitry to forward, when the given iteration is an iteration other than a final iteration, the result value produced in the given iteration as an operand of a next iteration of the iteration operation; wherein: while the result producing circuitry is executing the remainder of the given iteration other than the final iteration, the initial information producing circuitry is configured to begin executing the initial portion of the next iteration in parallel with the result producing circuitry completing the remainder of the current iteration, and wherein the result value of the given iteration comprises a rounded floating point value obtained by adding floating point operands.

16. The apparatus of claim 15, wherein, the initial information comprises at least one of: an indication of whether one of the floating point operands is subnormal; an indication of whether one of the floating point operands is infinite; an indication of whether one of the floating point operands is a non-numeric value; at least a portion of an exponent difference value indicating a difference between exponents of the floating point operands; an indication of whether a fractional part of a number of significant bits of one of the floating point operands is zero; an indication of whether the floating point operands are signed or unsigned operands.

17. An apparatus for data processing, comprising: means for decoding program instructions; and means for processing to perform, in response to a decoding of an iteration operation instruction by the instruction decoder, an iteration operation comprising a plurality of processing iterations for which an iteration other than a first iteration depends on an operand produced in a preceding iteration; the means for processing comprising: initial information producing circuitry to produce initial information by performing an initial portion of processing of a given iteration; result producing circuitry to produce a result value by performing a remainder of processing of the given iteration, the means using the initial information determined by the initial information producing circuitry; and forwarding circuitry to forward, when the given iteration is an iteration other than the final iteration, a result value produced in the given iteration as an operand for a next iteration of the iterative operation; wherein: the initial information generation circuitry is configured to start performing an initial portion of the next iteration in parallel with the result generation circuitry completing the remaining portion of the current iteration, and wherein a latency between the initial information generation circuitry starting the initial portion of the given iteration and the initial information generation circuitry starting the initial portion of the next iteration is less than a latency between the initial information generation circuitry starting the initial portion of the given iteration and the result generation circuitry completing the remaining portion of the given iteration.

18. A data processing method comprising: decoding, using an instruction decoder, an iterative operation instruction; and in response to the decoding of the iterative operation instruction, performing an iterative operation comprising a plurality of processing iterations, for which iterations other than a first iteration depend on operands produced in preceding iterations; wherein the iterative operation is performed using processing circuitry comprising: initial information generation circuitry to perform an initial portion of processing of a given iteration to produce initial information; result generation circuitry to perform a remaining portion of processing of the given iteration to produce a result value using the initial information determined by initial information generation circuitry; and forwarding circuitry to forward, when the given iteration is an iteration other than the final iteration, a result value produced in the given iteration as an operand for a next iteration of the iterative operation; wherein: the initial information generation circuitry starts performing an initial portion of the next iteration in parallel with the result generation circuitry completing the remaining portion of the current iteration, and wherein a latency between the initial information generation circuitry starting the initial portion of the given iteration and the initial information generation circuitry starting the initial portion of the next iteration is less than a latency between the initial information generation circuitry starting the initial portion of the given iteration and the result generation circuitry completing the remaining portion of the given iteration.

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