Display device

Abstract

The disclosure relates to a display device including: a data driving circuit disposed in a non-display area and including output terminals for outputting data voltages to data lines; a first fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a first area of a display area and a second end connected to a first contact portion disposed in an area adjacent to one end of the data driving circuit; a second fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a second area of the display area and a second end connected to the data lines in the second area; and a bypass fan-out line disposed in the non-display area and the display area and including a first end connected to the first contact portion and a second end connected to the data lines in the first area.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments relate generally to a display apparatus. More particularly, embodiments of the present disclosure relate to a display apparatus configured to reduce manufacturing costs thereof. BACKGROUND

[0002] Recently, as technology has developed, display apparatuses having a smaller and lighter structure and high performance have been produced. Although a conventional cathode ray tube ("CRT") television has been widely used for existing display apparatuses because the CRT has many advantages in terms of performance and price, flat display apparatuses such as plasma display apparatuses, liquid crystal display apparatuses, and organic light emitting display apparatuses have received attention in recent years because such flat display apparatuses have desirable characteristics such as miniaturization, light weight, low power consumption, and portability.

[0003] Such a display apparatus typically includes a display area in which an image is displayed and a peripheral area that is a non-display area surrounding the display area. As demand for display apparatuses having a reduced periphery such as a bezel-less display and a margin-less display increases, display apparatuses having various shapes such as a display apparatus having a rounded corner in the display area have been developed. SUMMARY

[0004] Some exemplary embodiments provide a display apparatus having an improved fan-out line arrangement that enables a reduction in development costs of a data driving circuit.

[0005] According to an exemplary embodiment, a display apparatus includes a display area in which a plurality of data lines are disposed and a non-display area surrounding the display area, the display apparatus including: a data driving circuit disposed in the non-display area and including a plurality of output terminals that output data voltages to the data lines; a first fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a first area of the display area and a second end connected to a first contact portion disposed in an area adjacent to one end of the data driving circuit; a second fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a second area of the display area and a second end connected to the data lines in the second area; and a bypass fan-out line disposed in the non-display area and the display area and including a first end connected to the first contact portion and a second end connected to the data lines in the first area.

[0006] In an exemplary embodiment, the non-display area can include a first non-display area extending from the second area of the display area in a first direction and a second non-display area surrounding an outer edge of the display area. In addition, the first fan-out line, the second fan-out line, and the bypass fan-out line can be disposed in the first non-display area.

[0007] In an exemplary embodiment, the first fan-out line can extend in a direction perpendicular to a longitudinal direction of the data driving circuit and be bent in the longitudinal direction.

[0008] In an exemplary embodiment, the second end of the second fan-out line can be connected to one end of the data line in the second area through a second contact portion. Also, the second contact portion can be disposed in an area of the non-display area corresponding to an outer edge of the second area.

[0009] In an exemplary embodiment, the second end of the bypass fan-out line can be connected to one end of the data line in the first area through a third contact portion. In such an embodiment, the third contact portion can be disposed in a portion of the non-display area corresponding to an outer edge of the first area.

[0010] In an exemplary embodiment, the first non-display area can include a fan-out area between the data driving circuit and the second area of the display area. In such an embodiment, the second fan-out line and the bypass fan-out line can be alternately disposed in the fan-out area adjacent to the second area of the display area.

[0011] In an exemplary embodiment, the power voltage line overlapping the second fan-out line and the bypass fan-out line can be disposed in the fan-out area adjacent to the second area of the display area.

[0012] In an exemplary embodiment, a portion of the first fan-out line can be disposed on the first insulating layer, and the remaining portion of the first fan-out line can be disposed on a second insulating layer disposed on the first insulating layer.

[0013] In an exemplary embodiment, a portion of the second fan-out line can be disposed on the first insulating layer, and the remaining portion of the second fan-out line can be disposed on a second insulating layer disposed on the first insulating layer.

[0014] In an exemplary embodiment, the data line and the power voltage line can be disposed on a third insulating layer disposed on the second insulating layer.

[0015] In an exemplary embodiment, the bypass fan-out line can be disposed on a fourth insulating layer disposed on the third insulating layer.

[0016] In an exemplary embodiment, the fan-out area can include a first fan-out area adjacent to the data driving circuit, a second fan-out area adjacent to the display area, and a bending area defined between the first fan-out area and the second fan-out area.

[0017] In an exemplary embodiment, the first contact portion can be disposed between the data driving circuit and the bending area.

[0018] In an exemplary embodiment, the first contact portion can be disposed between the bending area and the display area.

[0019] In an exemplary embodiment, the bypass fan-out line in the display area can include a straight portion disposed between the data lines and a crossing portion crossing the data lines.

[0020] In an exemplary embodiment, the display area can have a rectangular shape with rounded corners, the first area can correspond to an area having rounded corners, and the second area can correspond to a central area of the display area.

[0021] In an exemplary embodiment, the display device can further include a transistor disposed in the display area, and an organic light emitting diode disposed on the transistor and including a first electrode connected to the transistor, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer.

[0022] According to an exemplary embodiment, a display device includes a display area in which a plurality of data lines are disposed, and a non-display area surrounding the display area, the display device including: a data driving circuit disposed in the non-display area and including a plurality of first output terminals to output data voltages to the data lines; a first fan-out line disposed in the non-display area and including a first end connected to output terminals corresponding to data lines in a first area of the display area, and a second end connected to a first contact portion disposed in an area adjacent to one end of the data driving circuit; a second fan-out line disposed in the non-display area and including a first end connected to output terminals corresponding to data lines in a second area of the display area, and a second end connected to the data lines in the second area; a bypass fan-out line disposed in the non-display area and the display area and including a first end connected to the first contact portion, and a second end connected to the data lines in the first area; and a shield electrode disposed between the second fan-out line and the bypass fan-out line and overlapping the second fan-out line and the bypass fan-out line.

[0023] In an exemplary embodiment, the second end of the second fan-out line can be connected to one end of the data lines in the second area through a second contact portion. In such an embodiment, the second contact portion can be disposed in a portion of the non-display area corresponding to an outer edge of the second area.

[0024] In an exemplary embodiment, the second end of the bypass fan-out line can be connected to one end of the data lines in the first area through a third contact portion. In such an embodiment, the third contact portion can be disposed in a portion of the non-display area corresponding to an outer edge of the first area.

[0025] In an embodiment of the disclosure, as described herein, a display apparatus has a structure that enables a reduction in development costs of a new data driving circuit by designing an arrangement order of output terminals arranged in a data driving circuit to be the same as an arrangement order of data lines arranged in a display area. In such an embodiment, the display apparatus includes signal lines arranged to partially overlap to reduce a size of a fan-out area by providing fan-out lines in at least two layers different from each other in the fan-out area and by forming bypass fan-out lines using a source metal layer different from a layer corresponding to the fan-out lines. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above described and other features of the disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, by which:

[0027] Figure 1 is a plan view of a display apparatus according to an exemplary embodiment;

[0028] Figure 2 is an enlarged partial plan view of a display apparatus according to an exemplary embodiment;

[0029] Figure 3 is a plan view illustrating signal lines arranged in a fan-out area of a display apparatus according to an exemplary embodiment;

[0030] Figure 4 is a cross-sectional view illustrating a display apparatus according to an exemplary embodiment;

[0031] Figure 5 is an enlarged partial plan view of a display apparatus according to an exemplary embodiment;

[0032] Figure 6 is a block diagram illustrating an electronic apparatus according to an exemplary embodiment;

[0033] Figure 7A is a diagram illustrating an exemplary embodiment in which the electronic apparatus of Figure 6 is implemented as a television; and

[0034] Figure 7B is a diagram illustrating an exemplary embodiment in which the electronic apparatus of Figure 6 is implemented as a smart phone. DETAILED DESCRIPTION

[0035] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout the specification.

[0036] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0037] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. "Or" means "and / or". At least one of A and B means A or / and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0039] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's relationship to another element as the device is oriented in the drawing. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in one of the drawings is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides thereof, and vice versa. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation being referred to. Similarly, if the device in one of the drawings is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of "below" and "above," depending on the particular orientation being referred to.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated as a flat surface can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 is a plan view of a display device according to an exemplary embodiment.

[0044] Reference Figure 1 An exemplary embodiment of a display device 1000 includes a display area DA that displays an image and a peripheral area PA that is adjacent to the display area DA and surrounds the display area DA.

[0045] The display area DA can have a rectangular planar shape having sides in a first direction D1 and a second direction D2 perpendicular to the first direction D1 and having rounded corners.

[0046] The display area DA includes a first side area LA and a second side area RA which are laterally symmetrical with respect to a center line CT extending in the first direction D1. Each of the first side area LA and the second side area RA includes a first area A1 and a second area A2. The first area A1 is an area corresponding to a rounded corner of the display area DA, and the second area A2 is an area corresponding to a central area of the display area DA.

[0047] The display area DA can include a plurality of pixels arranged (or disposed) in a matrix form to display an image, and can include thin film transistors, a plurality of data lines DL1 to DLM electrically connected to the pixels, and a plurality of gate lines crossing the data lines DL1 to DLM.

[0048] The data lines DL1 to DLM extend in the first direction D1 and are arranged in the second direction D2. The gate lines can extend in the second direction D2 and be arranged in the first direction D1.

[0049] In an exemplary embodiment, the 1st data line DL1 to the mth data line DLm can be arranged in the first side area LA, and the (m+1)th data line DLm+1 to the Mth data line DLM can be arranged in the second side area RA.

[0050] In such an embodiment, the 1st data line DL1 to the kth data line DLk among the 1st data line DL1 to the mth data line DLm can be arranged in the first area A1 of the first side area LA, and the (k+1)th data line DLk+1 to the mth data line DLm can be arranged in the second area A2 of the first side area LA.

[0051] In such an embodiment, the (m+1)th data line DLm+1 to the qth data line DLq among the (m+1)th data line DLm+1 to the Mth data line DLM can be arranged in the second area A2 of the second side area RA, and the (q+1)th data line DLq+1 to the Mth data line DLM can be arranged in the first area A1 of the second side area RA. Here, k, m, q, and M are natural numbers satisfying the following inequalities: k < m < q < M.

[0052] The display area DA includes a bypass line area CLA in which a plurality of bypass fan-out lines CL1 to CLk and CLq+1 to CLM are arranged. Each of the bypass fan-out lines CL1 to CLk and CLq+1 to CLM can include a straight portion disposed between the data lines and a crossing portion crossing the data lines.

[0053] The bypass fan-out lines CL1 to CLk connect the 1st data lines DL1 to the kth data lines DLk arranged in the first area A1 of the first side area LA to a plurality of corresponding fan-out lines.

[0054] In such an embodiment, the bypass fan-out lines CLq+1 to CLM connect the (q+1)th data lines DLq+1 to the Mth data lines DLM arranged in the first area A1 of the second side area RA to a plurality of corresponding fan-out lines.

[0055] The peripheral area PA can include a first non-display area NDA1 and a second non-display area NDA2.

[0056] The first non-display area NDA1 extends in the first direction D1 with respect to a central area of the display area DA. In one exemplary embodiment, for example, the first non-display area NDA1 can include an area extending from the second area A2 in the display area DA. The first non-display area NDA1 includes a pad area PDA and a fan-out area FOA.

[0057] The pad area PDA is an area on which the data driving circuit DIC is arranged or mounted and on which a plurality of pads connecting or contacting terminals of the data driving circuit DIC can be arranged.

[0058] In the fan-out area FOA, a plurality of fan-out lines connecting output terminals of the data driving circuit DIC to the data lines DL1 to DLM of the display area DA can be arranged.

[0059] In an exemplary embodiment, the fan-out area FOA includes a first fan-out area FOA1 adjacent to the data driving circuit DIC and a second fan-out area FOA2 adjacent to the display area DA, and a bending area BA can be defined between the first fan-out area FOA1 and the second fan-out area FOA2. The bending area BA is an area that will be bent to allow the pad area PDA to be disposed on the rear side of the display device 1000 during a module assembly process.

[0060] The fan-out lines disposed in the fan-out area FOA can be connected to the data lines DL1 to DLM of the display area DA.

[0061] The 1st data lines DL1 to the kth data lines DLk arranged in the first area A1 of the first side area LA can be connected to corresponding fan-out lines through the bypass fan-out lines CL1 to CLk, and the (k+1)th data lines DLk+1 to the mth data lines DLm arranged in the second area A2 of the first side area LA can be directly connected to corresponding fan-out lines.

[0062] The (q+1)th data line DLq+1 to the Mth data line DLM arranged in the first area A1 of the second side area RA can be connected to the corresponding fan-out line through a bypass fan-out line CLq+1 to CLM, and the (m+1)th data line DLm+1 to the qth data line DLq arranged in the second area A2 of the second side area RA can be directly connected to the corresponding fan-out line.

[0063] The second non-display area NDA2 surrounds the outer edge of the display area DA.

[0064] A plurality of contact portions for connecting the data lines to the bypass fan-out lines can be provided in the second non-display area NDA2, and a plurality of contact portions for directly connecting the data lines to the fan-out lines can be provided in the second non-display area NDA2. In an exemplary embodiment, a gate driving circuit configured to generate a plurality of gate signals to drive the gate lines can be integrated in the second non-display area NDA2.

[0065] Figure 2 is an enlarged partial plan view of a display device according to an exemplary embodiment.

[0066] In one exemplary embodiment, for example, the display device includes 1st to 2880th data lines, and the data driving circuit DIC can include 1st to 2880th output terminals configured to output data voltages corresponding to the 1st to 2880th data lines, respectively.

[0067] Referring to Figure 1 and Figure 2 , the first side area LA and the second side area RA of the display area DA are laterally symmetrical with respect to a center line CT of the display area DA. Hereinafter, an arrangement relationship and a connection relationship between the 1st to 1440th data lines DL1 to DL1440 arranged in the first side area LA among the 1st to 2880th data lines of the display area DA and a plurality of signal lines arranged in the first non-display area NDA1 and the second non-display area NDA2 will be described.

[0068] Here, the 1st to 720th data lines DL1 to DL720 are sequentially arranged in the first area A1 of the display area DA along the second direction D2, and the 721st to 1440th data lines DL721 to DL1440 are sequentially arranged in the second area A2 of the display area DA along the second direction D2.

[0069] The data driving circuit DIC is disposed or mounted on the pad area PDA of the first non-display area NDA1. The data driving circuit DIC includes 1st to 1440th output terminals T1 to T1440 configured to respectively output data voltages corresponding to 1st to 1440th data lines DL1 to DL1440 of the display area DA. The 1st to 1440th output terminals T1 to T1440 are sequentially arranged along the second direction D2.

[0070] The first non-display area NDA1 can include a first fan-out area FOA1, a second fan-out area FOA2, and a bending area BA between the pad area PDA and the display area DA.

[0071] In the first fan-out area FOA1, 1st to 720th fan-out lines F1 to F720 corresponding to 1st to 720th data lines DL1 to DL720 arranged in the first area A1, 721st to 1440th fan-out lines F721 to F1440 corresponding to 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2, and 1st to 720th bypass fan-out lines CL1 to CL720 are arranged.

[0072] The 1st to 720th fan-out lines F1 to F720 are respectively connected to the 1st to 720th output terminals T1 to T720 of the data driving circuit DIC.

[0073] The 721st to 1440th fan-out lines F721 to F1440 are respectively connected to the 721st to 1440th output terminals T721 to T1440 of the data driving circuit DIC.

[0074] The 1st to 720th fan-out lines F1 to F720 extend and are sequentially arranged in an area adjacent to one end of the data driving circuit DIC or an area adjacent to the 1st output terminal T1. Figure 2 As shown in FIG. 1B, the 1st to 720th fan-out lines F1 to F720 extend in a first direction D1 perpendicular to a longitudinal direction (i.e., the second direction) D2 of the data driving circuit DIC and are bent in the longitudinal direction D2.

[0075] First ends of the 1st to 720th fan-out lines F1 to F720 are respectively connected to the 1st to 720th output terminals T1 to T720 of the data driving circuit DIC, and second ends are respectively connected to a plurality of first contact portions CP1 disposed in an area adjacent to one end of the data driving circuit DIC.

[0076] The 721st fan-out line F721 to the 1440th fan-out line F1440 corresponding to the 721st data line DL721 to the 1440th data line DL1440 extend in a direction toward the display area DA.

[0077] First ends of the 721st fan-out line F721 to the 1440th fan-out line F1440 are connected to 721st output terminal T721 to 1440th output terminal T1440 of the data driving circuit DIC, respectively, and second ends are connected to a plurality of second contact portions CP2 formed in the second non-display area NDA2 adjacent to the second area A2 of the display area DA.

[0078] The 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 connect the 1st fan-out line F1 to the 720th fan-out line F720 to the 1st data line DL1 to the 720th data line DL720, respectively.

[0079] First ends of the 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 are connected to the first contact portions CP1, respectively, and second ends of the 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 are connected to end portions of the 1st data line DL1 to the 720th data line DL720 through a plurality of third contact portions CP3, respectively. The third contact portions CP3 are disposed in the second non-display area NDA2 adjacent to the first area A1 of the display area DA.

[0080] The 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 extend from the first contact portions CP1 disposed in the first fan-out area FOA1, cross the bending area BA and the second fan-out area FOA2, bypass the first area A1 and the second area A2 of the display area DA, and are connected to the end portions of the 1st data line DL1 to the 720th data line DL720, respectively.

[0081] In the bending area BA and the second fan-out area FOA2, the 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 can be arranged alternately with the 721st fan-out line F721 to the 1440th fan-out line F1440, respectively.

[0082] In one exemplary embodiment, for example, the second bypass fan-out line CL2 can be arranged between the 1440th fan-out line F1440 and the 1439th fan-out line F1439. In addition, the 720th bypass fan-out line CL720 can be arranged between the 721st fan-out line F721 and the 722nd fan-out line F722.

[0083] Shielding electrodes extending in the second direction D2 can be provided in the second fan-out area FOA2. In embodiments, the shielding electrodes can be power voltage lines VL (shown) configured to transmit a power voltage EVVDD to drive organic light emitting diodes arranged in the display area DA. Figure 3 The power voltage lines VL can be formed or defined by a metal layer different from (e.g., provided in a different layer from) the metal layer defining the first 721 fan-out lines F721 to the 1440th fan-out line F1440 or the first 1 bypass fan-out line CL1 to the 720th bypass fan-out line CL720.

[0084] In exemplary embodiments, the first 1 fan-out line F1 to the 1440th fan-out line F1440 can be formed or defined by a first gate metal layer and a second gate metal layer in different layers from each other. In one exemplary embodiment, for example, odd fan-out lines can be formed or defined by the first gate metal layer, and even fan-out lines can be formed or defined by the second gate metal layer.

[0085] The first 1 data line DL1 to the 1440th data line DL1440 can be formed or defined by a first source metal layer different from the first gate metal layer and the second gate metal layer.

[0086] The power voltage lines VL can be formed or defined by the first source metal layer.

[0087] The first 1 bypass fan-out line CL1 to the 720th bypass fan-out line CL720 arranged to cross the first 1 fan-out line F1 to the 1440th fan-out line F1440 can be formed or defined by a second source metal layer different from the first source metal layer.

[0088] The power voltage lines VL can be provided between or overlap with the fan-out lines formed by the first gate metal layer and the second gate metal layer and the bypass fan-out lines formed by the second source metal layer, such that electrical coupling between the fan-out lines and the bypass fan-out lines can be shielded.

[0089] According to an exemplary embodiment, the fan-out lines and the bypass fan-out lines are arranged to cross each other in the fan-out area adjacent to the data driving circuit such that an arrangement order of the output terminals arranged in the data driving circuit can be designed to be the same as an arrangement order of the data lines arranged in the display area, and thus a development cost for a new data driving circuit can be reduced. In such an embodiment, the fan-out lines and the bypass fan-out lines can be rearranged not to cross each other in the fan-out area adjacent to the display area such that the signal lines overlap each other, and thus an arrangement gap between the fan-out lines and the bypass fan-out lines when viewed from a plan view of a thickness direction of the display device can be reduced. In such an embodiment, the fan-out lines are provided in at least two layers different from each other, and the bypass fan-out lines are formed or defined by a source metal layer different from the fan-out lines, such that the signal lines partially overlap each other, and thus the arrangement gap between the fan-out lines and the bypass fan-out lines when viewed from a plan view of a thickness direction of the display device can be reduced. Accordingly, a size of the fan-out area adjacent to the display area can be reduced or a size of the non-display area can be reduced, and thus a display quality of the display device can be improved.

[0090] Figure 3 is a plan view illustrating signal lines arranged in a fan-out area of a display device according to an exemplary embodiment, and Figure 4 is a cross-sectional view illustrating a display device according to an exemplary embodiment.

[0091] Referring to Figure 3 and Figure 4 , the display device includes a display area DA, a first non-display area NDA1, and a second non-display area NDA2.

[0092] The display device includes a base substrate 100, and thin film transistors TFT and organic light emitting diodes ("OLEDs") 180 connected to the thin film transistors TFT can be provided in the display area DA of the base substrate 100.

[0093] The base substrate 100 can include or be formed of a transparent or non-transparent material. In one exemplary embodiment, for example, the base substrate 100 can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda lime glass substrate, or a non-alkali glass substrate. Alternatively, the base substrate 100 can include or be formed of a transparent resin substrate having flexibility. In an embodiment, where the base substrate 100 is a transparent resin substrate, the base substrate 100 can be a polyimide substrate. In such an embodiment, the polyimide substrate can include or be composed of a first polyimide layer, a barrier film layer, and a second polyimide layer, etc. In one exemplary embodiment, for example, the polyimide substrate can be configured in such a manner that the first polyimide layer, the barrier film layer, and the second polyimide layer are stacked on a rigid glass substrate.

[0094] The buffer layer 110 is disposed on the base substrate 100. The buffer layer 110 can effectively prevent diffusion of metal atoms or impurities from the base substrate 100 and enable the active pattern ACT to be formed substantially uniformly by adjusting a heat transfer rate during crystallization processing to form the active pattern ACT, which is described later. In an exemplary embodiment, where the surface of the base substrate 100 is not uniform, the buffer layer 110 can be used to improve the flatness of the surface of the base substrate 100. The buffer layer 110 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ).

[0095] The active pattern ACT can be disposed on the buffer layer 110. In an exemplary embodiment, the active pattern ACT can include amorphous silicon or polysilicon. In an alternative exemplary embodiment, the active pattern ACT can include an oxide semiconductor including at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0096] The active pattern ACT can be included in thin film transistors TFT disposed in the display area DA to form a pixel structure. The active pattern ACT can include a drain region and a source region doped with impurities and a channel region between the drain region and the source region.

[0097] A first insulating layer 120 can be provided on the active pattern ACT. The first insulating layer 120 can include an inorganic insulating material. In one exemplary embodiment, for example, the first insulating layer 120 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ).

[0098] A first gate pattern can be provided on the first insulating layer 120. The first gate pattern can be formed of or defined by a first gate metal layer. The first gate pattern can include gate lines provided in the display area DA, gate electrodes GE connected to the gate lines, and first storage electrodes E1 of storage capacitors CST, and can include a plurality of fan-out lines F721, F723,..., and F1440 provided in the non-display area NDA1.

[0099] For example, the first gate pattern can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. In one exemplary embodiment, for example, the first gate pattern can include a metal having high conductivity such as copper or aluminum.

[0100] A second insulating layer 130 can be provided on the first insulating layer 120 on which the first gate pattern is provided. The second insulating layer 130 can include an inorganic insulating material. In one exemplary embodiment, for example, the second insulating layer 130 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ).

[0101] A second gate pattern can be provided on the second insulating layer 130. The second gate pattern can be formed of or defined by a second gate metal layer. The second gate pattern can include second storage electrodes E2 of the storage capacitors CST provided in the display area DA, and can include a plurality of fan-out lines F722, F724,..., and F1439 provided in the non-display area NDA1.

[0102] For example, the second gate pattern can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. In one exemplary embodiment, for example, the second gate pattern can include a metal having a high conductivity such as copper or aluminum.

[0103] A third insulating layer 140 can be disposed on the second insulating layer 130 on which the second gate pattern is disposed. The third insulating layer 140 can include an inorganic insulating material. In one exemplary embodiment, for example, the third insulating layer 140 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ).

[0104] A first source pattern can be disposed on the third insulating layer 140. The first source pattern can be formed or defined by a first source metal layer. The first source pattern can include data lines DL721, DL722,..., and DL1440, a source electrode SE, and a drain electrode DE disposed in the display area DA, and can include a power voltage line VL disposed in the non-display area NDA1.

[0105] The first source pattern can have a multi-layered structure. In one exemplary embodiment, for example, the first source pattern can include a titanium layer, an aluminum layer on the titanium layer, and another titanium layer on the aluminum layer.

[0106] A fourth insulating layer 150 can be disposed on the third insulating layer 140 on which the first source pattern is disposed. In one exemplary embodiment, for example, the fourth insulating layer 150 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ). Alternatively, for example, the fourth insulating layer 150 can be formed using a photoresist, a polyacrylate-based resin, a polyimide-based resin, or an acrylic-based resin.

[0107] A second source pattern can be provided on the fourth insulating layer 150. The second source pattern can be formed or defined by a second source metal layer. The second source pattern can include the bypass fan-out lines CL1 to CL720 provided in the display area DA and the connection electrode CE connected to the drain electrode DE, and can include the bypass fan-out lines CL1 to CL720 provided in the non-display area NDA.

[0108] The second source pattern can have a plurality of layer structures. In one exemplary embodiment, for example, the second source pattern can include a titanium layer, an aluminum layer on the titanium layer, and another titanium layer on the aluminum layer.

[0109] A fifth insulating layer 160 can be provided on the fourth insulating layer 150 on which the second source pattern is provided. In one exemplary embodiment, for example, the fifth insulating layer 160 can be formed using a silicon compound such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), or silicon carbonitride (SiC x N y ). Alternatively, the fifth insulating layer 160 can be formed using, for example, a photoresist, a polypropylene-based resin, a polyimide-based resin, or an acrylic-based resin.

[0110] An OLED 180 can be provided on the fifth insulating layer 160.

[0111] The OLED 180 can include a first electrode 181, a light emitting layer 182, and a second electrode 183.

[0112] The first electrode 181 can be provided on the fifth insulating layer 160. The first electrode 181 can be formed using a reflective material or a light-transmissive material to correspond to a light emitting mode of the display device. In an exemplary embodiment, the first electrode 181 can have a single layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0113] A pixel definition layer PDL can be provided on the fifth insulating layer 160 on which the first electrode 181 is provided. The pixel definition layer PDL can be formed using an organic material or an inorganic material, for example. In one exemplary embodiment, the pixel definition layer PDL can be formed using a photoresist, a polypropylene-based resin, a polyimide-based resin, an acrylic-based resin, or a silicon compound, for example. According to an exemplary embodiment, an opening for partially exposing the first electrode 181 can be defined by the pixel definition layer PDL, for example, by etching the pixel definition layer PDL. The light emitting area and the non-light emitting area of the display device can be defined by the opening of the pixel definition layer PDL. In one exemplary embodiment, for example, the portion in which the opening of the pixel definition layer PDL is located can correspond to the light emitting area, and the portion of the pixel definition layer PDL adjacent to the opening can correspond to the non-light emitting area.

[0114] The light emitting layer 182 can be provided on the first electrode 181 exposed through the opening of the pixel definition layer PDL. In an exemplary embodiment, the light emitting layer 182 can extend over the sidewall of the opening of the pixel definition layer PDL. In an exemplary embodiment, for example, the light emitting layer 182 can have a multi-layer structure including an organic light emitting layer ("EML"), a hole injection layer ("HIL"), a hole transport layer ("HTL"), an electron transport layer ("ETL"), and an electron injection layer ("EIL"). In an alternative exemplary embodiment, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer can be collectively provided in correspondence with a plurality of pixels, in addition to the organic light emitting layer. The organic light emitting layer of the light emitting layer 182 can be formed using a light emitting material capable of generating different color light such as red light, green light, and blue light in correspondence with each pixel of the display device. According to an alternative exemplary embodiment, the organic light emitting layer of the light emitting layer 182 can have a structure in which a plurality of light emitting material layers capable of respectively emitting different color light such as red light, green light, and blue light are stacked on each other to emit white light. In such an embodiment, a light emitting structure can be collectively provided in correspondence with a pixel, and each pixel can be distinguished by a color filter layer.

[0115] The second electrode 183 can be provided on the pixel definition layer PDL and the light emitting layer 182. The second electrode 183 can include a light-transmitting material or a reflective material in correspondence with the light emitting mode of the display device. In an exemplary embodiment, the second electrode 183 can have a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0116] A thin film encapsulation layer TFE can be provided on the second electrode 183. The thin film encapsulation layer TFE can effectively prevent the permeation of external moisture and oxygen. The thin film encapsulation layer TFE can have at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer can be alternately stacked with each other. In one exemplary embodiment, for example, the thin film encapsulation layer TFE can include two inorganic layers and one organic layer therebetween, but is not limited thereto. In an alternative exemplary embodiment, instead of the thin film encapsulation layer TFE, a sealing substrate configured to block the permeation of external air and moisture into the display device can be provided.

[0117] According to an exemplary embodiment, a portion of the fan-out line disposed in the first non-display area NDA1 is formed or defined by the first gate metal layer, and the remaining portion can be formed or defined by the second gate metal layer. In such an embodiment, the bypass fan-out line crossing the fan-out line can be formed or defined by the second source metal layer. In such an embodiment, the electrical coupling between the fan-out line and the bypass fan-out line can be shielded by the power voltage line formed or defined by the first source metal layer. Accordingly, in such an embodiment, the arrangement gap between the fan-out line and the bypass fan-out line can be reduced when viewed in a plan view from the thickness direction of the display device, and thus the non-display area can be reduced.

[0118] Figure 5 is a magnified partial plan view of a display device according to an exemplary embodiment.

[0119] In one exemplary embodiment, for example, the display device includes the 1st to 2880th data lines, and the data driving circuit DIC can include the 1st to 2880th output terminals respectively corresponding to the 1st to 2880th data lines.

[0120] Referring to Figure 1 and Figure 5 , the first side area LA and the second side area RA of the display area DA are laterally symmetrical with respect to the center line CT of the display area DA. Hereinafter, the arrangement relationship and connection relationship between the 1st to 1440th data lines DL1 to DL1440 arranged in the first side area LA among the 1st to 2880th data lines of the display area DA and the plurality of signal lines arranged in the first non-display area NDA1 and the second non-display area NDA2 will be described.

[0121] In an exemplary embodiment, the 1st to 720th data lines DL1 to DL720 are sequentially arranged in the first area A1 of the display area DA along the second direction D2, and the 721st to 1440th data lines DL721 to DL1440 are sequentially arranged in the second area A2 of the display area DA along the second direction D2.

[0122] A data driving circuit DIC is provided or mounted on the pad area PDA of the first non-display area NDA1. The data driving circuit DIC includes 1st to 1440th output terminals T1 to T1440 corresponding to 1st to 1440th data lines DL1 to DL1440 of the display area DA. The 1st to 1440th output terminals T1 to T1440 are sequentially arranged along the second direction D2.

[0123] The first non-display area NDA1 can include a first fan-out area FOA1, a second fan-out area FOA2, and a bending area BA between the pad area PDA and the display area DA.

[0124] The 1st to 1440th fan-out lines F1 to F1440 are arranged in the first fan-out area FOA1. The 1st to 1440th fan-out lines F1 to F1440 are sequentially connected to the 1st to 1440th output terminals T1 to T1440 of the data driving circuit DIC. The 1st to 1440th fan-out lines F1 to F1440 of the first fan-out area FOA1 can extend to the bending area BA in the first direction D1.

[0125] A portion of the 1st to 1440th fan-out lines F1 to F1440 can be formed or defined by the first gate metal layer, and the remaining portion can be formed or defined by the second gate metal layer which is electrically insulated from the first gate metal layer using an insulating layer.

[0126] The 1st to 1440th fan-out lines F1 to F1440 and the 1st to 720th bypass fan-out lines CL1 to CL720 are arranged in the second fan-out area FOA2.

[0127] The 1st to 720th fan-out lines F1 to F720 of the 1st to 1440th fan-out lines F1 to F1440 of the second fan-out area FOA2 corresponding to the 1st to 720th data lines DL1 to DL720 arranged in the first area A1 extend to and are sequentially arranged in an area adjacent to one end of the data driving circuit DIC, or an area adjacent to the 1st output terminal T1. In an exemplary embodiment, as shown in FIG. 1B, the 1st to 720th fan-out lines F1 to F720 extend in the first direction D1 perpendicular to the longitudinal direction D2 of the data driving circuit DIC and are bent in the longitudinal direction D2. Figure 5

[0128] First ends of the 1st to 720th fan-out lines F1 to F720 extend through the first fan-out area FOA1, and second ends are respectively connected to a plurality of first contact portions CP1 formed in the second fan-out area FOA2 adjacent to one end of the data driving circuit DIC.

[0129] ​The 721st fan-out line F721 to the 1440th fan-out line F1440 among the first 1st fan-out line F1 to the 1440th fan-out line F1440 corresponding to the 721st data line DL721 to the 1440th data line DL1440 arranged in the second area A2 extend toward the direction of the display area DA.

[0130] First ends of the 721st fan-out line F721 to the 1440th fan-out line F1440 extend through the first fan-out area FOA1, and second ends are connected to a plurality of second contact portions CP2 provided in the second non-display area NDA2 adjacent to the second area A2 of the display area DA.

[0131] The 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 connect the 1st fan-out line F1 to the 720th fan-out line F720 to the 1st data line DL1 to the 720th data line DL720, respectively.

[0132] First ends of the 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 are connected to the first contact portions CP1, respectively, and second ends of the 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 are connected to end portions of the 1st data line DL1 to the 720th data line DL720 through a plurality of third contact portions CP3, respectively. The third contact portions CP3 are provided in the second non-display area NDA2 adjacent to the first area A1 of the display area DA.

[0133] The 1st bypass fan-out line CL1 to the 720th bypass fan-out line CL720 extend from the first contact portions CP1 provided in the second fan-out area FOA2, bypass the first area A1 and the second area A2 of the display area DA, and are connected to the 1st data line DL1 to the 720th data line DL720, respectively.

[0134] In the second fan-out area FOA2, the 2nd bypass fan-out line CL2 to the 720th bypass fan-out line CL720 are arranged between the 721st fan-out line F721 to the 1440th fan-out line F1440, respectively.

[0135] In one exemplary embodiment, for example, the second bypass fan-out line CL2 is arranged between the 1440th fan-out line F1440 and the 1439th fan-out line F1439. In such an embodiment, the 720th bypass fan-out line CL720 is arranged between the 721st fan-out line F721 and the 722nd fan-out line F722.

[0136] In the second fan-out area FOA2, the power voltage line VL can extend in the second direction D2. For example, the power voltage line VL can transmit a power voltage EVVDD to drive the organic light emitting diode arranged in the display area DA. The power voltage line VL can be formed or defined by a different source metal layer from the first to 1440th fan-out lines F721 to F1440 and the first to 720th bypass fan-out lines CL1 to CL720.

[0137] The first to 1440th data lines DL1 to DL1440 can be formed or defined by a first source metal layer different from the first and second gate metal layers.

[0138] The power voltage line VL can be formed or defined by the first source metal layer. The first to 720th bypass fan-out lines CL1 to CL720 can be formed or defined by a second source metal layer different from the first source metal layer.

[0139] According to exemplary embodiments, the arrangement order of the output terminals arranged in the data driving circuit can be designed to be the same as the arrangement order of the data lines arranged in the display area, and thus development costs for a new data driving circuit can be reduced. In such embodiments, the fan-out lines arranged in the fan-out area are disposed in at least two layers different from each other, and the bypass fan-out lines are formed or defined by a source metal layer different from the fan-out lines, such that the signal lines partially overlap each other, and thus the size of the fan-out area can be reduced. In such embodiments, the voltage line is formed or defined by a metal layer different from the fan-out lines and the bypass fan-out lines and is arranged between the fan-out lines and the bypass fan-out lines, such that electrical coupling can be shielded. Accordingly, the non-display area of the display device can be reduced, and the display quality can be improved.

[0140] Figure 6 is a block diagram illustrating an electronic device according to an exemplary embodiment, Figure 7A is a block diagram illustrating an electronic device according to an exemplary embodiment, Figure 6 is a diagram illustrating an exemplary embodiment in which the electronic device of Figure 7B is a diagram illustrating an exemplary embodiment in which the electronic device of Figure 6 is a diagram illustrating an exemplary embodiment in which the electronic device of

[0141] Referring to Figures 6-7B In such embodiments, the display device 560 can be a display panel including a plurality of pixels arranged in a matrix form. For example, the display device 560 can include a plurality of pixels arranged in a matrix form, and each of the pixels can include an organic light emitting diode and a transistor for driving the organic light emitting diode. The display device 560 can be a display panel including a plurality of pixels arranged in a matrix form, and each of the pixels can include an organic light emitting diode and a transistor for driving the organic light emitting diode. Figure 1the display device 1000. In such embodiments, the electronic device 500 can further include a plurality of ports for communicating with video cards, sound cards, memory cards, universal serial bus ("USB") devices, other electronic devices, etc. In an example embodiment, as shown in FIG. 6A, the electronic device 500 can be implemented as a television. In an alternative example embodiment, as shown in FIG. 6B, the electronic device 500 can be implemented as a smart phone. However, the electronic device 500 is not limited thereto. In one example embodiment, for example, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head-mounted display ("HMD") device, etc. Figure 7A Figure 7B

[0142] The processor 510 can perform various computing functions. The processor 510 can be a microprocessor, a central processing unit ("CPU"), an application processor ("AP"), etc. The processor 510 can be coupled to other components by an address bus, a control bus, a data bus, etc. In such embodiments, the processor 510 can be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus. The memory device 520 can store data for operation of the electronic device 500. In one example embodiment, for example, the memory device 520 can include at least one non-volatile memory device such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase-change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, a ferroelectric random access memory ("FRAM") device, etc., and / or at least one volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile DRAM device, etc. The storage device 530 can include a solid state drive ("SSD") device, a hard disk drive ("HDD") device, a CD-ROM device, etc. The I / O device 540 can include an input device such as a keyboard, a keypad, a mouse device, a touchpad, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 550 can provide power for operation of the electronic device 500.

[0143] The display device 560 can be coupled to other components by a bus or other communication link. In one example embodiment, for example, the display device 560 can be included in the I / O device 540.

[0144] ​​In an exemplary embodiment, as described herein, the display device 560 includes bypass fanout lines in the display area, the fanout lines and the bypass fanout lines in the fanout area adjacent to the data driving circuit cross, and the fanout lines and the bypass fanout lines are rearranged in the fanout area adjacent to the display area so that an arrangement order of output terminals arranged in the data driving circuit can be implemented to be the same as an arrangement order of data lines arranged in the display area.

[0145] Accordingly, in such an embodiment, the size of a non-display area corresponding to the fanout area can be reduced, and display quality can be improved. In such an embodiment, the display device 560 is substantially the same as the exemplary embodiment of the above-described display device 1000, and any repetitive detailed description thereof will be omitted.

[0146] Exemplary embodiments of the present disclosure can be applied to display devices and electronic devices including the same, such as cellular phones, smart phones, video phones, smart pads, smart watches, tablet personal computers ("PCs"), car navigation systems, television sets, computer monitors, laptop computers, HMD devices, and the like.

[0147] The present disclosure should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0148] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device comprising a display area in which a plurality of data lines are arranged and a non-display area surrounding the display area, wherein, The display device includes: a data driving circuit disposed in the non-display area and including a plurality of output terminals for outputting data voltages to the data lines; a first fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a first area of the display area and a second end connected to a first contact portion disposed in an area adjacent to one end of the data driving circuit; a second fan-out line disposed in the non-display area and including a first end connected to the output terminals corresponding to the data lines in a second area of the display area and a second end connected to the data lines in the second area; and a bypass fan-out line disposed in the non-display area and the display area and including a first end connected to the first contact portion and a second end connected to the data lines in the first area, wherein the bypass fan-out line disposed in the display area includes straight portions disposed between the data lines and crossing portions crossing the data lines, wherein the non-display area includes a first non-display area extending from the second area of the display area in a first direction and a second non-display area surrounding an outer edge of the display area, wherein the first non-display area includes a fan-out area between the data driving circuit and the second area of the display area, and wherein the second fan-out line and the bypass fan-out line are alternately disposed in the fan-out area adjacent to the second area of the display area.

2. The display device of claim 1, wherein, the first fan-out line, the second fan-out line, and the bypass fan-out line are disposed in the first non-display area.

3. The display device according to claim 2, wherein the first fan-out line extends in a direction perpendicular to a longitudinal direction of the data driving circuit and is bent in the longitudinal direction.

4. The display device of claim 1, wherein the second end of the second fan-out line is connected to one end of the data lines in the second area through a second contact portion; and wherein the second contact portion is disposed in a portion of the non-display area corresponding to an outer edge of the second area.

5. The display device of claim 1, wherein the second end of the bypass fan-out line is connected to one end of the data lines in the first area through a third contact portion; and wherein the third contact portion is disposed in a portion of the non-display area corresponding to an outer edge of the first area.

6. The display device according to claim 1, wherein a power voltage line overlapping the second fan-out line and the bypass fan-out line is disposed in the fan-out area adjacent to the second area of the display area.

7. The display device of claim 6, wherein a portion of the first fan-out line is disposed on a first insulating layer; and a remaining portion of the first fan-out line is disposed on a second insulating layer disposed on the first insulating layer.

8. The display device of claim 6, wherein a portion of the second fan-out line is disposed on a first insulating layer; and a remaining portion of the second fan-out line is disposed on a second insulating layer disposed on the first insulating layer. A remaining portion of the second fan-out line is provided on a second insulating layer provided on the first insulating layer.

9. The display device of claim 8, wherein, The data line and the power voltage line are provided on a third insulating layer provided on the second insulating layer.

10. The display device of claim 9, wherein, The bypass fan-out line is provided on a fourth insulating layer provided on the third insulating layer.

11. The display device according to claim 1, wherein The fan-out area includes a first fan-out area adjacent to the data driving circuit, a second fan-out area adjacent to the display area, and a bending area defined between the first fan-out area and the second fan-out area.

12. The display device of claim 11, wherein, The first contact portion is provided between the data driving circuit and the bending area.

13. The display device of claim 11, wherein, The first contact portion is provided between the bending area and the display area.

14. The display device according to claim 1, wherein the display area has a rectangular shape with rounded corners; the first area corresponds to an area with rounded corners; and the second area corresponds to a central area of the display area.

15. The display device of claim 1, wherein, The display device further includes: a transistor provided in the display area; and an organic light emitting diode provided on the transistor and including a first electrode connected to the transistor, an emission layer provided on the first electrode, and a second electrode provided on the emission layer.

16. A display device comprising a display area in which a plurality of data lines are arranged and a non-display area surrounding the display area, wherein, The display device includes: a data driving circuit provided in the non-display area and including a plurality of output terminals to output data voltages to the data lines; a first fan-out line provided in the non-display area and including a first end connected to an output terminal corresponding to a data line in a first area of the display area, and a second end connected to a first contact portion provided in an area adjacent to one end of the data driving circuit; a second fan-out line provided in the non-display area and including a first end connected to an output terminal corresponding to a data line in a second area of the display area, and a second end connected to a data line in the second area; a bypass fan-out line provided in the non-display area and the display area and including a first end connected to the first contact portion, and a second end connected to a data line in the first area; and a shield electrode provided between the second fan-out line and the bypass fan-out line and overlapping the second fan-out line and the bypass fan-out line, wherein the non-display area includes a first non-display area extending from the second area of the display area in a first direction and a second non-display area surrounding an outer edge of the display area, wherein the first non-display area includes a fan-out area between the data driving circuit and the second area of the display area, and wherein the second fan-out line and the bypass fan-out line are alternately provided in the fan-out area adjacent to the second area of the display area.

17. The display device according to claim 16, wherein the second end of the second fan-out line is connected to one end of the data line in the second area through a second contact portion; and the second end of the second fan-out line is connected to one end of the data line in the second area through a second contact portion; and The second contact portion is disposed in a portion of the non-display area corresponding to an outer edge of the second area. 18.The display device according to claim 16, wherein The second end of the bypass fan-out line is connected to one end of the data line in the first area through a third contact portion; and The third contact portion is disposed in a portion of the non-display area corresponding to an outer edge of the first area. 19.The display device according to claim 16, wherein The first fan-out line, the second fan-out line, and the bypass fan-out line are disposed in the first non-display area.

Images