High speed and wide dynamic range input structure

Abstract

The present disclosure relates to a high speed wide dynamic range input structure. A method for utilizing the following protection circuit input (V INP ) at input voltage (V IN ) and associated methods: a high voltage PMOSFET (P1) having a gate, a drain connected to the gate across a Zener diode (ZD1), and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a supply voltage, a drain connected to the supply voltage across a Zener diode (ZD2), and a source connected to the gate of the high voltage PMOSFET; a high voltage NMOSFET (N3) having a gate connected to the supply voltage, a source providing a protected output voltage and connected to the gate across a Zener diode (ZD3), and a drain connected to a source follower node; and a level shifter circuit (214) connected between the drain of the high voltage PMOSFET and the source follower node.

Description

Technical Field

[0001] The present invention relates generally to the field of protection circuitry. In one aspect, the present invention relates to an apparatus, system, and method for providing high voltage protection to input circuitry in an integrated circuit device. Background Art

[0002] It is well known that monolithic integrated circuits can be damaged by exposing their input terminals to large abnormal voltages. These large abnormal voltages can destroy dielectric materials within the integrated device, such as gate oxides, or can melt conductive materials, such as polysilicon or aluminum interconnects, thereby causing irreversible damage to the integrated circuit.

[0003] Integrated circuits often include protection for external pins, such as ESD devices and series resistors to clamp external voltages and limit input currents. Other protection schemes for high voltage components (FETs or similar components) block (limit) the maximum voltage applied to internal low voltage circuits. These traditional solutions are used for one-time events (ESD) or continuous operation, but can be nonlinear, unidirectional (positive or negative excursion, but not both), or have limited bandwidth and are not suitable for real-time linear systems, such as direct fuel injection systems for gasoline and diesel internal combustion engines, where it is necessary to accurately sense repetitive voltage signals with a large dynamic range (-10V-+70V) that exceeds the system supply voltage. Summary of the invention

[0004] According to one aspect of the present invention, there is provided an input protection circuit for generating an output voltage in response to an input voltage, comprising: a first cascode switch, the first cascode switch being used to limit the output voltage when the input voltage deviates below a specified voltage operating range, the first cascode switch comprising a high-voltage PMOS field effect transistor (PMOSFET), the high-voltage PMOSFET having a control electrode, a first current-carrying electrode connected to the control electrode across a first Zener diode, and a second current-carrying electrode connected to receive the input voltage; a blocking field effect transistor (FET), the blocking FET having a control electrode connected to a supply voltage, a first current-carrying electrode connected to the supply voltage across a second Zener diode, and a second current-carrying electrode connected to the input voltage; and a second current-carrying electrode to the control electrode of the high-voltage PMOSFET; a second cascode switch, the second cascode switch being used to limit the output voltage when the input voltage excursion is higher than the specified voltage operating range, the second cascode switch comprising a high-voltage NMOS field effect transistor (NMOSFET), the high-voltage NMOSFET having a control electrode connected to the supply voltage, a first current-carrying electrode providing the output voltage and connected to the control electrode across a third Zener diode, and a second current-carrying electrode connected to a source follower node; and a level shifter circuit connected between the first current-carrying electrode of the high-voltage PMOSFET and the source follower node.

[0005] According to one or more embodiments, the level shifter circuit includes a transistor having a control electrode connected to the first current carrying electrode of the high-voltage PMOSFET, a first current carrying electrode including the source follower node connected to the control electrode of the transistor across a fourth Zener diode, and a second current carrying electrode coupled to the supply voltage via a diode.

[0006] According to one or more embodiments, each of the high-voltage PMOSFET, the blocking FET, the high-voltage NMOSFET, and the transistor is respectively connected to a second supply voltage through a current source circuit.

[0007] According to one or more embodiments, the transistor includes an NMOS field effect transistor (NMOSFET).

[0008] In accordance with one or more embodiments, the diode has a cathode connected to the second current carrying electrode of the NMOSFET and an anode connected to the supply voltage through a resistor.

[0009] According to one or more embodiments, the high-voltage PMOSFET is connected to prevent negative input voltage excursions that significantly exceed a gate oxide breakdown voltage of the high-voltage PMOSFET.

[0010] According to one or more embodiments, the negative input voltage offset is a voltage lower than the supply voltage by at least a reverse bias voltage of the first Zener diode.

[0011] According to one or more embodiments, the high-voltage NMOSFET is connected to prevent positive input voltage excursions that significantly exceed a gate oxide breakdown voltage of the high-voltage NMOSFET.

[0012] According to one or more embodiments, the positive input voltage excursion is a voltage exceeding the supply voltage.

[0013] According to a second aspect of the present invention, there is provided a method for protecting a circuit input from input voltage fluctuations at a voltage input, comprising: connecting the voltage input to the circuit input via a signal path in a protection circuit, the protection circuit comprising a first cascode switch, a level shifter and a second cascode switch connected in series between the voltage input and the circuit input; and generating an output voltage at the circuit input by the protection circuit when the input voltage at the voltage input is within a specified linear operating voltage range of the protection circuit, the output voltage being a threshold voltage lower than the input voltage; wherein the first cascode switch is connected between a first current source and a blocking field effect transistor connected to a supply voltage so as to provide negative voltage excursion protection at the circuit input when the input voltage at the voltage input is lower than the specified linear operating voltage range of the protection circuit, wherein the second cascode switch is connected between a second current source and the supply voltage so as to provide positive voltage excursion protection at the circuit input when the input voltage at the voltage input is higher than the specified linear operating voltage range of the protection circuit, and wherein the level shifter is connected between a third current source and a resistor circuit connected to the supply voltage so as to act as a resistor circuit having a threshold voltage drop V TH Source follower operation.

[0014] According to one or more embodiments, the first cascode switch includes a high-voltage PMOS field effect transistor (PMOSFET) having a control electrode, a first current-carrying electrode connected to the control electrode across a first Zener diode, and a second current-carrying electrode connected to the voltage input to receive an input voltage.

[0015] According to one or more embodiments, the blocking field effect transistor (FET) is connected between a fourth current source and the supply voltage and includes a control electrode connected to the supply voltage, a first current carrying electrode connected to the supply voltage across a second Zener diode, and a second current carrying electrode connected to the control electrode of the high-voltage PMOSFET.

[0016] According to one or more embodiments, the second cascode switch includes a high-voltage NMOS field effect transistor (NMOSFET) having a control electrode connected to the supply voltage, a first current-carrying electrode providing the circuit input and connected to the control electrode across a third Zener diode, and a second current-carrying electrode connected to a source follower node.

[0017] According to one or more embodiments, the level shifter circuit includes a transistor having a control electrode connected to the first current carrying electrode of the high-voltage PMOSFET, a first current carrying electrode including the source follower node connected to the control electrode of the transistor across a fourth Zener diode, and a second current carrying electrode connected to the resistor circuit.

[0018] According to one or more embodiments, the first cascode switch is connected to prevent negative input voltage excursions that significantly exceed a gate oxide breakdown voltage of the high-voltage PMOSFET.

[0019] In accordance with one or more embodiments, the second cascode switch is connected to prevent positive input voltage excursions exceeding the supply voltage.

[0020] According to a third aspect of the present invention, there is provided an input protection circuit for generating an output voltage from an input voltage received at a voltage input, comprising: a first cascode switch, the first cascode switch being connected between a first current source and a blocking field effect transistor connected to a supply voltage, wherein when the input voltage is lower than a specified linear operating voltage range of the input protection circuit, the first cascode switch provides negative voltage offset protection at the output voltage, wherein the first cascode switch comprises a high voltage FET of a first polarity type, the high voltage FET of the first polarity type having a control electrode, a first current carrying electrode connected to the control electrode across a first Zener diode, and a second current carrying electrode connected to receive the input voltage; and a second cascode switch, the second cascode switch being connected between a second current source and the supply voltage, wherein when the input voltage is higher than a specified linear operating voltage range of the input protection circuit, the second cascode switch provides positive voltage offset protection at the output voltage, wherein the second cascode switch comprises a second polarity type A high-voltage FET of the second polarity type, the high-voltage FET of the second polarity type having a control electrode connected to the supply voltage, a first current-carrying electrode providing the output voltage and connected to the control electrode across a second Zener diode, and a second current-carrying electrode connected to a source follower node; a blocking field effect transistor (FET) of the second polarity type, the blocking FET of the second polarity type connected between a third current source and the supply voltage to provide a reverse protection gate bias to the high-voltage FET of the first polarity type, wherein the blocking FET includes a control electrode connected to the supply voltage, a first current-carrying electrode connected to the supply voltage across a third Zener diode, and a second current-carrying electrode connected to the control electrode of the high-voltage FET of the first polarity type; and a level shifter circuit, the level shifter circuit being connected between a fourth current source and a resistor circuit connected to the supply voltage, wherein the level shifter circuit operates as a source follower between the first current-carrying electrode of the high-voltage FET of the first polarity type and the source follower node.

[0021] According to one or more embodiments, the high voltage FET of the first polarity type includes a PMOS field effect transistor, and wherein the high voltage FET of the second polarity type includes an NMOS field effect transistor.

[0022] According to one or more embodiments, the high voltage FET of the first polarity type includes an NMOS field effect transistor, and wherein the high voltage FET of the second polarity type includes a PMOS field effect transistor.

[0023] According to one or more embodiments, the supply voltage includes a first reference voltage VDD or a ground reference voltage VSS. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention may be understood and its numerous objects, features and advantages may be obtained when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0025] Figure 1 Depicted is a simplified schematic diagram of an integrated circuit controller for a fuel injector in which one or more input circuits are protected by a high speed dynamic range input protection circuit in accordance with selected embodiments of the present invention.

[0026] Figure 2 Depicted is a schematic circuit diagram of a high speed dynamic range input protection circuit in accordance with selected embodiments of the present invention.

[0027] Figure 3 Operation of a high speed dynamic range input protection circuit during a negative voltage excursion is depicted in accordance with selected embodiments of the present invention.

[0028] Figure 4 Operation of a high speed dynamic range input protection circuit during a positive voltage excursion is depicted in accordance with selected embodiments of the present invention.

[0029] Figure 5 Voltage waveforms according to selected embodiments of the present invention are graphically depicted to show the transfer function of the protected input voltage to the input voltage for linear, positive protection, and negative protection regions of operation. DETAILED DESCRIPTION

[0030] A device, system, architecture, method and circuit for providing a high-speed and low-device input protection circuit for a wide dynamic range of input voltages, thereby providing bidirectional protection for the inputs of low-voltage comparators and amplifiers from input voltage excursions that significantly exceed a threshold voltage or one or more supply voltages. In operation, the input protection circuit includes a current path with protection circuit elements to provide three operating regions (linear, positive protection and negative protection) for protecting the low-voltage circuit from large external voltages and any excessive currents that would degrade the performance of the input circuit and affect the performance of components connected to the input circuit. Specifically, the input protection circuit includes a high-voltage PMOS cascode / switch, which is connected to protect the low-voltage input stage from negative input voltage intrusion in a negative protection operating mode. In addition, the input protection circuit includes a high-voltage NMOS cascode / switch, which is connected to protect the low-voltage input stage from positive input voltage intrusion in a positive protection operating mode. In addition, the input protection circuit includes a Zener diode and a blocking transistor to bias the PMOS cascode / switch with reverse protection, and also includes a level shifter to ensure that the NMOS cascode / switch operates in Rdson (on-resistance) mode when the input voltage is within the linear operating range. When connected between an integrated circuit input pin and one or more comparator inputs, the disclosed input protection circuit provides comprehensive protection for both positive and negative offsets with low current consumption, high speed performance, high input impedance and high accuracy.

[0031] In order to provide additional details to enhance the contextual understanding of the present disclosure, reference is now made to Figure 1 , Figure 1 A simplified schematic diagram 100 of a fuel injector 105 connected to an integrated circuit controller 110 is depicted in which one or more input circuits 115-117 are protected by high-speed dynamic range input protection circuitry 112, 113, 118-120. In the depicted example embodiment, the fuel injector 105 may embody a next generation direct fuel injection (DFI) system connected in a boost-ramp direct injector architecture to receive an input signal V having a wide dynamic range (e.g., from -5V to +72V) and high-speed operation. P 、V NTo this end, the fuel injector 105 is connected to a battery power supply (BAT) and a boost voltage (BOOST) respectively via a first NMOS switch 102 and a second NMOS switch 103, each of which includes a body diode for providing a high-side power supply under the control of a gating signal I1, I2 generated by one or more digital-to-analog (DAC) generators 111. In a similar manner, the fuel injector 105 is connected to ground via a third NMOS switch 106, which includes a body diode for providing a low-side power supply under the control of a gating signal I3 generated by a digital-to-analog (DAC) generator 114.

[0032] In the case where the operation of the fuel injector 105 requires high speed and accurate measurement of the on / off switching rate, high-side and low-side current feedback is provided to the controller 110 at nodes 12, 13 for evaluation by a comparator, amplifier or similar circuit built into the integrated circuit. For example, the first comparator 115 converts the high-side input signal V P The high side comparison signal (C HS_BAT ). In addition, the second comparator 116 converts the high-side input signal V P With the high-side voltage generator VT HIGH The reference boost voltage BOOST is compared to generate the boost voltage high-side comparison signal (C HS_BOOST Finally, the third comparator 117 converts the low-side input signal V N With the low-side voltage generator VT LOW The ground voltage is compared to generate a low-side comparison signal (C LS ). However, it should be understood that such comparator circuits 115-117 require input protection from voltage excursions, particularly with high voltage systems (eg, electric vehicles) where the input voltage V P 、V N Exceeds the voltage from the generator VT HIGH VT LOW Therefore, before being provided to the protected input (eg, the non-inverting input of comparator 115-117), the input voltage V P 、V N The circuits are connected to the input protection circuits 112 and 113 in a feedback manner.

[0033] In the case where the input protection circuits 112, 113 are connected to protect the non-inverting input of the comparator, it is possible that the input voltage V IN With the protected input voltage V INPThe voltage threshold V between the TH In such cases, a replica of the input protection circuit may be connected to the inverting or reference input of the comparator to cancel this offset, as shown by the "IP" blocks 118, 119, 120 shown in dashed lines. Specifically, the input protection (IP) circuits 118, 119 each have the same circuitry as the input protection circuit 112, so that both inputs to the comparators 115, 116 have matched offsets through their respective IP circuits. Similarly, the input protection (IP) circuit 120 is the same circuitry as the input protection circuit 113, so that both inputs to the comparator 117 have matched offsets through their respective IP circuits.

[0034] In order to provide additional details to enhance understanding of selected embodiments of the present disclosure, reference is now made to Figure 2 , Figure 2 Depicts the connection at the input terminal V IN With the protected input V INP Schematic circuit diagram of a high speed dynamic range input protection circuit 200 between . In selected embodiments, the input protection circuit 200 includes a plurality of input terminals each connected to a supply voltage (eg, V DD ) and ground (for example, V SS ) are coupled between corresponding current sources 201-204 between the input protection circuit 200 and the input protection circuit 200. The high-voltage PMOS cascode / switch circuit 211, the high-voltage NMOS cascode / switch circuit 212, the reverse protection gate bias circuit 213 and the level shifter circuit 214. The high-voltage PMOS cascode / switch circuit 211 includes a PMOS FET P1, which operates as a switch within the linear operating range of the input protection circuit 200, and the PMOS FET P1 acts as both a cascode and a blocking device at an input voltage V less than the minimum linear operating limit. IN The Zener diode ZD2 sets the minimum linear operation limit to VDD-Vzd (about 5V). The reverse protection gate bias circuit 213 includes an NMOS FET N1. IN greater than approximately the supply voltage (e.g., V IN >VDD-Vgs), the NMOS FET N1 provides reverse blocking, making the original input voltage V INThe zener diode ZD1 limits the maximum Vgs on the PMOS FET P1 so that the maximum gate-source voltage is never exceeded, thereby protecting the PMOS FET P1 from over-voltage stress (EOS). The high-voltage NMOS cascode / switch circuit 212 includes an NMOS FET N3 that operates in the linear region of the input protection circuit 200 and at an input voltage (e.g., V IN <VDD-Vzd-V TH ) operates as a switch (or resistor). For input voltages greater than VDD, V IN , NMOS FET N3 acts as a common source and gate and an overvoltage appears across the drain-gate of NMOS FET N3, causing the input voltage V IN will not be transmitted (passed) to the protected input V INP Zener diode ZD3 limits the maximum Vgs on NMOS FET N3 to prevent EOS. Diode D1 and resistor R1 prevent V IN Input voltages exceeding VDD are fed back into the VDD supply. Zener diode ZD4 limits the maximum Vgs on NMOS FETN2 to prevent EOS. Current sources 201-204 bias the circuit for proper operation. The current values ​​are optional, depending on the supply current limits and speed. Suitable components of circuits 211-214 include resistors, diodes, and transistors connected to protect the protected input terminal V INP Free from input voltage terminal V IN and the supply voltage V DD The MOSFET can be used to provide both positive and negative voltage excursions on the MOSFET while operating within the safe operating limits of such resistors, diodes, and transistors.

[0035] In conjunction with the present disclosure, protection against negative voltage excursion is provided by a high voltage PMOS cascode / switch circuit 211, which is connected to the input voltage V IN and the first current source 201, and the high voltage PMOS cascode / switch circuit 211 includes a first breakdown Zener diode ZD1, the anode of which is connected to the source of the PMOS FET P1 (and the first current source 201) at node 1 and the cathode is connected to a node connected to the input voltage V INThe gate of PMOSFET P1 at the drain. To provide reverse protection for PMOS FET P1, a reverse protection gate bias circuit 213 is connected between the first supply voltage VDD and the second current source 202 and includes a second breakdown Zener diode ZD2. The anode of the second breakdown Zener diode ZD2 is connected to the drain of NMOS FET N1, the cathode is connected to the first supply voltage VDD, and is also connected to the gate of NMOS FET N1. The source of NMOS FET N1 is connected to the second current source 202 and is also connected to the high-voltage PMOS cascode / switching circuit 211 at the node shared by the gate of PMOSFET P1 and the cathode of the first breakdown Zener diode ZD1.

[0036] In addition, protection against positive voltage offsets is provided by a high-voltage NMOS cascode / switching circuit 212 that is connected between the first supply voltage VDD and the protected input voltage V INP and a third current source 203. The high-voltage NMOS cascode / switching circuit 212 includes a third breakdown Zener diode ZD3. The anode of the third breakdown Zener diode ZD3 is connected at node 3 to the source of NMOS FET N3 (and the third current source 203), and the cathode is connected to the gate of NMOSFET N3 having a drain connected to node 2. To ensure that when the input voltage is at the detection threshold, sufficient Vgs is provided at NMOS FET N3 to act like a low-resistance (Rdson) element, a level shifter circuit 214 is connected between the high-voltage NMOS cascode / switching circuit 212 (e.g., node 2) and the high-voltage PMOS cascode / switching circuit 211 (e.g., node 1). Specifically, the level shifter circuit 214 includes a fourth breakdown Zener diode ZD4. The anode of the fourth breakdown Zener diode ZD4 is connected at node 2 to the source of NMOS FET N2 (and the fourth current source 204), and the cathode is connected to the gate of NMOSFET N2 having a drain connected to the first supply voltage VDD through a series-connected diode D1 and resistor R1.

[0037] As disclosed herein, when the input voltage V IN is within the linear operating range of the supply voltage (e.g., VDD - Vz - V TH < V IN < VDD), the high-speed dynamic range input protection circuit 200 provides a first circuit path 210 (indicated by the dashed line) for the input voltage to pass through substantially unmodified to reach the output (V INP ). At the input voltage V INDuring linear operation at 100 Hz, the available Zener diode voltage drop Vz across the Zener diodes ZD1, ZD4, ZD3 is sufficient to clamp the gate oxide structures at the current path transistors P1, N2, N3. Z and VDD), the PFET transistor P1 behaves like a low resistance element (Rdson), and the NFET transistor N2 behaves like a transistor with a threshold voltage drop V TH The protected input voltage V INP Equal to the input voltage V IN Subtract the offset or threshold voltage drop across the NMOS source follower transistor N2, V TH (eg, Vgs). In applications where the input protection circuit 200 is connected to protect the non-inverting input of a comparator, V IN With V INP The voltage threshold between V TH The differential offset may affect the performance of the comparator, in which case a replica of the input protection circuit 200 may be connected to the inverting or reference input of the comparator to cancel this offset.

[0038] In addition, the high speed dynamic range input protection circuit 200 includes a first circuit portion 211, 213, which effectively INP ) to a lower clamping value (e.g., approximately VDD-V Z ) to prevent negative input voltage excursion. In the first circuit portion, the high voltage PMOS cascode / switch circuit 211 includes a PFET transistor P1, which prevents the voltage input V IN The negative offset of the PFET transistor P1 is prevented by the Zener diode ZD2, but the PFET transistor P1 acts as a low resistance Rdson switch during normal operation. In the reverse protection gate bias circuit 213, the Zener diode ZD2 biases the PFET transistor P1 to prevent negative offset, and when the input voltage V IN When the supply voltage VDD is exceeded, the NFET transistor N1 provides reverse blocking. In the second circuit portion, the high voltage NMOS cascode / switch circuit 212 includes an NFET transistor N3, which prevents the voltage input VDD from being reversed by acting as a cascode. IN, but the NFET transistor N3 acts as a low resistance Rdson switch during normal operation. In the level shifter circuit 214, when the NFET transistor N3 operates as a low resistance Rdson switch, the NFET transistor N2 ensures that the gate-source voltage Vgs of the NFET transistor N3 exceeds the drain-source voltage Vds. To this end, the gate-source voltage Vgs of the NFET transistor N2 must track or be greater than the gate-source voltage Vgs of the NFET transistor N3. To prevent transients in the supply voltage VDD, the high speed dynamic range input protection circuit 200 may also include a diode D1, a resistor R1, and Zener diodes ZD1, ZD3, and ZD4, as well as a bias circuit 200 and a configuration that causes the input voltage V IN The response time of the pull-down current sources 201-204 decreases.

[0039] To improve the understanding of the operation of the high speed dynamic range input protection circuit 200 during a negative voltage excursion, reference is now made to Figure 3 , Figure 3 Depicted reference Figure 2 1 is a schematic circuit diagram of a high speed dynamic range input protection circuit 300, wherein the same reference numerals are used to represent the same elements. As depicted, the input protection circuit 300 is connected to the input terminal V IN With the protected input V INP Between and including the input voltage V IN The negative offset protection provided by the high voltage PMOS cascode / switch circuit 211 and the reverse protection gate bias circuit 213 is passed through to reach the output (V INP ) of the circuit path 310 (indicated by a dotted line). Specifically, the prominent current path 311 of the input protection circuit 300 shows the flow of the protection current, which flows at the input voltage V IN Protect output voltage during negative excursion under V INP , so that under negative input voltage excursions down to the breakdown voltage of PMOS FET P1, the output voltage is limited to a lower clamping value (e.g., V INP =V DD -V ZRB During such negative input voltage excursions, the drain of PFET transistor P1 follows the input signal V IN However, negative voltage protection is provided by PFET transistor P1 and reverse protection gate bias circuit 213, which biases the gate (node ​​4) of PFET transistor P1 to a Zener reverse bias voltage V below the supply voltage. ZRB (For example, V DD -V ZRB) to prevent the gate-source oxide of the PFET transistor P1 from being damaged. After the source (node ​​1) of the PFET transistor P1 is clamped to no less than 2*Vzd below the supply voltage (e.g., V DD -V ZRB -V ZFB ), the PFET transistor P1 is turned off because the gate-source voltage Vgs of the PFET transistor P1 is <V ZFB =V BE When the NFET transistor N3 is turned on by the supply voltage VDD and the clamp voltage (node ​​1) passes through the source follower NFET transistor N2 to the drain (node ​​2) of the NFET transistor N3, the Zener diode ZD4 limits the NFET transistor N3 (node ​​3) to a Zener reverse bias voltage V below the supply voltage. ZRB (For example, V DD -V ZRB ), and thus the protected output V INP (Node 3) is clamped at a similar voltage (“backwards” through NMOS FET N3), assuming that the source-drain voltage drop across NFET transistor N3 is negligible. Therefore, the protected output voltage V INP Clamped to not exceed V DD -V ZRB , and all circuit currents are limited and well controlled.

[0040] In addition to preventing negative excursions, the high speed dynamic range input protection circuit 200 includes a second circuit portion 212, 214 that effectively INP ) to a higher clamp value (e.g., VDD-V BE =VDD-V ZFB ) to prevent positive input voltage excursions. To improve the understanding of the operation of the high speed dynamic range input protection circuit 200 during negative voltage excursions, now refer to Figure 4 , Figure 4 Depicted reference Figure 2 1 is a schematic circuit diagram of a high speed dynamic range input protection circuit 400, wherein the same reference numerals are used to represent the same elements. As depicted, the input protection circuit 400 is connected to the input terminal V IN With the protected input V INP Between and including the input voltage V IN The positive offset protection provided by the high voltage NMOS cascode / switch circuit 212 and the level shifter circuit 214 is passed through to reach the protected output (V INP) of the circuit path 410 (indicated by a dotted line). Specifically, the prominent current path 411 of the input protection circuit 400 shows the flow of the protection current, which flows at the input voltage V IN (e.g., above the supply voltage VDD) during positive excursions INP , so that under positive input voltage excursions up to the breakdown voltage of NMOS FET N3, the output voltage is limited to a higher clamping value (e.g., V INP =VDD-V ZFB ). During such positive input voltage excursions, the PMOS FET P1 is turned off, but the voltage drop V across the drain-body diode of the PMOS FET P1 is DB The source of PMOS FET P1 (node ​​1) will be allowed to rise to the input voltage minus the diode voltage drop (+VV DB Across the forward biased Zener diode ZD1, the voltage at node 4 (eg, node 1 = +VV DB -V ZFB ), which turns off NMOS FET N1 to prevent current flow. However, the node 1 voltage will also pass through the reverse biased Zener diode ZD4 to the NMOS source follower transistor N2. If the input voltage V IN exceeds a Zener voltage above the supply voltage (for example, V IN ≥V DD +V ZRB ), then diode D1 and resistor R1 will prevent the NMOS cascode / switch circuit 212 from clamping to the supply voltage VDD. Therefore, the input signal (node ​​2) will then pass to the NMOS FET N3, the gate of which is at the supply voltage VDD and is therefore turned on to provide the protected output voltage V INP Clamped to V DD -V ZRB and withstand positive voltages up to its BVDSS capability.

[0041] Although field effect transistor P1 is shown as a PMOS transistor having a first or "n" polarity type, and field effect transistors N1-N3 are shown as NMOS transistors having a second or "p" polarity type, this is not a limitation of the present invention. Thus, the polarity types of transistors P1 and N1-N3 may be reversed and the supply voltages (e.g., V DD ) and ground (for example, V SS ) to maintain the functionality of the input protection circuit.

[0042] In order to improve the understanding of the operation of the high speed dynamic range input protection circuit according to selected embodiments of the present disclosure, reference is now made to Figure 5 , Figure 5 Graphically depicts the cascode behavior of high-voltage PMOS and NMOS transistors and the protected output voltage (V INP ) and the input voltage (V IN ). As depicted by waveform 501, the drain-source voltage Vds of the high-voltage NMOSFET N3 acts as a resistor below the first input voltage transition point at the supply voltage VDD and acts as a cascode above the first input voltage transition point. Also, as depicted by waveform 502, the drain-source voltage Vds of the high-voltage PMOSFET P1 acts as a resistor below the supply voltage VDD and acts as a cascode above the first input voltage transition point. DD The Zener reverse bias voltage V ZRB acts as a resistor above the second input voltage transition point at or near the input voltage transition point (or more specifically, V DD -V ZRB -V TH ) and acts as a cascode below the second input voltage transition point (or more specifically, V DD -V ZRB -V TH ). Therefore, when both transistors N3 and P1 act as transistors, the protected output voltage (V INP ) with input voltage (V IN ) in a linear relationship, but the threshold voltage of NMOSFET N2 (for example, V TH ). However, when the high-voltage PMOSFET P1 acts as a cascode, the input protection circuit provides negative voltage protection or low voltage protection to prevent negative excursions below the linear operating voltage range. Also, when the high-voltage NMOSFET N3 acts as a cascode, the input protection circuit provides positive voltage protection or high voltage protection to prevent positive excursions above the linear operating voltage range. This behavior is expressed as the output voltage (V INP ) is used to depict the simulation plot when the input voltage (V IN ) has a negative excursion below the normal voltage operating range (for example, V IN <VDD-V Z -V TH ), the protected output voltage (V INP ) is limited to a lower value (e.g., V INP =VDD-V Z Moreover, when the input voltage (V IN ) within the normal voltage operating range (e.g., VDD-V Z -V TH <V INWhen (VDD), the protected output voltage has a linear deviation function with respect to the input voltage (V INP = V IN - V TH = V IN - Vgs). Finally, when the input voltage (V IN ) exceeds the normal voltage operating range (e.g., V IN > VDD), the protected output voltage (V INP ) is limited to a higher value (e.g., V INP = VDD - V TH ) by the second cascode switch N3 to prevent a positive offset in the input voltage (V IN ).

[0043] As described above, signal paths 210, 310, 410 illustrate the signal paths from the input (V IN ) to the output (V INP ) for all three operating modes providing negative protection, linear operation, and positive protection. This is achieved by using Zener diodes ZD1, ZD2 to set the maximum gate - source voltage Vgs on the corresponding FETs P1, N1 connected to them. Although current can flow in Zener diodes ZD1, ZD2, this is not the signal path. Additionally, when the input voltage V IN >> VDD, diodes D1 and resistor R1 provide reverse protection. As can be seen from the above, when the input voltage V IN is within the normal linear operating range, MOSFETs P1 and N3 are switches (resistors) and MOSFET N2 is a level shifter or source follower. Within this linear operating range, the maximum and minimum values of the input voltage V IN are defined as VDD - Vzd2 - V TH ≤ V IN ≤ VDD. However, when the input voltage V IN is below the minimum linear operating voltage (e.g., VDD - Vzd2 - V TH ), the disclosed input protection circuit provides negative voltage or low voltage (LV) protection such that PMOS FET P1 is in the off state (AbsValVgs < 0V) and NMOS FET N3 operates as a switch. Moreover, when the input voltage V INWhen above the maximum linear operating voltage (e.g., VDD), the disclosed input protection circuit provides positive voltage or high voltage (HV) protection such that PMOS FET P1 operates as a switch and NMOS FET N3 operates as a cascode. When acting as a switch, the drain-source voltage Vds on MOSFETs P1 and N3 is small. When acting as a cascode, the gate-source voltage Vgs is fixed or limited by a Zener diode such that the drain-source voltage can be very large, thus allowing it to extend to the limit voltage. When in the cut-off mode where the MOSFET is off, the gate-source voltage Vgs < VT, and the drain-source voltage Vds can be as large as the FET rating. In the case where MOSFETs P1 and N3 are constructed as high-voltage FETs, the resulting input protection circuit provides protection / blocking against large offset voltages.

[0044] It should now be appreciated that an input protection circuit, device, method, and system for generating a protected output voltage (VINP) from positive and negative overvoltages at an input voltage (VIN) has been provided. The disclosed input protection circuit includes a first cascode switch for limiting the output voltage when the input voltage excursion is below a specified voltage operating range, a high-voltage PMOS field effect transistor (PMOSFET), the high-voltage PMOSFET having a gate or control electrode, a drain or first current-carrying electrode connected to the control electrode across a first Zener diode, and a second current-carrying electrode connected to receive the input voltage. The input protection circuit also includes a blocking field effect transistor (FET), the blocking FET having a gate or control electrode connected to a supply voltage, a drain or first current-carrying electrode connected to the supply voltage across a second Zener diode, and a second current-carrying electrode connected to the control electrode of the high-voltage PMOSFET. In addition, the input protection circuit includes a second cascode switch, the second cascode switch is used to limit the output voltage when the input voltage excursion is higher than the specified voltage operating range, including a high-voltage NMOS field effect transistor (NMOSFET), the high-voltage NMOSFET having a gate or control electrode connected to the supply voltage, a source or first current-carrying electrode that provides the output voltage and is connected to the control electrode across a third Zener diode, and a drain or second current-carrying electrode connected to a source follower node. The input protection circuit also includes a level shifter circuit, the level shifter circuit is connected between the first current-carrying electrode and the source follower node of the high-voltage PMOSFET. In a selected embodiment, the level shifter circuit includes a transistor (e.g., NMOSFET), the transistor having a control electrode connected to the first current-carrying electrode of the high-voltage PMOSFET, a first current-carrying electrode connected to the control electrode of the transistor across a fourth Zener diode using a source follower node, and a second current-carrying electrode coupled to the supply voltage through a diode. In a selected embodiment, the diode has a cathode connected to the second current-carrying electrode of the NMOSFET and an anode connected to the supply voltage through a resistor. To set a response time for the input voltage to drop, each of the high-voltage PMOSFET, the blocking FET, the high-voltage NMOSFET, and the transistor may be connected to a second supply voltage, respectively, through a current source circuit. In selected embodiments of the disclosed input protection circuit, the high-voltage PMOSFET is connected to prevent a negative input voltage excursion that significantly exceeds a gate oxide breakdown voltage of the high-voltage PMOSFET, wherein the negative input voltage excursion may be a voltage that is lower than the supply voltage by at least the reverse bias voltage of the first Zener diode.Additionally, the high voltage NMOSFET may be connected to prevent positive input voltage excursions that significantly exceed a gate oxide breakdown voltage of the high voltage NMOSFET, wherein the positive input voltage excursion may be a voltage that exceeds the supply voltage.

[0045] In another form, a method, circuit, device, and system for protecting a circuit input from input voltage fluctuations at a voltage input is provided. In the disclosed method, the voltage input is connected to the circuit input via a signal path in a protection circuit, the protection circuit comprising a first cascode switch, a level shifter, and a second cascode switch connected in series between the voltage input and the circuit input. The disclosed method also generates an output voltage at the circuit input using the protection circuit when the input voltage at the voltage input is within a specified linear operating voltage range of the protection circuit, the output voltage being a threshold voltage lower than the input voltage. Specifically, the first cascode switch is connected between a first current source and a blocking field effect transistor connected to a supply voltage, thereby providing negative voltage excursion protection at the circuit input when the input voltage at the voltage input is lower than the specified linear operating voltage range of the protection circuit. In selected embodiments, the first cascode switch comprises a high voltage PMOS field effect transistor (PMOSFET), the high voltage PMOSFET having a control electrode, a first current carrying electrode connected to the control electrode across a first Zener diode, and a second current carrying electrode connected to the voltage input to receive an input voltage. In addition, the second cascode switch is connected between a second current source and the supply voltage, thereby providing positive voltage offset protection at the circuit input when the input voltage at the voltage input is higher than the specified linear operating voltage range of the protection circuit. In a selected embodiment, the second cascode switch includes a high-voltage NMOS field effect transistor (NMOSFET), the high-voltage NMOSFET having a control electrode connected to the supply voltage, a first current-carrying electrode that provides the circuit input and is connected to the control electrode across a third Zener diode, and a second current-carrying electrode connected to a source follower node. In addition, the blocking field effect transistor (FET) can be connected between a fourth current source and the supply voltage and includes a control electrode connected to the supply voltage, a first current-carrying electrode connected to the supply voltage across a second Zener diode, and a second current-carrying electrode connected to the control electrode of the high-voltage PMOSFET. In addition, the level shifter is connected between a third current source and a resistor circuit connected to the supply voltage, thereby acting as a resistor circuit having a threshold voltage drop V THIn a selected embodiment, the level shifter circuit includes a transistor having a control electrode connected to the first current carrying electrode of the high voltage PMOSFET, a first current carrying electrode including the source follower node connected to the control electrode of the transistor across a fourth Zener diode, and a second current carrying electrode connected to the resistor circuit. In the disclosed method, the first cascode switch is connected to prevent negative input voltage excursions that significantly exceed the gate oxide breakdown voltage of the high voltage PMOSFET. In addition, the second cascode switch is connected to prevent positive input voltage excursions that exceed the supply voltage.

[0046] In yet another form, an input protection circuit, method, apparatus, and system for generating a protected output voltage from an input voltage received at a voltage input is provided. The disclosed input protection circuit includes a first cascode switch, a second cascode switch, a blocking field effect transistor, and a level shifter circuit. The disclosed first cascode switch includes a high voltage FET of a first polarity type and is connected between a first current source and a blocking field effect transistor connected to a supply voltage, thereby providing negative offset protection at the output voltage when the input voltage is below a specified linear operating voltage range of the input protection circuit, the high voltage FET of the first polarity type having a control electrode, a first current carrying electrode connected to the control electrode across a first Zener diode, and a second current carrying electrode connected to receive the input voltage. The disclosed second cascode switch includes a high voltage FET of a second polarity type and is connected between a second current source and the supply voltage, thereby providing positive offset protection at the output voltage when the input voltage is above the specified linear operating voltage range of the input protection circuit, the high voltage FET of the second polarity type having a control electrode connected to the supply voltage, a first current-carrying electrode providing the output voltage and connected to the control electrode across a second Zener diode, and a second current-carrying electrode connected to a source follower node. The disclosed blocking field effect transistor includes a field effect of a second polarity type, the field effect of the second polarity type having a control electrode connected to the supply voltage, a first current-carrying electrode connected to the supply voltage across a third Zener diode, and a second current-carrying electrode connected to the control electrode of the high voltage FET of the first polarity type. The blocking field effect transistor connected between the third current source and the supply voltage provides a reverse protection gate bias to the high voltage FET of the first polarity type. The disclosed level shifter circuit is connected between a fourth current source and a resistor circuit connected to the supply voltage, thereby operating as a source follower between the first current-carrying electrode of the high voltage FET of the first polarity type and the source follower node. In selected embodiments, the high voltage FET of the first polarity type is a PMOS field effect transistor, and the high voltage FET of the second polarity type is an NMOS field effect transistor. In other embodiments, the high voltage FET of the first polarity type is an NMOS field effect transistor, and the high voltage FET of the second polarity type is a PMOS field effect transistor. Based on the polarity type of the field effect transistor, in selected embodiments, the supply voltage is a first reference voltage VDD, and in other embodiments, the supply voltage is a ground reference voltage VSS.

[0047] Although the described exemplary embodiments disclosed herein focus on an input protection circuit having a specified supply voltage range (e.g., 5V to 65V) in which the component transistors, Zener diodes, and current sources operate within a safe operating region to provide a method of protecting inputs from positive and negative overvoltages having a dynamic range of -5V to +72V that exceeds the gate oxide limits of the component transistors in the input protection circuit, the present invention is not necessarily limited to the exemplary embodiments shown herein and may be applied to any suitable input protection system that prevents positive and negative input voltage excursions utilizing a high speed, low current, high input impedance input protection circuit that can be fabricated using standard semiconductor processing techniques. Therefore, the particular embodiments disclosed above are merely illustrative and should not be construed as limitations of the invention as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Therefore, the foregoing description is not intended to limit the invention to the particular forms set forth, but on the contrary is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that various changes, substitutions and alterations may be made without departing from the spirit and scope of the invention in its broadest form.

[0048] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and any one or more elements that may cause any benefit, advantage, or solution to occur or become more significant should not be construed as key, required, or essential features or elements of any or all claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover non-exclusive inclusions such that a process, method, article, or device that includes a list of elements may include not only those elements, but may include other elements that are not explicitly listed or inherent to such process, method, article, or device.

Claims

1. An input protection circuit for generating an output voltage in response to an input voltage, characterized in that include: a first cascode switch for limiting the output voltage when the input voltage excurses below a specified voltage operating range, the first cascode switch comprising a high voltage PMOSFET having a control electrode, a first current carrying electrode connected to the control electrode across a first Zener diode, and a second current carrying electrode connected to receive the input voltage; a blocking FET having a control electrode connected to a supply voltage, a first current carrying electrode connected to the supply voltage across a second Zener diode, and a second current carrying electrode connected to the control electrode of the high voltage PMOSFET; a second cascode switch for limiting the output voltage when the input voltage excurses above the specified voltage operating range, the second cascode switch comprising a high voltage NMOSFET having a control electrode connected to the supply voltage, a first current carrying electrode providing the output voltage and connected to the control electrode across a third Zener diode, and a second current carrying electrode connected to a source follower node; as well as a level shifter circuit connected between the first current-carrying electrode of the high-voltage PMOSFET and the source follower node; The level shifter circuit comprises a transistor (N2), a control electrode of the transistor (N2) being connected to the first current carrying electrode of the high voltage PMOSFET, the first current carrying electrode of the transistor (N2) comprising the source follower node, the source follower node being connected to the control electrode of the transistor (N2) across a fourth Zener diode (ZD4), and a second current carrying electrode of the transistor (N2) being coupled to the supply voltage via a diode; Each of the high-voltage PMOSFET, the blocking FET, the high-voltage NMOSFET and the transistor (N2) is connected to a second power supply voltage through a current source circuit, respectively.

2. The input protection circuit according to claim 1, characterized in that: The transistor includes an NMOS field effect transistor NMOSFET.

3. The input protection circuit according to claim 2, characterized in that: The diode has a cathode connected to the second current carrying electrode of the NMOSFET and an anode connected to the supply voltage through a resistor.

4. The input protection circuit according to claim 1, characterized in that: The high voltage PMOSFET is connected to prevent negative input voltage excursions that significantly exceed the gate oxide breakdown voltage of the high voltage PMOSFET.

5. The input protection circuit according to claim 4, characterized in that: The negative input voltage offset is a voltage lower than the supply voltage by at least a reverse bias voltage of the first Zener diode.

6. A method for protecting a circuit input from input voltage fluctuations at a voltage input, characterized in that, include: connecting the voltage input to the circuit input through a signal path in a protection circuit, the protection circuit comprising a first cascode switch, a level shifter, and a second cascode switch connected in series between the voltage input and the circuit input; as well as generating, by the protection circuit, an output voltage at the circuit input when the input voltage at the voltage input is within a specified linear operating voltage range of the protection circuit, the output voltage being a threshold voltage lower than the input voltage; wherein the first cascode switch is connected between a first current source and a blocking field effect transistor connected to a supply voltage so as to provide negative voltage excursion protection at the circuit input when the input voltage at the voltage input is below a specified linear operating voltage range of the protection circuit, wherein the second cascode switch is connected between a second current source and the supply voltage to provide positive voltage excursion protection at the circuit input when the input voltage at the voltage input is above the specified linear operating voltage range of the protection circuit, and The level shifter is connected between the third current source and the resistor circuit connected to the supply voltage so as to act as a level shifter having a threshold voltage drop V TH Source follower operation; The level shifter circuit includes a transistor (N2), a control electrode of the transistor (N2) being connected to a first current-carrying electrode of a high-voltage PMOSFET (P1), the first current-carrying electrode of the transistor (N2) including the source follower node, the source follower node being connected to the control electrode of the transistor (N2) across a fourth Zener diode, and a second current-carrying electrode of the transistor (N2) being connected to a resistor circuit.

7. An input protection circuit for generating an output voltage from an input voltage received at a voltage input, characterized in that include: a first cascode switch connected between a first current source and a blocking field effect transistor connected to a supply voltage, wherein the first cascode switch provides negative voltage excursion protection at the output voltage when the input voltage is below a specified linear operating voltage range of the input protection circuit, wherein the first cascode switch comprises a high voltage FET of a first polarity type having a control electrode, a first current carrying electrode connected to the control electrode across a first Zener diode, and a second current carrying electrode connected to receive the input voltage; a second cascode switch connected between a second current source and the supply voltage, wherein the second cascode switch provides positive voltage excursion protection at the output voltage when the input voltage is above a specified linear operating voltage range of the input protection circuit, wherein the second cascode switch comprises a high voltage FET of a second polarity type having a control electrode connected to the supply voltage, a first current carrying electrode providing the output voltage and connected to the control electrode across a second Zener diode, and a second current carrying electrode connected to a source follower node; a blocking field effect transistor (FET) of the second polarity type, the blocking FET of the second polarity type connected between a third current source and the supply voltage to provide a reverse protection gate bias to the high voltage FET of the first polarity type, wherein the blocking FET includes a control electrode connected to the supply voltage, a first current carrying electrode connected to the supply voltage across a third Zener diode, and a second current carrying electrode connected to the control electrode of the high voltage FET of the first polarity type; as well as a level shifter circuit connected between a fourth current source and a resistor circuit connected to the supply voltage, wherein the level shifter circuit operates as a source follower between the first current carrying electrode of the high voltage FET of the first polarity type and the source follower node; The level shifter circuit comprises a transistor (N2), the control electrode of the transistor (N2) being connected to the first current carrying electrode of the high voltage FET of the first polarity type, the first current carrying electrode of the transistor (N2) comprising the source follower node, the source follower node being connected to the control electrode of the transistor (N2) across a fourth Zener diode, the second current carrying electrode of the transistor (N2) being coupled to the supply voltage (VDD) via a diode (D1); Each of the first polarity type high voltage FET, the blocking FET, the second polarity type high voltage FET and the transistor (N2) is connected to a second power supply voltage through a current source circuit, respectively.

8. The input protection circuit according to claim 7, characterized in that: The high voltage FET of the first polarity type comprises a PMOS field effect transistor, and wherein the high voltage FET of the second polarity type comprises an NMOS field effect transistor.

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