Bidirectional power device

Abstract

Disclosed is a bidirectional power device, which comprises a semiconductor layer, a trench in the semiconductor layer, a gate dielectric layer on the sidewall of the trench, a control gate at the lower part of the trench, and a channel region in the semiconductor layer and adjacent to the control gate, wherein the control gate is separated from the semiconductor layer by the gate dielectric layer. In the bidirectional power device provided by the application, the channel region is adjacent to the control gate at the lower part of the trench, the channel length can be reduced by reducing the width of the trench, and thus the channel resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a bidirectional power device. Background Technology

[0002] Power devices are primarily used in high-power power supply and control circuits, such as as switching or rectifying elements. In power devices, doped regions of different doping types form PN junctions, thereby achieving the function of diodes or transistors. Power devices typically need to carry large currents at high voltages in applications. On one hand, to meet the demands of high-voltage applications and improve device reliability and lifespan, power devices require high breakdown voltage. On the other hand, to reduce the power consumption and heat generated by the power devices themselves, they need low on-resistance. In power supply circuits, charging and discharging are frequently involved, and the current flows differently during charging and discharging, requiring power devices to have bidirectional conduction capabilities.

[0003] US patents US5612566 and US6087740 disclose a bidirectional power device. This bidirectional power device includes a substrate and a first output electrode and a second output electrode located on the substrate. The substrate is a P-type substrate, a P-type epitaxial layer, or a P-type doped well region; the two output electrodes are respectively composed of a lightly doped N- region and a heavily doped N+ region located within the lightly doped N- region. In the on-state of the power device, when the first output electrode is shorted to the substrate, current flows from the second output electrode to the first output electrode; when the second output electrode is shorted to the substrate, current flows from the first output electrode to the second output electrode.

[0004] However, the breakdown voltage and on-resistance of bidirectional power devices are contradictory parameters. While a better breakdown voltage can be achieved by reducing the impurity concentration in the lightly doped N-region, leading to an increase in on-resistance and thus increased power consumption, this also increases the breakdown voltage.

[0005] In bidirectional power devices, further improvements are still needed to balance the requirements of voltage withstand characteristics and on-resistance. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide a bidirectional power device, wherein the control gate adjacent to the lower part of the trench in the channel region controls the channel length by the width of the trench, thereby reducing the on-resistance.

[0007] According to a first aspect of the present application, there is provided a bidirectional power device comprising: a semiconductor layer; a trench in the semiconductor layer; a gate dielectric layer on a sidewall of the trench; a control gate at a lower portion of the trench; and a channel region in the semiconductor layer adjacent to the control gate; wherein the control gate is separated from the semiconductor layer by the gate dielectric layer.

[0008] Preferably, the bidirectional power device further comprises: a shield gate at an upper portion of the trench.

[0009] Preferably, the bidirectional power device further comprises: an isolation layer between the control gate and the shield gate.

[0010] Preferably, the shield gate has a length of 0.6-1.2um.

[0011] Preferably, the control gate and the shield gate are in contact with each other.

[0012] Preferably, the shield gate has a length of 0.4-0.8um.

[0013] Preferably, the bidirectional power device further comprises: a shield dielectric layer on a sidewall of the trench, the shield gate being separated from the semiconductor layer by the shield dielectric layer.

[0014] Preferably, the shield dielectric layer has a thickness of 0.1-0.25um.

[0015] Preferably, the shield dielectric layer has a thickness greater than or equal to a thickness of the gate dielectric layer.

[0016] Preferably, the control gate has a width greater than a width of the shield gate.

[0017] Preferably, the bidirectional power device further comprises: a source region and a drain region in the semiconductor layer adjacent to the shield gate, the source region and the drain region extending from a first surface of the semiconductor layer to overlap the control gate.

[0018] Preferably, the source region and the drain region have a length greater than a sum of lengths of the shield gate and the isolation layer, and less than a sum of lengths of the shield gate, the isolation layer and the control gate.

[0019] Preferably, the source region and the drain region have a length greater than a length of the shield gate, and less than a sum of lengths of the shield gate and the control gate.

[0020] Preferably, the bidirectional power device further comprises: a voltage dividing dielectric layer at an upper portion of the trench.

[0021] Preferably, the bidirectional power device further comprises: a source region and a drain region in the semiconductor layer and adjacent to the control gate, the source region and the drain region extending from the first surface of the semiconductor layer to overlap the control gate.

[0022] Preferably, the length of the resistive medium layer is greater than 0.3 um.

[0023] Preferably, the length of the source region and the drain region is greater than the length of the resistive medium layer and less than the length of the resistive medium layer and the control gate.

[0024] Preferably, the control gate extends from the first surface of the semiconductor layer to the lower portion of the trench.

[0025] Preferably, the bidirectional power device further comprises: a source region and a drain region in the semiconductor layer and adjacent to the control gate, the source region and the drain region extending from the first surface of the semiconductor layer to overlap the control gate.

[0026] Preferably, the length of the source region and the drain region extending in the semiconductor layer is 0.5-1.5 um.

[0027] Preferably, the length of the trench is 1.2-2.2 um and the width is 0.1-0.6 um.

[0028] Preferably, the semiconductor layer is of a first doping type, the source region and the drain region are of a second doping type, and the channel region is of the first doping type or the second doping type, the first doping type and the second doping type being opposite.

[0029] Preferably, the semiconductor layer is selected from one of a semiconductor substrate itself, an epitaxial layer formed on a semiconductor substrate, or a well region implanted in a semiconductor substrate.

[0030] Preferably, the bidirectional power device further comprises: a first contact contacting the source region to form a first output electrode; a second contact contacting the drain region to form a second output electrode; a third contact contacting the semiconductor layer to form a substrate electrode; and a fourth contact contacting the control gate to form a gate electrode.

[0031] Preferably, the bidirectional power device further comprises: a first lead region in the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region; a covering medium layer on the first surface of the semiconductor layer; and a first contact hole extending through the covering medium layer to the source region, the first contact contacting the source region through the first contact hole and the first lead region.

[0032] Preferably, the bidirectional power device further comprises: a second lead region in the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region; a second contact hole extending through the covering dielectric layer to the drain region; the second contact is in contact with the drain region through the second contact hole and the second lead region.

[0033] Preferably, the bidirectional power device further comprises: a third lead region in the semiconductor layer and close to the first surface of the semiconductor layer, wherein the doping concentration of the third lead region is greater than the doping concentration of the semiconductor layer; a third contact hole extending through the covering dielectric layer to the semiconductor layer; the third contact is in contact with the semiconductor layer through the third contact hole and the third lead region.

[0034] Preferably, the bidirectional power device further comprises: a fourth contact hole extending through the covering dielectric layer to the control gate.

[0035] Preferably, the third contact is on the second surface of the semiconductor layer.

[0036] Preferably, the bidirectional power device further comprises: a wiring layer, the wiring layer comprises a first wiring to a fourth wiring, respectively electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through a plurality of conductive holes.

[0037] Preferably, the bidirectional power device further comprises: a plurality of metal solder balls on the wiring layer, electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.

[0038] Preferably, when the bidirectional power device comprises a shielding gate on the control gate, the fourth contact is also electrically connected to the shielding gate.

[0039] Preferably, the shielding gate is electrically connected to the semiconductor layer or the control gate.

[0040] Preferably, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of current direction.

[0041] Preferably, when the substrate electrode is electrically connected to the first output electrode, the current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode, the current flows from the first output electrode to the second output electrode.

[0042] According to a second aspect of the present application, a bidirectional power device is provided, comprising a plurality of cell structures, the cell structure being the bidirectional power device described above, the source regions in the plurality of cell structures being electrically connected together, and the drain regions in the plurality of cell structures being electrically connected together.

[0043] The bidirectional power device provided by the embodiment of the present application can reduce the channel length by reducing the width of the trench, and further reduce the channel resistance.

[0044] Further, the control gate and the shielding gate are formed in the lower part and the upper part of the trench respectively, the control gate and the shielding gate are isolated from each other, the control gate is separated from the semiconductor layer by the gate dielectric layer, the shielding gate is separated from the source region and the drain region by the shielding dielectric layer, the shielding gate depletes the charges of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, and the voltage resistance characteristic of the device is improved; the source region and the drain region provide a low impedance conduction path with the semiconductor layer when the bidirectional power device is on.

[0045] Further, different threshold voltages can be realized by adjusting the thickness of the shielding dielectric layer, the doping concentration of the source region and the drain region, and the length of the shielding gate.

[0046] Further, the control gate and the shielding gate are formed in the lower part and the upper part of the trench respectively, the control gate and the shielding gate are in contact with each other, the control gate is separated from the semiconductor layer by the gate dielectric layer, the shielding gate is separated from the source region and the drain region by the shielding dielectric layer, the shielding gate depletes the charges of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, and the voltage resistance characteristic of the device is improved; the source region and / or the drain region provide a low impedance conduction path with the semiconductor layer when the bidirectional power device is on.

[0047] Further, different threshold voltages can be realized by adjusting the thickness of the shielding dielectric layer, the doping concentration of the source region and the drain region, and the length of the shielding gate.

[0048] Further, the control gate and the shielding gate are formed in the lower part and the upper part of the trench respectively, the control gate and the shielding gate are in contact with each other, the control gate is separated from the semiconductor layer by the gate dielectric layer, the shielding gate is separated from the source region and the drain region by the shielding dielectric layer, the shielding gate depletes the charges of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, and the voltage resistance characteristic of the device is improved; the source region and / or the drain region provide a low impedance conduction path with the semiconductor layer when the bidirectional power device is on.

[0049] Further, different threshold voltages can be realized by adjusting the thickness of the shielding dielectric layer, the doping concentration of the source region and the drain region, and the length of the shielding gate.

[0050] Further, when the bidirectional power device is on, the substrate electrode is electrically connected with one of the first output electrode and the second output electrode to realize bidirectional selection of the current direction. When the substrate electrode is electrically connected with the first output electrode, the current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected with the second output electrode, the current flows from the first output electrode to the second output electrode.

[0051] Further, the control gate in the trench extends from the first surface of the semiconductor layer to the lower part of the trench, and the source region and the drain region extend from the first surface of the semiconductor layer to overlap the control gate in the lower part of the trench. The source region and the drain region extend for a long length, so that the source region and the drain region can bear high voltage applied on the source region and the drain region in the vertical direction when the bidirectional power device is turned off, improving the withstand voltage characteristic of the bidirectional power device.

[0052] Further, different threshold voltages can be realized by adjusting the thickness of the gate dielectric layer and the doping concentration of the channel region.

[0053] Further, the substrate electrode, the first output electrode, the second output electrode and the gate electrode of the bidirectional power device are led out to the surface of the semiconductor substrate through the wiring layer, and a metal solder ball is formed on the wiring layer. Since the process of solder ball placement is adopted, the wire bonding of the conventional packaging is omitted, the parasitic inductance and the parasitic resistance of the packaging are reduced, and the packaging resistance of the bidirectional power device is reduced; since there is no encapsulation of the plastic packaging material, heat dissipation is easier, power consumption is reduced, and the reliability and safety of the bidirectional power device are improved.

[0054] Further, the bidirectional power device can be composed of a plurality of cell structures, the source regions of all the cell structures are electrically connected together as the first output electrode, and the drain regions are electrically connected together as the second output electrode, and by increasing the number of the cell structures, the current capacity of the bidirectional power device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0055] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken with reference to the accompanying drawings, in which:

[0056] Figure 1 A circuit schematic diagram of the bidirectional power device of the embodiment of the present application is shown;

[0057] Figures 2-4 Cross-sectional views and top views of different sections of the bidirectional power device of the first embodiment of the present application are shown respectively;

[0058] Figure 5 A cross-sectional view of a plurality of cell structures of the first embodiment of the present application is shown;

[0059] Figure 6 A top view of the bidirectional power device of the second embodiment of the present application is shown;

[0060] Figure 7 A cross-sectional view of the bidirectional power device of the third embodiment of the present application is shown;

[0061] Figures 8-10 Cross-sectional views and top views of different sections of the bidirectional power device of the fourth embodiment of the present application are shown respectively;

[0062] Figure 11 A cross-sectional view of multiple cell structures according to the fourth embodiment of the present invention is shown;

[0063] Figure 12 A cross-sectional view of a bidirectional power device according to a fifth embodiment of the present invention is shown;

[0064] Figures 13-15 Cross-sectional views and top views of different sections of the bidirectional power device according to the sixth embodiment of the present invention are shown respectively;

[0065] Figure 16 A cross-sectional view of multiple cell structures according to the sixth embodiment of the present invention is shown;

[0066] Figure 17 A cross-sectional view of a bidirectional power device according to a seventh embodiment of the present invention is shown;

[0067] Figures 18-20 Cross-sectional views and top views of different sections of the bidirectional power device according to the eighth embodiment of the present invention are shown respectively;

[0068] Figure 21 A cross-sectional view of multiple cell structures according to the eighth embodiment of the present invention is shown;

[0069] Figures 22-25 Cross-sectional views of the bidirectional power device according to the ninth embodiment of the present invention are shown respectively;

[0070] Figure 26 A top view of a bidirectional power device according to a ninth embodiment of the present invention is shown;

[0071] Figure 27 A schematic diagram of the package pins of the bidirectional power device according to the ninth embodiment of the present invention is shown;

[0072] Figure 28 A cross-sectional view of a bidirectional power device according to the tenth embodiment of the present invention is shown. Detailed Implementation

[0073] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0074] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0075] Figure 1 A circuit diagram of a bidirectional power device provided in an embodiment of the present invention is shown. This bidirectional power device is formed by a single transistor and has bidirectional conductor functionality. Figure 1As shown, the bidirectional power device includes a substrate Sub and two output terminals S1 and S2 located on the substrate Sub, as well as two parasitic body diodes D1 and D2. When the output terminal S2 and the substrate Sub are shorted, and a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and current flows from the output terminal S1 to the output terminal S2; when the output terminal S1 and the substrate Sub are shorted, and a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and current flows from the output terminal S2 to the output terminal S1; when the substrate Sub is connected to zero voltage, and a low voltage is applied to the gate G, the voltage is lower than the threshold voltage, and the bidirectional power device is turned off.

[0076] First Embodiment

[0077] Figures 2-4 Cross-sectional and top views of the bidirectional power device according to the first embodiment of the present invention are shown respectively; wherein, Figure 2 for Figure 4 The cross-sectional view taken along line AA' in the top view shown. Figure 3 for Figure 4 The cross-sectional view taken along line BB' in the top view shown. In this embodiment, the bidirectional power device is a trench-type device, which can be a metal-oxide-semiconductor field-effect transistor (MOSFET), an IGBT device, or a diode. In the following description, an N-type MOSFET is used as an example; however, the invention is not limited thereto.

[0078] exist Figure 2 The bidirectional power device shown is a vertical structural diagram containing only one cell structure. In actual products, the number of cell structures can be one or more. See also... Figures 2-4 The bidirectional power device includes a semiconductor layer 10, a trench 20 located within the semiconductor layer 10, a gate dielectric layer 21 located on the sidewall of the trench 20, a control gate 22 located at the lower part of the trench 20, a shielding gate 23 located at the upper part of the trench 20, and an isolation layer 24 located between the control gate 22 and the shielding gate 23.

[0079] In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14 to 3E16 cm⁻¹. -3 The semiconductor layer 10 is, for example, a silicon substrate, an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, and is p-type doped. The semiconductor layer 10 has the same doping type as the silicon substrate. The semiconductor layer 10 has opposing first and second surfaces.

[0080] The control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21.

[0081] Further, the bidirectional power device further comprises a shielding dielectric layer 25 on the sidewall of the trench 20, and the shielding gate 23 is separated from the semiconductor layer 10 by the shielding dielectric layer 25.

[0082] In the embodiment, the material of the gate dielectric layer 21, the isolation layer 24 and the shielding dielectric layer 25 can be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the three can be the same or different.

[0083] The thickness of the gate dielectric layer 21 is 200-1000 angstroms, i.e. 0.02-0.1 um, and the thickness of the shielding dielectric layer 25 is 1000-2500 angstroms, i.e. 0.1-0.25 um. The thickness of the shielding dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21.

[0084] The width W1 of the control gate 22 is greater than the width W2 of the shielding gate 23, and the length L1 of the control gate is less than the length L2 of the shielding gate 23. The length L2 of the shielding gate 23 is 0.6-1.2 um.

[0085] Further, the source region 31 and the drain region 32 of N-type doping are formed in the semiconductor layer 10 along the longitudinal direction, and the source region 31 and the drain region 32 can be interchanged; and the channel region 40 adjacent to the control gate 22 is formed in the semiconductor layer 10.

[0086] In the embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

[0087] In the embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22. The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the shielding gate 23 extending in the semiconductor layer 10, and preferably greater than the sum L2+L3 of the length of the shielding gate 23 and the length of the isolation layer 24 extending in the semiconductor layer 10, but less than the sum L1+L2+L3 of the length of the shielding gate 23, the length of the isolation layer 24 and the length of the control gate 22 extending in the semiconductor layer 10, i.e. L2+L3

[0088] The shield gate 23 is separated from the source region 31 and / or the drain region 32 by the shield dielectric layer 25. The shield gate depletes the charge of the source region and the drain region through the shield dielectric layer when the bidirectional power device is off, which improves the withstand voltage characteristic of the device; when the bidirectional power device is on, the source region and the drain region provide a low impedance conduction path with the semiconductor layer. Thus, the thickness of the shield dielectric layer, the doping concentration of the source region and the drain region, and the length of the shield gate can be adjusted to achieve different threshold voltages.

[0089] Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

[0090] Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32. The first lead region 311 has the same doping type as the source region 31, and the doping concentration of the first lead region 311 is greater than that of the source region 31. The second lead region 321 has the same doping type as the drain region 32, and the doping concentration of the second lead region 321 is greater than that of the drain region 32.

[0091] Further, a third lead region 101 is formed in the semiconductor layer 10, which is adjacent to the first surface of the semiconductor layer 10. The third lead region 101 has the same doping type as the semiconductor layer 10, and the doping concentration of the third lead region 101 is greater than that of the semiconductor layer 10.

[0092] Further, a covering dielectric layer 11 is formed on the first surface of the semiconductor layer 10, and a contact hole 50 is formed through the covering dielectric layer 11. The contact hole 50 includes a first contact hole 51, a second contact hole 52, a third contact hole 53, and a fourth contact hole 54. The first contact hole 51 is located on the source region 31 and extends through the covering dielectric layer 11 to the source region 31. The second contact hole is located on the drain region 32 and extends through the covering dielectric layer 11 to the drain region 32.

[0093] The third contact hole 53 extends through the covering dielectric layer 11 to the semiconductor layer 10 on both sides of the trench 20.

[0094] The fourth contact hole 54 extends through the covering dielectric layer 11 to the control gate 22 and / or the shield gate 23 in the trench 20.

[0095] In this embodiment, the covering dielectric layer 11 can be undoped silicon glass (USG) and boron-phosphorus-doped silicon glass (BPSG).

[0096] A metal layer 60 is deposited on the overlay dielectric layer 11. The metal layer 60 fills the first contact holes 51 to the fourth contact holes 54 to form the first contact 61 to the fourth contact 64, respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1. The second contact 62 contacts the drain region 32 through the second contact hole 52 and the second lead region 321 to form the second output electrode S2. The third contact 63 contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. Figure 3 As shown, the fourth contact 64 contacts the control gate 22 and / or the shielding gate 23 via the fourth contact hole 54 to form a gate electrode. Figure 4 As shown, the fourth contact hole 54 includes a contact hole 54a of the control gate 22 and a contact hole 54b of the shielding gate 23. In this embodiment, the control gate 22 and the shielding gate 23 are connected together.

[0097] In this embodiment, the material of the metal layer 60 can be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

[0098] Figure 2 In the original design, a single cell contains only three trenches, one source region, and one drain region. However, in actual products, there are more than one source region 31 and one drain region 32. Figure 2 Taking the example shown, the three trench structures are the first trench 20a, the second trench 20b, and the third trench 20c. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first output electrode S1; the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2; the third contact 63 leads the semiconductor layer 10 to form the substrate electrode Sub; and the fourth contacts 64a and 64b lead the control gate 22 and the shielding gate 23 in the trench 20 to the surface of the semiconductor layer 10 to form the gate electrode G. The control gate 22 and the shielding gate 23 are electrically connected together. The first trench 20a and the third trench 20c are symmetrically arranged outside the source region 31 and the drain region 32. The first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10, respectively, and are interchangeable. When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and current flows through the channel region in the second trench 20b. The direction of current can be selected by connecting one of the output electrodes to the substrate electrode. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S1 to the second output electrode S2.

[0099] When the voltage applied on the control gate 22 is less than the threshold voltage, the bidirectional power device is off, since the control gate 22 and the shield gate 23 are electrically connected together, the voltage applied on the shield gate 23 is low voltage at this time, high voltage is applied on the first output electrode S1 and the second output electrode S2, voltage difference is formed between the source region 31, the drain region 32 and the shield gate 23. The shield gate 23 in the first trench 20a and the third trench 20c induces electric charge in the source region 31 and the source region 32 through the shield dielectric layer 25, by adjusting the thickness and the material of the shield dielectric layer 25 and the impurity concentration of the source region 31 and the drain region 32, the source region and the drain region can be finally completely depleted, and the purpose of improving the withstand voltage of the device is achieved. At the same time, due to the increase of the impurity concentration of the source region 31 and the drain region 32, the resistance of the device is also greatly reduced.

[0100] Figure 5 Only the schematic diagram of two cell structures is shown, a plurality of first contacts 61 are connected together to form the first output electrode S1, and a plurality of second contacts 62 are connected together to form the second output electrode S2, so as to improve the current capacity of the device. Alternatively, for other types of bidirectional power devices, the current capacity of the device can be improved by increasing the number of cells, that is, selecting two or more cell structures connected in parallel.

[0101] Second embodiment

[0102] The technical solution adopted in this embodiment is basically the same as that in the first embodiment, the difference is that in the first embodiment, the control gate 22 and the shield gate 23 are connected together, while in this embodiment, the shield gate 23 and the semiconductor layer 10 are connected together, as shown in Figure 6 The contact hole 54b of the shield gate 23 is connected with the contact hole 53 of the substrate electrode, so that the shield gate 23 and the substrate electrode Sub are electrically connected together.

[0103] In this embodiment, the rest of the bidirectional power device is basically the same as that in the first embodiment, and the specific structure will not be described again.

[0104] In the first embodiment, the control gate 22 and the shield gate 23 are connected together, the shield gate 23 overlaps with the source region 31 and the drain region 32, and there is a parasitic capacitor. When the voltage of the control gate 22 and the shield gate 23 rises, the parasitic capacitor is charged, and the bidirectional power device is turned on; when the voltage of the control gate 22 and the shield gate 23 decreases, the parasitic capacitor is discharged, and the bidirectional power device is turned off. When the bidirectional power device switches at high speed, the charging and discharging time of the parasitic capacitor will reduce the switching frequency, and the charging and discharging of the parasitic capacitor will generate additional power consumption.

[0105] In the second embodiment, the shielding gate 23 and the semiconductor layer 10 are connected together. The voltage of the shielding gate 23 is fixed during the device switching process, which avoids the charging and discharging of parasitic capacitance caused by voltage changes in the shielding gate 23. This can improve the switching frequency of the bidirectional power device and reduce power consumption. In some applications that require bidirectional power devices to have not only the lowest possible resistance but also small parasitic capacitance, it can be used for high-speed switching.

[0106] Third Embodiment

[0107] This embodiment uses essentially the same technical solution as the first embodiment, except that in the first embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form a substrate electrode Sub. In this embodiment, however, the third contact 63 is formed on the second surface of the semiconductor layer 10, such as... Figure 7 As shown. Specifically, a bidirectional power device is formed on a substrate 1 with a high doping concentration, and then a metal layer is evaporated on the back side of the substrate 1 to form a third contact 63.

[0108] In the first embodiment, the gate, substrate electrode, first output electrode, and second output electrode of the bidirectional power device are all led out from the first surface of the semiconductor layer 10, which is suitable for chip-scale packaging (CSP).

[0109] In the third embodiment, the substrate electrode of the bidirectional power device is led out from the second surface of the semiconductor layer 10, which can not only adapt to traditional device packaging forms (such as SOP8, DIP8), but also increase the heat dissipation capability of the bidirectional power device.

[0110] In this embodiment, the rest of the bidirectional power device is basically the same as in the first embodiment, and the specific structure will not be described in detail.

[0111] Fourth embodiment

[0112] Figures 8-10 Cross-sectional and top views of the bidirectional power device according to the fourth embodiment of the present invention are shown respectively; wherein, Figure 8 for Figure 10 The cross-sectional view taken along line AA' in the top view shown. Figure 9 for Figure 10 The cross-sectional view taken along line BB' in the top view shown.

[0113] exist Figure 8 The bidirectional power device shown is a schematic diagram of a vertical structure containing only one cell. In actual products, the number of cells can be one or more. See also... Figures 8-10 ,

[0114] The bidirectional power device comprises a semiconductor layer 10, a trench 20 in the semiconductor layer 10, a gate dielectric layer 21 on the sidewall of the trench 20, a control gate 22 at the lower part of the trench 20, and a shielding gate 23 at the upper part of the trench 20. The control gate 22 and the shielding gate 23 are in contact with each other.

[0115] In this embodiment, the semiconductor layer 10 is, for example, a semiconductor substrate itself, an epitaxial layer formed on a semiconductor substrate, or a well region implanted in a semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14-3E16 cm -3 The semiconductor layer 10 is, for example, a silicon substrate, an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, and is of P-type. The semiconductor layer 10 has the same doping type as the silicon substrate.

[0116] The control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21.

[0117] Further, the bidirectional power device further comprises a shielding dielectric layer 25 on the sidewall of the trench 20, and the shielding gate 23 is separated from the semiconductor layer 10 by the shielding dielectric layer 25.

[0118] In this embodiment, the material of the gate dielectric layer 21 and the shielding dielectric layer 25 can be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the two can be the same or different.

[0119] The thickness of the gate dielectric layer 21 is 200-1000 angstroms, and the thickness of the shielding dielectric layer 25 is 1000-2500 angstroms, i.e. 0.1-0.25 um. The thickness of the shielding dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21. The length L2 of the shielding gate 23 is 0.4-0.8 um.

[0120] Further, a source region 31 and a drain region 32 of N-type are formed in the semiconductor layer 10 along the longitudinal direction, and the source region 31 and the drain region 32 can be interchanged. A channel region 40 adjacent to the control gate 22 is formed in the semiconductor layer 10.

[0121] In this embodiment, the semiconductor layer 10 is of a first doping type, the source region 31 and the drain region 32 are of a second doping type, and the channel region 40 is of the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

[0122] In the present embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22. The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the shielding gate 23 extending in the semiconductor layer 10, but is less than the sum L1+L2 of the length of the shielding gate 23 and the length of the control gate 22 extending in the semiconductor layer 10, i.e. L2

[0123] The shielding gate 23 is separated from the source region 31 and / or the drain region 32 by the shielding dielectric layer 25. The shielding gate depletes the charge of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, improving the withstand voltage characteristic of the device; when the bidirectional power device is on, the source region and the drain region provide a low impedance conduction path with the semiconductor layer. Thus, the thickness of the shielding dielectric layer, the doping concentration of the source region and the drain region, and the length of the shielding gate can be adjusted to achieve different threshold voltages.

[0124] Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

[0125] Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32. The first lead region 311 has the same doping type as the source region 31, and the doping concentration of the first lead region 311 is greater than that of the source region 31. The second lead region 321 has the same doping type as the drain region 32, and the doping concentration of the second lead region 321 is greater than that of the drain region 32.

[0126] Further, a third lead region 101 is formed in the semiconductor layer 10, which is close to the first surface of the semiconductor layer 10. The third lead region 101 has the same doping type as the semiconductor layer 10, and the doping concentration of the third lead region 101 is greater than that of the semiconductor layer 10.

[0127] Further, a covering dielectric layer 11 is formed on the first surface of the semiconductor layer 10, and a contact hole 50 is formed through the covering dielectric layer 11, which includes a first contact hole 51, a second contact hole 52, a third contact hole 53, and a fourth contact hole 54. The first contact hole 51 is located on the source region 31 and extends through the covering dielectric layer 11 to the source region 31, and the second contact hole is located on the drain region 32 and extends through the covering dielectric layer 11 to the drain region 32.

[0128] The third contact hole 53 extends through the covering dielectric layer 11 to the semiconductor layer 10 on both sides of the trench 20.

[0129] The fourth contact hole 54 is located on the trench 20 and extends through the covering medium layer 11 to the control gate 22 and / or shielding gate 23 in the trench 20.

[0130] In this embodiment, the covering dielectric layer 11 can be undoped silicon glass (USG) or boron-phosphorus doped silicon glass (BPSG).

[0131] A metal layer 60 is deposited on the overlay dielectric layer 11. The metal layer 60 fills the first contact holes 51 to the fourth contact holes 54 to form the first contact 61 to the fourth contact 64, respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1. The second contact 62 contacts the drain region 32 through the second contact hole 52 and the second lead region 321 to form the second output electrode S2. The third contact 63 contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. Figure 9 As shown, the fourth contact 64 contacts the control gate 22 and / or the shielding gate 23 via the fourth contact hole 54 to form a gate electrode.

[0132] In this embodiment, the material of the metal layer 60 can be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

[0133] Figure 8 In the original design, a single cell contains only three trenches, one source region, and one drain region. However, in actual products, there are more than one source region 31 and one drain region 32. Figure 8 Taking the example shown, the three trench structures are the first trench 20a, the second trench 20b, and the third trench 20c. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first output electrode S1; the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2; the third contact 63 leads the semiconductor layer 10 to form the substrate electrode Sub; and the fourth contact 64 leads the control gate 22 and the shielding gate 23 to the surface of the semiconductor layer 10 to form the gate electrode G. The control gate 22 and the shielding gate 23 are electrically connected together. The first trench 20a and the third trench 20c are symmetrically disposed outside the source region 31 and the drain region 32. The first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10, respectively, and are interchangeable.

[0134] When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and there is current only in the channel region of the second trench 20b between the source region 31 and the drain region 32. The current direction can be selected by connecting one of the output electrodes to the substrate electrode. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S1 to the second output electrode S2.

[0135] When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off. Since the control gate 22 and the shield gate 23 are electrically connected, the voltage applied to the shield gate 23 is low, while the voltage applied to the first output electrode S1 and the second output electrode S2 is high, creating a voltage difference between the source region 31, the drain region 32, and the shield gate 23. The shield gate 23 in the first trench 20a and the third trench 20c induces charges in the source region 31 and the source region 32 through the shielding dielectric layer 25. By adjusting the thickness and material of the shielding dielectric layer 25 and the impurity concentration in the source region 31 and the drain region 32, the source and drain regions can eventually be completely depleted, thereby improving the device's withstand voltage. At the same time, the increased impurity concentration in the source region 31 and the drain region 32 also greatly reduces the device's resistance.

[0136] Figure 11 Only a schematic diagram of two cell structures is shown. Multiple first contacts 61 are connected together to form a first output electrode S1, and multiple second contacts 62 are connected together to form a second output electrode S2, thereby improving the current capability of the device. Alternatively, for other types of bidirectional power devices, the current capability of the device can be improved by increasing the number of cells, i.e., by selecting two or more cell structures connected in parallel.

[0137] Fifth embodiment

[0138] This embodiment uses essentially the same technical solution as the fourth embodiment, except that in the fourth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form a substrate electrode Sub. In this embodiment, however, the third contact 63 is formed on the second surface of the semiconductor layer 10, such as... Figure 12 As shown. Specifically, a bidirectional power device is formed on a substrate 1 with a high doping concentration, and then a metal layer is evaporated on the back side of the substrate 1 to form a third contact 63. In the fourth embodiment, the gate, substrate electrode, first output electrode and second output electrode of the bidirectional power device are all led out from the first surface of the semiconductor layer 10, which is suitable for chip-scale packaging (CSP).

[0139] In the fifth embodiment, the substrate electrode of the bidirectional power device is led out from the second surface of the semiconductor layer 10, which can adapt to the traditional device packaging form (for example, SOP8, DIP8) and increase the heat dissipation capacity of the bidirectional power device.

[0140] In the embodiment, the rest of the bidirectional power device is basically the same as the fourth embodiment, and the specific structure will not be described again.

[0141] Sixth embodiment

[0142] Figures 13-15 The cross-sectional view and the top view of the bidirectional power device of the sixth embodiment of the present application are shown respectively; wherein, Figure 13 The cross-sectional view taken along the AA' line in the top view shown in Figure 15 The cross-sectional view taken along the BB' line in the top view shown in Figure 14 The cross-sectional view taken along the BB' line in the top view shown in Figure 15 The cross-sectional view taken along the AA' line in the top view shown in

[0143] The bidirectional power device shown in Figure 13 only contains a longitudinal structure diagram of one cell, and in the actual product, the number of cell structures can be one or more. Referring to Figures 13-15 , the bidirectional power device comprises a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on the side wall of the trench 20, a control gate 22 located at the lower part of the trench 20, and a voltage division dielectric layer 26 located at the upper part of the trench 20.

[0144] In the embodiment, the semiconductor layer 10 is, for example, a semiconductor substrate itself, or an epitaxial layer formed on a semiconductor substrate, or a well region implanted in a semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14-3E16 cm -3 The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, and the doping type is P type, and the doping type of the semiconductor layer 10 is the same as that of the silicon substrate. The semiconductor layer 10 has a first surface and a second surface opposite to each other.

[0145] The control gate 22 and the semiconductor layer 10 are separated by the gate dielectric layer 21.

[0146] In the embodiment, the materials of the gate dielectric layer 21 and the voltage division dielectric layer 26 can be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the two can be the same or different.

[0147] The thickness of the gate dielectric layer 21 is 200-1000 angstroms, and the length of the voltage division dielectric layer 26 is at least greater than 0.3 um.

[0148] Further, source region 31 and drain region 32 of N-type are formed in semiconductor layer 10, wherein source region 31 and drain region 32 can be interchangeable; and channel region 40 is formed in semiconductor layer 10 adjacent to control gate 22.

[0149] In the embodiment, the doping type of semiconductor layer 10 is the first doping type, the doping type of source region 31 and drain region 32 is the second doping type, and the doping type of channel region 40 is the first doping type or the second doping type, wherein the first doping type and the second doping type are opposite.

[0150] In the embodiment, source region 31 and drain region 32 extend from the first surface of semiconductor layer 10 to overlap with control gate 22. The length K of source region 31 and drain region 32 extending in semiconductor layer 10 is greater than the length L4 of voltage dividing dielectric layer 26, and less than the sum L1+L4 of the lengths of voltage dividing dielectric layer 26 and control gate 22 extending in semiconductor layer 10. Voltage dividing dielectric layer 26 makes control gate 22 away from source region 31 and drain region 32.

[0151] Voltage dividing dielectric layer has a higher dielectric constant and can withstand a higher electric field strength than semiconductor layer. With the increase of the thickness of voltage dividing dielectric layer, the high voltage applied on source region and drain region in the longitudinal direction is borne, and the withstand voltage characteristic of bidirectional power device is improved. Thus, different threshold voltages can be achieved by adjusting the thickness of voltage dividing dielectric layer and the doping concentration of source region and drain region.

[0152] Since channel region 40 is adjacent to control gate 22 located at the lower part of trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

[0153] Further, first lead region 311 and second lead region 321 are formed in source region 31 and drain region 32, respectively. The doping type of first lead region 311 is the same as that of source region 31, and the doping concentration of first lead region 311 is greater than that of source region 31. The doping type of second lead region 321 is the same as that of drain region 32, and the doping concentration of second lead region 321 is greater than that of drain region 32.

[0154] Further, third lead region 101 is formed in semiconductor layer 10, and third lead region 101 is close to the first surface of semiconductor layer 10. The doping type of third lead region 101 is the same as that of semiconductor layer 10, and the doping concentration of third lead region 101 is greater than that of semiconductor layer 10.

[0155] Further, a covering dielectric layer 11 is formed on the first surface of the semiconductor layer 10, and a contact hole 50 is formed through the covering dielectric layer 11, wherein the contact hole 50 includes a first contact hole 51, a second contact hole 52, a third contact hole 53 and a fourth contact hole 54. The first contact hole 51 is located on the source region 31 and extends through the covering dielectric layer 11 to the source region 31, and the second contact hole is located on the drain region 32 and extends through the covering dielectric layer 11 to the drain region 32.

[0156] The third contact hole 53 extends through the covering dielectric layer 11 to the semiconductor layer 10 on both sides of the trench 20.

[0157] The fourth contact hole 54 extends through the covering dielectric layer 11 to the control gate 22 in the trench 20.

[0158] In this embodiment, the covering dielectric layer 11 can be an undoped silicon glass (USG) and a boron and phosphorus doped silicon glass (BPSG).

[0159] A metal layer 60 is deposited on the covering dielectric layer 11, and the metal layer 60 fills the first to fourth contact holes 51-54 to form first to fourth contacts 61-64, respectively. The first contact 61 contacts the source region 31 through the first contact hole 51, the first lead region 311 and forms a first output electrode S1, the second contact 62 contacts the drain region 32 through the second contact hole 52, the second lead region 321 and forms a second output electrode S2, and the third contact 63 contacts the semiconductor layer 10 through the third contact hole 53, the third lead region 101 and forms a substrate electrode Sub. As shown in the figure, the fourth contact 64 contacts the control gate 22 through the fourth contact hole 54 and forms a gate electrode. Figure 14

[0160] In this embodiment, the material of the metal layer 60 can be titanium and titanium nitride, aluminum copper, aluminum silicon copper or aluminum silicon.

[0161] Figure 13 One cell only contains three trenches, one source region and one drain region, and in actual products, the number of source regions 31 and drain regions 32 is more than one. As shown in the figure, Figure 13

[0162] ​​The three trench structures are a first trench 20a, a second trench 20b and a third trench 20c. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form a first output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form a second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form a substrate electrode Sub, and the fourth contact 64 leads the control gate 22 to the surface of the semiconductor layer 10 to form a gate electrode G. The first trench 20a and the third trench 20c are symmetrically arranged outside the source region 31 and the drain region 32. The first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10, respectively, and can be interchangeable.

[0163] When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and the channel region in the second trench 20b has current flowing through it. By selecting one of the output electrodes to be connected to the substrate electrode, the direction of the current can be selected. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S1 to the second output electrode S2.

[0164] When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off, and a high voltage is applied to the first output electrode S1 and the second output electrode S2. The voltage dividing dielectric layer 26 in the first trench 20a and the third trench 20c can withstand a higher electric field strength than the semiconductor layer. As the length of the voltage dividing dielectric layer 26 increases, it can withstand the high voltage applied to the source region 31 and the drain region 32, thereby improving the withstand voltage characteristics of the bidirectional power device.

[0165] Figure 16 Only the schematic diagram of two cell structures is shown, and a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the current capacity of the device. Alternatively, for other types of bidirectional power devices, the current capacity of the device can be improved by increasing the number of cells, i.e. selecting two or more cell structures connected in parallel.

[0166] Seventh Embodiment

[0167] The seventh embodiment and the sixth embodiment use substantially the same technical solutions, except that in the sixth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and the third contact hole 53 and the third lead region 101 are used to contact the semiconductor layer 10 to form the substrate electrode Sub. In the present embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown in Figure 17As shown. Specifically, a bidirectional power device is formed on a substrate 1 with a high doping concentration, and then a metal layer is evaporated on the back side of the substrate 1 to form a third contact 63.

[0168] In the sixth embodiment, the gate, substrate electrode, first output electrode, and second output electrode of the bidirectional power device are all led out from the first surface of the semiconductor layer 10, which is suitable for chip-scale packaging (CSP).

[0169] In the seventh embodiment, the substrate electrode of the bidirectional power device is led out from the second surface of the semiconductor layer 10, which can not only adapt to traditional device packaging forms (such as SOP8, DIP8), but also increase the heat dissipation capability of the bidirectional power device.

[0170] In this embodiment, the rest of the bidirectional power device is basically the same as in the sixth embodiment, and the specific structure will not be described again.

[0171] Eighth embodiment

[0172] Figures 18-20 Cross-sectional and top views of the bidirectional power device according to the eighth embodiment of the present invention are shown respectively; wherein, Figure 18 for Figure 20 The cross-sectional view taken along line AA' in the top view shown. Figure 19 for Figure 20 The cross-sectional view taken along line BB' in the top view shown.

[0173] exist Figure 18 The bidirectional power device shown is a schematic diagram of a vertical structure containing only one cell. In actual products, the number of cells can be one or more. See also... Figures 18-20 The bidirectional power device includes a semiconductor layer 10, a trench 20 located within the semiconductor layer 10, a gate dielectric layer 21 located on the sidewall of the trench 20, and a control gate 22 located within the trench 20.

[0174] In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14 to 3E16 cm⁻¹. -3 The semiconductor layer 10 is, for example, a silicon substrate, an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, and is p-type doped. The semiconductor layer 10 has the same doping type as the silicon substrate. The semiconductor layer 10 has opposing first and second surfaces.

[0175] The control gate 22 extends from the first surface of the semiconductor layer 10 to the lower part of the trench 20, and the control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21.

[0176] In the embodiment, the material of the gate dielectric layer 21 and the voltage dividing dielectric layer 26 can be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the two can be the same or different. The width of the trench 20 is 0.1-0.6 um, and the length is 1.2-2.2 um.

[0177] Further, the source region 31 and the drain region 32 of N-type are formed in the semiconductor layer 10 along the longitudinal direction, and the source region 31 and the drain region 32 can be interchanged; and the channel region 40 of the control gate 22 adjacent to the lower part of the trench is formed in the semiconductor layer 10.

[0178] In the embodiment, the semiconductor layer 10 is of the first doping type, the source region 31 and the drain region 32 are of the second doping type, and the channel region 40 is of the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

[0179] In the embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22 of the lower part of the trench. The length of the source region 31 and the drain region 32 extending in the semiconductor layer 10 does not exceed the length of the trench 20 extending in the semiconductor layer 10. The length of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is 0.5-1.5 um.

[0180] The source region 31 and the drain region 32 on both sides of the trench 20 extend in the semiconductor layer for a long length, overlap with the control gate 22 of the lower part of the trench, and can bear the high voltage applied to the source region 31 and the drain region 32 in the longitudinal direction when the device is off, thereby improving the withstand voltage characteristics of the bidirectional power device.

[0181] Since the channel region 40 is adjacent to the control gate 22 of the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

[0182] Further, different threshold voltages can be achieved by adjusting the thickness of the gate dielectric layer 21 and the doping concentration of the channel region 40.

[0183] Further, the first lead region 311 and the second lead region 321 are formed in the source region 31 and the drain region 32. The doping type of the first lead region 311 is the same as that of the source region 31, and the doping concentration of the first lead region 311 is greater than that of the source region 31. The doping type of the second lead region 321 is the same as that of the drain region 32, and the doping concentration of the second lead region 321 is greater than that of the drain region 32.

[0184] Further, a third lead region 101 is formed in the semiconductor layer 10, the third lead region 101 is close to the first surface of the semiconductor layer 10, wherein the doping type of the third lead region 101 is the same as the doping type of the semiconductor layer 10, and the doping concentration of the third lead region 101 is greater than the doping concentration of the semiconductor layer 10.

[0185] Further, a covering dielectric layer 11 is formed on the first surface of the semiconductor layer 10, and a contact hole 50 is formed through the covering dielectric layer 11, the contact hole 50 includes a first contact hole 51, a second contact hole 52, a third contact hole 53 and a fourth contact hole 54. The first contact hole 51 is located on the source region 31 and extends through the covering dielectric layer 11 to the source region 31, and the second contact hole is located on the drain region 32 and extends through the covering dielectric layer 11 to the drain region 32.

[0186] The third contact hole 53 extends through the covering dielectric layer 11 to the semiconductor layer 10 on both sides of the trench 20.

[0187] The fourth contact hole 54 is located on the trench 20 and extends through the covering dielectric layer 11 to the control gate 22 in the trench 20.

[0188] In this embodiment, the covering dielectric layer 11 can be undoped silicon glass (USG) and boron and phosphorus doped silicon glass (BPSG).

[0189] A metal layer 60 is deposited on the covering dielectric layer 11, the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form a first contact 61 to a fourth contact 64. The first contact 61 contacts the source region 31 through the first contact hole 51, the first lead region 311 and the first output electrode S1 is formed, the second contact 62 contacts the drain region 32 through the second contact hole 52, the second lead region 321 and the second output electrode S2 is formed, and the third contact 63 contacts the semiconductor layer 10 through the third contact hole 53, the third lead region 101 and the substrate electrode Sub is formed. As shown in Figure 19 The fourth contact 64 contacts the control gate 22 through the fourth contact hole 54 to form the gate electrode.

[0190] In this embodiment, the material of the metal layer 60 can be titanium and titanium nitride, aluminum copper, aluminum silicon copper or aluminum silicon.

[0191] Figure 18 One cell only contains three trenches, one source region and one drain region, and in actual products, the number of source regions 31 and drain regions 32 is more than one. As shown in the figure, Figure 18 As shown in the figure,

[0192] The three grooves are a first groove 20a, a second groove 20b and a third groove 20c. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form a first output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form a second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form a substrate electrode Sub, and the fourth contact 64 leads the control gate 22 to the surface of the semiconductor layer 10 to form a gate electrode G. The first groove 20a and the third groove 20c are symmetrically arranged outside the source region 31 and the drain region 32. The first output electrode S1 and the second output electrode S2 are respectively formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10, and the two can be interchanged.

[0193] When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and the channel region in the second groove 20b has current flowing through it. By selecting one of the output electrodes to be connected to the substrate electrode, the direction of the current can be selected. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S1 to the second output electrode S2.

[0194] When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off, and a high voltage is applied to the first output electrode S1 and the second output electrode S2. As the length of the source region 31 and the drain region 32 extending in the semiconductor increases, the source region 31 and the drain region 32 bear the high voltage applied to them, improving the withstand voltage characteristics of the bidirectional power device.

[0195] Figure 21 Only the schematic diagram of two cell structures is shown, and a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, to improve the current capacity of the device. Alternatively, for other types of bidirectional power devices, the current capacity of the device can be improved by increasing the number of cells, i.e. selecting two or more cell structures connected in parallel.

[0196] Ninth embodiment

[0197] Compared with the first embodiment, the fourth embodiment, the sixth embodiment and the eighth embodiment, the present embodiment further comprises a wiring layer 70 and a plurality of metal solder balls 80 located on the wiring layer 70.

[0198] Because the pitch of the grooves 20 is very small, the gate electrode led out by the groove structure is relatively narrow and small, resulting in a large parasitic resistance. In order to reduce the parasitic resistance, a wiring layer 70 is added above the bidirectional power device provided in the first embodiment, the fourth embodiment, the sixth embodiment and the eighth embodiment.

[0199] like Figures 22-26 As shown, the wiring layer 70 is located on the surface of the bidirectional power device and is used to lead out the first output electrode S1, the second output electrode S2, the substrate electrode Sub and the gate electrode G formed by the first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 to the surface of the bidirectional power device.

[0200] The first contact 61, the second contact 62, the third contact 63, and the fourth contact 64 are located in the first metal layer M1, and the wiring layer 70 is located in the second metal layer M2. The first metal layer M1 and the second metal layer M2 are isolated by a covering dielectric layer 11. The wiring layer 70 is electrically connected to the first contact 61, the second contact 62, the third contact 63, and the fourth contact 64 through multiple conductive vias 90. The wiring layer 70 includes a first wiring 71, a second wiring 72, a third wiring 73, and a fourth wiring 74 (not shown in the figure), wherein the first wiring 71 is electrically connected to the first contact 61; the second wiring 72 is electrically connected to the second contact 62; the third wiring 73 is electrically connected to the third contact 63; and the fourth wiring 74 is electrically connected to the fourth contact 64.

[0201] In this embodiment, the wiring layer 70 uses wider metal lines to reduce the parasitic resistance of the metal layer.

[0202] Multiple metal solder balls 80 are located on the wiring layer 70 and are electrically connected to the first output electrode S1, the second output electrode S2, the substrate electrode Sub, and the gate electrode G through the wiring layer 70. The metal solder balls 80 include a metal solder ball 81 electrically connected to the first output electrode S1, a metal solder ball 82 electrically connected to the second output electrode S2, a metal solder ball 83 electrically connected to the substrate electrode Sub, and a metal solder ball 84 (not shown in the figure) electrically connected to the gate electrode G.

[0203] In this embodiment, a ball-mounting process is used to form multiple metal solder balls 80 on the wiring layer to complete chip-level packaging. Metal solder ball 81 is the pad pin for connecting the first output electrode S1 to the outside, metal solder ball 82 is the pad pin for connecting the second output electrode S2 to the outside, metal solder ball 83 is the pad pin for connecting the substrate electrode to the outside, and metal solder ball 84 is the pad pin for connecting the gate electrode to the outside.

[0204] In a preferred embodiment, an electroplated metal layer M3 is further formed between the metal solder ball 80 and the wiring layer 70, making the bond between the metal solder ball 80 and the wiring layer 70 stronger.

[0205] Because the first output electrode S1 and the second output electrode S2 need to carry a large current, they are equipped with a relatively large number of metal solder balls 81 and 82, such as... Figure 27As shown, the current distribution between the bidirectional power device and the external system can be increased.

[0206] The ninth embodiment omits the wire bonding of the conventional package, reduces the parasitic inductance and parasitic resistance of the package, and reduces the package resistance of the bidirectional power device due to the use of the ball mounting process. The heat dissipation is easier due to the absence of the encapsulation of the plastic sealing material, the power consumption is reduced, and the reliability and safety of the bidirectional power device are improved.

[0207] The tenth embodiment

[0208] The eighth embodiment and the present embodiment use basically the same technical solution, and the difference lies in that, in the eighth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10 and contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. In the present embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown. Figure 28 Specifically, the bidirectional power device is formed on the substrate 1 with a higher doping concentration, and then the third contact 63 is formed by evaporating a metal layer on the back surface of the substrate 1.

[0209] In the eighth embodiment, the gate, the substrate electrode, the first output electrode, and the second output electrode of the bidirectional power device are all led out from the first surface of the semiconductor layer 10, which is suitable for the chip scale package (CSP).

[0210] In the tenth embodiment, the substrate electrode of the bidirectional power device is led out from the second surface of the semiconductor layer 10, which can adapt to the conventional device packaging form (for example, SOP8, DIP8) and increase the heat dissipation capacity of the bidirectional power device.

[0211] In the present embodiment, the rest of the bidirectional power device is basically the same as the eighth embodiment, and the specific structure is not described again.

[0212] The embodiments according to the present application are described above, and these embodiments do not describe all the details, nor limit the application to the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their entire scope and equivalents.

Claims

1. A bidirectional power device, characterized in that, include: Semiconductor layer; Trench located in the semiconductor layer; The grid dielectric layer is located on the sidewall of the trench; The control gate is located at the bottom of the trench; as well as The channel region located in the semiconductor layer and adjacent to the control gate; The control gate and the semiconductor layer are separated by the gate dielectric layer. A covering dielectric layer is located on the first surface of the semiconductor layer; A fourth contact hole is located on the trench and extends through the covering medium layer into the control gate in the trench.

2. The bidirectional power device according to claim 1, characterized in that, Also includes: A shielding grid located at the top of the trench.

3. The bidirectional power device according to claim 2, characterized in that, Also includes: An isolation layer located between the control gate and the shielding gate.

4. The bidirectional power device according to claim 3, characterized in that, The length of the shielding grid is 0.6~1.2um.

5. The bidirectional power device according to claim 2, characterized in that, The control gate and the shielding gate are in contact with each other.

6. The bidirectional power device according to claim 5, characterized in that, The length of the shielding grid is 0.4~0.8um.

7. The bidirectional power device according to any one of claims 2-6, characterized in that, Also includes: A shielding dielectric layer is located on the sidewall of the trench, and the shielding gate is separated from the semiconductor layer by the shielding dielectric layer.

8. The bidirectional power device according to claim 7, characterized in that, The thickness of the shielding medium layer is 0.1~0.25um.

9. The bidirectional power device according to claim 7, characterized in that, The thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.

10. The bidirectional power device according to claim 2, characterized in that, The width of the control gate is greater than the width of the shielding gate.

11. The bidirectional power device according to claim 7, characterized in that, Also includes: The source and drain regions are located in the semiconductor layer and adjacent to the shielding gate, and the source and drain regions extend from the first surface of the semiconductor layer to overlap with the control gate.

12. The bidirectional power device according to claim 3, characterized in that, The lengths of the source region and the drain region are greater than the sum of the lengths of the shielding gate and the isolation layer, but less than the sum of the lengths of the shielding gate, the isolation layer, and the control gate.

13. The bidirectional power device according to claim 11, characterized in that, The lengths of the source region and the drain region are greater than the length of the shielding gate, but less than the sum of the lengths of the shielding gate and the control gate.

14. The bidirectional power device according to claim 1, characterized in that, Also includes: The pressure-dividing medium layer located on the upper part of the trench.

15. The bidirectional power device according to claim 14, characterized in that, Also includes: The source and drain regions are located in the semiconductor layer and adjacent to the voltage divider dielectric layer, and the source and drain regions extend from the first surface of the semiconductor layer to overlap with the control gate.

16. The bidirectional power device according to claim 14, characterized in that, The length of the pressure-distributing medium layer is greater than 0.3 μm.

17. The bidirectional power device according to claim 14, characterized in that, The lengths of the source and drain regions are greater than the length of the voltage divider layer, but less than the lengths of the voltage divider layer and the control gate.

18. The bidirectional power device according to claim 1, characterized in that, The control gate extends from the first surface of the semiconductor layer to the lower part of the trench.

19. The bidirectional power device according to claim 18, characterized in that, Also includes: The source and drain regions are located in the semiconductor layer and adjacent to the control gate, and the source and drain regions extend from the first surface of the semiconductor layer to overlap with the control gate at the bottom of the trench.

20. The bidirectional power device according to claim 19, characterized in that, The source and drain regions extend in the semiconductor layer for a length of 0.5~1.5µm.

21. The bidirectional power device according to claim 1, characterized in that, The trench has a length of 1.2~2.2 μm and a width of 0.1~0.6 μm.

22. The bidirectional power device according to any one of claims 11, 15, and 19, characterized in that, The semiconductor layer is doped with a first doping type, the source and drain regions are doped with a second doping type, and the channel region is doped with either the first or second doping type, with the first and second doping types being opposite.

23. The bidirectional power device according to claim 1, characterized in that, The semiconductor layer is selected from one of the following: the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.

24. The bidirectional power device according to claim 22, characterized in that, Also includes: The first contact is made in contact with the source region to form the first output electrode; The second contact is in contact with the drain region to form the second output electrode; The third contact is in contact with the semiconductor layer to form a substrate electrode; The fourth contact is made into contact with the control gate to form a gate electrode.

25. The bidirectional power device according to claim 24, characterized in that, Also includes: A first lead region is located within the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region; The first contact hole extends through the covering dielectric layer to the source region; The first contact is in contact with the source region through the first contact hole and the first lead area.

26. The bidirectional power device according to claim 25, characterized in that, Also includes: The second lead region is located within the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region; The second contact hole extends through the covering medium layer to the drain area; The second contact is in contact with the drain area through the second contact hole and the second lead area.

27. The bidirectional power device according to claim 26, characterized in that, Also includes: The third lead region is located within the semiconductor layer and close to the first surface of the semiconductor layer, wherein the doping concentration of the third lead region is greater than the doping concentration of the semiconductor layer; The third contact hole extends through the covering dielectric layer to the semiconductor layer; The third contact is in contact with the semiconductor layer through the third contact hole and the third lead area.

28. The bidirectional power device according to claim 26, characterized in that, The third contact is located on the second surface of the semiconductor layer.

29. The bidirectional power device according to claim 24, characterized in that, Also includes: The wiring layer includes a first wiring layer to a fourth wiring layer, which are electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through multiple conductive holes.

30. The bidirectional power device according to claim 29, characterized in that, Also includes: Multiple metal solder balls are located on the wiring layer and are electrically connected to the first output electrode, the second output electrode, the substrate electrode, and the gate electrode through the wiring layer.

31. The bidirectional power device according to claim 24, characterized in that, When the bidirectional power device includes a shielding gate located on the control gate, the fourth contact is also electrically connected to the shielding gate.

32. The bidirectional power device according to claim 31, characterized in that, The shielding gate is electrically connected to the semiconductor layer or the control gate.

33. The bidirectional power device according to any one of claims 11, 15, and 19, characterized in that, When the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to achieve bidirectional selection of the current direction.

34. The bidirectional power device according to claim 33, characterized in that, When the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; When the substrate electrode is electrically connected to the second output electrode, current flows from the first output electrode to the second output electrode.

35. A bidirectional power device, characterized in that, It includes multiple cell structures, wherein the cell structure is a bidirectional power device as described in any one of claims 1-34; The source regions in multiple cell structures are electrically connected together, and the drain regions in multiple cell structures are electrically connected together.

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