Tunable resonator and method of manufacturing the same

Abstract

An adjustable resonator and its manufacturing method are disclosed. The resonator includes: a resonant cavity in a substrate, comprising at least a central first resonant cavity and a peripheral second resonant cavity; a first stacked structure on the first resonant cavity, comprising a lower electrode first portion, a piezoelectric layer first portion, and an upper electrode first portion in sequence; a second stacked structure on the second resonant cavity, comprising a lower electrode second portion, a piezoelectric layer second portion, and an upper electrode second portion in sequence; and a first insulating layer on the substrate, located between the lower electrode first portion and the lower electrode second portion. According to the adjustable resonator and its manufacturing method of the present invention, adding a secondary resonator around the main resonator to actively adjust the resonance state is beneficial for improving device integration and efficiency.

Description

Technical Field

[0001] This invention relates to an adjustable resonator and its manufacturing method, particularly an adjustable resonator and its manufacturing method. Background Technology

[0002] In wireless communication, radio frequency (RF) filters act as intermediaries for filtering signals of specific frequencies, reducing signal interference across different frequency bands. In wireless transceivers, they perform functions such as image cancellation, parasitic filtering, and channel selection. With the deployment of 4G LTE networks and market growth, RF front-end design is trending towards miniaturization, low power consumption, and integration, leading to increasingly higher market demands for filtering performance. Film Bulk Acoustic Resonators (FBARs, also known as Bulk Acoustic Waves or BAWs) have become widely used and are considered essential components in the RF communication field due to their small size, high operating frequency, low power consumption, high quality factor (Q value), direct output frequency signal, and compatibility with CMOS processes.

[0003] FBARs are thin-film devices with a sandwich structure of electrodes-piezoelectric films-electrodes fabricated on a substrate. FBAR structures include cavity type, SMR type, and back-etched type. Cavity type FBARs offer higher Q values, lower losses, and higher electromechanical coupling coefficients compared to SMR type FBARs; compared to back-etched type FBARs, they do not require the removal of a large substrate area, resulting in higher mechanical strength. Therefore, cavity type FBARs are the preferred choice for integration into CMOS devices.

[0004] Traditionally, once a resonant cavity is fabricated in a substrate, the resonant frequency of the device is determined. When it needs to be applied to different frequencies or a wide frequency band, in order to improve the filtering accuracy, a large number of resonant cavities of different sizes must be fabricated on the same substrate. This unnecessarily increases the size of the system, and while some resonators are working, most of the other resonators are idle, resulting in low system utilization. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide an adjustable resonator that overcomes the above-mentioned technical obstacles and its fabrication method.

[0006] This invention provides an adjustable resonator, comprising:

[0007] The resonant cavity, in the substrate, includes at least a central first resonant cavity and a peripheral second resonant cavity;

[0008] The first stacked structure, on the first resonant cavity, sequentially includes a lower electrode first part, a piezoelectric layer first part, and an upper electrode first part;

[0009] The second stacked structure, on the second resonant cavity, sequentially includes a lower electrode second part, a piezoelectric layer second part, and an upper electrode second part;

[0010] A first insulating layer is located on the substrate between the first portion of the lower electrode and the second portion of the lower electrode.

[0011] It further includes a second insulating layer on the first portion and the second portion of the piezoelectric layer, located between the first portion and the second portion of the upper electrode; preferably, the first portion and the second portion of the piezoelectric layer are connected or separated by the second insulating layer.

[0012] In the plan view, the first resonant cavity, the first part of the lower electrode, and the first part of the upper electrode are polygonal, circular, or elliptical. Preferably, the top dimension of the first resonant cavity is larger than the dimension of the first part of the lower electrode or the first part of the upper electrode. Optionally, the top dimension of the second resonant cavity is larger than the dimension of the second part of the lower electrode or the second part of the upper electrode. Preferably, the edges of the first part of the lower electrode and the first part of the upper electrode are aligned, and the edges of the second part of the lower electrode and the second part of the upper electrode are aligned.

[0013] Specifically, a signal different from that of the first stacked structure is applied to the second stacked structure to adjust the resonant state of the resonator, wherein the resonant state includes at least one or a combination of amplitude, frequency, and phase.

[0014] The substrate material is Si, SOI, Ge, GeOI, or a compound semiconductor. Optionally, the materials of the first and second piezoelectric layers are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium lead barium niobate), or PT (lead titanate), and more preferably, the piezoelectric material is doped with rare earth elements. Optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, or boron nitride. Optionally, the material of any one of the first, second, first, and second lower electrodes is a metallic element or alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or conductive oxides or conductive nitrides of these metals, or any combination of the above materials.

[0015] The present invention also provides a method for manufacturing an adjustable resonator, comprising:

[0016] A sacrificial layer is formed in the substrate, including a central first sacrificial layer pattern and a peripheral second sacrificial layer pattern;

[0017] A lower electrode layer is formed on the sacrificial layer, including a first portion of the lower electrode on the first sacrificial layer pattern and a second portion of the lower electrode on the second sacrificial layer pattern;

[0018] A first insulating layer is formed between the first part of the lower electrode and the second part of the lower electrode;

[0019] A piezoelectric layer is formed on the first insulating layer and the lower electrode layer, including at least a first portion of the piezoelectric layer on the first sacrificial layer pattern and a second portion of the piezoelectric layer on the second sacrificial layer pattern;

[0020] An upper electrode layer is formed on the piezoelectric layer, including a first upper electrode portion on a first portion of the piezoelectric layer and a second upper electrode portion on a second portion of the piezoelectric layer;

[0021] The sacrificial layer is removed, leaving a resonant cavity in the substrate, including a central first resonant cavity and a peripheral second resonant cavity.

[0022] After forming the upper electrode layer, the process further includes forming a second insulating layer at least between the first portion and the second portion of the upper electrode; preferably, the first portion and the second portion of the piezoelectric layer are connected or separated by the second insulating layer.

[0023] In the plan view, the first resonant cavity, the first part of the lower electrode, and the first part of the upper electrode are polygonal, circular, or elliptical. Preferably, the top dimension of the first resonant cavity is larger than the dimension of the first part of the lower electrode or the first part of the upper electrode. Optionally, the top dimension of the second resonant cavity is larger than the dimension of the second part of the lower electrode or the second part of the upper electrode. Preferably, the edges of the first part of the lower electrode and the first part of the upper electrode are aligned, and the edges of the second part of the lower electrode and the second part of the upper electrode are aligned.

[0024] The substrate material is Si, SOI, Ge, GeOI, or a compound semiconductor. Optionally, the materials of the first and second piezoelectric layers are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium lead barium niobate), or PT (lead titanate), and more preferably, the piezoelectric material is doped with rare earth elements. Optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, or boron nitride. Optionally, the material of any one of the first, second, first, and second lower electrode portions is a metallic element or alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, and Mg, or conductive oxides or conductive nitrides of these metals, or any combination of the above materials. Optionally, the sacrificial layer material is an oxide, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide (USG), or porous silicon oxide.

[0025] After forming the upper electrode layer and before removing the sacrificial layer, the process further includes etching a piezoelectric layer between the first portion and the second portion of the upper electrode to form an opening that exposes the substrate, and forming a second insulating layer on the upper electrode layer and on the bottom and sidewalls of the opening.

[0026] According to the adjustable resonator and its manufacturing method of the present invention, an auxiliary resonator is added around the main resonator to actively adjust the resonance state, which is beneficial to improving the device integration and efficiency.

[0027] The objectives described herein, and other objectives not listed herein, are satisfied within the scope of the independent claims of this application. Embodiments of the invention are defined in the independent claims, and specific features are defined in the dependent claims. Attached Figure Description

[0028] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0029] Figure 1 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0030] Figure 2 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0031] Figure 3 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0032] Figure 4 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0033] Figure 5 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0034] Figure 6 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0035] Figure 7 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0036] Figure 8 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown;

[0037] Figure 9 A cross-sectional view showing the resonator manufacturing process according to an embodiment of the present invention is shown; and

[0038] Figure 10 A plan view of the top electrode of a resonator according to an embodiment of the present invention is shown. Detailed Implementation

[0039] The features and technical effects of the present invention will be described in detail below with reference to the accompanying drawings and illustrative embodiments, disclosing a resonator and its fabrication method that are beneficial to improving device integration and efficiency. It should be noted that similar reference numerals denote similar structures, and the terms "first," "second," "upper," "lower," etc., used in this application can be used to modify various device structures. Unless otherwise specified, these modifications do not imply the spatial, sequential, or hierarchical relationship of the modified device structures.

[0040] like Figure 1 As shown, a sacrificial layer 2 is formed in substrate 1. Substrate 1 is provided, and its material can be bulk Si or silicon-on-insulator (SOI), or bulk Ge, GeOI to be compatible with CMOS processes and integrated with other digital and analog circuits. It can also be a compound semiconductor such as GaN, GaAs, SiC, InP, GaP, etc., used in MEMS, optoelectronic devices, and power devices. More preferably, substrate 1 is a single-crystal material. Multiple cavities are formed by etching substrate 1. Figure 1 (Not shown in the image), and a sacrificial layer 2 is deposited to fill it. The etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching with fluorocarbon-based etching gases, or wet etching with TMAH. The deposition process is a low-temperature process such as LPCVD, APCVD, or PECVD (deposition temperature below 500 degrees Celsius, preferably 100 to 400 degrees Celsius). The sacrificial layer 2 is made of a silicon oxide-based material, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide, etc. This reduces residual thermal stress in the substrate 1 and facilitates faster subsequent etching removal, saving time and costs. Figure 1 As shown, the sacrificial layer 2 comprises at least two parts: a first part 2a for filling the main resonant cavity and a second part 2b for filling the secondary resonant cavity surrounding the main resonant cavity. Preferably, the sacrificial layer 2 is processed using a CMP planarization process until the surface of the substrate 1 is exposed. In a preferred embodiment of the present invention, the projection of the central part of the cavity formed by etching the substrate 1, i.e., the main resonant cavity, in a plan view is a polygon (e.g., quadrilateral, pentagon, hexagon, octagon, etc.), a circle, an ellipse, etc., while the projection of the peripheral part, i.e., the secondary resonant cavity, in a plan view is a similar shape concentric with the main resonant cavity. Therefore, a ring-shaped portion of the substrate 1S is sandwiched between the main and secondary resonant cavities as a subsequent mechanical support or isolation structure, and the first part 2a and the second part 2b of the filled sacrificial layer also have corresponding morphologies.

[0041] like Figure 2As shown, a patterned lower electrode 3 is formed on substrate 1. A conductive material layer is formed using processes such as magnetron sputtering, thermal evaporation, and MOCVD. The material is, for example, elemental or alloy metals such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, and Mg, or conductive oxides or conductive nitrides of these metals, or any combination thereof. Preferably, before forming the conductive material layer, a seed layer (not shown) is further formed on substrate 1 and sacrificial layer 2 to improve the crystal orientation of the electrode layer and the upper functional layer. In a preferred embodiment of the invention, the seed layer is AlN, HfN, HfAlN, TiN, TaN, etc., and preferably also serves as a barrier layer to prevent the lower electrode metal material from migrating downwards, thus avoiding affecting the interface state between the top of the resonant cavity and the lower film layer. Subsequently, a photolithography-etching process is used, such as spin-coating photoresist, exposure and development to form a photoresist pattern, and using the photoresist pattern as a mask to etch the conductive material layer to pattern the conductive material layer and form... Figure 2 The lower electrode 3 is shown. The lower electrode 3 includes at least a first portion 3a located at the center and a second portion 3b located at the periphery. The projection of the first portion 3a of the lower electrode, the first portion 2a of the sacrificial layer, and the main resonant cavity in a plan view is a polygon (e.g., quadrilateral, pentagon, hexagon, octagon, etc.), a circle, an ellipse, etc., while the second portion 3b is a ring structure concentric with the first portion 3a, with a gap between the two. It is worth noting that in order to ensure sufficient insulation between the lower electrodes of the main resonator and the sub-resonator used for adjustment, the distance between the peripheral second portion 3b and the central first portion 3a must be at least greater than the width of the top of the substrate support structure 1S sandwiched between the main and sub-resonant cavities. Preferably, the edge of the first portion 3a of the lower electrode is recessed inward from the edge of the first portion 2a of the sacrificial layer by 0.1-10 micrometers, preferably 0.05-5 micrometers, and most preferably 1-3 micrometers. Further or similarly, the edge of the second portion 3b of the lower electrode is also recessed inward by the same distance from the edge of the second portion 2b of the sacrificial layer. After forming the patterned lower electrode 3, the photoresist pattern is removed by wet etching.

[0042] like Figure 3 As shown, an insulating layer 4 is filled between the lower electrode patterns. For example, processes such as LPCVD, PECVD, spin coating, spraying, and screen printing are used to fill the space between the first portion 3a and the second portion 3b of the lower electrode layer with insulating dielectric material, thereby forming a ring-shaped insulating layer pattern 4. The insulating layer 4 is made of a different material than the sacrificial layer 2 to avoid excessive erosion during the subsequent removal of the sacrificial layer 2 to form the resonant cavity. In a preferred embodiment of the invention, the insulating layer 4 is made of a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, etc. Preferably, a planarization process such as etch-back or CMP is used to treat the insulating layer until the lower electrode patterns 3a and 3b are exposed.

[0043] like Figure 4 As shown, a piezoelectric layer 5 is formed on the lower electrode patterns 3a and 3b and the insulating layer 4. For example, the piezoelectric layer 5 is formed using processes such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, and thermal evaporation. Preferably, the material of the piezoelectric layer 5 is different from that of the insulating layer 4. In a preferred embodiment of the present invention, the piezoelectric layer 5 is made of piezoelectric ceramic materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium lead barium niobate), and PT (lead titanate). Preferably, the piezoelectric layer 5 is doped with rare earth elements, such as any one or a combination of scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) to improve the piezoelectric coefficient. In a preferred embodiment of the present invention, the piezoelectric layer 5 is doped with Sc, or a mixture of Sc and Yb, or a mixture of Sc, Yb, and Sm. Subsequently, an upper conductive material layer 6 is formed on the piezoelectric layer 5. The fabrication process and materials of the conductive material layer 6 are the same as those of the lower electrode layer 3, and will not be described again here.

[0044] like Figure 5 As shown, the conductive material layer 6 is patterned to form a first upper electrode portion 6a and a second upper electrode portion 6b. Photoresist is spin-coated, and a photoresist pattern is formed through an exposure and development process. Using the photoresist pattern as a mask, the conductive material layer 6 is etched to form the first upper electrode portion 6a at the center and the annular second upper electrode portion 6b at the periphery. Preferably, the edge of the first upper electrode portion 6a is aligned with the edge of the first lower electrode portion 3a, and the edge of the second upper electrode portion 6b is aligned with the edge of the second lower electrode portion 3b, thereby leaving a gap between the first portion 6a and the second portion 6b, which is aligned with the insulating layer 4 between the lower electrode patterns 3a and 3b. Subsequently, a wet etching process is preferably used to remove the photoresist pattern.

[0045] like Figure 6 As shown, a second insulating layer 7 is formed on the piezoelectric layer 5 and the upper electrode patterns 6a / 6b. The material and process of the second insulating layer 7 are the same as or similar to those of the insulating layer 4, and will not be described in detail here.

[0046] like Figure 7As shown, the sacrificial layer pattern 2 is removed, leaving resonant cavities in the substrate 1. The sacrificial layer pattern is removed by applying a wet etchant through release holes (not shown) located around the device periphery. For silicon oxide-based materials, an HF-based etchant such as dHF (diluted HF) or dBOE (a slow-release etchant, a mixture of HF and NH4F) is used to remove the sacrificial layer pattern 2, leaving multiple resonant cavities. Each resonant cavity includes at least a central first portion 1c and a peripheral annular second portion 1c'. As previously shown, the width of the insulating layer 4 is greater than the top width of the support structure 1S, and the widths of the lower electrode first portion 3a and second portion 3b are smaller than the sacrificial layer patterns 2a and 2b. Therefore, the width of the remaining main resonant cavity 1c is greater than that of the lower electrode first portion 3a, and the width of the secondary resonant cavity 1c' is greater than that of the lower electrode second portion 3b.

[0047] like Figure 8 As shown, the second insulating layer 7 is processed using planarization processes such as etching back and CMP until the upper electrode patterns 6a and 6b are exposed. The final resonator structure is as follows. Figure 8 As shown, the device includes a substrate 1, a first resonant cavity 1c and a second resonant cavity 1c' located within the substrate 1. The first lower electrode 3a, piezoelectric layer 5, and first upper electrode 6a above the first resonant cavity 1c constitute the main resonator, while the second lower electrode 3b, piezoelectric layer 5, and second upper electrode 6b above the second resonant cavity 1c' constitute the secondary resonator. The distribution morphology of the upper electrodes 6a / 6b and the second insulating layer 7 is as follows. Figure 10 As shown, the lower electrodes 3a / 3b and the insulating layer pattern 4 are identical or conformally similar, all being concentric polygonal, circular, or elliptical structures. That is, a second insulating layer 7 is sandwiched between the central part of the upper electrode (i.e., the first part 6a) and the peripheral second part 6b. The second part 6b has at least one notch to accommodate the lead-out portion of the first part 6a, which protrudes under the second insulating layer 7 to achieve external electrical connection. During device operation, by applying a signal different from that of the main resonator to the electrodes (3b, 6b), such as at least one difference in amplitude, frequency, or phase, the sub-resonator surrounding the main resonator vibrates differently from the main resonator. The superposition of these two mechanical waves with different states alters the final signal waveform. Thus, the vibration state of the sub-resonator can be flexibly changed in real time by controlling the input waveform, thereby affecting the overall resonator operation. This allows for adjustment of the frequency response of the entire resonator system when needed, which is beneficial for saving chip area, increasing integration density, reducing product costs, and improving device utilization.

[0048] In another preferred embodiment of the invention, such as Figure 9As shown, the piezoelectric layer 5 is no longer connected as a single unit, but rather a support structure 1S extending from the second insulating layer 7 directly to the surface of the substrate 1. This improves the insulation isolation between the electrodes of the main resonator and the secondary resonator, preventing lateral crosstalk between the upper and lower electrodes of different resonators. Its manufacturing process is similar to... Figures 1 to 8 The two are basically the same, the difference being... Figure 5 In the process steps shown, after etching the patterned upper electrodes 6a and 6b, the piezoelectric layer 5 is further etched using the photoresist pattern or the upper electrode pattern as a mask until the support structure 1S on the surface of the substrate 1 is exposed. Figure 6 In the process steps shown, the second insulating layer 7 is filled using PECVD, HDPCVD, and magnetron sputtering processes with good step coverage. The final device structure is similar to... Figure 8 Similar to the example shown, the difference is that the second insulating layer 7 is not only sandwiched between the first part 6a and the second part 6b of the upper electrode, but also penetrates through the piezoelectric layer 5 to the substrate surface, and is sandwiched between the first part 3a and the second part 3b of the lower electrode.

[0049] According to the adjustable resonator and its manufacturing method of the present invention, an auxiliary resonator is added around the main resonator to actively adjust the resonance state, which is beneficial to improving the device integration and efficiency.

[0050] Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize that various suitable changes and equivalents to the device structure can be made without departing from the scope of the invention. Furthermore, many modifications that may be suitable for particular situations or materials can be made from the disclosed teachings without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the specific embodiments disclosed as the best mode for carrying out the invention, but the disclosed device structures and methods of manufacturing thereof will include all embodiments falling within the scope of the invention.

Claims

1. A resonator, comprising: The resonant cavity, in the substrate, includes at least a central first resonant cavity and a peripheral second resonant cavity, the first resonant cavity corresponding to the main resonator and the second resonant cavity corresponding to the sub-resonator; The first stacked structure, on the first resonant cavity, sequentially includes a lower electrode first part, a piezoelectric layer first part, and an upper electrode first part; The second stacked structure, on the second resonant cavity, sequentially includes a lower electrode second part, a piezoelectric layer second part, and an upper electrode second part. A signal different from that of the main resonator is applied to the electrode of the sub-resonator to adjust the resonant state of the resonator, so that the sub-resonator around the main resonator generates a vibration different from that of the main resonator. The two mechanical waves with different states are superimposed, thereby changing the final signal waveform. A first insulating layer is located on the substrate between the first portion of the lower electrode and the second portion of the lower electrode.

2. The resonator of claim 1, further comprising a second insulating layer located between the first portion of the upper electrode and the second portion of the upper electrode on the first portion of the piezoelectric layer and the second portion of the piezoelectric layer.

3. The resonator according to claim 2, wherein the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or separated by a second insulating layer.

4. The resonator according to claim 1, wherein, The first resonant cavity, the first part of the lower electrode, and the first part of the upper electrode are polygonal, circular, or elliptical in a plan view.

5. The resonator according to claim 4, wherein the top dimension of the first resonant cavity is larger than the dimension of the first portion of the lower electrode or the first portion of the upper electrode.

6. The resonator according to claim 4, wherein the top dimension of the second resonant cavity is larger than the dimension of the second portion of the lower electrode or the second portion of the upper electrode.

7. The resonator according to claim 4, wherein the edges of the first portion of the lower electrode and the first portion of the upper electrode are aligned, and the edges of the second portion of the lower electrode and the second portion of the upper electrode are aligned.

8. The resonator of claim 1, wherein the resonant state includes at least one or a combination of amplitude, frequency, and phase.

9. The resonator according to claim 1, wherein, The substrate materials are Si, SO I, Ge, GeO I, and compound semiconductors.

10. The resonator according to claim 1, wherein the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium lead barium niobate), and PT (lead titanate).

11. The resonator according to claim 10, wherein the piezoelectric material is doped with rare earth elements.

12. The resonator according to claim 2, wherein the material of the first or second insulating layer is a nitride.

13. The resonator according to claim 12, wherein the nitride is silicon nitride, silicon oxynitride, aluminum nitride, or boron nitride.

14. The resonator according to claim 1, wherein the material of any one of the lower electrode first part, the lower electrode second part, the upper electrode first part, and the upper electrode second part is a metallic element or metallic alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or conductive nitride of these metals, and any combination of the above materials.

15. A method for manufacturing a resonator, comprising: A sacrificial layer is formed in the substrate, including a central first sacrificial layer pattern and a peripheral second sacrificial layer pattern; A lower electrode layer is formed on the sacrificial layer, including a first portion of the lower electrode on the first sacrificial layer pattern and a second portion of the lower electrode on the second sacrificial layer pattern; A first insulating layer is formed between the first part of the lower electrode and the second part of the lower electrode; A piezoelectric layer is formed on the first insulating layer and the lower electrode layer, including at least a first portion of the piezoelectric layer on the first sacrificial layer pattern and a second portion of the piezoelectric layer on the second sacrificial layer pattern; An upper electrode layer is formed on the piezoelectric layer, including a first upper electrode portion on a first portion of the piezoelectric layer and a second upper electrode portion on a second portion of the piezoelectric layer; The sacrificial layer is removed, leaving a resonant cavity in the substrate, including a central first resonant cavity and a peripheral second resonant cavity. The first resonant cavity corresponds to the main resonator, and the second resonant cavity corresponds to the sub-resonator. A signal different from that of the main resonator is applied to the electrodes of the sub-resonator to adjust the resonant state of the resonator, so that the sub-resonator on the periphery of the main resonator generates a vibration different from that of the main resonator. The two mechanical waves with different states are superimposed, thereby changing the final signal waveform.

16. The resonator manufacturing method of claim 15, further comprising, after forming the upper electrode layer, forming at least a second insulating layer between the first portion of the upper electrode and the second portion of the upper electrode.

17. The resonator manufacturing method according to claim 16, wherein the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or separated by a second insulating layer.

18. The method for manufacturing a resonator according to claim 15, wherein, The first resonant cavity, the first part of the lower electrode, and the first part of the upper electrode are polygonal, circular, or elliptical in a plan view.

19. The resonator manufacturing method according to claim 18, wherein the top dimension of the first resonant cavity is larger than the dimension of the first portion of the lower electrode or the first portion of the upper electrode, or the top dimension of the second resonant cavity is larger than the dimension of the second portion of the lower electrode or the second portion of the upper electrode.

20. The resonator manufacturing method according to claim 18, wherein the edges of the first portion of the lower electrode and the first portion of the upper electrode are aligned, and the edges of the second portion of the lower electrode and the second portion of the upper electrode are aligned.

21. The method for manufacturing a resonator according to claim 15, wherein, The substrate materials are Si, SO I, Ge, GeO I, and compound semiconductors.

22. The resonator manufacturing method according to claim 15, wherein the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium lead barium niobate), and PT (lead titanate).

23. The resonator manufacturing method according to claim 22, wherein the piezoelectric material is doped with rare earth elements.

24. The resonator manufacturing method according to claim 16, wherein the material of the first or second insulating layer is a nitride.

25. The resonator manufacturing method according to claim 24, wherein the nitride is silicon nitride, silicon oxynitride, aluminum nitride, or boron nitride.

26. The resonator manufacturing method according to claim 15, wherein the material of any one of the lower electrode first part, the lower electrode second part, the upper electrode first part, and the upper electrode second part is a metallic element or metallic alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or conductive nitride of these metals, and any combination of the above materials.

27. The resonator manufacturing method according to claim 15, wherein the sacrificial layer material is an oxide.

28. The resonator manufacturing method according to claim 27, wherein the oxide is boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide (USG), or porous silicon oxide.

29. The resonator manufacturing method of claim 16, further comprising, after forming the upper electrode layer and before removing the sacrificial layer, etching a piezoelectric layer between the first portion and the second portion of the upper electrode to form an opening exposing the substrate, and forming a second insulating layer on the upper electrode layer and on the bottom and sidewalls of the opening.

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