Design method of semiconductor package and semiconductor package design system

Abstract

A design method of a semiconductor package including a first chip, a second chip, a 2.5-dimensional (2.5D) interposer, a package substrate, and a board includes: generating a layout including the 2.5D interposer on the package substrate and the first chip and the second chip respectively arranged on the 2.5D interposer based on design information; analyzing signal integrity and power integrity between the first chip and the second chip according to the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board according to the layout; and determining whether to modify the layout based on an analysis result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0040290 filed on April 5, 2019, and Korean Patent Application No. 10-2019-0100538 filed on August 16, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a design method of a semiconductor package, and more particularly, to a design method of analyzing signal integrity and power integrity and designing a semiconductor package based on the analyzed signal integrity and power integrity, and a semiconductor package design system. Background Art

[0004] Existing process flows for designing semiconductor packages focus solely on planar wafer designs, making it difficult to detect the effects of stacking structures in chips stacked on a 2.5-dimensional (2.5D) interposer or in chips with multiple vertically stacked wafers. Therefore, research has been conducted on design methods suitable for semiconductor packages that include stacked structures. Summary of the Invention

[0005] The present inventive concept provides a method of detecting an influence on an overall design caused by a stack structure of a semiconductor package including a 2.5-dimensional (2.5D) interposer or a plurality of vertically stacked wafers and designing a semiconductor package based on the influence to produce a semiconductor package with improved functions, and a semiconductor package design system.

[0006] According to one aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, the semiconductor package including a first chip, a second chip, a 2.5D interposer, a package substrate, and a board, the method including: generating a layout based on design information, the layout including the 2.5D interposer on the package substrate and the first chip and the second chip respectively arranged on the 2.5D interposer; analyzing at least one of signal integrity and power integrity between the first chip and the second chip according to the layout; analyzing the signal integrity or power integrity between the first chip and at least one third chip on the board according to the layout; determining whether to modify the layout based on analysis results of analyzing at least one of the signal integrity and power integrity between the first chip and the second chip and analyzing the signal integrity or power integrity between the first chip and at least one third chip on the board; and when it is determined not to modify the layout, forming a semiconductor package including the first chip, the second chip, the 2.5-dimensional (2.5D) interposer, the package substrate, and the board.

[0007] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, which includes a first chip having multiple vertically stacked chips, a packaging substrate, and a board, the method including: generating a layout including the first chip on the packaging substrate; analyzing at least one of signal integrity and power integrity between the multiple chips of the first chip according to the layout; analyzing the signal integrity or power integrity between the first chip and at least one second chip on the board according to the layout; modifying the layout based on the analysis results of analyzing at least one of signal integrity and power integrity between the multiple chips of the first chip and analyzing the signal integrity or power integrity between the first chip and at least one second chip on the board; and forming a semiconductor package including the first chip having multiple vertically stacked chips, the packaging substrate, and the board based on the modified layout.

[0008] According to another aspect of the inventive concept, a design system for designing a semiconductor package including a first chip, a second chip, a 2.5D interposer, a package substrate, and a board is provided, the design system including: a layout generation module configured to generate a first layout including a 2.5D interposer on a package substrate and a first chip and a second chip respectively arranged on the 2.5D interposer; an extraction module configured to extract first electrical characteristics and second electrical characteristics of the configuration of the 2.5D interposer from the first layout; a feature analysis module configured to analyze at least one of signal integrity and power integrity between the first chip and the second chip based on the extracted first electrical characteristics, and to analyze the signal integrity or power integrity between the first chip and at least one third chip on the board based on the extracted second electrical characteristics; and a review module configured to modify the first layout based on the analysis results of at least one of signal integrity and power integrity between the first chip and the second chip and the signal integrity or power integrity between the first chip and at least one third chip on the board. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A digital design flow of a design method for a semiconductor package according to an exemplary embodiment of the present inventive concept is shown;

[0011] Figure 2 is a block diagram of a semiconductor package design system according to an exemplary embodiment of the present inventive concept;

[0012] Figure 3 is a flowchart of a method for designing a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0013] Figure 4A and Figure 4Bis an implementation example of a semiconductor package design including a stacked structure according to an exemplary embodiment of the present inventive concept, and is used to describe a semiconductor package design method;

[0014] Figure 5 is a table according to an exemplary embodiment of the inventive concept, for describing a method of analyzing specific features at a chip design level;

[0015] Figure 6 is a flowchart of a method of generating feature information performed by a semiconductor package design system according to an exemplary embodiment of the present inventive concept;

[0016] Figure 7 is a table according to an exemplary embodiment of the inventive concept, for describing a method of analyzing specific features at a chip design level;

[0017] Figure 8 is a flowchart of a method of generating feature information performed by a semiconductor package design system according to an exemplary embodiment of the present inventive concept;

[0018] Figure 9 is a flowchart of a method of designing a semiconductor package including a 2.5-dimensional (2.5D) interposer according to an exemplary embodiment of the present inventive concept;

[0019] Figure 10 is a flowchart of a method of designing a semiconductor package according to an exemplary embodiment of the present inventive concept, wherein the semiconductor package includes a chip having a plurality of vertically stacked dies;

[0020] Figure 11 is a flowchart of a semiconductor package design method according to an exemplary embodiment of the present inventive concept;

[0021] Figure 12 is a block diagram of a semiconductor package manufacturing apparatus according to an exemplary embodiment of the present inventive concept; and

[0022] Figure 13 is a block diagram of a computing system to which a semiconductor package design system is applied according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Embodiments of the present inventive concept will be described in detail below in conjunction with the accompanying drawings. In the accompanying drawings, like reference numerals represent like elements throughout. As is conventional in the disclosed art, features and embodiments are described and illustrated in the drawings as "modules." As is conventional in the disclosed art, features and embodiments are described and illustrated in the drawings as functional modules. Those skilled in the art will understand that these modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, and that these circuits can be formed using semiconductor-based or other manufacturing technologies. Where modules are implemented by microprocessors or similar devices, these modules can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and these modules can optionally be driven by firmware and / or software. Alternatively, each module can be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions.

[0024] In addition, according to some embodiments of the present invention, a module can be configured in an addressable storage medium or configured to be executed by at least one processor. Therefore, a module can include the following components, such as software components, object-oriented software components, class components and task components, procedures, functions, properties, programs, subroutines, program code segments, drivers, firmware, microcode circuits, data, databases, data structures, tables, arrays and variables.

[0025] Figure 1 A digital design flow of a design method for a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0026] refer to Figure 1 At a high level, the process begins with a product idea (operation 100) and can be implemented through an electronic design automation (EDA) software design process (operation 110). Once the design is complete, the process can be taken offline (operation 140). After being taken offline, the manufacturing process can be performed (operation 150), followed by the packaging and assembly process (operation 160), which results in a finished semiconductor package (or semiconductor chip) (operation 170).

[0027] The EDA software design process (operation 110) may include multiple operations (operations 112 to 130). However, Figure 1 The operations shown (operations 112 to 130 ) are merely illustrative, and thus the present embodiment is not limited thereto, and new operations may be added or any operations may be omitted. Hereinafter, the EDA software design process (operation 110 ) will be schematically described.

[0028] In system design (operation 112 ), the designer may perform hypothetical planning that includes describing the desired functionality to be implemented, refining the functionality, and calculating the cost. Hardware-software architecture segmentation may be performed in this operation.

[0029] In logic design and functional verification (operation 114), the Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL) or Verilog code of the modules in the system can be recorded and checked to see if the functionality is correct relative to the semiconductor package design. Specifically, it can be checked to see if the semiconductor package design produces the correct output.

[0030] During the synthesis and design of tests (operation 116), the VHDL / Verilog code can be converted into a netlist. The netlist can be optimized to meet the target technology. In addition, the design and implementation of multiple tests can be performed to verify the finished semiconductor package.

[0031] In netlist verification (operation 118), the netlist can be tested for compliance with timing constraints and VHDL / Verilog code. In design planning (operation 120), the overall floor plan of the semiconductor package can be configured, and the timing and top-priority routing of the semiconductor package can be analyzed. In physical implementation (operation 122), placement (determination of the location of circuit elements) and routing (connection of circuit elements) can be implemented. In analysis and extraction (operation 124), circuit functionality can be verified at the transistor level. In physical verification (operation 126), various tests or inspection functions can be performed to ensure accuracy of fabrication, electrical issues, lithography issues, and circuits. In resolution enhancement (operation 128), geometric fabrication of the layout can be performed to enhance design manufacturability. In mask data preparation (operation 130), "tapping" data for mask production can be used to generate semiconductor packages including photolithographic integrated circuits.

[0032] In a design flow for designing a semiconductor package including a 2.5D interposer or a chip having a plurality of vertically stacked wafers, according to an embodiment of the present inventive concept, in at least one of design planning (operation 120), analysis and extraction (operation 124), and physical verification (operation 126), an influence caused by a stacking structure of the semiconductor package may be detected, and design of the semiconductor package may be performed based on the detected influence.

[0033] Specifically, in the design of a semiconductor package including a 2.5D interposer, the signal integrity and power integrity between chips stacked on the 2.5D interposer can be analyzed, and the signal integrity and power integrity between the chips stacked on the 2.5D interposer and other chips stacked on the semiconductor package or board can be analyzed, and the analysis results can be reflected in the design of the semiconductor package. In addition, in the design of a semiconductor package including a chip having multiple vertically stacked chips, the signal integrity or power integrity between the multiple chips included in each chip on the package substrate can be analyzed, and the signal integrity or power integrity between the chip on the package substrate and other chips stacked on the semiconductor package or board can be analyzed, and the analysis results can be reflected in the design of the semiconductor package.

[0034] Figure 2 is a block diagram of a semiconductor package design system 200 according to an exemplary embodiment of the inventive concept.

[0035] refer to Figure 2 The semiconductor package design system 200 may include a layout generation module 210, an extraction module 220, a feature analysis module 230, and a review module 240. The semiconductor package design system 200 may be operated using a computing system. Each component constituting the semiconductor package design system 200 may be implemented to operate on the computing system.

[0036] The layout generation module 210 can generate a layout LO of a semiconductor package including a stacked structure based on the design information DI, and can provide the generated layout LO to the extraction module 220. According to an embodiment of the present invention, the semiconductor package may include a 2.5D interposer, a package substrate, a board, and a plurality of chips. According to another embodiment of the present invention, the semiconductor package may include a package substrate, a board, and at least one chip having a plurality of vertically stacked wafers. As disclosed herein, the chips (e.g., a plurality of chips and at least one chip) may be memory chips and / or logic chips. The design information DI may include layout parameters for each component of the semiconductor package. According to some embodiments of the present invention, the layout parameters may be provided as a library. According to an exemplary embodiment of the present invention, the layout generation module 210 may generate the layout LO by stacking a plurality of wafers according to corresponding positions in the following manner: wherein the positions are determined relative to the chip having the plurality of vertically stacked wafers based on at least one of a temperature parameter, a power consumption parameter, and a noise parameter of each of the plurality of wafers.

[0037] The extraction module 220 can generate extraction information EI by extracting electrical characteristics of the stacked structure of the semiconductor package from the layout LO, and can provide the generated extraction information EI to the feature analysis module 230. For example, when the semiconductor package includes a 2.5D interposer, the extraction module 220 can extract electrical characteristics of the configuration of the 2.5D interposer. For another example, when the semiconductor package includes a chip having multiple vertically stacked wafers, the extraction module 220 can extract electrical characteristics of the configuration of the chip. Figure 5 The electrical characteristics of a 2.5D interposer configuration and a chip configuration with multiple vertically stacked wafers are described in detail.

[0038] The feature analysis module 230 can generate feature information CAI by analyzing the features of the semiconductor package considering the stacked structure based on the extracted information EI, and provide the generated feature information CAI to the review module 240. The features of the semiconductor package considering the stacked structure may include the signal integrity or power integrity of the stacked structure. According to an embodiment of the present invention, when the semiconductor package includes a 2.5D interposer, the feature analysis module 230 can analyze the signal integrity or power integrity between the chips on the 2.5D interposer, and analyze the signal integrity or power integrity between the chip on the 2.5D interposer and at least one chip on the package substrate or board. According to another embodiment of the present invention, when the semiconductor package includes a chip having multiple vertically stacked chips, the feature analysis module 230 can analyze the signal integrity or power integrity between the multiple chips of the chip, and analyze the signal integrity or power integrity between the chip and another chip. Figure 5 Specific embodiments for performing signal integrity or power integrity analysis are described.

[0039] The review module 240 can determine whether to modify the layout LO based on the feature information CAI. In detail, the review module 240 can determine whether the layout LO meets the sign-off conditions by referring to the feature information CAI, and determine whether to modify the layout LO based on the determination result. In some embodiments, the sign-off conditions can reflect whether one or more approval conditions are met, thereby allowing further processing. When the layout LO does not meet the sign-off conditions, the review module 240 can determine to modify the layout LO, generate feedback FB necessary to modify or regenerate the layout LO, and provide the generated feedback FB to the layout generation module 210. The feedback FB may include design information necessary to improve the signal integrity or power integrity related to the stacking structure of the semiconductor package. When the layout LO meets the sign-off conditions, the review module 240 can determine not to modify the layout LO, determine the layout LO as the final layout FL, and use the final layout FL to perform the next design operation.

[0040] By using the above method, the semiconductor package design system 200 according to the exemplary embodiment of the present inventive concept can analyze the characteristics of the stacking structure by considering the stacking structure and reflect the analysis results in the design. By detecting the influence caused by the stacking structure of the semiconductor package when performing the design of the semiconductor package, a semiconductor package with improved performance can be manufactured.

[0041] Figure 3 FIG. 1 is a flow chart of a method for designing a semiconductor package according to an exemplary embodiment of the present inventive concept. Figure 3 In this article, a method of analyzing characteristics by considering the stacking structure of semiconductor packages will be mainly described.

[0042] refer to Figure 3 The semiconductor package design system may analyze features of the semiconductor package at a first chip design level (S100) and analyze features of the semiconductor package at a second chip design level (S120). The first chip design level of the semiconductor package may be defined in different ways depending on the configuration of the semiconductor package.

[0043] For example, when a semiconductor package includes a 2.5D interposer, a level corresponding to the relationship between the chips stacked on the 2.5D interposer can be defined as a first chip design level. In operation S100, the semiconductor package design system may extract first electrical characteristics of the 2.5D interposer configuration and analyze characteristics of the first chip design level based on the extracted first electrical characteristics. The 2.5D interposer configuration used to extract the first electrical characteristics may include multiple through-silicon vias (TSVs), multiple through-vias, and multiple metal lines for connecting the chips on the 2.5D interposer. However, this configuration is merely illustrative, and the present embodiment is not limited thereto, and the 2.5D interposer may further include various configurations. Alternatively, a level corresponding to the relationship between the chips stacked on the 2.5D interposer and the chips stacked on the package substrate or board can be defined as a second chip design level. In this case, in operation S120, the semiconductor package design system may extract second electrical characteristics of the 2.5D interposer configuration and analyze features of the second chip design level based on the extracted second electrical characteristics. The configuration of the 2.5D interposer for extracting the second electrical characteristic may include a plurality of TSVs, a plurality of through-holes, a plurality of grids, and a plurality of bumps for achieving a connection between the package substrate or board and the chip on the 2.5D interposer. The grids may correspond to strips of a metal layer included in the 2.5D interposer. However, this configuration is merely illustrative, and thus the present embodiment is not limited thereto, and the 2.5D interposer may also include various configurations.

[0044] For another example, when a semiconductor package includes a chip having a plurality of vertically stacked wafers, a level corresponding to the relationship between the plurality of wafers in the chip may be defined as a first chip design level. In operation S100, the semiconductor package design system may extract a first electrical characteristic of the configuration of the chip, and may analyze features of the first chip design level based on the extracted first electrical characteristic. The configuration of the chip for extracting the first electrical characteristic may include a plurality of TSVs, a plurality of through-holes, and a plurality of metal lines corresponding to the plurality of wafers, respectively. However, this configuration is merely illustrative, so the present embodiment is not limited thereto, and the chip may include various other configurations. In addition, a level corresponding to the relationship between the chip having the plurality of vertically stacked wafers and another chip stacked on a package substrate or board may be defined as a second chip design level. In this case, in operation S120, the semiconductor package design system may extract a second electrical characteristic of the configuration of the chip, and may analyze features of the second chip design level based on the extracted second electrical characteristic. The configuration of the chip for extracting the second electrical characteristic may include components for communication between the plurality of wafers in the chip and another chip or components for supplying power to the plurality of wafers. Reference will be made to Figure 5 The first electrical characteristic and the second electrical characteristic are described in detail.

[0045] Figure 4A and Figure 4B is an implementation example of a semiconductor package design including a stacked structure according to an exemplary embodiment of the present invention, to describe a semiconductor package design method. However, Figure 4A and Figure 4B An illustrative implementation example of a semiconductor package designed by applying the technical idea of ​​the present inventive concept is shown, and it will be fully understood that the embodiments of the present inventive concept are not limited thereto.

[0046] refer to Figure 4ASemiconductor package 300 may include a first chip 311, a second chip 313, microbumps 312 and 314, a 2.5D interposer 320, interconnect bumps 326 and 327, a package substrate 330, a plurality of ball grid arrays 331, 351, and 361, a board 340, a power management integrated circuit (PMIC) 350, and a data interface chip 360. The first chip 311 and the second chip 313 may include semiconductor chips that perform different operations. For example, the first chip 311 may be a processor, while the second chip 313 may be a memory chip. The 2.5D interposer 320 may include a front layer 321, a substrate 323, and a back layer 325. According to embodiments of the present inventive concept, the 2.5D interposer 320 may include a back-end-of-line (BEOL) structure. According to some embodiments of the present inventive concept, the 2.5D interposer 320 may include a front-end-of-line (FEOL) structure. Furthermore, according to some embodiments of the present inventive concept, the front layer 321 may be referred to as a metal layer. The first chip 311 and the second chip 313 can be stacked on the front layer 321 of the 2.5D interposer 320 via microbumps 312 and 314, respectively, and the first chip 311, the second chip 313 and the 2.5D interposer 320 can form a stacked structure. The substrate 323 can be formed of silicon, glass, etc. and can include a plurality of TSVs 324_1 and 324_2. The active circuits in the first chip 311 and the second chip 313 can be connected to the TSVs 324_1 and 324_2 via metal lines 322 formed in the front layer 321 and the microbumps 312 and 314. In addition, the first chip 311 and the second chip 313 can communicate with each other via a first data path DP_1 formed in the 2.5D interposer 320, a first interface 311_2 formed in the first chip 311, and a third interface 313_1 formed in the second chip 313.

[0047] The back layer 325 of the 2.5D interposer 320 can be connected to the package substrate 330 via interconnect bumps 326 and 327. According to an exemplary embodiment of the present inventive concept, the interconnect bumps 326 and 327 may include solder balls. The package substrate 330 can be connected to a board (e.g., a printed circuit board (PCB)) 340 via a plurality of ball grid arrays 331. The PMIC 350 and the data interface chip 360 can also be connected to the board 340 via the plurality of ball grid arrays 351 and 361. According to an exemplary embodiment of the present inventive concept, the PMIC 350 can supply power to the first chip 311 via a power supply path PSP formed in the 2.5D interposer 320, the package substrate 330, and the board 340. Furthermore, the data interface chip 360 and the first chip 311 can communicate with each other via a second data path DP_2 and a second interface 311_1 formed in the 2.5D interposer 320, the package substrate 330, and the board 340. According to some embodiments of the inventive concept, the data interface chip 360 may be implemented by a serializer / deserializer (SerDes) chip for data communication.

[0048] According to exemplary embodiments of the present inventive concept, Figure 4A The first chip design level in the embodiment may be a level corresponding to the relationship between the first chip 311 and the second chip 313. For example, the communication between the first chip 311 and the second chip 313 may be performed through the first data path DP_1 based on a memory interface (e.g., a high-speed parallel interface (HPI)), and in this case, the signal integrity and power integrity of the memory interface (i.e., the interface between the first chip 311 and the second chip 313) may correspond to particularly relevant factors in the design of the 2.5D interposer 320. However, for ease of description, the first data path DP_1 is schematically illustrated, so the present embodiment is not limited thereto, and the first data path DP_1 actually formed may be different from the first data path DP_1. Figure 4A Different as shown.

[0049] The semiconductor package design system can extract first electrical characteristics of the configuration of the 2.5D interposer 320 connecting the first chip 311 to the second chip 313, and can analyze first chip design-level features based on the extracted first electrical characteristics. For example, the first chip design-level features may include at least one of signal integrity and power integrity between the first chip 311 and the second chip 313. For another example, the configuration of the 2.5D interposer 320 used to extract the first electrical characteristics may include a plurality of TSVs 324_1 and 324_2 (or at least some of the TSVs 324_1 and 324_2) forming the first data path DP_1, a plurality of vias (not shown), and a plurality of metal lines 322. However, this configuration is merely illustrative, and the present embodiment is not limited thereto. The first electrical characteristics can be extracted from various configurations of the 2.5D interposer 320.

[0050] in addition, Figure 4A The second chip design level in may be a level corresponding to the relationship between the first chip 311 and the PMIC 350 or the relationship between the first chip 311 and the data interface chip 360. Regarding the power supply between the first chip 311 and the PMIC 350, the system-level power integrity through the power supply path PSP may correspond to a particularly relevant factor in the design of the 2.5D interposer 320. In addition, the communication between the first chip 311 and the data interface chip 360 may be performed based on a memory interface (e.g., HSI) through the second data path DP_2, and in this case, the signal integrity and power integrity of the memory interface (i.e., the interface between the first chip 311 and the data interface chip 360) may correspond to particularly relevant factors in the design of the 2.5D interposer 320. However, for ease of description, the power supply path PSP and the second data path DP_2 are schematically illustrated, so the present embodiment is not limited thereto, and the power supply path PSP and the second data path DP_2 actually formed may correspond to particularly relevant factors in the design of the 2.5D interposer 320. Figure 4A Different as shown.

[0051] The semiconductor package design system can extract second electrical characteristics of the configuration of the 2.5D interposer 320 connecting the first chip 311 to the PMIC 350 or the configuration of the 2.5D interposer 320 connecting the first chip 311 to the data interface chip 360, and analyze second chip design-level features based on the extracted second electrical characteristics. For example, the second chip design-level features may include power integrity between the first chip 311 and the PMIC 350, or at least one of signal integrity and power integrity between the first chip 311 and the data interface chip 360. For example, the configuration of the 2.5D interposer 320 used for extracting the second electrical characteristics may include a plurality of TSVs 324_1 and 324_2 (or at least some of the TSVs 324_1 and 324_2) forming the power supply path PSP or the second data path DP_2, a plurality of through-vias (not shown), a plurality of meshes (not shown), and a plurality of interconnect bumps 326 and 327 (or at least some of the interconnect bumps 326 and 327). However, this configuration is merely illustrative, and thus the present embodiment is not limited thereto, and the second electrical characteristic may be extracted from various configurations of the 2.5D interposer 320 .

[0052] refer to Figure 4BSemiconductor package 300' may include a third chip 315, interconnect bumps 328, a package substrate 330, multiple ball grid arrays 332, 351, and 361, a board 340, a PMIC 350, and a data interface chip 360. Third chip 315 may include multiple vertically stacked dies (e.g., first die 315_1 through third die 315_3) and multiple microbumps (e.g., first microbump 315_4 and second microbump 316_4). For example, first die 315_1 through third die 315_3 may be stacked based on a position determined based on at least one of a temperature parameter, power consumption parameter, and noise parameter of each of the first die 315_1 through third die 315_3. According to some embodiments of the present inventive concept, third chip 315 may be implemented as a high-bandwidth memory (HBM) chip. A stacked structure may be formed by placing second die 315_2 below first die 315_1 and third die 315_3 below second die 315_2. According to some embodiments of the present inventive concept, the first to third wafers 315_1 to 315_3 may be referred to as semiconductor chips. Each of the first to third wafers 315_1 to 315_3 may include a BEOL or FEOL structure. Specifically, the first wafer 315_1 may include a first semiconductor layer 315_1a and a second semiconductor layer 315_1b, the second wafer 315_2 may include a third semiconductor layer 315_2a and a fourth semiconductor layer 315_2b, and the third wafer 315_3 may include a fifth semiconductor layer 315_3a and a sixth semiconductor layer 315_3b. According to some embodiments of the present inventive concept, the second semiconductor layer 315_1b, the fourth semiconductor layer 315_2b, and the fifth semiconductor layer 315_3a may be referred to as metal layers.

[0053] The first semiconductor layer 315_1a may include multiple first TSVs (TSV1), and the second semiconductor layer 315_1b may include multiple vias (not shown) and multiple metal lines (not shown). The first wafer 315_1 may be connected to the second wafer 315_2 via first microbumps 315_4. The third semiconductor layer 315_2a may include multiple second TSVs (TSV2), and the fourth semiconductor layer 315_2b may include multiple vias (not shown) and multiple metal lines (not shown). The second wafer 315_2 may be connected to the third wafer 315_3 via second microbumps 316_4. The fifth semiconductor layer 315_3a may include multiple vias (not shown) and multiple metal lines (not shown), and the sixth semiconductor layer 315_3b may include multiple third TSVs (TSV3).

[0054] According to an exemplary embodiment of the present inventive concept Figure 4BThe first chip design level may be a level corresponding to the relationship between the first to third wafers 315_1 and 315_3 in the third chip 315. Signal integrity and power integrity between the first to third wafers 315_1 and 315_3 may correspond to specific relevant factors in the design of the third chip 315.

[0055] The semiconductor package design system can extract first electrical characteristics of the configuration of the third chip 315 connecting the first wafer 315_1 to the third wafer 315_3, and can analyze first chip design-level features based on the extracted first electrical characteristics. For example, the first chip design-level features may include at least one of signal integrity and power integrity between the first wafer 315_1 and the third wafer 315_3. For another example, the configuration of the third chip 315 used for extracting the first electrical characteristics may include a plurality of TSVs TSV1, TSV2, and TSV3 (or at least some of TSVs TSV1, TSV2, and TSV3) forming the first data path DP_1, a plurality of vias (not shown), and a plurality of metal lines (not shown). However, this configuration is merely illustrative, and the present embodiment is not limited thereto. The first electrical characteristics can be extracted from various configurations of the third chip 315.

[0056] in addition, Figure 4B The second chip design level in may be a level corresponding to the relationship between the third chip 315 and the PMIC 350 or the relationship between the third chip 315 and the data interface chip 360. Regarding the power supply through the power supply path PSP between the first chip 315_1 to the third chip 315_3 and the PMIC 350, the system-level power integrity may correspond to a particularly relevant factor in the design of the third chip 315. In addition, the signal integrity and power integrity in the communication between the first chip 315_1 to the third chip 315_3 and the data interface chip 360 in the third chip 315 may correspond to a particularly relevant factor in the design of the third chip 315. However, for ease of description, the power supply path PSP and the second data path DP_2 are schematically illustrated, so the present embodiment is not limited thereto, and the power supply path PSP and the second data path DP_2 actually formed may be different from the power supply path PSP and the second data path DP_2. Figure 4B Different as shown.

[0057] The semiconductor package design system can extract second electrical characteristics of the configuration of the third chip 315 connecting the first wafer 315_1 to the third wafer 315_3 to the PMIC 350, or the configuration of the third chip 315 connecting the first wafer 315_1 to the third wafer 315_3 to the data interface chip 360, and analyze second chip design-level features based on the extracted second electrical characteristics. For example, the second chip design-level features may include power integrity between the third chip 315 and the PMIC 350, or at least one of signal integrity and power integrity between the third chip 315 and the data interface chip 360. The configuration of the third chip 315 used for extracting the second electrical characteristics may include a plurality of TSVs TSV1, TSV2, and TSV3 (or at least some of TSVs TSV1, TSV2, and TSV3) forming the power supply path PSP or the second data path DP_2, a plurality of through-vias (not shown), a plurality of grids (not shown), and a plurality of interconnect bumps 328 (or at least some of the interconnect bumps 328). However, this configuration is merely illustrative, and thus the present embodiment is not limited thereto, and the second electrical characteristics may be extracted from various configurations of the third chip 315 .

[0058] Although not shown, a semiconductor package including a 2.5D interposer and a chip (having a plurality of dies vertically stacked on the 2.5D interposer) may be designed, and in this case, Figure 4A and Figure 4B Both embodiments can be applied to this design, and since ordinary technicians in this field can fully understand the detailed description, they will not be repeated here.

[0059] Figure 5 Table TB1 is a table of an exemplary embodiment of the present invention, which is used to describe a method for analyzing specific features at the chip design level. However, Table TB1 is merely an example for describing the concept of the present invention, and thus, the present embodiment is not limited thereto, and various electrical characteristics may be extracted to analyze features.

[0060] refer to Figure 5 , the semiconductor package design system can analyze the features of the first chip design level Level-1 and the features of the second chip design level Level-2 based on the electrical characteristics. Specifically, the first chip design level Level-1 (for example, Figure 4A The level corresponding to the relationship between the first chip 311 and the second chip 313 in Figure 4B The characteristics of the level corresponding to the relationship between the first chip 315_1 and the third chip 315 in the third chip 315 may include signal integrity SI and power integrity PI. The first electrical characteristics extracted to analyze SI may include the stacking structure of the semiconductor package (for example,Figure 4A The configuration of the 2.5D interposer 320 or Figure 4B The first electrical characteristics extracted to analyze the PI may include the stacking structure of the semiconductor package (for example, Figure 4A The configuration of the 2.5D interposer 320 or Figure 4B The synchronous switching noise (SSN), DC resistance (DC-R) and AC impedance (AC-Z) of the third chip 315 in the configuration are shown in FIG.

[0061] With the second chip design level Level-2 (for example, with Figure 4A The level corresponding to the relationship between the first chip 311 and the data interface chip 360, or Figure 4B The features corresponding to the first relationship Relationship-1 (the level corresponding to the relationship between the third chip 315 and the data interface chip 360) may include SI and PI. The second electrical characteristics extracted to analyze SI may include the stacking structure of the semiconductor package (for example, Figure 4A The configuration of the 2.5D interposer 320 or Figure 4B The second electrical characteristic extracted to analyze the PI may include a stacked structure of semiconductor packages (eg, Figure 4A The configuration of the 2.5D interposer 320 or Figure 4B DC-R and AC-Z of the third chip 315 in the configuration).

[0062] With the second chip design level Level-2 (for example, with Figure 4A The level corresponding to the relationship between the first chip 311 and the PMIC 350 in the embodiment, or Figure 4B The feature corresponding to the second relationship Relationship-2 (a level corresponding to the relationship between the third chip 315 and the PMIC 350 in FIG1 ) may include PI. The second electrical characteristic extracted to analyze the PI may include a stacking structure of the semiconductor package (eg, Figure 4A The configuration of the 2.5D interposer 320 or Figure 4B DC-R and AC-Z of the third chip 315 in the configuration).

[0063] Figure 6 is a flowchart of a method of generating feature information performed by a semiconductor package design system according to an exemplary embodiment of the inventive concept.

[0064] refer to Figure 6In operation S200, the semiconductor package design system may extract the values ​​of the electrical characteristics of the stacked structure of the semiconductor packages. In operation S210, the semiconductor package design system may apply corresponding weights to the values ​​of the electrical characteristics, respectively. For example, referring to Figure 5 To describe specifically, the semiconductor package design system may assign a greater weight to the insertion loss of the stacked structure of the semiconductor package than to other electrical characteristics, thereby analyzing the SI of the first chip design level Level-1. In addition, the semiconductor package design system may assign a greater weight to the AC-Z of the stacked structure of the semiconductor package than to other electrical characteristics, thereby analyzing the PI corresponding to the first relationship Relationship-1 of the second chip design level Level-2. However, this weight assignment is merely illustrative, so the present embodiment is not limited thereto, and various weights may be applied to electrical characteristics when analyzing the features. In operation S220, the semiconductor package design system may generate feature information indicating features of a certain chip design level based on the electrical characteristics to which the weights are applied.

[0065] Figure 7 Table TB2 is a table of an exemplary embodiment of the present invention, which describes a method for analyzing specific characteristics at the chip design level. However, Table TB2 is merely an example for describing the concept of the present invention, and thus, the present embodiment is not limited thereto, and electrical characteristics may be extracted based on various physical variables.

[0066] refer to Figure 7 , the semiconductor package design system can extract electrical characteristics based on corresponding physical variables of the stacked structure of the semiconductor package.

[0067] Physical variables used to extract first electrical characteristics to analyze SI of the first chip design level Level-1 will now be described.

[0068] The impedance can be extracted based on physical variables such as metal lines (e.g., Figure 4A The metal wire 322 or Figure 4B The width and height of the metal lines of the plurality of semiconductor layers 315_1b, 315_2b and 315_3a, the spaces between the metal lines, and the dielectric constant of the metal lines.

[0069] The skew may be extracted based on physical variables such as metal lines (eg, Figure 4A The metal wire 322 or Figure 4B The length and impedance (or dielectric constant) of the metal lines of the multiple semiconductor layers 315_1b, 315_2b and 315_3a are determined.

[0070] The return loss can be extracted based on physical variables such as metal lines (e.g., Figure 4A The metal wire 322 or Figure 4B The impedance of the metal lines of the multiple semiconductor layers 315_1b, 315_2b and 315_3a is determined.

[0071] Insertion loss can be extracted based on physical variables such as metal lines (e.g., Figure 4A The metal wire 322 or Figure 4B The length, impedance and dielectric loss of the metal lines of the multiple semiconductor layers 315_1b, 315_2b and 315_3a are determined.

[0072] X-talk can be extracted based on physical variables such as metal lines of a stacked structure of a semiconductor package (e.g., Figure 4A The metal wire 322 or Figure 4B The length of the metal lines of the plurality of semiconductor layers 315_1b, 315_2b and 315_3a, the space between the metal lines and the resistance of the metal lines.

[0073] Physical variables used to extract first electrical characteristics to analyze PI of the first chip design level Level-1 will now be described.

[0074] The SSN may be extracted based on physical variables such as X-talk occurring in a stacked structure of semiconductor packages.

[0075] The DC-R can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 4A 2.5D interposer 320 or Figure 4B The number of vias (Via No), the resistance of the vias (Via R), the number of TSVs (TSV No), and the resistance of the TSVs (TSV R) of the third chip 315 in FIG.

[0076] AC-Z can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 4A 2.5D interposer 320 or Figure 4B The TSV No and the inductance of the TSV (TSV L) of the third chip 315 in FIG.

[0077] Physical variables used to extract second electrical characteristics to analyze signal integrity SI corresponding to the first relationship Relationship-1 of the second chip design level Level-2 will now be described.

[0078] The capacitance can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 4A 2.5D interposer 320 or Figure 4B The number of meshes (Mesh No), the resistance of the mesh (Mesh R), the capacitance of the mesh (Mesh C), TSV No, TSV R, the capacitance of the TSV (TSV C), the number of interconnection bumps (Bump No), and the pitch between the interconnection bumps (Bump Pitch) of the third chip 315 in FIG.

[0079] Physical variables used to extract the second electrical characteristics to analyze the PI corresponding to the first relationship Relationship-1 of the second chip design level Level-2 will now be described.

[0080] The DC-R can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 4A 2.5D interposer 320 or Figure 4B Via No., Via R, TSV No. and TSV R of the third chip 315).

[0081] AC-Z can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 4A 2.5D interposer 320 or Figure 4B The TSV No, TSV C, and TSV inductance (TSVL) of the third chip 315 in FIG.

[0082] Physical variables used to extract the second electrical characteristics to analyze the PI corresponding to the second relationship Relationship-2 of the second chip design level Level-2 will now be described.

[0083] The DC-R can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 8 2.5D interposer 320 or Figure 8 Via No., Via R, TSV No. and TSV R of the third chip 315).

[0084] AC-Z can be extracted based on physical variables such as the stacking structure of the semiconductor package (e.g., Figure 7 2.5D interposer 320 or Figure 9 TSV No and TSV L of the third chip 315).

[0085] Figure 9is a flowchart of a method of generating feature information performed by a semiconductor package design system according to an exemplary embodiment of the inventive concept.

[0086] Referring to Figure 1 In operation S202, the semiconductor package design system can acquire a physical variable value corresponding to each of a plurality of electrical characteristics of a stack structure of a semiconductor package. In operation S212, the semiconductor package design system can apply respective weights to the physical variable values, respectively. For example, referring to Figure 10 For a specific description, the semiconductor package design system can assign a greater weight to the length of the metal line than the weight assigned to other physical variables, thereby extracting insertion loss for analysis of SI of a first chip design level Level-1. The semiconductor package design system can assign a greater weight to TSV No, Bump No, and Bump Pitch than the weight of other physical variables, thereby extracting capacitance for analysis of SI corresponding to a first relationship Relationship-1 of a second chip design level Level-2. In addition, the semiconductor package design system can assign a greater weight to TSV C than the weight of other physical variables, thereby extracting AC-Z for analysis of PI corresponding to the first relationship Relationship-1 of the second chip design level Level-2. However, this weight assignment is merely illustrative, and thus the present embodiment is not limited thereto, and various weights can be applied to the electrical characteristics in extracting the electrical characteristics. In operation S222, the semiconductor package design system can extract electrical characteristics based on the physical variables to which the weights are applied, and generate feature information indicating a feature of a certain chip design level using the extracted electrical characteristics.

[0087] Figure 10 is a flowchart of a method of designing a semiconductor package including a 2.5D interposer according to an exemplary embodiment of the inventive concept.

[0088] Referring to Figure 1In operation S300, logic synthesis may be performed on a semiconductor package design including semiconductor intellectual property (IP) blocks such as digital logic (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) or memory (e.g., HBM). In operation S310, a netlist for the semiconductor package design may be generated. In operation S320, components may be arranged taking into account the signals and power supplies of the semiconductor package design, and routing may be performed to connect the components. In operation S330, a netlist and layout of the semiconductor package design may be generated. In operation S340, resistance-capacitance (RC) and interconnects may be extracted from the semiconductor package design. In operation S350, current resistance drop (IRD), which indicates the value of current I drop caused by resistance R (which does not change over time), and dynamic voltage drop (DVD), which indicates the value of voltage drop caused by impedance (which changes over time), may be analyzed for the semiconductor package design. In operation S360, the signals and power supplies of the semiconductor package design may be analyzed. In operation S370, a design rule check (DRC) / library vs. schematic (LVS) (connectivity check) / electrostatic discharge (ESD) (anti-static circuit check) / design for manufacturing (DFM) (checking whether a design supporting manufacturing (or process) is performed) may be performed on the semiconductor package design. Thereafter, Figure 11 Operation S130.

[0089] According to exemplary embodiments of the present inventive concept, in operations S320, S360, etc., electrical characteristics of the configuration of the 2.5D interposer in the semiconductor package may be extracted, characteristics of the semiconductor package may be analyzed based on the extracted electrical characteristics, and the analyzed characteristics may be reflected in the semiconductor package design. According to embodiments of the present inventive concept, the characteristics of the semiconductor package may include at least one of signal integrity and power integrity.

[0090] Figure 11 is a flowchart of a method of designing a semiconductor package according to an exemplary embodiment of the inventive concept, wherein the semiconductor package includes a chip having a plurality of vertically stacked dies.

[0091] refer to Figure 12In operation S400, logic synthesis may be performed on a semiconductor package design including semiconductor IP blocks such as digital logic or memory. In operation S410, a netlist for the semiconductor package design and timing constraint elements for static timing analysis may be generated. In operation S420, components may be laid out by considering the signal, power, electromagnetic interference (EMI), and temperature characteristics of the semiconductor package design. In operation S430, a temperature-based clock tree may be synthesized, and routing may be performed to connect the components of the semiconductor package design. In operation S440, a netlist and layout of the semiconductor package design may be generated. In operation S450, RC and interconnects may be extracted from the semiconductor package design. In operation S460, static timing analysis (STA), glitch noise, IRD, DVD, electromigration (EM) (a phenomenon in which power / signal routing degrades due to current flow), and jitter may be analyzed (or checked) for the semiconductor package design. In operation S470, the signal, power, and temperature characteristics of the semiconductor package design may be analyzed. In operation S480, TSV-based DRC, LVS, ESD, and DFM may be performed on the semiconductor package design. Thereafter, Figure 12 Operation S130.

[0092] According to exemplary embodiments of the present inventive concept, in operations S420, S470, etc., electrical characteristics of a configuration of chips having a plurality of vertically stacked dies in a semiconductor package may be extracted, characteristics of the semiconductor package may be analyzed based on the extracted electrical characteristics, and the analyzed characteristics may be reflected in the semiconductor package design. According to embodiments of the present inventive concept, the characteristics of the semiconductor package may include at least one of signal integrity and power integrity.

[0093] Figures 1 to 11 is a flowchart of a semiconductor package design method according to an exemplary embodiment of the inventive concept.

[0094] refer to Figure 13 , in operation S500, the design of the semiconductor package can be performed. In operation S510, a plurality of electrical characteristics of the stack structure of the semiconductor package can be extracted. In operation S520, the chip design level specific SI / PI about the stack structure of the semiconductor package can be analyzed based on the extracted electrical characteristics. In operation S530, it can be determined whether the SI or PI meets the sign-off condition. When the determination result in operation S530 is "No", the design of the semiconductor package can be performed again in operation S500, and in this case, the analysis result in operation S520 can be reflected in the design. When the determination result in operation S530 is "Yes", the next design step can be performed.

[0095] As described above, the semiconductor package design method according to the exemplary embodiment of the present inventive concept can achieve the following effect: by analyzing the characteristics of the stacked structure of the semiconductor package and applying the analysis results as feedback to the design, a semiconductor package with improved performance can be designed efficiently and quickly.

[0096] Figures 1 to 11 is a block diagram of a semiconductor package manufacturing apparatus 1000 according to an exemplary embodiment of the inventive concept.

[0097] refer to Figure 13 , the semiconductor package manufacturing apparatus 1000 may include a method according to the combination Figures 1 to 11 The semiconductor package design system 1100 and the semiconductor package manufacturing system 1200 of the described embodiment are described. The semiconductor package design system 1100 may include an analyzer 1110, and the analyzer 1110 may include an SI / PI analysis module 1112. The analyzer 1110 may extract the electrical characteristics of the stacked structure of the semiconductor package through the SI / PI analysis module 1112, and may analyze the SI or PI of the stacked structure based on the extracted electrical characteristics. The semiconductor package design system 1100 may design an optimized semiconductor package of the stacked structure by reflecting the analysis results in the semiconductor package design. The semiconductor package manufacturing system 1200 may manufacture the semiconductor package according to the final layout output by the semiconductor package design system 1100. According to some exemplary embodiments of the present inventive concept, the semiconductor package design system 1100 may be embedded in the semiconductor package manufacturing apparatus 1000, and the semiconductor package design system 1100 and the semiconductor package manufacturing system 1200 may interact with each other to manufacture the semiconductor package.

[0098] ​ 2 is a block diagram of a computing system 2000 to which a semiconductor package design system is applied according to an exemplary embodiment of the present inventive concept. ​ The semiconductor package design system of the described embodiment is applied to the computing system 2000.

[0099] refer to ​ The computing system 2000 may include a storage device 2100 , a CPU 2200 , a southbridge (or southbridge) 2300 , a northbridge (or northbridge) 2400 , an accelerated graphics port (AGP) device 2500 , a main memory 2600 , a keyboard controller 2700 , and a printer controller 2800 .

[0100] The CPU 2200, the AGP device 2500, and the main memory 2600 can be connected to the north bridge 2400. The AGP device 2500 can be a bus standard that enables fast implementation of three-dimensional graphic representation, and the AGP device 2500 can include a video card configured to reproduce a monitor image or the like. The CPU 2200 can perform various arithmetic operations required to operate the computer system 2000, and can also execute an operating system and an application program. The main memory 2600 can load and store data required to perform operations of the CPU 2200 from the storage 2100. The main memory 2600 can be implemented by a dynamic random access memory (DRAM), but the inventive concept is not limited thereto.

[0101] The storage 2100, the keyboard controller 2700, the printer controller 2800, and various peripheral devices (not shown) can be connected to the south bridge 2300. The storage 2100 is a large-capacity data storage device that stores contents such as data, and can be implemented by a computer-readable recording medium, but the inventive concept is not limited thereto.

[0102] According to an exemplary embodiment of the inventive concept, the storage 2100 can store therein a layout generation module 2110, an extraction module 2120, a feature analysis module 2130, a review module 2140, and a library 2150. The CPU 2200 can read the layout generation module 2110, the extraction module 2120, the feature analysis module 2130, the review module 2140, and the library 2150 from the storage 2100, and design a semiconductor package. Detailed descriptions thereof are the same as described in connection with ​ described in connection with the layout generation module 2110, the extraction module 2120, the feature analysis module 2130, the review module 2140, and the library 2150, and thus will be omitted herein.

[0103] Although the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of manufacturing a semiconductor package, the semiconductor package comprising a first chip, a second chip, a 2.5-dimensional (2.5D) interposer, a package substrate, and a board, the method comprising: generating a layout based on the design information, the layout including the 2.5D interposer on the package substrate and the first chip and the second chip respectively arranged on the 2.5D interposer; analyzing at least one of signal integrity and power integrity between the first chip and the second chip according to the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board according to the layout; determining whether to modify the layout based on analysis results of analyzing at least one of the signal integrity and the power integrity between the first chip and the second chip and analyzing the signal integrity or the power integrity between the first chip and at least one third chip on the board; and When it is determined not to modify the layout, forming the semiconductor package including the first chip, the second chip, the 2.5D interposer, the package substrate, and the board, The analysis of the signal integrity and the power integrity between the first chip and the second chip further includes: extracting a first electrical characteristic of the configuration of the 2.5D interposer; and The signal integrity and the power integrity are generated by using the extracted first electrical characteristics.

2. The method according to claim 1, wherein The configuration of the 2.5D interposer includes a plurality of through silicon vias (TSVs), a plurality of through-vias (VASs), and a plurality of metal lines.

3. The method according to claim 1 , wherein generating the signal integrity and the power integrity between the first chip and the second chip further comprises: generating the signal integrity from the extracted first electrical characteristics by using at least one of impedance, skew, return loss, insertion loss, and crosstalk (X-talk) of a first configuration of the 2.5D interposer for communication between the first chip and the second chip; and The power integrity is generated from the extracted first electrical characteristic by using at least one of simultaneous switching noise (SSN), resistance, and impedance of a second configuration of the 2.5D interposer for powering the first chip and the second chip.

4. The method of claim 3 , wherein generating the signal integrity comprises: The signal integrity is generated by assigning a maximum weight to the insertion loss of at least one of the impedance, the skew, the return loss, the insertion loss, and the X-talk.

5. The method according to claim 1 , wherein the analyzing of the signal integrity or the power integrity between the first chip and the at least one third chip further comprises: extracting a second electrical characteristic of the configuration of the 2.5D interposer; and The signal integrity or the power integrity is generated by using the extracted second electrical characteristic. 6 . The method of claim 5 , wherein the configuration of the 2.5D interposer comprises a plurality of through silicon vias (TSVs), a plurality of through-vias (Vs), a plurality of grids, and a plurality of bumps for connection to the package substrate.

7. The method according to claim 5, wherein generating the signal integrity or the power integrity between the first chip and the at least one third chip further comprises: The signal integrity is generated from the extracted second electrical characteristic by using capacitance or insertion loss of a first configuration of the 2.5D interposer for communication between the first chip and the at least one third chip.

8. The method according to claim 5, wherein generating the signal integrity or the power integrity between the first chip and the at least one third chip further comprises: The power integrity is generated from the extracted second electrical characteristic by using at least one of a resistance and an impedance of a second configuration of the 2.5D interposer for powering the first chip from the at least one third chip.

9. The method of claim 1 , wherein determining whether to modify the layout further comprises: When the analysis result does not meet the approval condition, determining to modify the layout; and Based on the analysis result, the design information is modified.

10. The method according to claim 9, wherein generating the layout further comprises: The layout is regenerated based on the modified design information.

11. A method of manufacturing a semiconductor package, the semiconductor package comprising a first chip having a plurality of vertically stacked dies, a package substrate, and a board, the method comprising: generating a layout including the first chip on the packaging substrate; analyzing at least one of signal integrity and power integrity between the plurality of dies of the first chip according to the layout; analyzing signal integrity or power integrity between the first chip and at least one second chip on the board according to the layout; modifying the layout based on analysis results of analyzing at least one of the signal integrity and the power integrity between the plurality of dies of the first chip and analyzing the signal integrity or the power integrity between the first chip and at least one second chip on the board; and forming the semiconductor package including the first chip having a plurality of dies stacked vertically, the package substrate, and the board based on the modified layout, The analysis of the signal integrity and the power integrity between the plurality of chips further includes: extracting a first electrical characteristic of the configuration of the first chip; and The signal integrity and the power integrity are generated using the extracted first electrical characteristic. 12 . The method according to claim 11 , wherein the configuration of the first chip includes a plurality of through silicon vias (TSVs), a plurality of through vias, and a plurality of metal lines corresponding to each of the plurality of dies.

13. The method according to claim 11, wherein the analyzing of the signal integrity and the power integrity between the plurality of dies further comprises: generating the signal integrity from the extracted first electrical characteristics by using at least one of impedance, skew, return loss, insertion loss, and crosstalk (X-talk) of a first configuration of the first chip for communication between the plurality of dies; and The power integrity is generated from the extracted first electrical characteristic by using at least one of a synchronous switching noise (SSN), a resistance, and an impedance of a second configuration of the first chip for powering the plurality of dies.

14. The method according to claim 11, wherein the analyzing of the signal integrity or the power integrity between the first chip and the at least one second chip further comprises: extracting a second electrical characteristic of the configuration of the first chip; and The signal integrity or the power integrity is generated using the extracted second electrical characteristic.

15. The method according to claim 14, wherein generating the signal integrity or the power integrity between the first chip and the at least one second chip further comprises: The signal integrity is generated from the extracted second electrical characteristic by using capacitance or insertion loss of a first configuration of the first chip for communication between each die of the plurality of dies and the at least one second chip.

16. The method according to claim 14, wherein generating the signal integrity or the power integrity between the first chip and the at least one second chip further comprises: The power integrity is generated from the extracted second electrical characteristic by using at least one of a resistance and an impedance of a second configuration of the first chip for powering each of the plurality of dies.

17. The method according to claim 11, wherein generating the layout further comprises: The plurality of dies are stacked according to positions determined based on at least one of a temperature parameter, a power consumption parameter, and a noise parameter of each of the plurality of dies in the first chip.

18. A design system for designing a semiconductor package comprising a first chip, a second chip, a 2.5-dimensional (2.5D) interposer, a package substrate, and a board, the design system comprising: a layout generating module configured to generate a first layout, the first layout including the 2.5D interposer on the package substrate and the first chip and the second chip respectively arranged on the 2.5D interposer; an extraction module configured to extract first and second electrical characteristics of the configuration of the 2.5D interposer from the first layout; a feature analysis module configured to analyze at least one of signal integrity and power integrity between the first chip and the second chip based on the extracted first electrical characteristic, and to analyze signal integrity or power integrity between the first chip and at least one third chip on the board based on the extracted second electrical characteristic; as well as The review module is configured to modify the first layout based on analysis results of at least one of the signal integrity and the power integrity between the first chip and the second chip and the signal integrity or the power integrity between the first chip and at least one third chip on the board.

19. The design system of claim 18, wherein the extracted first electrical characteristic comprises at least one of impedance, skew, return loss, insertion loss, and crosstalk (X-talk) of the first configuration of the 2.5D interposer for communication between the first chip and the second chip. 20 . The design system of claim 18 , wherein the extracted first electrical characteristic comprises at least one of simultaneous switching noise (SSN), resistance, and impedance of a second configuration of the 2.5D interposer for powering the first chip and the second chip. 21 . The design system of claim 18 , wherein the extracted second electrical characteristic comprises at least one of capacitance and insertion loss of a first configuration of the 2.5D interposer for communication between the first chip and the at least one third chip. 22 . The design system of claim 18 , wherein the extracted second electrical characteristic comprises at least one of a resistance and an impedance of a second configuration of the 2.5D interposer for supplying power from the at least one third chip to the first chip.

23. The design system according to claim 18, wherein the semiconductor package further comprises a fourth chip having a plurality of vertically stacked dies, The layout generation module is further configured to generate a second layout including the fourth chip on the packaging substrate, wherein the extraction module is further configured to extract third electrical characteristics and fourth electrical characteristics of the configuration of the plurality of wafers in the fourth chip from the second layout, wherein the feature analysis module is further configured to analyze the signal integrity and power integrity between the plurality of dies in the fourth chip based on the extracted third electrical characteristic, and to analyze the signal integrity or power integrity between the fourth chip and the at least one third chip on the board based on the extracted fourth electrical characteristic; and The review module is configured to modify the second layout based on the analysis result corresponding to the second layout.

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