Direct measurement test structure for measuring static noise margin of static random access memory

Abstract

The present application relates to direct measurement test structures for measuring static random access memory static noise margin, and discloses a test structure for measuring static noise margin (SNM) of one or more static random access memory (SRAM) cells, which can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In embodiments, an interconnect between an output of a first inverter and an input of a second inverter of an SRAM cell can be electrically disconnected using a shunt. During operation of the SRAM cell, an internal storage node within the SRAM cell can be electrically coupled to, for example, an external pin and a test device through the first TG and the second TG. An electrical parameter, such as a voltage, can be measured at the internal storage node through the external pin and used to calculate the SNM of the SRAM cell.

Description

Technical Field

[0001] This disclosure generally relates to test structures and methods for measuring the static noise margin (SNM) of static random access memory (SRAM). More specifically, this disclosure relates to direct measurement memory cell test structures suitable for directly measuring the SNM of SRAM cells. Background Technology

[0002] Static Noise Margin (SNM) is a measure of how well an SRAM cell maintains its binary state when subjected to disturbances or agitations. In other words, SNM is the maximum amount of static voltage noise an SRAM cell can tolerate without altering its state. Changes in state can corrupt the data stored in the SRAM cell.

[0003] Some traditional techniques for determining the SNM of SRAM include simulating SRAM memory cells to estimate voltage. However, these simulations may not be accurate under all possible operating conditions of the SRAM cells. Another traditional technique is to measure SNM indirectly or through probe points, which can be inefficient. Furthermore, these current methods do not allow for the measurement of the SNM of a large number of SRAM cells in a short period of time with a simple setup. Summary of the Invention

[0004] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory, and do not limit the scope of this teaching.

[0005] This document describes a test structure for directly measuring the stability of one or more static random access memory (SRAM) cells in an integrated circuit (IC) device. For each of the one or more SRAM cells, the test structure includes: a first transmission gate (TG) electrically coupled to a first side of a cutoff gate in the SRAM cell; a second TG electrically coupled to a second side of the cutoff gate; a first external pin electrically coupled to the first TG; and a second external pin electrically coupled to the second TG; and a first internal node electrically coupled to the first TG and a second internal node electrically coupled to the second TG. Feedback between the first and second internal nodes is broken at the cutoff gate, and the first internal node is electrically coupled to the first external pin, and the second internal node is electrically coupled to the second external pin.

[0006] As further described herein, a method for measuring the stability of static random access memory (SRAM) cells in an integrated circuit (IC) includes measuring a voltage transfer curve from a first side of a test structure, wherein the first side of the test structure is electrically coupled to a first internal node of the SRAM cell on a first side of a cutoff via a first transmission gate (TG); obtaining a butterfly curve by plotting a curve substantially symmetrical to the measured voltage transfer curve; and determining the static noise margin (SNM) of each of one or more SRAM cells by measuring the area defined by the butterfly curve. Feedback between the first internal node and a second internal node is disconnected at the cutoff. The first internal node is electrically coupled to a first external pin via a first TG, and the second internal node is electrically coupled to a second external pin via a second TG.

[0007] As further described herein, an array of test structures for directly measuring the stability of a plurality of static random access memory (SRAM) cells includes a multi-stage transmission gate (TG), a first chip analog input / output (IO), and a second chip analog IO. Multiple internal nodes of the plurality of SRAM cells are electrically coupled to one of the first and second chip analog IOs via the multi-stage transmission gate (TG), wherein each of the test structures is operable to address a corresponding one of the plurality of SRAM cells, and each of the plurality of test structures is operable to measure the static noise margin (SNM) of a corresponding one of the plurality of SRAM cells. Attached Figure Description

[0008] Embodiments of this teaching are illustrated in conjunction with the accompanying drawings, which are included and form part of this specification, and together with the description, serve to explain the principles of this disclosure. In the drawings:

[0009] Figure 1 This is a block diagram of a test structure including a transmission gate (TG) for measuring the static noise margin (SNM) of a 6-transistor static random access memory (SRAM) cell, according to an example of this disclosure.

[0010] Figure 2 This is a block diagram of a test structure for measuring an array of SRAM cells according to an example of this disclosure.

[0011] Figure 3 Examples depicting those provided in this disclosure may be offered in Figure 2 The input and output paths of two SRAM cells within the SRAM cell array are used to measure voltage drop.

[0012] Figure 4 This is a block diagram of a test structure for measuring a 7-transistor SRAM cell according to an example of this disclosure.

[0013] Figure 5 This is a block diagram of another test structure for measuring a 7-transistor SRAM cell, according to an example of this disclosure.

[0014] Figure 6 This is a block diagram of another test structure for measuring a 7-transistor SRAM cell, according to an example of this disclosure.

[0015] Figure 7 This is a block diagram of a test structure for measuring an 8-transistor SRAM cell, according to an example of this disclosure.

[0016] Figure 8 This is a block diagram of another test structure for measuring an 8-transistor SRAM cell, according to an example of this disclosure.

[0017] Figure 9 This is a block diagram of a test structure for measuring the SNM of a dual interlocked cell (DICE) SRAM cell, according to an example of this disclosure.

[0018] Figure 10 The diagram shows a transfer curve measured using an SRAM SNM test structure according to an example of this disclosure, and a butterfly curve obtained using the measured transfer curve and the symmetrical transfer curve.

[0019] Figure 11A A graph showing the transfer curves measured using an SRAM SNM test structure according to an example of this disclosure.

[0020] Figure 11B Examples of use according to this disclosure are shown. Figure 11A The curve of the butterfly curve obtained from the measurement of the transfer curve.

[0021] Figure 12 A graph showing a series of transfer curves measured using multiple SRAM SNM test structures according to an example of this disclosure, and a butterfly curve created by statistically sampling the distribution of the series of transfer curves.

[0022] Figure 13 A flowchart illustrating a method for directly measuring the SNM of an SRAM cell using a test structure according to an embodiment is shown.

[0023] It should be noted that some details in the accompanying drawings have been simplified and drawn to facilitate understanding of this teaching, rather than to maintain strict structural accuracy, detail, and proportion. Detailed Implementation

[0024] Exemplary embodiments of this teaching will now be described in detail, examples of which are illustrated in the accompanying drawings. Where convenient, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0025] As used herein, the “static noise tolerance (SNM)” of an SRAM cell refers to the maximum static voltage noise that an SRAM cell can tolerate without flipping (i.e., changing) the binary state of the SRAM cell or otherwise altering the stored contents of the SRAM cell. In other words, SNM is the maximum static voltage noise that an SRAM cell can tolerate without changing its binary state. In some cases, exceeding the SNM may corrupt the data stored in the SRAM cell. In many applications, such as aircraft avionics, especially in flight-critical components, data corruption or data loss is unacceptable. Static noise is at least partly caused by offsets and mismatches resulting from variations in processing and operating conditions. Furthermore, for the purposes of this disclosure and unless otherwise stated, the term “electrically coupled” (e.g., a first point or structure “electrically coupled” to a second point or structure) means that the first point or structure is electrically affected by the second point or structure. Electrical coupling can be a direct electrical connection or an indirect electrical connection between one or more points or structures having electrical orientation between the first and second points or structures. Furthermore, the term "cutoff" refers to an electrical disconnection formed or located at a position between two points or structures within a circuit, where the two points are typically shorted together during normal operation of the circuit or during its intended use.

[0026] In various implementations, a test structure is provided to measure the stability of a static memory cell or multiple SRAM cells in an integrated circuit (IC) manufactured using a complementary metal-oxide-semiconductor (CMOS) fabrication process, wherein feedback between internal memory nodes is interrupted during the manufacturing process, and the internal memory nodes of the memory cells are connected to external pins.

[0027] In some such implementations, a connection to an external pin is established via a transmission gate (TG). According to some of these implementations, the TG uses the same transistors used in the SRAM cell.

[0028] According to some such implementations, the test structure includes an array of addressable cells to measure SRAM in a plurality of SRAM cells.

[0029] In various implementations, the method measures the stability of multiple SRAM cells within an IC fabricated using a CMOS process. This measurement may include using a test structure in which feedback between internal memory nodes is disconnected (i.e., interrupted), and the internal memory nodes are connected to external pins.

[0030] In some such implementations, the method includes measuring the transfer curve from one side, assuming that the other side of the transfer curve (i.e., the unmeasured side) is symmetrical.

[0031] According to some such implementations, the method includes: measuring the corresponding transfer curves of a plurality of SRAM cells; and statistically extracting or extrapolating the other side of the transfer curves based on the distribution of the measured transfer curves.

[0032] According to some such implementations, the method includes using a column (first column) to measure the SRAM cells, including, for example... Figure 1 The inverter 136 in the first side (e.g., the left side) and the other column (the second column) are used to measure the SRAM cells, including, for example... Figure 1 The second side (e.g., the right side) of the inverter 130 in the middle.

[0033] SRAM stability is a factor of the ability to read, hold, and write cells. For example, the more stable an SRAM cell is to be read or held, the more difficult it is to write to the cell, and vice versa. SNM measurements provide insight into most of the problems that may arise during SRAM operation in extreme environments, such as space and other high-radiation environments, cryogenic applications, and high-reliability applications. In these extreme environments, the SNM of SRAM cells must be particularly low to reduce or avoid data loss.

[0034] SNM simulation is used during SRAM cell design when silicon measurements for SNM are often infeasible or difficult to obtain. Limited access to silicon manufacturing resources and project schedules, SRAM designers often rely on transistor models provided by semiconductor foundries and perform simulations alone to determine SNM. While this may be sufficient in many cases, accuracy can vary depending on the seriousness with which the semiconductor foundry models the SRAM cell. Because SRAM cells are essential components in many technologies and applications, foundries typically offer a wide variety of SRAM cells to meet design requirements, such as, for example, high-speed or high-density SRAM requirements. As SRAM cell manufacturing technologies have evolved, designers often use foundry-provided SRAM cells and typically rely on device simulation rather than actual device testing to perform SNM characterization of new device designs, with varying degrees of success.

[0035] When SRAM cells need to operate under special conditions not covered by foundry models, such as in space or other high-radiation environments or at low temperatures, SNM must be measured on the fabricated device, rather than through device simulation. Traditionally, SNM measurement is performed in three ways. The first method involves using probe points to electrically access and measure the internal nodes of the SRAM cell. The second method involves fabricating isolated individual SRAM cells, where internal nodes are electrically connected to conductive bumps to provide electrical access and allow measurement. However, the drawback of these two traditional methods is that they require significant test time on expensive qualification or test equipment, and therefore can only measure and / or characterize a small number of SRAM cells. The third traditional method is to measure SNM indirectly. This method is sufficient to measure write SNM, where write SNM is measured by reducing power from ground to the bit line (i.e., bit line "BL" or negative bit line "NBL") or from the normal operating voltage until the SRAM cell flips while the word line remains on power. The voltage difference between the electrical ground and the bit line is the write capability tolerance (WAM). Alternatively, the bit lines (BL and NBL) are set at power and ground, while the word line (WL) can be ramped up until the SRAM cell flips, in which case the voltage difference between power and WL is the write capability tolerance. The write capability tolerance obtained in these two indirect measurement methods provides an indirect indication of the write SNM. However, measuring read and hold SNM using indirect measurement methods is not easy, nor is it always feasible.

[0036] The implementation of this teaching allows for various technical advantages over previous SNM measurements. For example, see the following reference... Figures 1-13 The improved direct SNM measurement test structure and technique described directly measure the SNM of SRAM cells and address the aforementioned problems of conventional methods. The following paragraphs describe example test structures and techniques for measuring SNM using transmission gates (TGs) to provide flexible direct access to the internal nodes of SRAM. The example test structure can measure the SNM of a large number of SRAM bits in a short time. For example, refer to... Figure 2 The test structure 200 allows for serial (sequential) testing of each SRAM cell 206, 206', 206" within a single column 1-4. Furthermore, the setup of the example test structure is relatively simple. In some examples, the test structure can be implemented using commercial 14 nanometer (nm) technology. Moreover, the test structure can be implemented without the measurement cells required by some conventional SNM measurement devices, thus avoiding the need to form and / or use measurement cells in the embodiments of this teaching.

[0037] To facilitate understanding of the various implementations, a general architecture of an exemplary SRAM SNM test structure will be described. Then, specific architectures of various alternative implementations of a direct test structure for measuring the SNM of various types of SRAM memory cells will be described.

[0038] Figure 1 This is a block diagram of a measurement circuit including a test structure 100 according to an example of this disclosure. The test structure 100 and the measurement circuit include a transmission gate (TG) 102 (i.e., a first TG 102) and a TG 104 (i.e., a second TG) for measuring the SNM of a 6-transistor SRAM cell 106. Figure 1 The 6-transistor SRAM cell 106 and measurement circuitry depicted and described below may include a cutoff 108, bit lines (BL 112 and NBL 114), word lines (depicted as WL 116 and WL 118, wherein WL 116 and WL 118 are electrically coupled together), and internal nodes (C 120; B 122; and NC 128).

[0039] Test structure 100 provides controllability and observability for the internal nodes C120, B122, and NC128 of SRAM cell 106 to measure the SNM of SRAM cell 106. In various embodiments, the design of test structure 100 can begin with, for example, a 14nm high-density SRAM cell supplied by a foundry. Other types of SRAM cells and densities can also be considered. That is, in Figure 1 In the example shown, SRAM cell 106 can be a 14nm high-density SRAM cell. See also... Figure 1 Test structure 100 includes TG 102 and TG 104, where TG 102 is connected to internal node C120 and TG 104 is connected to internal node B122. In example test structure 100, the transistors of TG 102 and TG 104 can be the same transistor type as SRAM cell 106, which at least partially enables the layout to pass strict design rule checks (DRC). To reduce or prevent interference from the right inverter 130 during testing, the electrical connection from the output 132 of the right inverter 130 to the input 134 of the left inverter 136 is removed. Figure 1 It is depicted as a cutter 108. For example... Figure 1 As shown, SRAM cell 106 includes bit lines BL 112 and NBL 114 connected to external write or read circuitry, and word lines (WL 116 and WL 118, electrically coupled together and collectively referred to herein as "word lines") that can ramp up until SRAM cell 106 flips. At least partially through word lines ( Figure 1Word lines WL 116 and WL 118 enable electrical access to SRAM cell 106. These word lines control the first access transistor 140 and the second access transistor 142, which in turn control the connection of SRAM cell 106 to bit lines BL 112 and NBL 114. In some embodiments, bit lines BL 112 and NBL 114 can be used to transfer data for read and write operations.

[0040] To operate within the limited available space, in example test structure 100, only nodes B122 and C120 are connected to the outside of SRAM cell 106. Figure 1 As shown, node NC 128 is not directly electrically connected to the outside of SRAM cell 106. That is, node NC 128 is not externally connected or directly accessible. Because SRAM cell 106 is typically symmetrical, the left and right transistors should have the same electrical and operational characteristics, except for process variations. This assumption can be verified by measuring the left side of the cell with one column of SRAM cells and the right side with another column. Using test structure 100, the voltage transfer characteristic (VTC) of the left transistor from SRAM cell 106 is sufficient to calculate SNM. Therefore, it is not necessary to control and measure node NC 128 to allow calculation. Figure 1 The SNM of SRAM cell 106 is depicted in the figure, where “NC” indicates that the node is not directly connected to the outside of the cell.

[0041] Figure 1 The first external pin 150 and the second external pin 152 are further depicted. Figure 1 In this configuration, internal node C120 is electrically coupled to a first external pin 150 via TG 102. Furthermore, internal node B122 is electrically coupled to a second external pin 152 via TG 104. External pins 150 and 152 thus allow electrical access to each of the internal nodes C120 and B122. The external pins 150 and 152 of test structure 100 can be electrically coupled to test device 160 (e.g., a semiconductor test apparatus) configured to apply appropriate test voltages and currents to SRAM cell 106. It should be understood that, although not depicted separately for simplicity, internal node NC 128 is similarly connected to a third external pin and to test device 160. Each internal node in the embodiments discussed below can similarly be electrically coupled to an external pin to allow interfacing with test device 160, but is not depicted separately for simplicity.

[0042] Figure 2This is a block diagram of a test structure 200 for measuring an array of SRAM cells according to an example of this disclosure. The test structure 200 is capable of testing a large number of SRAM cells in an SRAM array in a short time with a relatively simple setup.

[0043] like Figure 2 As shown, the internal nodes from each bit are connected to the chip's input / output (I / O) via a multi-stage transmission gate (TG) including TG, TG_C, and TG_B (e.g., in...). Figure 2 The structures are depicted as chip analog IO 220 and chip analog IO 222 for testing. For example, TG 202, 202', 202" etc. can be connected to chip analog IO 220, and TG 204, 204', 204" etc. can be connected to chip analog IO 222. Those skilled in the art will understand that the structures depicted in Column 1 are similarly reproduced in Columns 2-4, but are not depicted separately for simplicity. Furthermore, it will be understood that although... Figure 2 At least four rows of SRAM cells (206, 206', 206", plus one unnumbered) are depicted in column 1, and ellipses represent additional rows; however, actual devices can have any number of SRAM rows. Access to the internal nodes of the SRAM cells is allowed by enabling transfer gates for specific rows and columns. Figure 2 In the example implementation of the test structure 200 shown, each row includes multiple SRAM cells and a TG adjacent to each SRAM cell (e.g., see SRAM cells 206, 206', 206” and their corresponding adjacent TGs 202, 202', 202”, 204, 204', 204”). Similarly, each column in the test structure 200 may include connections to chip analog I / Os 220 and 222 (e.g., see...). Figure 2 (Columns 224, 226, 228, and 230 in the diagram and their corresponding connections to chip analog I / O 220 and chip analog I / O 222). In test structure 200, access to SRAM cells 206, 206', and 206" can be quickly and easily switched via the row decoding circuitry of test structure 200. For example, in test structure 200, bit lines BL 212 and NBL 214 are independently driven by control logic to allow various settings for reading, holding, and writing SNM measurements to SRAM cells 206, 206', and 206" in column 224. The internal node of each SRAM cell can be accessed individually to perform SNM measurements. Similarly, the internal nodes of each SRAM cell in each of columns 2-4 are addressed and accessed, but are not shown individually for simplicity.

[0044] The voltage drop along the path from the chip's analog input / output (I / O) to the internal nodes of the SRAM cell is a significant factor contributing to SNM measurement errors. For example, the reference... Figure 2 The voltage drop occurs along the path from the chip analog IO 220 to the internal nodes of SRAM cells 206, 206', and 206'". Although not depicted for simplicity... Figure 2 The internal nodes accessed by the feature, but reference Figure 1 Similar internal nodes 120, 122, and 128 are depicted and described. See also: Figure 2 The following components can contribute to the voltage drop along the path from chip analog IO 220 to chip analog IO 222: 1) The voltage between the drain and source of the transfer gate (e.g., Figure 2 1) The voltage between the drain and source of TG 202, 202', 202”, 204, 204', 204”; 2) The decrease in current resistance (IR) caused by the metal resistance along the path; 3) The voltage drop in chip analog IO 220 or chip analog IO 222.

[0045] exist Figure 2 In the example test structure 200 depicted, each transistor in the transmission gate that is laterally adjacent to each SRAM cell has the same size as each one in the SRAM cell. For example, reference Figure 2 Column 224, adjacent to SRAM cells 206, 206', and 206" are TGs 202, 202', 202" , 204, 204', and 204" with fixed dimensions, wherein the size of each TG is the same as the size of its paired SRAM cell 206, 206', and 206" . Furthermore, Figure 2 A first transmission gate 232 and a second transmission gate 234 are depicted, enabling the selection (addressing or access) of the internal node of each SRAM cell in one of columns 1-4 (i.e., 224-230). These transmission gates can be sized sufficiently to make the voltage drop from drain to source small enough that measurement accuracy is not adversely affected (e.g., not excessively affected) as they handle the active current from the selected (active) SRAM cell and the leakage current from the other unselected (inactive) SRAM cells. In an example implementation of 14nm technology, the voltage across all stages of the transmission gates can be limited to, for example, less than 1% of the supply voltage (e.g., 8mV when VDD = 0.8V or lower).

[0046] In some implementations, unacceptably large voltage drops can be reduced, for example, by reducing the resistance and / or current along the electrical input and output paths to and from each internal node of each SRAM cell in the SRAM array. Increasing the cross-sectional area of ​​the interconnects, for example, by increasing the width and / or thickness of the interconnects, will reduce resistance and current. Furthermore, the length of the interconnects can be reduced, for example, by using multiple shorter interconnects to form electrical paths in multilayer metal and redundant conductive vias. Since SNM measurements require the effective current of selected SRAM cells, it is understood that by using fewer rows of SRAM cells in each column, leakage current from unselected SRAM cells can be reduced only. That is, reducing... Figure 2 The number of SRAM cells 206, 206', 206" in each of columns 1-4 (224-230) of the test structure 200 will reduce leakage current from unselected SRAM cells, with fewer cells contributing leakage current. In some implementations, the IO structure, chip analog IO 220, and chip analog IO 222 are selected and configured to ensure an acceptable voltage drop while also providing sufficient electrostatic discharge (ESD) protection for the test structure 200.

[0047] Figure 2 The test structure 200 may include peripheral circuitry using the same word line (WL) decoder 240 and column multiplexer (mux) 242 used by one or more SRAM cells (e.g., 206, 206', 206") to calibrate the voltage drop in the measurement circuit as depicted. Those skilled in the art will recognize that the structures depicted within the four dashed rectangles are reproduced on structural iterations of any number of similar or corresponding structures, where each structural iteration (not depicted separately for simplicity) is coupled to one of the interconnects labeled “LINE_C1” through “LINE_CN” and one of the interconnects labeled “LINE_B1” through “LINE_BN”.

[0048] Figure 3 Examples of what can be described according to this disclosure Figure 2 The input and output paths of two embodiments of SRAM cells 300 and 350 for measuring voltage drop are formed within the array of SRAM cells.

[0049] like Figure 3As shown, example SRAM cell 300 includes a path to C <1> 320's output path and path to C <0> The output path of cell 321. Specifically, in SRAM cell 300, calibration (CAL) cell 336 and CAL cell 336' are connected to each other and connected to the path to C... <1> The output path of 320 is connected to the path to C. <0> The output path of 321. SRAM cell 300 also includes TG 302, CAL cell 336, CAL cell 336' and TG 302'. Figure 3 It is also shown that in SRAM cell 350, TG 302 and TG 304 are interconnected via CAL cell 356 and lead to C <1> The output paths of the 320 include TG 302, CAL unit 356, and TG 304. For example... Figure 3 Further depicted, in SRAM cell 350, input path B 322 includes TG 304 and TG 304', where TG 304 can be connected to CAL cell 356, which in turn is connected to TG 302. In some embodiments, SNM measurement is based on compensating for paths along internal nodes of SRAM cells 300 and 350 (e.g., CAL cells 336, 336', 356, and 356') (e.g., paths to C...). <1> 320 and C <0> Readings of voltage drop along the output path of 321 and the input path of 322).

[0050] The above references Figure 2 In the described scheme, the voltage drop along the conductive path to the SRAM node is the primary cause of measurement error. Although this voltage drop can be minimized by using large transmission gates (TGs), careful consideration of the layout, and selection of the optimal I / O structure, it can still be large enough to cause SNM measurement errors. For example, in reliability testing, cryogenic conditions, and radiation testing, the voltage drop through the TG and metal resistors in the layout can increase dramatically. In this example, it may be necessary to monitor and compensate for voltage variations during SNM measurements.

[0051] Figure 3 It can be shown that Figure 2 Two different implementations of example SRAM cells 300 and 350 formed within an SRAM array to measure voltage drop are described. SRAM cells 300 and 350 are similar to... Figure 1 The SRAM cell 106 shown is divided into CAL cells (e.g., Figure 3 The CAL units 336, 336', 356, and 356' in the example are replaced. Figure 3As shown in the examples, CAL cells 336, 336', 356, and 356' can have short connections or open connections. According to some implementations, CAL cells 336, 336', 356, and 356' can be implemented starting from an SRAM cell (e.g., SRAM cell 300 or 350) and by changing the metal connections. Figure 3 The SRAM cell 300 shown can be used to measure the distance from the internal node of the SRAM to C. <1> 320 and C <0> 321's output path. By configuring the transmission selection, the path to C can be changed. <0> The output path of 321 is connected to a voltage source, while simultaneously measuring the path to C. <1> The voltage at the output path of the 320. The voltage difference between the voltage from the voltage source and the measured voltage is along the path to C. <1> 320 and C <0> The voltage drop along the output path of the 321. Figure 3 In the example implementation, half of the value is along an output path (e.g., to C). <1> 320 and the road to C <0> The voltage drop in one of the output paths of 321. According to some implementations, this output path can be the same as the path from an internal SRAM node, except that the SRAM cell (e.g., Figure 1 The SRAM cell 106 is replaced with a CAL cell (e.g., Figure 3 (CAL 336 or 336'). In some implementations, CAL 336 or 336' can be used. Figure 3 The SRAM cell 300 shown is used to measure along the path to C. <1> Voltage drop across the output path of the 320. In additional or alternative implementations, Figure 3 The SRAM cell 350 shown can be used to measure along input path B 322 and output path C. <0> The voltage drop along input path B322 can be calculated. That is, Figure 3 The two SRAM cells 300 and 350 can be used to measure voltage drop. In embodiments of this teaching, the measurement circuitry for SRAM cells 300 and 350 may include one or more connection lines 340, 360A, and 360B, wherein each connection line 340, 360A, and 360B is electrically coupled to a first TG and a second TG, and extends from the first TG to the second TG, such as... Figure 3 What is depicted.

[0052] According to certain implementations, a complete design architecture (e.g., a direct measurement test architecture) can be implemented using commercial 14nm technology. Such a test architecture can be used to simulate the read, write, and hold SNM of SRAM cells provided by the foundry. Connectivity descriptions of the SRAM circuit design (i.e., netlist) can be used in the simulation, with parasitics extracted for this test architecture and I / O structure. Example simulation results provided in Table 1 below show that the VTC curve obtained from the direct measurement test architecture simulation is very close to the VTC curve obtained directly from the SRAM cell simulation. The difference is too small to be shown in the figure. That is, the difference between the VTC curve obtained from the direct measurement test architecture simulation and the VTC curve obtained directly from the SRAM cell simulation is not statistically significant. Therefore, only the calculated SNM values ​​are listed in Table 1 below. The simulations in this example cover typical (TT), slow (SS), and fast (FF) process corners. The voltage range is from 0.7V to 0.9V, with a typical operating voltage of 0.8V. In the example results shown in Table 1, the operating temperature range is from -55°C to 125°C, with an intermediate simulation temperature of 27°C. The maximum or worst error or difference between the SNM from the direct measurement test structure and the SRAM cell is 4.0%.

[0053]

[0054]

[0055]

[0056] Table 1

[0057] Comparison of simulated SRAM measurements from SRAM test structures and SRAM cells

[0058] As shown in the example results in Table 1, the direct measurement test structure described herein provides a method for measuring the read, write, and hold SNM of SRAM cells by directly controlling and observing the internal nodes of the SRAM. This method allows for rapid SNM measurement using a relatively simple setup. The direct measurement test structure described herein can be advantageously used to characterize the SNM of a large number of SRAM bits in a relatively short time. For example, this method is suitable for characterizing SRAM SNM under conditions such as reliability testing to understand the SRAM SNM over its lifetime, low-temperature conditions, and radiation testing to understand the degradation of the SRAM SNM in a radiated environment. As described above with reference to the results in Table 1, simulations using the example direct measurement test structure show that this method has a maximum error of 4.0% compared to results from simulated SRAM cells.

[0059] Refer to the following paragraphs Figures 4-9The example implementation described herein illustrates an additional direct measurement test structure for measuring the SNM of different types of SRAM cells. Reference is made to the external TG connected to the internal nodes of various types of SRAM cells for description. Figures 4-9 Test structures 400, 500, 600, 700, 800, and 900. Test structures 400-900 are configured to target the above references. Figure 1 The example described is an additional type of SRAM cell besides the transistor SRAM cell 106, directly measured in SNM. For the sake of brevity, generally, only those described below are considered. Figures 4-9 The differences that appear in the attached figures compared to those before or after.

[0060] Figure 4 This is a block diagram of a test structure 400, including TG 402 and TG 404, for measuring the SNM of a 7-transistor SRAM cell 406 according to an example of this disclosure. Figure 4 As shown and described below, the 7-transistor SRAM cell 406 may include a cutoff 408, word lines (depicted as word lines WL 416 and WL 418, wherein WL 416 and WL 418 are electrically coupled together and are collectively referred to herein as “word lines”), negative read word line (NRWL) 424, bit lines BL 412 and NBL 414, and internal nodes B 420, C422, and NC 428.

[0061] Test structure 400 provides controllability and observability to the internal nodes of the 7-transistor SRAM cell 406, which is crucial for measuring the SNM of the SRAM cell 406. Figure 4 In the example implementation shown, TG 402 is connected to internal node C422 and TG 404 is connected to internal node B 420. In the example test structure 400, the transistors of TG 402 and TG 404 can be the same transistor type as SRAM cell 406, which at least partially enables the layout to pass strict DRC. To reduce or prevent interference from the right inverter 430 during testing, the electrical connection from the output 432 of the right inverter 430 to the input 434 of the left inverter 436 is removed. Figure 4 It is described as cutter 408. For example... Figure 4 As shown, SRAM cell 406 includes bit lines BL 412 and NBL 414 electrically coupled to external write or read circuitry, and word lines (WL 416 and WL 418, which are electrically coupled together and collectively referred to herein as "word lines") that can ramp up until SRAM 406 toggles. The voltage difference between the power supply and the word lines is the write capability tolerance. At least partially through the word lines ( Figure 4The word lines BL 416 and BL 418 in the code enable electrical access to SRAM cell 406. These word lines control the first access transistor BL 412 and the second access transistor NBL 414, thereby controlling the connection of the control unit 406 to the bit lines BL 412 and NBL 414. In some embodiments, the bit lines BL 412 and NBL 414 can be used to transfer data for read and write operations. Figure 4 As further shown, SRAM cell 406 also includes an internal node NC428. During a read operation, NRWL 424 is set to ground to interrupt feedback, thereby preventing cell disturbances during the read operation.

[0062] Figure 5 This is a block diagram of another test structure 500 for measuring the SNM of a 7-transistor SRAM cell 506, according to an example of this disclosure. Figure 5 As shown and described below, the 7-transistor SRAM cell 506 may include a cutoff 508, word lines (e.g., WL 516 and WL 518, which are electrically coupled together and are referred to herein as “word lines”), NRWL 524, bit lines BL 512 and NBL 514, and internal nodes B 520, C 522, and NC 528.

[0063] exist Figure 5 In the illustrated example implementation, test structure 500 includes TG 502 and TG 504, where TG 502 is connected to internal node C 522 and TG 504 is connected to internal node B 520 of the 7-transistor SRAM cell 506. In the example test structure 500, the transistors of TG 502 and TG 504 can be the same transistor type as those of the SRAM cell 506 to allow the layout to pass strict DRC. To avoid interference from the right inverter 530, the connection from the output 532 of the right inverter 530 near internal node B 520 to the input 534 of the left inverter 536 is removed, as shown below. Figure 5 The cutter is shown as cutter 508.

[0064] like Figure 5As further shown, SRAM cell 506 includes bit lines BL 512 and NBL 514 electrically coupled to external write or read circuitry, and word lines including WL 516 and WL 518, which can ramp up until SRAM cell 506 toggles. The voltage difference between the power supply and the word lines is the write capability tolerance. Access to SRAM cell 506 is enabled via word lines (WL 516 and WL 518), which control two access transistors at BL 512 and NBL 514, thereby controlling the connection of control unit 506 to bit lines BL 512 and NBL 514. According to some embodiments, bit lines BL 512 and NBL 514 can be used to transfer data for read and write operations. During a read operation, NRWL 524 is set to ground to interrupt feedback, thereby preventing cell disturbances during the read operation.

[0065] Figure 6 This is a block diagram of yet another test structure 600 for measuring the SNM of a 7-transistor SRAM cell 606, according to an example of this disclosure. Figure 6 As shown and described in detail below, the 7-transistor SRAM cell 606 may include a cutoff 608, word lines (WL 616 and WL 618, which are electrically coupled together and are referred to herein as “word lines”), NRWL 624, bit lines BL 612 and NBL 614, and internal nodes B 620, C 622 and NC 628.

[0066] exist Figure 6 In the illustrated example implementation, test structure 600 includes TG 602 and TG 604, where TG 602 is connected to internal node C 622 and TG 604 is connected to internal node B 620 of the 7-transistor SRAM cell 606. In example test structure 600, the transistors of TG 602 and TG 604 can be the same transistor type as the SRAM cell 606 to enable the layout to pass strict DRC. (Refer to the above...) Figure 4 and Figure 5 As mentioned in test structures 400 and 500, to avoid interference from the right inverter 630, in test structure 600, the connection from the output 632 of the right inverter 630 to the input 634 of the left inverter 636 near internal node B 620 is removed, as shown. Figure 6 The cutter is shown as cutter 608.

[0067] like Figure 6As further shown, SRAM cell 606 includes bit lines BL 612 and NBL 614 electrically coupled to external write or read circuitry, and word lines including WL 616 and WL 618, which can ramp up until SRAM cell 606 toggles. The voltage difference between the power supply and the word lines is the write capability tolerance. Access to SRAM cell 606 is achieved via word lines WL 616 and WL 618, which control two access transistors at BL 612 and NBL 614, thereby controlling the connection of SRAM cell 606 to bit lines BL 612 and NBL 614. In some embodiments, bit lines BL 612 and NBL 614 can be used to transfer data for read and write operations.

[0068] Figure 7 This is a block diagram of a test structure 700 for measuring the SNM of an 8-transistor SRAM cell 706, according to an example of this disclosure. Figure 7 As depicted and described below, the 8-transistor SRAM cell 706 may include a cutoff 708, word lines (including WL 715, WL 716 and read word line (RWL) 718, which are electrically coupled together and are collectively referred to herein as “word lines”), bit lines including RBL 726, BL 712 and NBL 714, and internal nodes B 720, C 722 and NC 728.

[0069] exist Figure 7 In the example implementation, test structure 700 includes TG 702 and TG 704, where TG 702 is connected to internal transistor C 722 and TG 704 is connected to internal node B 720 of the 8-transistor SRAM cell 706. In example test structure 700, the transistors of TG 702 and TG 704 can be the same transistor type as SRAM cell 706 to enable the layout to pass strict DRC. To avoid interference from the right inverter 730, the connection from the output 732 of the right inverter near internal node NC 728 to the input 734 of the left inverter 736 is removed, as shown below. Figure 7 The cutter is shown as 708.

[0070] like Figure 7As further shown, SRAM cell 706 includes: bit lines BL 712 and NBL 714, which can be electrically coupled to external write or read circuitry; a read word line 718, which can be electrically coupled to ground; and word lines WL 715 and WL 716, which can be ramped up until SRAM cell 706 toggles. To set the voltage of RBL 726, RBL 726 can be pre-charged before a read cycle. During a read operation, the voltage across RBL 726 can be pulled down or held high. Writing to SRAM cell 706 is performed via word lines WL 715 and WL 716, which control the connection of bit lines BL 712 and NBL 714. During a read operation, RWL 718 is set high to connect RBL 726 to the internal SRAM node. Writes to SRAM cell 706 are implemented using word lines WL 715 and WL 716, which control the connection of bit lines BL 712 and NBL 714. During a read operation, RWL 718 is set high to connect RBL 726 to the internal SRAM node. In some implementations, bit lines BL 712 and NBL 714 can be used to transfer data for read and write operations.

[0071] Figure 8 This is a block diagram of another test structure 800 for measuring the SNM of an 8-transistor SRAM cell 806, according to an example of this disclosure. Figure 8 As shown and discussed below, the 8-transistor SRAM cell 806 may include a cutoff 808, word lines (including WL 815, WL 816 and RWL 818, which are electrically coupled together and are collectively referred to herein as “word lines”), bit lines RBL 826, BL812 and NBL 814, and internal nodes B 820, C 822 and NC 828.

[0072] exist Figure 8 In the example implementation, test structure 800 includes TG 802 and TG 804, where TG 802 is connected to internal node NC 828 and TG 804 is connected to internal node B822. In example test structure 800, the transistors of TG 802 and TG 804 can be the same transistor type as SRAM cell 806 to enable the layout to pass strict DRC. To avoid interference from the right inverter 830, the electrical connection from input 832 of the right inverter 830 to output 834 of the left inverter 836 is removed, as shown below. Figure 8 It is described as cutter 808.

[0073] like Figure 8As further shown, SRAM cell 806 includes: bit lines BL 812 and NBL 814, which can be electrically coupled to external write or read circuitry; and word lines WL 815, WL 816, and RWL 818, which can be ramped up until SRAM cell 806 toggles. To set the voltage of RBL 826, RBL 826 can be pre-charged before a read cycle. During a read cycle, the voltage across RBL 826 can be pulled down or held high. Writing to SRAM cell 806 is performed via word lines WL 815, WL 816, and RWL 818, which control the connection of bit lines BL 812 and NBL 814. During a read operation, RWL 818 is set high to connect RBL 826 to the internal SRAM node. Writes to SRAM cell 806 are implemented using word lines WL 815, WL 816, and RWL 818, which control the connection of bit lines BL 812 and NBL 814. During a read operation, RWL 818 is set high to connect RBL 826 to the internal SRAM node. In some implementations, bit lines BL 812 and NBL 814 can be used to transfer data for read and write operations.

[0074] Figure 9 This is a block diagram of a test structure 900 for measuring the SNM of a dual interlocked cell (DICE) SRAM cell 906, according to an example of this disclosure. Figure 9 As shown, the test structure 900 for the DICE SRAM cell 906 can be implemented as including cutters 908, 908', 908” and 908”', word lines (e.g., including WL 916), bit lines BL 912 and BLB 914, TG 902, 902', 904 and 904', and internal nodes B1, C1, B2 and C2.

[0075] exist Figure 9In the example implementation, the internal nodes B1, C1, B2, and C2 in the DICE SRAM cell 906 on the left are electrically identical to the internal nodes B1, C1, B2, and C2 on the right side of the figure, and are described separately for simplicity. TG 902 is electrically coupled to internal node B1 between cutters 908 and 908', TG 902' is electrically coupled to internal node B2 between cutters 908" and 908"', TG 904 is electrically coupled to internal node C1, and TG 904' is electrically coupled to internal node C2. In the example test structure 900, the transistors of TG 902, 902', 904, and 904' can be the same transistor type as those in SRAM cell 906 to enable the layout to pass strict DRC.

[0076] Figure 9 Internal nodes B1 and cutoffs 908 and 908' are depicted between the output 950 of inverter 952 and the input 954 of transistor 956. Furthermore, internal nodes B2 and cutoffs 908" and 908"' are located between the output 958 of inverter 960 and the input 962 of transistor 964. C1 is located between the output 966 of inverter 968 and the input 970 of transistor 972. C2 is located between the output 974 of inverter 976 and the input 978 of transistor 980. Figure 9 Transistors 982, 984, 986, and 988, electrically coupled to WL 916, BL 912, and BLB 914, are further depicted.

[0077] like Figure 9 As further shown, SRAM cell 906 includes a bit line BL 912, its logic complementary bit line (BLB) 914, and a word line WL 916. BL 912 can be electrically coupled to a power supply, and its complementary BLB 914 can be electrically coupled to ground, and the word line WL 916 can be ramped up until SRAM cell 906 toggles. Access to SRAM cell 906 is achieved through word line WL 916. DICE SRAM cells are known in the art, and those skilled in the art will recognize that... Figure 9 The formation, implementation, and use of devices and similar devices.

[0078] Figure 10 Graph 1000 depicts a transfer curve 1006 measured using an SRAM SNM test structure, and graph 1020 depicts a butterfly curve 1022 using the measured transfer curve 1006 and the symmetrical transfer curve 1008, according to an example of this disclosure. Figure 10In the diagram, transfer curve 1006 is obtained from the voltage transfer characteristic (VTC) of half of the SRAM cell. In each of graphs 1000 and 1020, the horizontal axis 1004 represents the first voltage, and the vertical axis 1002 represents the second voltage. Graph 1020 shows two VTC curves: the measured transfer curve 1006 and the symmetrical transfer curve 1008, which together form a butterfly curve 1022. In graph 1020, region 1010 indicates the SNM, where region 1010 represents the largest square that can be obtained between the measured transfer curve 1006 and its symmetrical transfer curve 1008.

[0079] In some implementations, it can be achieved by using Figure 1 The test setup shown (for measuring the VTC of the right inverter) and Figure 1 The symmetrical version of the test structure shown (for measuring the VTC of the left inverter) directly measures the VTC on each side of the SRAM cell (left and right, or left and right inverters) to obtain the butterfly curve 1022 shown in graph 1020. Figure 10 In the diagram, the butterfly curve 1022 is formed by mirroring one side of VTC relative to a line passing through the origin at a 45-degree angle to the horizontal axis 1004. SNM is given by the length of the diagonal of region 1010. Figure 10 In the example, the measured transfer curve 1006 and the symmetrical transfer curve 1008 are completely (or substantially) symmetrical with respect to each other, the region 1010 on the upper part of the butterfly curve 1022 represents SNM, and will fit the lower part of the butterfly curve 1022.

[0080] Figure 11A Graphs 1100 and 1101 show transfer curves measured using an SRAM SNM test structure according to an example of this disclosure. Figure 11A Graph 1100 shows the transfer curve 1106 measured using an SRAM SNM test structure, and graph 1101 shows the symmetrical transfer curve 1108. Figure 11A In this diagram, transfer curve 1106 is obtained from the VTC of half of the SRAM cell. In each of graphs 1100 and 1101, the horizontal axis 1104 represents the first voltage, and the vertical axis 1102 represents the second voltage. Graphs 1100 and 1101 depict two VTC curves: the measured transfer curve 1106 and the symmetrical transfer curve 1108, which together form... Figure 11B The butterfly curve 1122 shown below (discussed below).

[0081] Figure 11B Examples of use according to this disclosure are shown. Figure 11AA graph 1120 is obtained from the measured transfer curve 1106 and the symmetrical transfer curve 1108 to form a butterfly curve 1122. In graph 1120, region 1110 indicates SNM, where region 1110 represents the largest square that can be contained between the measured transfer curve 1106 and its symmetrical transfer curve 1108.

[0082] exist Figure 11B In the diagram, the butterfly curve 1122 is formed by mirroring one side of VTC relative to a line passing through the origin at a 45-degree angle to the horizontal axis 1104. SNM is given by the length of the diagonal of region 1110. Figure 11B In the example, the measured transfer curve 1106 and the symmetrical transfer curve 1108 are completely (or substantially) symmetrical with respect to each other, the region 1110 on the upper part of the butterfly curve 1122 represents SNM, and will fit the lower part of the butterfly curve 1022.

[0083] Figure 12 A graph 1200 shows a series of voltage transfer curves 1206. Each individual member of this series of transfer curves is provided by measuring SRAM cells using the SRAM SNM test structure described above, where a transfer curve is provided for each SRAM cell, thus providing the series of transfer curves 1206. In other words, multiple measurements of multiple SRAM cells are taken using multiple SRAM SNM test structures to provide the series of transfer curves 1206. A butterfly curve 1220 is then created or derived by statistically sampling and plotting the distribution of this series of transfer curves 1206.

[0084] In graph 1200, for each voltage transfer curve in the series of curves 1206, the horizontal axis 1204 represents the first voltage, and the vertical axis 1202 represents the second voltage. Graph 1200 shows this series of transfer curves 1206 as VTC curves, which represent transfer curves measured from multiple SRAM SNM test cells. In some embodiments, this can be achieved by using, for example... Figure 2 The test structure shown directly measures the VTC on each side of the SRAM cell array (left and right sides, or left inverter or right inverter) to obtain or derive the series of curves 1206 and the butterfly curve 1220 shown in Figure 1200. Figure 12 In this sequence of curves 1206, the statistically sampled VTC 1206' is used in conjunction with the symmetrical transfer curve 1208 to form a butterfly curve 1220. In the butterfly curve 1220, region 1210 indicates the SNM, where region 1210 represents the largest square that can be contained between the statistically sampled VTC 1206' of the sequence of curves 1206 and its symmetrical transfer curve 1208. Figure 12 In this model, the butterfly curve 1220 is formed by mirroring one side of the VTC relative to a line at a 45-degree angle to the horizontal axis 1204 passing through the origin. The SNM for the sampled SRAM cell is given by the length of the diagonal of region 1210. In other embodiments, the statistically sampled VTC 1206' of the series of curves 1206 is used in conjunction with a second statistically sampled VTC formed by mirroring one side of the second VTC relative to a line at a 45-degree angle to the horizontal axis 1204 passing through the origin. Region 1210 indicates the SNM, where region 1210 represents the largest square that can be contained between the statistically sampled VTC 1206' of the series of curves 1206 and the second sampled transfer curve 1208.

[0085] Figure 13 A flowchart is shown of a method 1300 for directly measuring the SNM of an SRAM cell using a test structure, according to an embodiment. The above references can be used in various embodiments. Figures 1-9 One or more of the described test structures are used to execute method 1300.

[0086] At box 1302, method 1300 begins by applying a power supply voltage to one or more direct measurement test structures. (As...) Figure 13 As shown, block 1302 may include grounding (V SS ) and power supply (V DD ) Applied to one or more direct measurement test structures. For example Figure 13 As further shown, one or more test structures (e.g., Figure 1 A single test structure 100 or Figure 2 The array of test structures in the array can be operated to measure the SNM of one or more SRAM cells.

[0087] At block 1304, method 1300 includes measuring voltage transfer curves from a first side of each of one or more test structures. Figure 13 As shown, the first side of each of one or more test structures can be connected to the internal node of the corresponding SRAM cell (i.e., the SRAM cell whose SNM will be measured) of one or more SRAM cells. Figure 13 As further shown, the first side of each test structure may also be located on the first side of the cut-off gate of the SRAM cell whose SNM is to be measured, wherein the first side of the cut-off gate is connected to the transmission gate (TG) of the test structure in one or more test structures for measuring the voltage transfer curve of the SRAM cell.

[0088] Then, at box 1306, method 1300 further includes obtaining a butterfly curve by drawing a curve substantially symmetrical to the voltage transfer curve measured by completing box 1304.

[0089] Next, at block 1308, method 1300 further includes determining the static noise margin (SNM) of each of one or more SRAM cells by measuring the area defined by the butterfly curve obtained by completing block 1306.

[0090] Figures 1-13 The illustrations of the direct measurement test structure, transfer curves, and methods in the diagrams do not imply any physical or architectural limitations on the ways in which the illustrative embodiments can be implemented. Other components besides those shown, or components that replace the shown components, may be used. Some components may be optional. Furthermore, the diagrams presented... Figures 1-12 The items depicted herein are some functional components of an example test structure for measuring SRAM cells and the resulting measurements. When implemented in the illustrative embodiments, one or more of these components may be combined, divided, or combined and divided into different components.

[0091] Although the numerical ranges and parameters described in this teaching are approximations, the numerical values ​​illustrated in specific examples are reported as precisely as possible. However, any numerical value inherently contains some error necessarily caused by the standard deviation found in their corresponding test measurements. Furthermore, all ranges disclosed herein should be understood to encompass any and all subranges contained therein. For example, the range “less than 10” can include any and all subranges between the minimum value of zero and the maximum value of 10 (inclusive), i.e., any and all subranges with a minimum value equal to or greater than zero and a maximum value equal to or less than 10, such as 1 to 5. In some cases, the numerical values ​​specified for the parameters can take negative values. In such cases, example values ​​for the range expressed as “less than 10” can take negative values, such as -1, -2, -3, -10, -20, -30, etc.

[0092] Furthermore, this disclosure includes embodiments pursuant to the following provisions:

[0093] Clause 1: A test structure (100, 200, 400, 500, 600, 700, 800, 900) for directly measuring the stability of one or more static random access memory (SRAM) cells in an integrated circuit (IC) device, wherein for each SRAM cell (406, 506) in one or more SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906), the test structure (100, 200, 400, 500, 600, 700, 800, 900) comprises:

[0094] The first transmission gate (TG) (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') is electrically coupled to the first side of the cutoff in the SRAM cell (406, 506);

[0095] The second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') is electrically coupled to the other side of the cut-off device;

[0096] A first external pin (150) electrically coupled to a first TG (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and a second external pin (152) electrically coupled to a second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'); and

[0097] The first internal node electrically coupled to the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and the second internal node electrically coupled to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'), wherein:

[0098] The cutter provides electrical disconnection between the first side and the second side of the cutter; and

[0099] The first internal node is electrically coupled to the first external pin (150), and the second internal node is electrically coupled to the second external pin (152).

[0100] Clause 2. The test structures (100, 200, 400, 500, 600, 700, 800, 900) described in Clause 1, wherein the IC devices are manufactured using complementary metal-oxide-semiconductor (CMOS) technology.

[0101] Clause 3. The test structure (100, 200, 400, 500, 600, 700, 800, 900) described in any of Clauses 1-2, wherein the first internal node passes through the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 904). The second internal node is electrically coupled to the first external pin (150) via the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0102] Clause 4. The test structure (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 1-3, wherein the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904) The first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and the SRAM cells (406, 506) each contain the same transistor (956, 964, 972, 980) type.

[0103] Clause 5. The test structures (100, 200, 400, 500, 600, 700, 800, 900) described in any of Clauses 1-4, further comprising an array of multiple test structures (100, 200, 400, 500, 600, 700, 800, 900), each of the multiple test structures (100, 200, 400, 500, 600, 700, 800, 900) paired with multiple SRAM cells (106, 206, 206', 206'). Addressing one of the corresponding SRAM cells (100, 200, 400, 500, 600, 706, 806, 906), wherein each of the plurality of test structures (100, 200, 400, 500, 600, 700, 800, 900) is operable to measure the static noise margin (SNM) of the corresponding one of the plurality of SRAM cells (106, 206, 206', 206", 300, 350, 406, 506, 606, 706, 806, 906).

[0104] Clause 6. The test structure (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 1-5, wherein one or more SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) comprise one or more of 6-cell (406, 506) SRAM cells, 7-cell (406, 506) SRAM cells, 8-cell (406, 506) SRAM cells, and Dual Interlocked Cell (DICE) SRAM cells (406, 506).

[0105] Clause 7. The test structure (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 1-6 further includes a measurement circuit, wherein voltage drop calibration in the measurement circuit includes:

[0106] The peripheral circuitry uses word lines (WL) (116, 118, 416, 418, 516, 518, 616, 618, 715, 716, 718, 815, 816, 916) of SRAM cells (406, 506) to decode and multiplexer (242); and

[0107] The measurement circuit also includes connecting lines (340, 360A, 360B) that electrically couple the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0108] Clause 8: Test structure (100, 200, 400, 500, 600, 700, 800, 900) according to any of Clauses 1-7, wherein the feedback between the first internal node and the second internal node is interrupted at the cut-off point.

[0109] Clause 9. A method (1300) for measuring the stability of static random access memory (SRAM) cells (406, 506) in an integrated circuit (IC) device, comprising:

[0110] Voltage transfer curves (1006, 1106) are measured from the first side of the test structures (100, 200, 400, 500, 600, 700, 800, 900), wherein the first side of the test structures (100, 200, 400, 500, 600, 700, 800, 900) is electrically connected to the first internal node of the SRAM cell (406, 506) on the first side of the cut-off device via the first transmission gate (TG) (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0111] By plotting and measuring voltage transfer curves (1006, 1106) that are essentially symmetrical to the curves, butterfly curves (1022, 1122, 1220) are obtained; and

[0112] The static noise margin (SNM) of each of one or more SRAM cells (106, 206, 206', 206"; 300, 350, 406, 506, 606, 706, 806, 906) is determined by measuring the area (1010, 1110, 1210) defined by the butterfly curves (1022, 1122, 1220), where:

[0113] The cutter provides electrical disconnection between the first side and the second side of the cutter; and

[0114] The first internal node is electrically coupled to the first external pin (150) via the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'); and

[0115] The second internal node on the second side of the cut-off is electrically coupled to the second external pin (152) via the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0116] Clause 10. The method (1300) according to Clause 9, wherein the IC device is manufactured using a complementary metal-oxide-semiconductor (CMOS) process.

[0117] Clause 11. The method (1300) according to any one of Clauses 9-10 further includes:

[0118] Multiple SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) were measured using multiple SRAM SNM test structures (100, 200, 400, 500, 600, 706, 806, 906) to provide a series of voltage transfer profiles (1206);

[0119] Statistical sampling was performed on the distribution of this series of voltage transfer curves (1206);

[0120] The butterfly curves (1022, 1122, 1220) are derived from the statistical sampling distribution of this series of voltage transfer curves (1206); and

[0121] The static noise margin (SNM) of multiple SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) is determined by measuring the area (1010, 1110, 1210) defined by the derived butterfly curves (1022, 1122, 1220).

[0122] Clause 12. The method (1300) according to any one of Clauses 9-11 further comprises: a column (1, 224) of the measurement filling SNM measurement table (1) obtained from the left side of the cutter of the SRAM cells (406, 506) and another column (1, 224) of the measurement filling SNM measurement table (1) obtained from the right side of the cutter of the SRAM cells (406, 506).

[0123] Clause 13. The method (1300) according to any one of Clauses 9-12, wherein the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'), the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and the SRAM cell (406, 506) each comprise the same transistor (956, 964, 972, 980) type.

[0124] Clause 14. The method (1300) according to any one of Clauses 9-13 further includes: calibrating the voltage drop in the measurement circuit of the test structure (100, 200, 400, 500, 600, 700, 800, 900), wherein calibrating the voltage drop includes:

[0125] The peripheral circuitry for the word lines (WL) (116, 118, 416, 418, 516, 518, 616, 618, 715, 716, 718, 815, 816, 916) decoder and column (1, 224) multiplexer using SRAM cells (406, 506); and

[0126] Form connecting lines (340, 360A, 360B) that electrically couple the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0127] Clause 15. The method (1300) according to any one of Clauses 9-14, wherein the feedback between the first internal node and the second internal node is interrupted at the cut-off point.

[0128] Clause 16. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) comprising multiple test structures (100, 200, 400, 500, 600, 700, 800, 900) for directly measuring the stability of multiple static random access memory (SRAM) cells, the array of test structures (100, 200, 400, 500, 600, 700, 800, 900) comprising:

[0129] Multilevel transmission gate (TG) (202, 202', 202", 204, 204', 204", 902, 902', 904, 904');

[0130] The first chip has analog inputs (134, 434, 534, 634, 734, 832, 954, 962, 970, 978) / outputs (132, 432, 532, 632, 732, 834, 950, 958, 966, 974, 974) (IO); and

[0131] The second chip simulates I / O (220, 222), where:

[0132] Multiple internal nodes of multiple SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 606, 706, 806, 906) are electrically coupled to one of the first chip analog I / O (220, 222) and the second chip analog I / O (220, 222) through multi-level transmission gates (TG) (202, 202', 202”, 204, 204', 204”, 902, 902', 904, 904').

[0133] Each of the multiple test structures (100, 200, 400, 500, 600, 700, 800, 900) is operable to address a corresponding one of a plurality of SRAM cells (106, 206, 206', 206", 300, 350, 406, 506, 606, 706, 806, 906), and wherein the plurality of test structures are operable to address a corresponding one of a plurality of SRAM cells (106, 206, 206', 206", 300, 350, 406, 506, 606, 706, 806, 906). Each test structure (100, 200, 400, 500, 600, 700, 800, 900) in the test structures (100, 200, 400, 500, 600, 700, 800, 900) is operable to measure the static noise margin (SNM) of a corresponding one of a plurality of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906).

[0134] Clause 17. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) as described in Clause 16, wherein for SRAM cells (406, 506) in a plurality of SRAM cells (106, 206, 206', 206"), each of the plurality of test structures (100, 200, 400, 500, 600, 700, 800, 900) comprises:

[0135] The first transmission gate (TG) (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') is electrically coupled to the first side of the cutoff in the SRAM cell (406, 506);

[0136] The second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'), is electrically coupled to the second side of the cut-off switch; and

[0137] A first external pin (150) electrically coupled to a first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and a second external pin (152) electrically coupled to a second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'), wherein:

[0138] The feedback between the internal nodes of the SRAM cells (406, 506) is interrupted at the cut-off point;

[0139] The first internal node among multiple internal nodes is electrically coupled to the first external pin (150) via the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'); and

[0140] The second internal node among the multiple internal nodes is electrically coupled to the second external pin (152) via the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904').

[0141] Clause 18. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 16-17, wherein multiple internal nodes of a plurality of SRAM cells (106, 206, 206', 206", 300, 350, 406, 506, 606, 706, 806, 906) include calibration (CAL) (336, 336') cells.

[0142] Clause 19. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 16-18, wherein a plurality of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) comprises 6 cells (406, 506) of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906).

[0143] Clause 20. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 16-19, wherein a plurality of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) comprises 7 cells (406, 506) of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906).

[0144] Clause 21. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 16-20, wherein a plurality of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) comprises 8 cells (406, 506) of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906).

[0145] Clause 22. An array of test structures (100, 200, 400, 500, 600, 700, 800, 900) according to any one of Clauses 16-21, wherein a plurality of SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906) include dual interlocked cell (DICE) SRAM cells (106, 206, 206', 206”, 300, 350, 406, 506, 606, 706, 806, 906).

[0146] Although this teaching has been shown with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, it will be appreciated that although the process is described as a series of actions or events, this teaching is not limited to the order of these actions or events. Some actions may occur in a different order and / or simultaneously with other actions or events not described herein. Similarly, according to one or more aspects or embodiments of this teaching, not all process stages may be required to implement the method. It should be understood that structural components and / or processing stages may be added, or existing structural components and / or processing stages may be removed or modified. Furthermore, one or more actions depicted herein may be performed in one or more separate actions and / or stages. In addition, the use of the terms “comprising,” “including,” “containing,” “having,” “with,” or variations thereof in the Detailed Description and Claims is intended to be included in a manner similar to the term “comprising.” The term “at least one” is used to indicate that one or more of the listed items may be selected. As used herein, the term “one or more of…” with respect to a list of items (such as, for example, A and B) means only A, only B, or A and B. Furthermore, in the discussion and claims herein, the term "on" (one "on" the other) used with respect to two materials indicates that there is at least some contact between the materials, while "above" indicates that the materials are adjacent but may have one or more other intermediate materials, making contact possible but not required. Neither "on" nor "above" implies any directionality as used herein. The term "conformal" describes a coating material in which the conformal material maintains the angle of the material below. The term "about" indicates that the listed values ​​may be varied, as long as such variation does not result in inconsistencies in the process or structure of the illustrated embodiments. Finally, "exemplary" indicates that the description is used as an example and not implying that it is ideal. Other embodiments of this teaching will be apparent to those skilled in the art upon consideration of the specification and practice of the disclosure herein. It is intended that the specification and examples be considered merely exemplary, and the true scope and spirit of this teaching are indicated by the appended claims.

Claims

1. A test structure for directly measuring the stability of one or more static random access memory (SRAM) cells in an integrated circuit device, i.e., an IC device, wherein the SRAM cell includes a first inverter and a second inverter, and for each SRAM cell of the one or more SRAM cells, the test structure comprises: The first transmission gate, or first TG, is electrically coupled to the first side of the cut-off in the SRAM cell; The second TG is electrically coupled to the second side of the cut-off device; Electrically coupled to a first external pin of the first TG, and electrically coupled to a second external pin of the second TG; as well as Electrically coupled to the first TG and to a first internal node of the first inverter, and electrically coupled to the second TG and to a second internal node of the second inverter, wherein the cut-off is located between the first inverter and the second inverter, wherein: The cutter provides an electrical disconnect between the first side and the second side of the cutter; and The first internal node is electrically coupled to the first external pin via the first TG, and the second internal node is electrically coupled to the second external pin via the second TG.

2. The test structure according to claim 1, wherein the IC device is manufactured using complementary metal-oxide-semiconductor (CMOS) technology.

3. The test structure according to claim 1, wherein the first TG, the second TG and the SRAM cell each contain the same transistor type.

4. The test structure according to claim 1 further includes an array of multiple test structures, each of the multiple test structures addressing a corresponding one of the multiple SRAM cells, wherein each of the multiple test structures is operable to measure the static noise margin (SNM) of a corresponding one of the multiple SRAM cells.

5. The test structure according to claim 1, wherein the one or more SRAM cells include one or more of a 6-cell SRAM cell, a 7-cell SRAM cell, an 8-cell SRAM cell, and a dual interlocked SRAM cell, i.e., a DICE SRAM cell.

6. The test structure according to claim 1 further includes a measurement circuit, wherein the calibration of the voltage drop in the measurement circuit includes: The word line decoder, namely the WL decoder, and the column multiplexer peripheral circuitry of the SRAM cell are used. and The measurement circuit also includes a connecting line that electrically couples the first TG to the second TG.

7. The test structure according to claim 1, wherein the feedback between the first internal node and the second internal node is interrupted at the cutter.

8. A method for measuring the stability of a static random access memory cell (SRAM cell) in an integrated circuit device, i.e., an IC device, wherein the SRAM cell includes a first inverter and a second inverter, the method comprising: The voltage transfer curve is measured from a first side of the test structure, wherein the first side of the test structure is electrically coupled to a first internal node of the SRAM cell of the first inverter via a first transmission gate, i.e., a first TG, and coupled to the first internal node of the SRAM cell of the first inverter on the first side of the cut-off device. A butterfly curve is obtained by plotting a curve that is essentially symmetrical to the measured voltage transfer curve; and The static noise margin (SNM) of the SRAM cell is determined by measuring the area defined by the butterfly curve, where: The cutter provides an electrical disconnect between the first side and the second side of the cutter; and The first internal node is electrically coupled to the first external pin via the first TG; and The second internal node of the cut-off device, coupled to the second inverter on the second side, is electrically coupled to the second external pin via the second TG, wherein the cut-off device is located between the first inverter and the second inverter.

9. The method of claim 8, wherein the IC device is manufactured using a complementary metal-oxide-semiconductor process, i.e., a CMOS process.

10. The method of claim 8, further comprising: Multiple SRAM cells are measured using multiple SRAM SNM test structures to provide a series of voltage transfer profiles; Statistical sampling is performed on the distribution of the series of voltage transfer curves; The butterfly curve is derived from the distribution of statistical samples of the series of voltage transfer curves; as well as The static noise margin (SNM) of the plurality of SRAM cells is determined by measuring the area defined by the derived butterfly curve.

11. The method of claim 8, further comprising: One column of the SNM measurement table is filled based on measurements obtained from the left side of the cutter of the SRAM cell, and another column of the SNM measurement table is filled based on measurements obtained from the right side of the cutter of the SRAM cell.

12. The method of claim 8, wherein the first TG, the second TG, and the SRAM cell each comprise the same transistor type.

13. The method of claim 8, further comprising: Calibrate the voltage drop in the measurement circuit of the test structure, wherein calibrating the voltage drop includes: The word line decoder (WL decoder) and column multiplexer peripheral circuitry using the SRAM cell; and A connection line is formed to electrically couple the first TG to the second TG.

14. The method of claim 8, wherein the feedback between the first internal node and the second internal node is interrupted at the cutter.

15. An array of test structures comprising a plurality of test structures for directly measuring the stability of a plurality of static random access memory cells, i.e., a plurality of SRAM cells, the array of test structures comprising: Multi-level transmission gates are also known as multi-level transmission gates (TGs). The first chip simulates input / output, i.e., the first chip simulates I / O. as well as The second chip simulates I / O, wherein: Multiple internal nodes of the plurality of SRAM cells are electrically coupled to one of the first chip analog I / O and the second chip analog I / O through the multi-level transmission gate, i.e., the multi-level TG; and Each of the plurality of test structures is operable to address a corresponding one of the plurality of SRAM cells, and each of the plurality of test structures is operable to measure the static noise margin (SNM) of a corresponding one of the plurality of SRAM cells.

16. The array of test structures according to claim 15, wherein each SRAM cell includes a first inverter and a second inverter, and wherein for each of the plurality of SRAM cells, each of the plurality of test structures includes: The first transmission gate, or first TG, is electrically coupled to the first side of the cut-off in the SRAM cell; The second TG is electrically coupled to the second side of the cut-off device; and A first external pin electrically coupled to the first TG and a second external pin electrically coupled to the second TG, wherein: The feedback between the internal nodes of the SRAM cell is interrupted at the cut-off point; The first internal node of the plurality of internal nodes is electrically coupled to the first external pin and to the first inverter via the first TG; and The second internal node of the plurality of internal nodes is electrically coupled to the second external pin via the second TG and to the second inverter, wherein the cut-off is located between the first inverter and the second inverter.

17. The array of test structures according to claim 15, wherein the plurality of internal nodes of the plurality of SRAM cells include calibration units, i.e., CAL units.

18. The array of test structures according to claim 15, wherein the plurality of SRAM cells comprises 6-cell SRAM cells.

19. The array of test structures according to claim 15, wherein the plurality of SRAM cells comprises 7-cell SRAM cells.

20. The array of test structures according to claim 15, wherein the plurality of SRAM cells comprises 8-cell SRAM cells.

21. The array of test structures according to claim 15, wherein the plurality of SRAM cells include dual interlocked SRAM cells, i.e., DICES RAM cells.

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