Voltage measuring device, voltage detection circuit and device address generating method

Abstract

A voltage measuring device (100) is a voltage measuring device (100) having a plurality of voltage detection circuits (1) for measuring the voltage of a plurality of unit cells connected in series. The voltage detection circuit (1) comprises: a device address generation circuit (271, 281) for generating a device address based on a first address assignment command received from a voltage detection circuit at a previous stage; and an address assignment command generation circuit (273, 283) for generating a second address assignment command based on the first address assignment command and sending the second address assignment command to a voltage detection circuit at a subsequent stage.

Description

Technical Field

[0001] The present invention relates to a voltage measuring device, a voltage detection circuit and a device address generating method. Background Art

[0002] Patent Document 1 discloses a conventional voltage measuring device including a plurality of voltage detection circuits connected in a daisy chain.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-50176 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In the conventional technology, when a communication path between voltage detection circuits is blocked, there is a problem that the device address cannot be set for the voltage detection circuit above the blocked part.

[0008] An object of the present invention is to provide a voltage measuring device, a voltage detection circuit, and a device address generating method that enable setting of a device address for a voltage detection circuit at a location after a fault location.

[0009] Means used to solve problems

[0010] A voltage measuring device according to a technical solution of the present invention is a voltage measuring device having a plurality of voltage detection circuits for measuring the voltage of a plurality of unit cells connected in series, wherein the voltage detection circuit comprises: a device address generating circuit for generating a device address based on a first address assignment command received from the voltage detection circuit at the previous stage; and an address assignment command generating circuit for generating a second address assignment command based on the first address assignment command and sending the command to the voltage detection circuit at the next stage.

[0011] A voltage detection circuit according to a technical solution of the present invention is a voltage detection circuit included in a voltage measuring device that measures the voltage of a plurality of unit cells connected in series and has a plurality of voltage detection circuits. The voltage detection circuit comprises: a device address generating circuit that generates a device address based on a first address assignment command received from the voltage detection circuit at the preceding stage; and an address assignment command generating circuit that generates a second address assignment command based on the first address assignment command and sends the command to the voltage detection circuit at the succeeding stage.

[0012] A device address generation method according to a technical solution of the present invention is a device address generation method in a voltage measuring device which measures the voltage of a plurality of unit cells connected in series and has a plurality of voltage detection circuits. The method generates a device address based on a first address assignment command received from the voltage detection circuit of the preceding stage; generates a second address assignment command based on the first address assignment command and sends it to the voltage detection circuit of the subsequent stage.

[0013] A technical solution of the present invention is a voltage measuring device, which is a voltage measuring device comprising a plurality of voltage detection circuits, a controller, a first communication circuit and a second communication circuit for measuring the voltage of a unit cell of a battery pack composed of a plurality of unit cells connected in series, wherein the plurality of voltage detection circuits are connected in a daisy chain; the voltage detection circuit comprises: a lower side communication circuit for receiving communications from the lower side and sending communications to the lower side; a lower side device address generation circuit for generating a device address according to an address assignment command received by the lower side communication circuit; a lower side sub-device address generation circuit for generating a device address of a secondary voltage detection circuit according to the address assignment command; a lower side address assignment command generation circuit for generating a secondary address assignment command using the device address generated by the lower side sub-device address generation circuit as the value of a data field; an upper side communication circuit for receiving communications from the upper side and sending communications to the upper side; and an upper side device address generation circuit for generating a device address according to an address assignment command received by the lower side communication circuit. The upper communication circuit receives the address assignment command and generates a device address; the upper sub-device address generation circuit generates a device address of the secondary voltage detection circuit according to the address assignment command; the upper address assignment command generation circuit uses the device address generated by the upper sub-device address generation circuit as the value of the data field to generate a secondary address assignment command; and the device address holding circuit stores the device address generated by the lower device address generation circuit and the device address generated by the upper device address generation circuit; the lower communication circuit sends the address assignment command generated by the upper address assignment command generation circuit; the upper communication circuit sends the address assignment command generated by the lower address assignment command generation circuit; the controller is connected to the lowest voltage detection circuit via the first communication circuit and is connected to the highest voltage detection circuit via the second communication circuit to send the address assignment command.

[0014] One technical solution of the present invention is a voltage detection circuit used in the above-mentioned voltage measurement device.

[0015] One aspect of the present invention is a battery pack system including the voltage measuring device described above and a battery pack including a plurality of unit cells connected in series.

[0016] A technical solution of the present invention is a voltage measurement method, comprising a plurality of voltage detection circuits for measuring the voltage of a battery pack formed by connecting a plurality of battery cells in series, a controller, a first communication circuit, and a second communication circuit, wherein the plurality of voltage detection circuits are connected in a daisy chain, the controller is connected to the voltage detection circuit at the lowest level via the first communication circuit, and is connected to the voltage detection circuit at the highest level via the second communication circuit, and transmits a communication command. The voltage detection circuit has a device address holding circuit. The voltage measurement method includes the following steps: the controller sends an address assignment command to the lower side of the voltage detection circuit at the lowest level via the first communication circuit; generates a device address based on the value of the data field of the address assignment command received by the voltage detection circuit from the lower side and stores it in the device address holding circuit; updates the value of the data field of the address assignment command received by the voltage detection circuit from the lower side to generate a new address assignment command and sends it to the upper side; the controller sends an address assignment command to the upper side of the voltage detection circuit at the highest level via the second communication circuit; generates a device address based on the value of the data field of the address assignment command received by the voltage detection circuit from the upper side and stores it in the device address holding circuit; and updates the value of the data field of the address assignment command received by the voltage detection circuit from the upper side to generate a new address assignment command and sends it to the lower side.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to set a device address for the voltage detection circuit at a location after the fault location.

[0019] For example, according to the present invention, when there is an obstacle in the communication path between voltage detection circuits, the voltage detection circuit on the lower side of the obstacle can also set the device address with an address assignment command from the lower side, and the voltage detection circuit on the upper side of the obstacle can also set the device address with an address assignment command from the upper side. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A This is a configuration diagram of a voltage detection circuit, a voltage measurement device, and a battery pack system according to the first embodiment.

[0021] Figure 1B This is another structural diagram of the voltage detection circuit, voltage measurement device, and battery pack system according to the first embodiment.

[0022] Figure 2 This is a general configuration diagram of a battery pack system according to the first embodiment.

[0023] Figure 3This is a configuration diagram of a voltage detection circuit according to the first embodiment.

[0024] Figure 4 This is a diagram for explaining the address assignment command related to the first embodiment.

[0025] Figure 5A This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0026] Figure 5B This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0027] Fig. 6A This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0028] Figure 6B This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0029] Figure 7 This is a configuration diagram of a voltage detection circuit according to the second embodiment.

[0030] Figure 8 This is a diagram for explaining the address assignment command related to the second implementation mode.

[0031] Fig. 9A This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0032] Fig. 9B This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0033] Fig.10 This is a structural diagram of a voltage detection circuit, a voltage measurement device, and a battery pack system related to the third embodiment.

[0034] Fig.11 This is a diagram for explaining the address assignment command related to the third embodiment.

[0035] Fig. 12A This is a diagram for explaining the voltage measuring method according to the first embodiment.

[0036] Fig. 12B This is a diagram for explaining the voltage measuring method according to the first embodiment. DETAILED DESCRIPTION

[0037] (Implementation Method 1)

[0038] Figure 1A This is a configuration diagram of a voltage detection circuit, a voltage measurement device, and a battery pack system according to Embodiment 1 of the present invention.

[0039] The battery pack system 10 includes a voltage measuring device 100 and a battery pack 200. The voltage measuring device 100 includes a plurality of voltage detection circuits 1 to 5, a first communication circuit 11, a second communication circuit 12, and a controller 13. The controller 13 Figure 1A In the figure, the battery pack 200 is referred to as MCU (Micro Computer Unit). In addition, the battery pack 200 is composed of a plurality of unit batteries (cells) 20 connected in series. Figure 1B As shown, it is also possible to use Figure 1A The first communication circuit 11 and the second communication circuit 12 are provided with a single communication circuit 14.

[0040] like Figure 1A to Figure 6B As shown, the voltage measuring device 100 of the first embodiment is a voltage measuring device 100 having a plurality of voltage detection circuits for measuring the voltage of a unit cell of a battery pack 200 formed by connecting a plurality of unit cells 20 in series, a controller 13, a first communication circuit 11 and a second communication circuit 12, wherein the plurality of voltage detection circuits are connected in a daisy chain, and the voltage detection circuits have: a lower side communication circuit 26 for receiving communications from the lower side and sending communications to the lower side; a lower side device address generation circuit 281 for generating a device address according to an address assignment command received by the lower side communication circuit 26; a lower side secondary device address generation circuit 282 for generating a device address of a secondary voltage detection circuit according to the address assignment command; and a lower side address assignment command generation circuit 283 for assigning the lower side device address to the lower side. The device address generated by the address generation circuit 282 is used as the value of the data field to generate a secondary address assignment command; the upper side communication circuit 25 receives communications from the upper side and sends communications to the upper side; the upper side device address generation circuit 271 generates a device address according to the address assignment command received by the above-mentioned upper side communication circuit 25; the upper side secondary device address generation circuit 272 generates a device address of the secondary voltage detection circuit according to the above-mentioned address assignment command; the upper side address assignment command generation circuit 273 generates a secondary address assignment command by using the device address generated by the above-mentioned upper side secondary device address generation circuit 272 as the value of the data field; and the device address holding circuit 21 stores the device address generated by the above-mentioned lower side device address generation circuit 281 and the device address generated by the above-mentioned upper side device address generation circuit 271. The lower side communication circuit 26 sends the address assignment command generated by the upper side address assignment command generating circuit 273, the upper side communication circuit 25 sends the address assignment command generated by the lower side address assignment command generating circuit 283, the controller 13 is connected to the voltage detection circuit at the lowest level via the first communication circuit 11, and is connected to the voltage detection circuit at the highest level via the second communication circuit 12, to send the address assignment command.

[0041] In addition, the lower device address generation circuit 281 extracts the value of the data field included in the address assignment command and outputs it as the device address, the lower sub-device address generation circuit 282 reduces the value of the data field included in the address assignment command to generate the device address of the secondary voltage detection circuit, the upper device address generation circuit 271 subtracts the value of the data field included in the address assignment command from the provided correction value and outputs it as the device address, and the upper sub-device address generation circuit 272 reduces the value of the data field included in the address assignment command to generate the device address of the secondary voltage detection circuit.

[0042] In addition, the correction value is included in the address assignment command and is extracted by the upper device address generation circuit 271 .

[0043] Furthermore, the details will be described with reference to the drawings.

[0044] according to Figure 1A The voltage measuring device 100 according to the first embodiment includes a plurality of voltage detection circuits for measuring cell voltages in a battery pack 200 formed by connecting a plurality of cells 20 in series, a controller 13 (MCU), and first and second communication circuits 12. The plurality of voltage detection circuits are connected in a daisy chain.

[0045] Here, in order to facilitate understanding of the present invention, a general voltage measuring device 100 will be described.

[0046] Figure 2 1 is a block diagram of a general battery pack system. The battery pack system 10 in the figure includes a voltage measuring device 100 and a battery pack 200. The voltage measuring device 100 includes a plurality of voltage detection circuits 1 to 4, a controller 13, and a communication circuit 14. Figure 2 The voltage detection circuits 1 to 4 include a device address holding circuit 21 , an upper communication circuit 25 , a lower communication circuit 26 , and an address assigning circuit 27 , respectively.

[0047] like Figure 2 As shown, a general voltage measuring device 100 includes a plurality of voltage detection circuits for measuring cell voltages in a battery pack 200 formed by connecting a plurality of cells 20 in series, a controller 13 (MCU), and a communication circuit. The plurality of voltage detection circuits are connected in a daisy chain.

[0048] The address assignment command is a command for setting a device address for identifying each voltage detection circuit, and the command has a data field, and a value of the data field is set as the device address.

[0049] Furthermore, the voltage detection circuit includes an upper communication circuit 25 , a lower communication circuit 26 , an address assignment circuit 27 , and a device address holding circuit 21 .

[0050] In addition, the address assignment circuit 27 decodes the communication command received by the lower communication circuit 26 from the lower voltage detection circuit, and in the case of an address assignment command, sets the value of the data field to the device address holding circuit 21, subtracts 1 from the value of the data field to generate a new address assignment command, and provides it to the upper communication circuit 25. The upper communication circuit 25 sends the new address assignment command to the upper voltage detection circuit.

[0051] Through such a structure, for example, for four voltage detection circuits, if the MCU provides an address assignment command with a data field value of 4 to the lowest-level voltage detection circuit via the communication circuit, the values ​​4, 3, 2, and 1 are set in the device address holding circuit 21 in sequence from the lowest level.

[0052] However, in this structure, if there is a problem in the communication path between any of the voltage detection circuits, the device address cannot be set for the voltage detection circuit above the problem site. For example, if the communication path between the voltage detection circuits 2 and 3 is disconnected, the device address cannot be set for the voltage detection circuits 1 and 2.

[0053] On the other hand, the voltage detection circuit, the voltage measurement device 100, the battery system 10, and the voltage measurement method according to the first embodiment can solve the above-mentioned problems. The details will be described with reference to the drawings.

[0054] Figure 3 This is a configuration diagram of a voltage detection circuit according to the first embodiment.

[0055] The voltage detection circuit 1 of the figure includes a device address holding circuit 21, an upper communication circuit 25, a lower communication circuit 26 and an address granting circuit 27. The upper communication circuit 25 includes a sending circuit 251 and a receiving circuit 252. The lower communication circuit 26 includes a sending circuit 261 and a receiving circuit 262. The address granting circuit 27 includes an upper device address generation circuit 271, an upper sub-device address generation circuit 272, an upper address granting command generation circuit 273, a lower device address generation circuit 281, a lower sub-device address generation circuit 282 and a lower address granting command generation circuit 283. The upper device address generation circuit 271 includes an extraction circuit 274 and a subtractor 275. The upper sub-device address generation circuit 272 includes an extraction circuit 276 and a subtractor 277. The lower sub-device address generation circuit 282 includes an extraction circuit 286 and a subtractor 287. In addition, Figure 1A , Figure 1B The voltage detection circuits 2 to 4 shown are also Figure 3 Same structure.

[0056] like Figure 3 As shown, it has: a lower side communication circuit 26 for receiving communications from the lower side and sending communications to the lower side; a lower side device address generation circuit 281 for generating a device address according to an address assignment command received by the lower side communication circuit 26; a lower side sub-device address generation circuit 282 for generating a device address of a secondary voltage detection circuit according to the address assignment command; a lower side address assignment command generation circuit 283 for generating a secondary address assignment command using the device address generated by the lower side sub-device address generation circuit 282 as a data field; an upper side communication circuit 25 for receiving communications from the upper side and sending communications to the upper side. The upper side device address generating circuit 271 generates a device address according to the address assignment command received by the upper side communication circuit 25; the upper side sub-device address generating circuit 272 generates a device address of the secondary voltage detection circuit according to the address assignment command; the upper side address assignment command generating circuit 273 uses the device address generated by the upper side sub-device address generating circuit 272 as the data field to generate a secondary address assignment command; and the device address holding circuit 21 stores the device address generated by the lower side device address generating circuit 281 and the device address generated by the upper side device address generating circuit 271.

[0057] In addition, according to Figure 3 The lower side communication circuit 26 sends the address assignment command generated by the upper side address assignment command generating circuit 273, the upper side communication circuit 25 sends the address assignment command generated by the lower side address assignment command generating circuit 283, the controller 13 is connected to the voltage detection circuit at the lowest level via the first communication circuit 11, and is connected to the voltage detection circuit at the highest level via the second communication circuit 12, to send the address assignment command.

[0058] In addition, according to Figure 3 If the lower communication circuit 26 receives an address assignment command from the lower side as an address assignment command from the lower side, the lower device address generation circuit 281 extracts the value of the data field of the received address assignment command and stores it in the device address holding circuit 21 as a device address.

[0059] At the same time, the lower side sub-device address generation circuit 282 uses a subtractor to subtract 1 from the value of the extracted data field and outputs it as the sub-device address. The lower side address assignment command generation circuit 283 generates a new address assignment command with the sub-device address as the value of the data field, and the upper side communication circuit 25 sends the new address assignment command to the upper side.

[0060] In addition, according to Figure 3If the upper communication circuit 25 receives an address assignment command from the upper side as an address assignment command from the upper side, the upper device address generation circuit 271 extracts the value of the data field of the received address assignment command, subtracts the value of the data field from the provided correction value, and saves it as the device address to the device address holding circuit 21.

[0061] At the same time, the upper side sub-device address generation circuit 272 uses a subtractor to subtract 1 from the value of the extracted data field and outputs it as the sub-device address. The upper side address assignment command generation circuit 273 generates a new address assignment command with the sub-device address as the value of the data field, and the lower side communication circuit 26 sends the new address assignment command to the lower side.

[0062] Alternatively, the correction value may be included in an address assignment command and provided to the upper-side sub-device address generation circuit 272, or may be set in advance in each voltage detection circuit through another communication command.

[0063] Next, the address assignment command will be described.

[0064] Figure 4 This is a diagram for explaining the address assignment command related to the first embodiment. Figure 4 This is an example of an operation when there is an obstacle on the communication path. Regarding the flow of address assignment commands when there is an obstacle on the communication path between the voltage detection circuit 2 and the voltage detection circuit 3, the MCU sends an address assignment command to the lower side of the voltage detection circuit 4 via the first communication circuit 11. The data field of the address assignment command is specified as 4, which is the number of voltage detection circuits.

[0065] Furthermore, when the lower communication circuit 26 of the voltage detection circuit 4 receives the address assignment command, the lower device address generation circuit 281 extracts the data field, outputs the value 4 as the device address, and stores it in the device address holding circuit 21. The lower sub-device address generation circuit 282 subtracts 1 from the value 4 of the extracted data field, and outputs the result 3 as the sub-device address.

[0066] Furthermore, the lower address assignment command generation circuit 283 generates a new address assignment command in which the secondary device address 3 is set in the data field, and transmits the command to the voltage detection circuit 3 via the upper communication circuit 25 .

[0067] Similarly, the voltage detection circuit 3 that has received the address assignment command with the data field being 3 stores the value 3 of the data field in the device address holding circuit 21 .

[0068] The MCU transmits an address assignment command to the upper side of the voltage detection circuit 1 via the second communication circuit 12. The data field of the address assignment command specifies 4, which is the number of voltage detection circuits. 5 is specified for the correction value of each voltage detection circuit.

[0069] When the upper communication circuit 25 of the voltage detection circuit 1 receives the address assignment command, the upper device address generation circuit 271 extracts the data field, and outputs the result 1 obtained by subtracting the value 4 of the data field from the correction value as the device address, and stores it in the device address holding circuit 21. The upper sub-device address generation circuit 272 outputs the result 3 obtained by subtracting 1 from the extracted value 4 of the data field as the sub-device address. The upper address assignment command generation circuit 273 generates a new address assignment command in which the sub-device address 3 is set in the data field, and sends it to the voltage detection circuit 2 through the lower communication circuit 26.

[0070] Similarly, the voltage detection circuit 2 that has received the address assignment command with the data field being 3 stores the result 2 obtained by subtracting the value of the data field from the correction value in the device address holding circuit 21 .

[0071] In this way, 1 to 4 are correctly set in the device addresses of the voltage detection circuits 1 to 4.

[0072] In this example, the correction value is set to a value obtained by adding 1 to the number of voltage detection circuits.

[0073] Therefore, in the voltage detection device according to embodiment 1, even when there is an obstacle in the communication path between the voltage detection circuits, the voltage detection circuit on the lower side of the obstacle can set the device address according to the address assignment command from the lower side, and the voltage detection circuit on the upper side of the obstacle can set the device address according to the address assignment command from the upper side.

[0074] Next, the device address assignment method according to the first embodiment will be described. Figure 5A , Figure 5B This is a diagram for explaining the device address assignment method related to the first embodiment. Figure 5A , Figure 5B is a process showing the device address assignment method according to the first embodiment. Figure 5A This is the case where the controller 13 sends an address assignment command from the bottom side. Figure 5B This is the case where the controller 13 sends an address assignment command from the upper side.

[0075] Figure 5AThe device address assignment method comprises: step (S51), the controller 13 sends an address assignment command to the lower side of the lowest voltage detection circuit via the first communication circuit 11; step (S52), generating a device address according to the value of the data field of the address assignment command received by the voltage detection circuit from the lower side and saving it to the device address holding circuit 21; and step (S53), updating the value of the data field of the address assignment command received by the voltage detection circuit from the lower side to generate a new address assignment command, and sending it to the upper side.

[0076] Figure 5B The device address assignment method comprises: step (S55), the controller 13 sends an address assignment command to the upper side of the uppermost voltage detection circuit via the second communication circuit 12; step (S56), generating a device address according to the value of the data field of the address assignment command received by the voltage detection circuit from the upper side and saving it to the device address holding circuit 21; and step (S57), updating the value of the data field of the address assignment command received by the voltage detection circuit from the upper side, generating a new address assignment command and sending it to the lower side.

[0077] Implementation Figure 5A and Figure 5B The voltage measuring device 100 includes a plurality of voltage detection circuits 1 to 5 for measuring the voltage of a battery pack 200 formed by connecting a plurality of battery cells 20 in series, a controller 13, a first communication circuit 11, and a second communication circuit 12. The plurality of voltage detection circuits are connected in a daisy chain, and the controller 13 is connected to the voltage detection circuit at the lowest level via the first communication circuit 11, and is connected to the voltage detection circuit at the highest level via the second communication circuit 12. Each of the voltage detection circuits includes a device address holding circuit 21.

[0078] The battery pack system 10 according to the first embodiment is constituted by the voltage measuring device 100 described above and a battery pack 200 in which a plurality of unit cells 20 are connected in series.

[0079] (Variation of Implementation Example 1)

[0080] Fig. 6A , Figure 6B This is a diagram showing a method of assigning device addresses according to a variation of the first embodiment. Fig. 6A This is the case where the controller 13 sends an address assignment command from the bottom side. Figure 6B This is the case where the controller 13 sends an address assignment command from the upper side.

[0081] Fig. 6AThe device address assignment method comprises: step (S61), the controller 13 sends an address assignment command to the lower side of the lowest voltage detection circuit via the first communication circuit 11; step (S62), the value of the data field of the address assignment command received by the voltage detection circuit from the lower side is saved as the device address to the device address holding circuit 21; and step (S63), the value of the data field of the address assignment command received by the voltage detection circuit from the lower side is reduced to generate a new address assignment command, and send it to the upper side.

[0082] Figure 6B The device address assignment method comprises: step (S65), the controller 13 sends an address assignment command to the upper side of the highest-level voltage detection circuit via the second communication circuit 12; step (S66), taking the result obtained by subtracting the value of the data field of the address assignment command received by the voltage detection circuit from the upper side from the provided correction value as the device address, and saving it to the device address holding circuit 21; and step (S67), reducing the value of the data field of the address assignment command received by the voltage detection circuit from the upper side to generate a new address assignment command, and sending it to the lower side.

[0083] In addition, you can also Figure 1B As shown, a communication circuit 14 is provided in place of the first communication circuit 11 and the second communication circuit 12. The communication circuit 14 may perform unidirectional communication instead of bidirectional communication.

[0084] As described above, the voltage measuring device 100 according to the first embodiment is a voltage measuring device having a plurality of voltage detection circuits for measuring the voltage of a plurality of unit cells connected in series, and the voltage detection circuits include: a device address generating circuit for generating a device address based on a first address assignment command received from the voltage detection circuit at the preceding stage; and an address assignment command generating circuit for generating a second address assignment command based on the first address assignment command and sending the command to the voltage detection circuit at the succeeding stage.

[0085] Here, it may be that, when the end of one side of the plurality of voltage detection circuits is set as the lowest level and the end of the other side is set as the highest level, the voltage detection circuit of the preceding level is one side of the voltage detection circuit on the lower side and the voltage detection circuit on the upper side, and the voltage detection circuit of the succeeding level is the other side of the voltage detection circuit on the lower side and the voltage detection circuit on the upper side, the address assignment command generating circuit generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the lower side, and sends it to the voltage detection circuit on the upper side, and generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the upper side, and sends it to the voltage detection circuit on the lower side.

[0086] Here, the device address generation circuit may make the device address generated according to the first address assignment command received from the lower voltage detection circuit the same as the device address generated according to the first address assignment command received from the upper voltage detection circuit. Here, the first address assignment command may include a data field.

[0087] Here, the device address generation circuit may generate the device address using the value of the data field.

[0088] Here, the address assignment command generating circuit may generate the second address assignment command to decrease or increase the value of the data field.

[0089] Here, when the device address generating circuit receives the first address assigning command from the voltage detecting circuit on the lower side, the device address generating circuit may set the value of the data field included in the received address assigning command as the device address.

[0090] Here, when receiving the first address assignment command from the voltage detection circuit on the upper side, the device address generation circuit may set a value obtained by subtracting the value of the data field from a correction value as the device address.

[0091] Here, the address assignment command generating circuit may generate the second address assignment command by reducing a value of the data field included in the first address assignment command received from the lower voltage detection circuit.

[0092] Here, the second address assigning command may be generated by reducing the value of the data field of the first address assigning command received from the upper voltage detection circuit.

[0093] Here, the voltage measuring device may include a controller connected to the voltage detection circuit at the lowest level among the plurality of voltage detection circuits and connected to the voltage detection circuit at the highest level, and transmits the address assignment command.

[0094] Here, the correction value may be included in the address assignment command.

[0095] Here, the correction value may be a preset value.

[0096] Here, the voltage measuring device may include a battery pack including the plurality of unit cells connected in series.

[0097] In addition, the voltage detection circuit of the first embodiment is a voltage detection circuit included in a voltage measurement device having a plurality of voltage detection circuits and measuring a cell voltage of a plurality of cells connected in series, and includes: a device address generation circuit that generates a device address based on a first address assignment command received from the voltage detection circuit of the preceding stage; and an address assignment command generation circuit that generates a second address assignment command based on the first address assignment command and sends it to the voltage detection circuit of the following stage. In addition, the device address generation method of the first embodiment is a device address generation method in a voltage measurement device having a plurality of voltage detection circuits and measuring a cell voltage of a plurality of cells connected in series, and includes: a device address is generated based on a first address assignment command received from the voltage detection circuit of the preceding stage, and a second address assignment command is generated based on the first address assignment command and sent to the voltage detection circuit of the following stage.

[0098] (Implementation Method 2)

[0099] The voltage detection circuit, the voltage measuring device 100, the battery system 10 and the voltage measuring method according to the second embodiment use Figures 7 to 9B , the description will focus on the differences from the above-mentioned implementation mode.

[0100] Figure 7 1 is a block diagram of a voltage detection circuit according to Embodiment 2. Figure 3 The difference is that the upper device address generation circuit 272 has an adder 279 instead of the subtractor 277, and the lower device address generation circuit 282 has an adder 289 instead of the subtractor 287. The following description will focus on the differences. Figure 7 Same structure.

[0101] In implementation mode 2, the lower device address generation circuit 281 extracts the value of the data field included in the address assignment command and outputs it as the device address, the lower sub-device address generation circuit 282 generates a device address of a secondary voltage detection circuit by increasing the value of the data field included in the address assignment command, the upper device address generation circuit 271 subtracts the value of the data field included in the address assignment command from the provided correction value and outputs it as the device address, and the upper sub-device address generation circuit 272 increases the value of the data field included in the address assignment command and generates the device address of the secondary voltage detection circuit.

[0102] also, Figure 7 As shown, the voltage detection circuit of the second embodiment is different from the voltage detection circuit of the first embodiment ( Figure 3 ) is that, in the lower-side sub-device address generation circuit 282 and the upper-side sub-device address generation circuit 272, the subtractors used for generating the sub-device addresses are changed to adders.

[0103] Furthermore, the lower-side sub-device address generation circuit 282 extracts the value of the data field from the received address assignment command, and outputs the value added by 1 by the adder as the sub-device address.

[0104] Likewise, the upper-side slave device address generation circuit 272 outputs a value obtained by adding 1 to the value of the data field as the slave device address.

[0105] Furthermore, as an operation example when there is a problem in the communication path, since the device address is used to identify each voltage detection circuit, it may be set to 1, 2, 3, and 4 in ascending order from the lowest voltage detection circuit.

[0106] Figure 8 This is a diagram for explaining the address assignment command related to the second implementation mode.

[0107] Figure 8 The flow of address assignment commands when a failure occurs in the communication path between the voltage detection circuit 2 and the voltage detection circuit 3 is shown.

[0108] The MCU transmits an address assignment command for setting the value of the data field to 1 to the lower side of the voltage detection circuit 4 via the first communication circuit 11 .

[0109] The lower device address generation circuit 281 of the voltage detection circuit 4 extracts the data field, outputs the value 1 as the device address, and stores it in the device address holding circuit 21. The lower sub-device address generation circuit 282 adds 1 to the extracted data field value 1, and outputs the result 2 as the sub-device address. The lower address assignment command generation circuit 283 generates a new address assignment command that sets the value of the data field to 2, and sends it to the voltage detection circuit 3 through the upper communication circuit 25.

[0110] Similarly, the voltage detection circuit 3 that has received the address assignment command with the data field being 2 stores the value 2 of the data field in the device address holding circuit 21 .

[0111] The MCU transmits an address assignment command for setting the value of the data field to 1 to the upper side of the voltage detection circuit 1 via the second communication circuit 12 .

[0112] The upper device address generation circuit 271 of the voltage detection circuit 1 outputs the result 4 obtained by subtracting the value 1 of the extracted data field from the correction value as the device address, and stores it in the device address holding circuit 21. The upper sub-device address generation circuit 272 outputs the result 2 obtained by adding 1 to the value 1 of the extracted data field as the sub-device address. The upper address assignment command generation circuit 273 generates a new address assignment command that sets the value of the data field to 2, and sends it to the voltage detection circuit 2 through the lower communication circuit 26.

[0113] Similarly, the voltage detection circuit 2 that has received the address assignment command with the data field being 2 stores the result 3 obtained by subtracting the value 2 of the data field from the correction value in the device address holding circuit 21 .

[0114] In this way, the device addresses 4 to 1 are correctly set for the voltage detection circuits 1 to 4.

[0115] In addition, if Figure 7 As shown, in the voltage detection circuit of embodiment 2, even when there is an obstacle in the communication path between the voltage detection circuits, the voltage detection circuit on the lower side of the obstacle can set the device address by the address assignment command from the lower side, and the voltage detection circuit on the upper side of the obstacle can set the device address by the address assignment command from the upper side.

[0116] then, Fig. 9A , Fig. 9B This is a diagram showing a device address assignment method according to the second embodiment. Fig. 9A This is the case where the controller 13 sends an address assignment command from the bottom side. Fig. 9B This is the case where the controller 13 sends an address assignment command from the upper side.

[0117] Fig. 9AThe device address assignment method comprises: step (S91), the controller 13 sends an address assignment command to the lower side of the lowest voltage detection circuit via the first communication circuit 11; step (S92), using the value of the data field of the address assignment command received from the lower side by the voltage detection circuit as the device address, and saving it in the device address holding circuit 21; and step (S93), increasing the value of the data field of the address assignment command received from the lower side by the voltage detection circuit to generate a new address assignment command, and sending it to the upper side.

[0118] Fig. 9B The device address assignment method comprises: step (S95), the controller 13 sends an address assignment command to the upper side of the uppermost voltage detection circuit via the second communication circuit 12; step (S96), taking the result obtained by subtracting the value of the data field of the address assignment command received by the voltage detection circuit from the upper side from the provided correction value as the device address, and saving it to the device address holding circuit 21; and step (S97), increasing the value of the data field of the address assignment command received by the voltage detection circuit from the upper side to generate a new address assignment command, and sending it to the lower side.

[0119] The battery pack system 10 according to the second embodiment is constituted by the voltage measuring device 100 described above and a battery pack 200 in which a plurality of unit cells 20 are connected in series.

[0120] As described above, in the voltage measuring device 100 according to the second embodiment, the address assignment command generating circuit generates the second address assignment command by increasing the value of the data field included in the first address assignment command received from the lower voltage detection circuit.

[0121] Here, the second address assigning command may be generated by increasing the value of the data field of the first address assigning command received from the voltage detection circuit on the upper side.

[0122] (Implementation 3)

[0123] The voltage detection circuit, the voltage measuring device 100, the battery system 10 and the voltage measuring method according to the third embodiment use Figure 10 to Figure 12B , the description will focus on the differences from the above-mentioned implementation mode.

[0124] In implementation mode 3, the lower device address generation circuit 281 extracts the value of the data field included in the address assignment command and outputs it as the device address, the lower sub-device address generation circuit 282 reduces the value of the data field included in the address assignment command and generates the device address of the secondary voltage detection circuit, the upper device address generation circuit 271 extracts the value of the data field included in the address assignment command and outputs it as the device address, and the upper sub-device address generation circuit 272 increases the value of the data field included in the address assignment command and generates the device address of the secondary voltage detection circuit.

[0125] exist Fig.10 A block diagram of a voltage detection circuit according to Embodiment 3 is shown in FIG. Figure 3 The difference is that the upper device address generation circuit 271 does not have a subtractor 275, and the upper sub-device address generation circuit 272 has an adder 279 instead of a subtractor 277. The following description will focus on the difference. Fig.10 Same structure.

[0126] also, Fig.10 and Figure 7 The voltage detection circuit of FIG. 27 is different in that the subtractor 275 used for generating the device address in the upper device address generating circuit 271 is removed.

[0127] Furthermore, the upper device address generation circuit 271 extracts the value of the data field of the received address assignment command, and stores it in the device address holding circuit 21 as a device address.

[0128] At the same time, the upper-side sub-device address generation circuit 272 uses an adder to add 1 to the value of the extracted data field and outputs it as the sub-device address.

[0129] Then, in Fig.11 , as an operation example when there is a failure in the communication path, a flow of address assignment commands when there is a failure in the communication path between the voltage detection circuit 2 and the voltage detection circuit 3 is shown.

[0130] according to Fig.11 , the MCU sends an address assignment command to the lower side of the voltage detection circuit 4 via the first communication circuit 11. The data field of the address assignment command specifies 4, which is the number of voltage detection circuits.

[0131] Furthermore, when the lower communication circuit 26 of the voltage detection circuit 4 receives the address assignment command, the lower device address generation circuit 281 extracts the data field, outputs the value 4 as the device address, and stores it in the device address holding circuit 21. The lower sub-device address generation circuit 282 subtracts 1 from the extracted data field value 4, and outputs the result 3 as the sub-device address. The lower address assignment command generation circuit 283 generates a new address assignment command for setting the sub-device address 3 in the data field, and sends it to the voltage detection circuit 3 via the upper communication circuit 25.

[0132] Similarly, the voltage detection circuit 3 that has received the address assignment command with the data field being 3 stores the value 3 of the data field in the device address holding circuit 21 .

[0133] The MCU transmits an address assignment command to the upper side of the voltage detection circuit 1 via the second communication circuit 12. 1 is designated in the data field of the address assignment command.

[0134] When the upper communication circuit 25 of the voltage detection circuit 1 receives the address assignment command, the upper device address generation circuit 271 outputs the value 1 of the extracted data field as the device address and stores it in the device address holding circuit 21. The upper sub-device address generation circuit 272 outputs the result 2 obtained by adding 1 to the value 1 of the extracted data field as the sub-device address. The upper address assignment command generation circuit 273 generates a new address assignment command that sets the sub-device address 2 in the data field, and sends it to the voltage detection circuit 2 through the lower communication circuit 26.

[0135] Similarly, the voltage detection circuit 2 that has received the address assignment command with the data field being 2 stores the extracted data field value 2 in the device address holding circuit 21 .

[0136] In this way, the device addresses 1 to 4 are correctly set to the voltage detection circuits 1 to 4.

[0137] Therefore, in the voltage measuring device 100 according to embodiment 3, even when there is an obstruction in the communication path between the voltage detection circuits, the voltage detection circuit on the lower side of the obstruction can set the device address by an address assignment command from the lower side, and the voltage detection circuit on the upper side of the obstruction can set the device address by an address assignment command from the upper side.

[0138] then, Fig. 12A , Fig. 12B This is a diagram showing a device address assignment method according to the third embodiment. Fig. 12A This is the case where the controller 13 sends an address assignment command from the bottom side. Fig. 12B This is the case where the controller 13 sends an address assignment command from the upper side.

[0139] Fig. 12A The device address assignment method comprises: step (S121), the controller 13 sends an address assignment command to the lower side of the lowest voltage detection circuit via the first communication circuit 11; step (S122), using the value of the data field of the address assignment command received by the voltage detection circuit from the lower side as the device address, and saving it in the device address holding circuit 21; and step (S123), reducing the value of the data field of the address assignment command received by the voltage detection circuit from the lower side to generate a new address assignment command, and sending it to the upper side.

[0140] Fig. 12B The device address assignment method comprises: step (S125), the controller 13 sends an address assignment command to the upper side of the uppermost voltage detection circuit via the second communication circuit 12; step (S126), using the value of the data field of the address assignment command received by the voltage detection circuit from the upper side as the device address, and saving it in the device address holding circuit 21; and step (S127), increasing the value of the data field of the address assignment command received by the voltage detection circuit from the upper side to generate a new address assignment command, and sending it to the lower side.

[0141] As described above, in the voltage measuring device 100 related to embodiment 3, the device address generating circuit, when receiving the first address assigning command from the voltage detecting circuit on the lower side, sets the value of the data field included in the received first address assigning command to the device address, and when receiving the first address assigning command from the voltage detecting circuit on the upper side, sets the value of the data field included in the received first address assigning command to the device address; the address assigning command generating circuit generates the second address assigning command by reducing the value of the data field included in the first address assigning command received from the voltage detecting circuit on the lower side, and generates the second address assigning command by increasing the value of the data field included in the first address assigning command received from the voltage detecting circuit on the upper side.

[0142] The battery pack system 10 according to the third embodiment is constituted by the voltage measuring device 100 described above and a battery pack 200 formed by connecting a plurality of unit cells 20 in series.

[0143] Industrial Applicability

[0144] The present invention is useful as, for example, a voltage measuring device, a voltage detection circuit, and a device address generating method for vehicle-mounted use.

[0145] Description of symbols

[0146] 1~4 Voltage detection circuit

[0147] 10 Battery System

[0148] 11 1st communication circuit

[0149] 12. Second communication circuit

[0150] 13 Controller

[0151] 14 Communication circuit

[0152] 20 cell battery

Claims

1. A voltage measuring device comprising a plurality of voltage detection circuits for measuring cell voltages of a plurality of cells connected in series, wherein: The voltage detection circuit has: a device address generating circuit that generates a device address according to a first address assignment command received from the voltage detecting circuit at a previous stage; and The address assignment command generating circuit generates a second address assignment command based on the first address assignment command and sends the second address assignment command to the secondary voltage detection circuit. When one end of the plurality of voltage detection circuits is set as the lowest stage and the other end is set as the highest stage, The voltage detection circuit at the preceding stage is one of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; The voltage detection circuit at the rear stage is the other of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; The address assignment command generating circuit generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the lower side, and sends the second address assignment command to the voltage detection circuit on the upper side, and generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the upper side, and sends the second address assignment command to the voltage detection circuit on the lower side, The device address generation circuit makes the device address generated in accordance with the first address assignment command received from the lower voltage detection circuit the same as the device address generated in accordance with the first address assignment command received from the upper voltage detection circuit.

2. The voltage measuring device according to claim 1, wherein: The first address assignment command includes a data field.

3. The voltage measuring device according to claim 2, wherein: The device address generation circuit generates the device address using the value of the data field.

4. The voltage measuring device according to claim 2, wherein: The address assignment command generating circuit generates the second address assignment command in which the value of the data field is decreased or increased.

5. The voltage measuring device according to claim 2, wherein: When receiving the first address assignment command from the voltage detection circuit on the lower side, the device address generation circuit sets the value of the data field included in the received address assignment command as the device address.

6. The voltage measuring device according to claim 2, wherein: When receiving the first address assignment command from the voltage detection circuit on the upper side, the device address generation circuit sets a value obtained by subtracting the value of the data field from the correction value as the device address.

7. The voltage measuring device according to claim 2, wherein: The address assignment command generation circuit generates the second address assignment command by reducing the value of the data field included in the first address assignment command received from the lower voltage detection circuit.

8. The voltage measuring device according to claim 2, wherein: The second address assigning command is generated by reducing the value of the data field of the first address assigning command received from the upper voltage detection circuit.

9. The voltage measuring device according to claim 2, wherein: The address assignment command generating circuit generates the second address assignment command by increasing a value of the data field included in the first address assignment command received from the lower voltage detection circuit.

10. The voltage measuring device according to claim 2, wherein: The second address assigning command is generated by increasing the value of the data field of the first address assigning command received from the upper voltage detection circuit.

11. The voltage measuring device according to claim 2, wherein: The above device address generation circuit, When the first address assignment command is received from the voltage detection circuit on the lower side, the value of the data field included in the received first address assignment command is set as the device address; When the first address assignment command is received from the voltage detection circuit on the upper side, the value of the data field included in the received first address assignment command is set as the device address; The above address is assigned to the command generation circuit, generating the second address assigning command by reducing the value of the data field included in the first address assigning command received from the voltage detection circuit on the lower side; The second address assigning command is generated by increasing the value of the data field included in the first address assigning command received from the upper voltage detection circuit.

12. The voltage measuring device according to claim 1, wherein: The voltage measuring device includes a controller connected to the voltage detection circuit at the lowest level among the plurality of voltage detection circuits and connected to the voltage detection circuit at the highest level, and the controller transmits the first address assignment command.

13. A voltage detection circuit, comprising a voltage measuring device including a plurality of voltage detection circuits for measuring a voltage of a plurality of cells connected in series, wherein the voltage detection circuit is characterized in that: have: a device address generating circuit that generates a device address according to a first address assignment command received from the voltage detecting circuit at a previous stage; and The address assignment command generating circuit generates a second address assignment command based on the first address assignment command and sends the second address assignment command to the secondary voltage detection circuit. When one end of the plurality of voltage detection circuits is set as the lowest stage and the other end is set as the highest stage, The voltage detection circuit at the preceding stage is one of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; The voltage detection circuit at the rear stage is the other of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; The address assignment command generating circuit generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the lower side, and sends the second address assignment command to the voltage detection circuit on the upper side, and generates the second address assignment command based on the first address assignment command received from the voltage detection circuit on the upper side, and sends the second address assignment command to the voltage detection circuit on the lower side, The device address generation circuit makes the device address generated in accordance with the first address assignment command received from the lower voltage detection circuit the same as the device address generated in accordance with the first address assignment command received from the upper voltage detection circuit.

14. A device address generation method in a voltage measurement device having a plurality of voltage detection circuits and measuring a plurality of unit cells connected in series, characterized in that: generating a device address according to a first address assignment command received from the voltage detection circuit of the preceding stage; According to the first address assignment command, a second address assignment command is generated and sent to the secondary voltage detection circuit. When one end of the plurality of voltage detection circuits is set as the lowest stage and the other end is set as the highest stage, The voltage detection circuit at the preceding stage is one of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; The voltage detection circuit at the rear stage is the other of the voltage detection circuit at the lower side and the voltage detection circuit at the upper side; generating the second address assignment command based on the first address assignment command received from the voltage detection circuit on the lower side and sending it to the voltage detection circuit on the upper side, and generating the second address assignment command based on the first address assignment command received from the voltage detection circuit on the upper side and sending it to the voltage detection circuit on the lower side, The device address generated in accordance with the first address assignment command received from the lower voltage detection circuit is made identical to the device address generated in accordance with the first address assignment command received from the upper voltage detection circuit.

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