Memory device with non-uniform refresh

Abstract

An integrated circuit memory device includes: a memory cell array configured into a plurality of memory banks. Each memory bank includes a plurality of segments. A register storage device stores segment-by-segment values ​​representing segment-by-segment refresh parameters. Refresh logic refreshes each segment according to the corresponding segment-by-segment value.

Description

Technical Field

[0001] The disclosure herein relates to memory systems, and more particularly to memory devices, controllers, and methods for varying refresh rates on a segment-by-segment basis. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings and in which like reference numerals refer to like elements and in which:

[0003] Figure 1 One embodiment of a memory system employing non-uniform refresh is shown.

[0004] Figure 2 Shown in Figure 1 A flow chart of one example of operations performed during operation of a memory system.

[0005] Figure 3 Shown for Figure 1 A code / decode table of one embodiment of a mode refresh bit encoding / decoding of a memory system. DETAILED DESCRIPTION

[0006] Embodiments of memory devices, controllers, associated methods, and integrated circuits are disclosed herein. One embodiment of a memory device includes a memory cell array configured into a plurality of memory banks. Each memory bank includes a plurality of segments. A register storage device stores a segment-by-segment value representing a segment-by-segment refresh rate. Refresh logic refreshes each segment according to the corresponding segment-by-segment value. By non-uniformly varying the segment-by-segment refresh rate based on an acceptable error rate associated with data stored in each segment, substantial power savings attributable to refresh operations can be achieved.

[0007] Certain embodiments described herein provide an apparatus and method that varies the refresh rate on a segment-by-segment basis and according to pre-specified error criteria associated with the data stored in each segment. The refresh rate can thus be increased or decreased to correspondingly refresh the memory cells in a manner that tightens or relaxes read data errors due to refresh operations.

[0008] refer to Figure 1, a memory system, generally designated as 100, is shown, which includes a memory controller 102 coupled to a memory device 104 via a bus 106. For one embodiment, the memory controller is a DRAM controller, wherein the memory device is implemented as a dynamic random access (DRAM) memory device. In some embodiments, the memory controller and the memory device may be embodied as an integrated circuit or chip. Other embodiments may use the memory controller as a circuit in a general-purpose processor. Specific embodiments of the DRAM memory controller and the memory device may comply with various DRAM standards, including double data rate (DDR) variants, low power (LPDDR) versions, and graphics (GDDR) types. Other embodiments may include, for example, multi-chip modules using stacked memory dies or stacked packages. Such embodiments may be used with memory modules. Additional embodiments may stack memory dies and logic dies together in a common package, or in separate packages stacked on top of each other.

[0009] Further references Figure 1 , the memory controller 102 includes a controller interface 107 for transmitting data, commands, and control signals between the memory controller and the memory device 104. The command generation circuit 109 generates read / write and mode register write (MRW) commands for transmission to the memory device. For one embodiment, as described below, the command generation circuit 109 generates an MRW command for storing a value associated with a segment-by-segment refresh rate in a mode register on the memory device. The physical memory allocator 112 determines the bank and segment address of the physical memory corresponding to the memory requested by the host / processor 114. The memory controller may also include automatic refresh logic 116 to generate refresh commands applied externally to the DRAM memory device during an automatic refresh operation. Automatic refresh occurs when the memory system is in an active state to support an electronic device in active operation.

[0010] Continue to refer Figure 1 , the host / processor 114 may take the form of a general purpose processor that responds to instructions generated by an operating system (OS) 118. The OS, in turn, allocates logical memory in response to memory requested by a given application 120, and for one embodiment, generates tags for the allocated memory, as described more fully below.

[0011] Further references Figure 1, the memory device 104 includes an array of volatile memory cells, which in one embodiment are organized into memory banks 122 and 124. Each memory bank is further organized into a plurality of addressable segments 126. In one embodiment, each memory device includes eight memory banks, wherein each memory bank has eight segments. The memory device may include any memory integrated circuit (IC) chip having volatile memory cells that maintain a given charge state through periodic refresh operations.

[0012] Continue to refer Figure 1 To perform refresh operations on a segment-by-segment basis, one embodiment of the memory device integrates refresh logic 128. Refresh logic 128 controls internal DRAM operations for self-refresh, auto-refresh, or both. In one embodiment, refresh logic 128 includes a refresh counter that tracks the next address to be refreshed. Mode register circuit 130 provides register storage for a segment-by-segment refresh rate value based on an acceptable data error threshold or BER generated by application 120 and OS 118. Refresh logic 128 accesses the register value when performing a segment-by-segment non-uniform self-refresh operation.

[0013] Further references Figure 1 , the memory device 104 includes a memory interface 131 that receives data, commands, and control signals from the memory controller 102. As described above, for one embodiment, the controller interface 107 on the memory controller communicates each segment-by-segment refresh rate value for a given segment to the memory interface 131 with an accompanying mode register write (MRW) command. In response to the MRW command, the segment-by-segment refresh rate value is loaded and stored in the mode register circuit 130.

[0014] For some embodiments, the memory device 104 may employ temperature sensing circuitry 132, such as a temperature sensor, to operate in concert with a temperature compensated self-refresh (TCSR) technique to assist in the segment-by-segment non-uniform self-refresh operation described herein. Other embodiments may employ temperature sensing circuitry on the memory controller 102. For one embodiment, a global refresh rate for the memory device segments may be established via a TCSR approach, wherein a segment-by-segment non-uniform refresh rate multiplier is stored in the mode register circuitry 130 as a segment-by-segment refresh rate value selectively applied to the global refresh rate for finer refresh rate control.

[0015] In operation, in both self-refresh and auto-refresh cases, the "segment-by-segment non-uniform refresh" operation is performed by Figure 1Although most of the discussion herein focuses on embodiments that vary the refresh rate on a segment-by-segment basis during a self-refresh operation, auto-refresh typically occurs during active operation of an electronic device, while self-refresh occurs when the electronic device is in a "sleep" or inactive mode to reduce power consumption. Self-refresh is timed by the DRAM itself, independent of the memory controller, using, for example, a ring oscillator and a counter to generate row addresses on chip. The controller triggers auto-refresh on a command-by-command basis, where each auto-refresh command will instruct the DRAM to refresh one or more rows.

[0016] use Figure 1 An electronic device that uses a memory system typically runs one or more applications for a user. Prior to actual operation, a preconfiguration process will be performed to initialize and optimize the memory system settings for the application. A given application may need to load different types of data into the memory device 104, such as program code and / or bulk data utilized by the application. In some cases, it may be desirable to have a very low error threshold associated with the program code data, such as a bit error rate (BER), to ensure proper program execution. On the other hand, in some cases, bulk data such as image or audio data can be managed at a higher error rate while still being able to achieve acceptable use of the application.

[0017] Reference now Figure 2 In one embodiment, to manage the classification of different types of data using different acceptable BER parameters, at 202, the OS 118 and the application 120 collaborate to classify the requested memory according to an acceptable data error threshold, such as BER, during memory allocation, and at 204, mark the requested memory according to the classification. At 206, the memory controller 102 receives the allocation information from the host / processor 114 and generates a physical memory allocation based on the memory bank and segment addresses. At 208, the memory controller also writes mode register bit information for non-uniform refresh operation into the memory device mode register. At 210, the memory controller also issues auto-refresh commands during operation. In one embodiment, the rate at which the memory controller issues auto-refresh is the same as the rate used when non-uniform refresh (NUR) is not used. In another embodiment, when NUR is used, the memory controller uses a different rate for issuing auto-refresh commands.

[0018] Figure 3An exemplary mode register decoder diagram for mode register bits participating in a segment-by-segment refresh operation according to one embodiment is shown. The diagram is organized into rows representing eight segments (labeled S0-S7) and columns representing eight banks (labeled B0-B7). Each bank and segment includes a set of mode bits to indicate refresh parameter values, such as an absolute refresh rate, or a modifier value for modifying a global refresh rate. For one embodiment, the bank / segment bits are set according to the following code:

[0019] 00: Refresh the bank or segment at a nominal value (e.g. 64ms).

[0020] 01: The refresh of the bank or segment took 2 times longer than the nominal value (128 ms).

[0021] 10: Refresh of a bank or segment takes 4 times longer than nominal (256 ms).

[0022] 11: The refresh of a bank or segment takes 8 times longer (ls) than the nominal value.

[0023] In the case where both the bank and segment bits display codes that specify a refresh rate other than the nominal rate, the bank code replaces the segment code. Although two-bit encoding is shown and described herein for a particular embodiment, additional bits may be provided to provide even finer granularity. For example, additional bits may specify additional refresh rates / modifiers and / or specify separate segments.

[0024] Further references Figure 3 , as an example, the first portion of the figure shows at 302 a segment code "11" for the fifth segment S4. At 304, the nominal code "00" for memory bank B0 specifies a refresh rate of 64ms for segments S0-S3 and S5-S7 of memory bank B0, while the refresh rate for segment S4 is specified as 1s at 306. Code 01 for memory bank B1 replaces code 11 for segment S4, and thus specifies a refresh rate of 128ms for all eight segments of memory bank B1 (shown at 210). Although Figure 3 A decoder chart is shown that specifies absolute settings referenced to nominal values, but the code may alternatively represent segment-by-segment multiplication factors to be applied to global refresh settings, such as those associated with a temperature compensated self-refresh scheme (TCSR).

[0025] Typically, TCSR provides a way to reduce power consumption when the memory device is operating under self-refresh conditions. The temperature detection circuit 132 detects the ambient temperature of the memory device, wherein the global refresh rate change is performed in response to the detected temperature. The increase / decrease in the refresh rate generally compensates for the increased / decreased leakage rate in the volatile memory cells at different temperatures. In such an embodiment, the temperature detection circuit 132 detects the operating temperature of the memory device 104, generates corresponding temperature information, and provides the temperature information to the refresh logic 128. The refresh logic can then apply the appropriate global refresh rate setting (stored in the mode register circuit 130) based on the temperature, and apply a segment-by-segment multiplier to the non-uniform refresh rate between the segments based on the non-uniform bits stored in the mode register circuit.

[0026] In one embodiment, the memory controller issues auto-refresh commands at the same rate as when NUR is not used. When the refresh counter points to a row in a segment with a longer refresh time assigned by the NUR bit in the mode register, the refresh logic on the DRAM periodically skips the execution of refreshes. For example, when the assigned refresh rate for a segment is 128ms and the memory controller issues auto-refresh commands every 64ms, the refresh logic will skip every second refresh of the segment.

[0027] At the memory controller, the auto-refresh controller may employ an alternative form of segment-by-segment refresh to perform the auto-refresh operation. As described above, the auto-refresh typically occurs during active operation of the electronic device. Knowing the acceptable bit error rates for the different allocated memory regions, a variable segment-by-segment refresh rate may be implemented by the auto-refresh controller on the memory controller by, for example, skipping the appropriate segment when an external global refresh command is issued.

[0028] The memory systems, devices, and methods described above provide finer granularity segment-by-segment non-uniform refresh, which allows for more efficient power savings achievable by the memory system.The embodiments described herein are well suited for mobile device applications where power efficiency is a key concern.

[0029] When such data and / or instruction-based representations of the above-described circuits are received within a computer system via one or more computer-readable media, such data and / or instruction-based representations may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs to generate a representation or image of the physical manifestation of such circuits, including but not limited to netlist generation programs, placement and routing programs, etc. This representation or image may then be used in device fabrication, for example, by enabling the generation of one or more masks used to form various components of the circuits during the device fabrication process.

[0030] In the foregoing description and in the accompanying drawings, specific terms and accompanying drawings have been set forth to provide a thorough understanding of the present invention. In some cases, terms and symbols may imply specific details that are not required for implementing the present invention. For example, any of a specific number of bits, signal path width, signaling or operating frequency, component circuits or devices, etc. may be different from those described above in alternative embodiments. Moreover, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single-conductor signal links may alternatively be multi-conductor signal links. The signal and signaling paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, signals described or depicted as having a high logic level valid or a low logic level valid may have opposite logic levels. Component circuits within an integrated circuit device may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology, or any other technology that may implement logic and analog circuits. With regard to terminology, when a signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a specific condition, the signal is referred to as "assertion". Conversely, a signal is "de-asserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or a floating state that may occur when the signal driving circuit transitions to a high impedance state, such as an open drain or open collector state). When a signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by the context) a signal on a signal line coupled between the signal driving circuit and the signal receiving circuit, the signal driving circuit is said to "output" the signal to the signal receiving circuit. When a signal is asserted on the signal line, the signal line is said to be "active," and when the signal is de-asserted, the signal line is said to be "de-active." In addition, a prefix symbol " / " appended to a signal name indicates that the signal is a low-state active signal (i.e., the asserted state is a logic low state). A dash on a signal name (e.g. ) is also used to indicate an active low signal. The term "coupled" is used herein to refer to a direct connection as well as a connection through one or more intermediate circuits or structures. Integrated circuit device "programming" may include, for example, but is not limited to, loading control values ​​into registers or other storage circuits within the device in response to host instructions to control operational aspects of the device, establish a device configuration, or control operational aspects of the device through a one-time programming operation (e.g., blowing fuses within configuration circuits during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as bundling) to establish a specific device configuration or operational aspect of the device. The term "exemplary" is used to indicate an example, not a preference or requirement.

Claims

1. An integrated circuit (IC) memory device, comprising: A memory cell array configured into a plurality of memory banks, each memory bank including a plurality of segments, each segment being accessible via a memory bank address and a segment address; an interface circuit for receiving a segment-by-segment value representing a segment-by-segment refresh rate, the segment-by-segment value received from a memory controller disposed external to the IC memory device, wherein the refresh rate is determined based on an error threshold associated with a type of data loaded into the memory device; a register storage device for storing a set of mode bits representing the segment-by-segment value across each of the plurality of memory banks; as well as self-refresh logic for refreshing each segment according to a corresponding said segment-by-segment value during a self-refresh mode of operation; and Wherein, in a case where the memory bank and the segments in the memory bank are assigned different specified refresh rates instead of the nominal refresh rate, the specified refresh rate for the memory bank is used to replace the specified refresh rate for the segments.

2. The IC memory device of claim 1, wherein the memory cell array comprises dynamic random access memory (DRAM) memory cells.

3. The IC memory device of claim 2, wherein the segment-by-segment refresh rate represents a refresh rate relative to a nominal refresh rate.

4. The IC memory device according to claim 1, further comprising: A temperature compensated refresh circuit is provided for cooperating with the refresh logic to refresh each segment based on temperature.

5. The IC memory device of claim 4, wherein the segment-by-segment refresh rate represents a multiplier value applied to a global temperature-based refresh rate determined by the temperature compensated refresh circuit.

6. An operation method in a memory device, the method comprising: storing data in a memory cell array comprising a plurality of memory banks, each memory bank comprising a plurality of segments, each segment being accessible via a memory bank address and a segment address; receiving, with an interface circuit, from a memory controller disposed external to the memory device, a segment-by-segment value representing a segment-by-segment refresh rate, wherein the refresh rate is determined based on an error threshold associated with a type of data loaded into the memory device; loading a set of mode bits representing the segment-by-segment value across each of the plurality of memory banks into a register storage device; as well as refreshing each segment according to the corresponding segment-by-segment value using self-refresh logic during a self-refresh mode of operation; and Wherein, in a case where the memory bank and the segments in the memory bank are assigned different specified refresh rates instead of the nominal refresh rate, the specified refresh rate for the memory bank is used to replace the specified refresh rate for the segments.

7. The method according to claim 6, wherein the refreshing comprises: Each segment is refreshed during an auto-refresh operation.

8. The method of claim 6, wherein the storing data is performed according to a dynamic random access memory (DRAM) protocol.

9. The method of claim 6, wherein the segment-by-segment refresh rate represents a refresh rate relative to a nominal rate.

10. The method according to claim 6, further comprising: A temperature-based refresh rate is generated to cooperate with the received segment-by-segment values ​​to refresh each segment based on temperature.

11. The method of claim 10, wherein the segment-by-segment refresh rate represents a multiplier value applied to a temperature-based refresh parameter generated by the temperature compensated refresh circuit.

12. The method of claim 11 , wherein loading the segment-by-segment values ​​into a register storage device comprises: The segment-by-segment values ​​are transferred to the register storage device in response to a mode register write (MRW) command.

13. An integrated circuit (IC) dynamic random access memory (DRAM) device comprising: A memory cell array configured into a plurality of memory banks, each memory bank comprising at least a first segment and a second segment, the first segment being accessible via a memory bank address and a first segment address, and the second segment being accessible via the memory bank address and the second segment address; an interface for receiving a first value representing a first refresh rate for refreshing the first segment, the interface for receiving a second value representing a second refresh rate for refreshing the second segment, the first value and the second value being received from a memory controller disposed external to the IC DRAM device, wherein the first refresh rate and the second refresh rate are determined based on an error threshold associated with a type of data loaded into the memory device; a mode register for storing a set of mode bits representing the first value and the second value for a given memory bank; as well as self-refresh logic for refreshing the first segment and the second segment according to the corresponding first value and the second value during a self-refresh mode of operation; and Wherein, in a case where the memory bank and the segments in the memory bank are assigned different specified refresh rates instead of the nominal refresh rate, the specified refresh rate for the memory bank is used to replace the specified refresh rate for the segments.

14. The IC DRAM device of claim 13, wherein: The first value and the second value may freely differ from each other.

15. The IC DRAM device of claim 13, wherein each of the first refresh rate and the second refresh rate represents an absolute refresh rate.

16. The IC DRAM device of claim 13, further comprising: temperature compensated refresh circuitry for cooperating with the refresh logic to refresh each segment based on temperature; and Wherein each of the first refresh rate and the second refresh rate represents a multiplier value applied to a global temperature-based refresh rate determined by the temperature compensated refresh circuit.

Images