System-on-chip and smart wearable devices

Abstract

The present invention discloses a system-level chip and an intelligent wearable device, wherein the system-level chip includes a power management chip, RAM, a main control subsystem, a sub-control subsystem and a plurality of functional subsystems; the main control subsystem, the sub-control subsystem and the functional subsystem all include an MCU; the main control subsystem, the sub-control subsystem and the functional subsystem are all connected to the RAM through a bus; the power management chip is used to provide power to the RAM, the main control subsystem, the sub-control subsystem and the plurality of functional subsystems. The present invention integrates the power management chip, RAM, the main control subsystem, the sub-control subsystem and the plurality of functional subsystems into a system-level chip, which not only reduces power consumption and cost, but also effectively reduces the space required for PCB layout, compared with the prior art that uses multiple chips to achieve the same function, thereby providing a solution with rich functional applications, low power consumption, no restrictions on PCB layout and low cost for intelligent wearable devices.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a system on chip (SoC) and a smart wearable device. Background Art

[0002] Smart wearable devices are a general term for wearable devices that are designed and developed using wearable technology to intelligently design daily wearables, such as watches, bracelets, glasses, clothing, etc. Among them, smart watches are the most widely used type of smart wearable devices.

[0003] For smart watches, an important feature is long standby and long battery life. Due to physical size limitations, all electronic components must be integrated into a dial with a diameter of about 40mm. If you want to integrate more functions into a smart watch, it will cause limitations in PCB layout and battery capacity. In addition, smart watches often cannot be equipped with large-capacity batteries. At the same time, due to the convenience of wearing them on the body, users often expect smart watches to be charged once a week or even two weeks. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the defects in the prior art that smart wearable devices cannot take into account low power consumption, multi-functions and PCB layout, and to provide a system-level chip and a smart wearable device.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] A first aspect of the present invention provides a system-level chip, including a power management chip, a RAM (Random Access Memory), a main control subsystem, a sub-control subsystem, and a plurality of functional subsystems; wherein different functional subsystems are used to implement different functions;

[0007] The main control subsystem, the auxiliary control subsystem and the functional subsystem all include an MCU (Microcontroller Unit);

[0008] The main control subsystem, the auxiliary control subsystem and the functional subsystem are all connected to the RAM via a bus;

[0009] The main control subsystem and the auxiliary control subsystem are connected to the functional subsystem via interrupt lines respectively, and the main control subsystem and the auxiliary control subsystem are used to respond to the interrupt signal sent by the functional subsystem in a time-sharing manner;

[0010] The power management chip is used to provide power for the RAM, the main control subsystem, the auxiliary control subsystem and the multiple functional subsystems.

[0011] Preferably, the RAM includes SRAM (Static Random-Access Memory) and DRAM (Dynamic Random Access Memory).

[0012] Preferably, the SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem are integrated into one chip, and are packaged with the DRAM and the power management chip through SIP.

[0013] Preferably, the system-level chip also includes ROM (Read-Only Memory), and the ROM is packaged with the chip integrating the SRAM, the main control subsystem, the sub-control subsystem and the functional subsystem, the DRAM and the power management chip through SIP (System In a Package).

[0014] Preferably, the system-level chip further includes a display subsystem for acquiring image data from the DRAM, and the display subsystem is integrated into the same chip with the SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem.

[0015] Preferably, the main control subsystem, the auxiliary control subsystem and the functional subsystem all have independent power domains.

[0016] Preferably, the system-on-chip is embedded with an RTOS (Real Time Operating System) operating system.

[0017] Preferably, the functional subsystem includes multiple ones of the following: a wireless modem subsystem, a Bluetooth subsystem, a Wi-Fi subsystem, a GPS (Global Positioning System) subsystem, and a camera subsystem.

[0018] A second aspect of the present invention provides an intelligent wearable device, comprising a touch screen, a plurality of sensors, and the system-level chip as described in the first aspect, wherein the touch screen and the sensors are electrically connected to the system-level chip respectively.

[0019] Preferably, the smart wearable device is a smart watch.

[0020] The positive progressive effect of the present invention is that the present invention integrates a power management chip, RAM, a main control subsystem, a sub-control subsystem and multiple functional subsystems into a system-level chip. Compared with the prior art of using multiple chips to achieve the same function, it not only reduces power consumption and cost, but also effectively reduces the space required for PCB layout, thereby providing smart wearable devices with rich functional applications, low power consumption, no restrictions on PCB layout and low-cost solutions.

[0021] In addition, in order to further reduce power consumption, the system-level chip provided by the present invention adopts a lightweight MCU and an ultra-low power consumption RTOS operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural block diagram of the system-on-chip provided in Example 1 of the present invention.

[0023] Figure 2 It is a schematic diagram of the connection relationship between each subsystem and RAM in Example 1 of the present invention.

[0024] Figure 3 This is a structural block diagram of another system-on-chip provided in Embodiment 1 of the present invention.

[0025] Figure 4 This is a structural block diagram of the smart wearable device provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0027] Example 1

[0028] This embodiment provides a system-level chip, such as Figure 1 As shown, it includes a power management chip, RAM, a main control subsystem, a sub-control subsystem and multiple functional subsystems.

[0029] The main control subsystem, the auxiliary control subsystem and the functional subsystem all include an MCU. Figure 1 As shown, the main control subsystem includes MCU-main control, the sub-control subsystem includes MCU-sub-control, the functional subsystem 1 includes MCU-1, the functional subsystem 2 includes MCU-2, and the functional subsystem N includes MCU-N. Each subsystem can be switched between working mode and sleep mode to achieve the purpose of low power consumption and power saving.

[0030] MCU, also known as single chip microcomputer or single chip microcomputer, is a chip-level computer that appropriately reduces the frequency and specifications of the central processing unit, and integrates peripheral interfaces such as memory, counter, USB, A / D conversion, UART, PLC, DMA, etc. on a single chip to perform different combination controls for different application scenarios. The MCU in this embodiment can be a processor with RISC architecture such as ARM Cortex-M / R series, MIPS (Microprocessor without InterlockedPipelined Stages), RISC-V, MCS8051, etc.

[0031] In some examples, the MCUs in the main control subsystem, the auxiliary control subsystem, and each functional subsystem are the same, for example, they are all ARM Cortex-M series processors. In other examples, the MCUs in the main control subsystem, the auxiliary control subsystem, and each functional subsystem are different, and different MCUs can be selected according to the functions implemented by the subsystem, and there is no specific limitation.

[0032] The main control subsystem, the auxiliary control subsystem and the functional subsystem are all connected to the RAM through a bus, and the main control subsystem and the auxiliary control subsystem are respectively connected to the functional subsystem through an interrupt line, and the main control subsystem and the auxiliary control subsystem are used to respond to the interrupt signal sent by the functional subsystem in a time-sharing manner, thereby realizing the transmission of message streams and data streams between the subsystems. In a specific example, the main control subsystem, the auxiliary control subsystem and the functional subsystem realize the shared RAM memory space through a unified memory access matrix.

[0033] In a specific implementation, if the main control subsystem is in working mode, the main control subsystem responds to the interrupt signals sent by each functional subsystem, and the auxiliary control subsystem is prohibited from responding to the interrupt signals sent by each functional subsystem. If the main control subsystem is in sleep mode or power-off, the auxiliary control subsystem responds to the interrupt signals sent by each functional subsystem, and the main control subsystem is prohibited from responding to the interrupt signals sent by each functional subsystem.

[0034] In an optional implementation, the main control subsystem and the sub-control subsystem are connected via an interrupt line, and the main control subsystem can respond to an interrupt signal sent by the sub-control subsystem no matter it is in working mode or sleep mode.

[0035] In a specific example, the main control subsystem can complete complex multimedia system applications, fully respond to user operations, and even execute complex user applications. The sub-control subsystem is mainly used for AOD (Always On Display) display and control of various external sensors when the main control subsystem is in sleep mode. Therefore, the main frequency, memory consumption and power consumption of the MCU in the main control subsystem are higher than those of the MCU in the sub-control subsystem. Each functional subsystem implements a separate function and is only turned on to work when needed. It enters a sleep state when not needed, and even needs to be powered off to completely save power consumption.

[0036] The power management chip is used to provide power for the RAM, the main control subsystem, the sub-control subsystem and the multiple functional subsystems. The power management chip in this embodiment can output multiple different voltages to provide power for different subsystems. In a specific example, the power management chip includes a PWM charger, a multi-channel DC-DC converter (Buck DC-DC), and a multi-channel linear regulator (LDO).

[0037] Different functional subsystems are used to implement different functions. The functional subsystems in this embodiment may include a wireless modem subsystem, a Bluetooth subsystem, a Wi-Fi subsystem, a GPS subsystem, a camera subsystem, and the like.

[0038] Among them, the wireless modem subsystem includes a wireless modem, which is used to realize functions such as answering / making calls and mobile data network. The wireless modem is generally composed of baseband processing, modulation and demodulation, signal amplification and filtering, equalization, etc., and is used to wirelessly transmit the digital signal of data communication on an analog channel with limited bandwidth. The Bluetooth subsystem is used to realize wireless communication with external devices within a short distance. The Wi-Fi subsystem is used to realize wireless Internet access. The GPS subsystem is used to realize real-time positioning and navigation functions on a global scale. The camera subsystem includes a camera, which is used to capture static images or videos.

[0039] In an optional implementation, the RAM includes SRAM and DRAM. In some examples, the DRAM may be LPDDR2, LPDDR3, etc. Among them, LPDDR (Low Power Double Data Rate SDRAM) is a type of DDR SDRAM (double data rate synchronous dynamic random access memory), which is a communication standard developed for low-power memory. LPDDR2 is the second-generation low-power memory technology, and LPDDR3 is the third-generation low-power memory technology.

[0040] Figure 2It is a schematic diagram for showing the connection relationship between various subsystems and RAM. Figure 2 As shown, the main control subsystem, the sub-control subsystem and the functional subsystem are all connected to the SRAM and DRAM through a bus, and the main control subsystem is connected to the sub-control subsystem and each functional subsystem through an interrupt line.

[0041] In an optional implementation, the above-mentioned SRAM, main control subsystem, auxiliary control subsystem and multiple functional subsystems are integrated into one chip, and packaged with DRAM and power management chip through SIP. Among them, SIP packaging is an electronic device packaging solution that integrates multiple functional chips, including processors, memories and other functional chips, into one package to achieve a basically complete function.

[0042] In this embodiment, since SRAM is integrated with the main control subsystem, the sub-control subsystem and multiple functional subsystems in one chip, SRAM can also be called on-chip SRAM, and DRAM can also be called off-chip DRAM. Among them, on-chip SRAM has the characteristics of low power consumption and high speed, but small memory capacity and high price. Off-chip DRAM has the characteristics of large memory capacity but high power consumption. In order to avoid excessive use of high-power off-chip DRAM, this embodiment classifies the message streams and data streams transmitted between the subsystems, and realizes the transmission of message streams and data streams by sharing the space of on-chip SRAM and off-chip DRAM, thereby reducing the power consumption of the system-level chip.

[0043] In an optional embodiment, Figure 3 As shown, the system-level chip also includes a ROM, and the ROM is packaged with the chip integrating the SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem, the DRAM and the power management chip through a SIP package. The ROM in this embodiment includes but is not limited to EMMC, NAND Flash, NOR Flash and other memories.

[0044] In a specific example, the ePoP packaging process is first used to stack ROM and DRAM on a chip that integrates SRAM, a main control subsystem, a sub-control subsystem and all functional subsystems, and then the FCCSP (FlipChip ChipScale Package, a chip-level packaging) packaging process is used to integrate it with the power management chip to obtain the system-level chip of this embodiment.

[0045] In an optional embodiment, the system-level chip further includes a display subsystem for acquiring image data from the DRAM, and the display subsystem is integrated into the same chip with the SRAM, the main control subsystem, the sub-control subsystem, and the functional subsystem. The main control subsystem or the sub-control subsystem is used to write the image data to be displayed into the DRAM, and the display subsystem reads the image data from the DRAM and processes it, and outputs it to an external display for display. In this embodiment, the display subsystem does not include an MCU.

[0046] In an optional implementation, the main control subsystem, the sub-control subsystem, and the functional subsystem all have independent power domains, that is, each subsystem can be powered on or off independently without affecting each other. In a specific example, the main control subsystem outputs a preset level signal to the power domain of the functional subsystem to control the power-on of the functional subsystem. In another specific example, the sub-control subsystem outputs a preset level signal to the power domain of the main control subsystem to control the power-on of the main control subsystem.

[0047] In an optional embodiment, the system-on-chip is embedded with an RTOS operating system. Wherein, unlike intelligent operating systems such as Android, Windows, and IOS, the RTOS operating system is a lightweight microkernel operating system that can be applied to an MCU controller, providing a response speed of microseconds, and is an ultra-low power operating system. In one example, each MCU in the system-on-chip is embedded with an RTOS operating system. In another example, some MCUs in the system-on-chip are embedded with an RTOS operating system. Specifically, it can be designed according to the resources required for each subsystem to implement different functions.

[0048] This embodiment integrates the power management chip, RAM, main control subsystem, auxiliary control subsystem and multiple functional subsystems into a system-level chip. Compared with the prior art of using multiple chips to achieve the same function, it not only reduces power consumption and cost, but also effectively reduces the space required for PCB layout, thereby providing smart wearable devices with rich functional applications, low power consumption, no restrictions on PCB layout and low-cost solutions.

[0049] Example 2

[0050] This embodiment provides a smart wearable device, such as Figure 4 As shown, it includes a touch screen, multiple sensors and the system-level chip described in Example 1, and the touch screen and the sensor are electrically connected to the system-level chip respectively. In this embodiment, the user can operate the content displayed on the smart wearable device through the touch screen, and the smart wearable device makes different responses based on different operations of the user.

[0051] Since the system-level chip provided in Example 1 is used, the smart wearable device provided in this embodiment has the advantages of rich functional applications, low power consumption and low cost.

[0052] In some optional implementations, the above sensors include heart rate sensors, acceleration sensors, gyroscope sensors, etc. Among them, the sub-control subsystem in the system-level chip is used to realize the functions of the Sensor Hub (sensor control center), specifically including real-time control of sensors, and fusing data from different types of sensors to realize functions that can only be achieved by combining data from multiple sensors.

[0053] In an optional implementation, the above-mentioned smart wearable device is a smart watch, such as an adult smart watch, a children's smart watch, an elderly smart watch, etc.

[0054] In some optional implementations, the above-mentioned smart wearable device can also be a smart bracelet, smart glasses, smart clothing, etc.

[0055] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A system-on-chip, characterized in that: It includes a power management chip, RAM, a main control subsystem, a sub-control subsystem and multiple functional subsystems; among which different functional subsystems are used to realize different functions; The main control subsystem, the auxiliary control subsystem and the functional subsystem all include an MCU; The main control subsystem, the auxiliary control subsystem and the functional subsystem are all connected to the RAM via a bus; The main control subsystem and the sub-control subsystem are connected to the functional subsystem via interrupt lines respectively. The main control subsystem and the sub-control subsystem are used to respond to the interrupt signal sent by the functional subsystem in a time-sharing manner. Specifically, if the main control subsystem is in a working mode, the main control subsystem responds to the interrupt signal sent by the functional subsystem, and the sub-control subsystem is prohibited from responding to the interrupt signal sent by the functional subsystem; if the main control subsystem is in a sleep mode or is powered off, the sub-control subsystem responds to the interrupt signal sent by the functional subsystem, and the main control subsystem is prohibited from responding to the interrupt signal sent by the functional subsystem; The power management chip is used to provide power for the RAM, the main control subsystem, the auxiliary control subsystem and the multiple functional subsystems.

2. The system-on-chip according to claim 1, wherein: The RAM includes SRAM and DRAM.

3. The system-on-chip according to claim 2, wherein: The SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem are integrated into one chip and packaged with the DRAM and the power management chip through SIP.

4. The system-on-chip according to claim 3, wherein: The system-level chip also includes a ROM, and the ROM is packaged with the chip integrating the SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem, the DRAM and the power management chip through a SIP package.

5. The system-on-chip according to claim 3, wherein: The system-level chip also includes a display subsystem for acquiring image data from the DRAM. The display subsystem is integrated into the same chip with the SRAM, the main control subsystem, the auxiliary control subsystem and the functional subsystem.

6. The system-on-chip according to claim 1, wherein: The main control subsystem, the auxiliary control subsystem and the functional subsystem all have independent power domains.

7. The system-on-chip according to claim 1, wherein: The system-level chip is embedded with an RTOS operating system.

8. The system-on-chip according to any one of claims 1 to 7, characterized in that: The functional subsystems include multiple ones of the following: a wireless modem subsystem, a Bluetooth subsystem, a Wi-Fi subsystem, a GPS subsystem, and a camera subsystem.

9. A smart wearable device, characterized in that: The invention comprises a touch screen, a plurality of sensors and a system-level chip as claimed in any one of claims 1 to 8, wherein the touch screen and the sensors are electrically connected to the system-level chip respectively.

10. The smart wearable device according to claim 9, characterized in that: The smart wearable device is a smart watch.

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