Method for etching metal interconnect layers

Abstract

This application discloses a method for etching a metal interconnect layer. In some examples, one method (100) includes: obtaining a substrate having a metal interconnect layer deposited over a substrate (402); forming a first dielectric layer (406) on the metal interconnect layer (404); forming a second dielectric layer (408) on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer onto the first dielectric layer to leave portions of the capacitor metal layer and the second dielectric layer on the first dielectric layer (410); forming an anti-reflective coating to cover portions of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer (412); and patterning the metal interconnect layer to form the first metal layer and the second metal layer (414).

Description

Summary of the Invention

[0001] According to at least one example of this disclosure, a method includes: obtaining a substrate having a metal interconnect layer deposited over a substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer onto the first dielectric layer such that portions of the capacitor metal layer and the second dielectric layer remain on the first dielectric layer; forming an anti-reflective coating to cover portions of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form the first metal layer and the second metal layer.

[0002] According to at least one example of this disclosure, a method includes forming a silicon nitride layer on a metal layer; forming a titanium nitride layer on the silicon nitride layer; patterning and etching the titanium nitride layer and the silicon nitride layer to form a capacitor dielectric, such that a portion of the silicon nitride layer remains on the metal layer; and forming an anti-reflective coating to cover exposed portions of the titanium nitride layer and the silicon nitride layer.

[0003] According to at least one example of this disclosure, an integrated circuit includes: a substrate; a first metal layer and a second metal layer located at the same lateral level above the substrate; a first dielectric disposed on the first metal layer; a first anti-reflective coating disposed on the first dielectric; a second dielectric disposed on the second metal layer and a third dielectric disposed on the second dielectric; a capacitor metal layer disposed on the third dielectric layer; and a second anti-reflective coating disposed on the capacitor metal layer and the second dielectric. Attached Figure Description

[0004] For a detailed explanation of the various examples, reference will now be made to the accompanying drawings, in which:

[0005] Figure 1(a) is a cross-sectional view of an illustrative integrated circuit fabricated on a semiconductor substrate according to various examples.

[0006] Figure 1(b) depicts a portion of the integrated circuit shown in Figure 1(a) according to various examples.

[0007] Figure 2 The reflectivity of antireflective coatings according to various examples is shown.

[0008] Figure 3 The reflectivity of antireflective coatings according to various examples is shown.

[0009] Figure 4 The methods are shown based on various examples.

[0010] Figures 5(a) to 5(l) The methods are shown based on various examples.

[0011] Figure 6 A portion of the integrated circuit shown in Figure 1(a) according to various examples is depicted. Detailed Implementation

[0012] Integrated circuits (ICs) are typically manufactured in large quantities on a single semiconductor wafer of high-quality (e.g., electronic-grade) silicon (or other semiconductor materials such as gallium arsenide) using microfabrication techniques. ICs comprise microelectronic components such as transistors, which are coupled to each other using metal interconnect layers. These metal interconnect layers (or sometimes referred to herein as metal layers) provide signal paths between the microelectronic components. In some cases, metal layers appear at different lateral levels that are perpendicularly spaced from each other. These lateral levels are positioned above the semiconductor wafer and are connected via structures that act as vertical trenches filled with suitable metal.

[0013] In some cases, integrated circuits include capacitors, which may be fabricated on one of a metal interconnect layer, where the metal interconnect layer acts as a conductive plate for the capacitor. Dielectric material, along with the metal layer, may be deposited together on the aforementioned metal interconnect layer to form the capacitor. In some cases, the dielectric material used to realize the capacitor also functions as an anti-reflective coating on the underlying metal interconnect layer. The anti-reflective coating patterns the metal interconnect layer. In other words, because metal reflects light, the anti-reflective coating prevents the reflection of light used in the photolithography process, thereby patterning the metal interconnect layer.

[0014] ICs operating at high voltages (e.g., 48V or higher) employ thick dielectrics to meet reliability specifications. Patterning the underlying metal interconnect layer in the presence of this thick dielectric, which also serves as an anti-reflective coating, is challenging. Patterning the underlying metal interconnect layer is particularly challenging for ICs fabricated at technology nodes such as 130nm. Therefore, new manufacturing methods are needed to mitigate these issues.

[0015] Therefore, a method and apparatus are described in which the dielectric does not perform the function of an anti-reflective coating, and during manufacturing, a separate layer performing the function of an anti-reflective coating is deposited. Because a separate layer is used as the anti-reflective coating, the properties of the anti-reflective coating and the dielectric layer can be independently adjusted to provide the desired low reflectivity and high dielectric constant characteristics, respectively.

[0016] In some examples, the capacitor is formed on a metal interconnect layer and includes a dielectric comprising a silicon nitride layer and a silicon dioxide layer, wherein the silicon dioxide layer is on the metal interconnect layer and the silicon nitride layer is on the silicon dioxide layer.

[0017] In some examples, the capacitor includes a dielectric comprising a silicon nitride layer. In this example, the silicon nitride layer is situated on a metal interconnect layer. The metal interconnect layer serves as a first capacitor plate and a second metal layer, such as a titanium nitride layer deposited on the dielectric, serving as the second capacitor plate. After etching the second metal layer and the dielectric, an anti-reflective coating, including, for example, silicon oxynitride, is deposited to pattern the underlying metal interconnect layer for subsequent fabrication processes.

[0018] In an example where the capacitor dielectric comprises a silicon nitride layer on a silicon dioxide layer, an anti-reflective coating of silicon oxynitride is formed on the portion of the silicon dioxide layer not covered by the silicon oxynitride layer (after etching), such that the portion of the silicon dioxide layer covered by silicon oxynitride can be considered as part of the anti-reflective coating. In an example where the capacitor dielectric comprises a silicon nitride layer on a metal interconnect layer, an anti-reflective coating of silicon oxynitride is formed on the portion of the silicon nitride layer remaining after etching the silicon nitride layer to form the capacitor dielectric, such that the portion of the silicon nitride layer covered by silicon oxynitride can be considered as part of the anti-reflective coating.

[0019] Figure 1(a) is a cross-sectional view of a portion of the illustrative integrated circuit 1 fabricated on a semiconductor substrate 51. For clarity, the semiconductor substrate 51 is shown as a block. From the viewpoint of the fabricated IC, the substrate 51 may also contain multiple isolation features (not explicitly shown in Figure 1(a)), such as shallow trench isolation (STI) features or localized oxidation of silicon (LOCOS) features. Isolation features define and isolate various microelectronic components (not explicitly shown in Figure 1(a)). Examples of various microelectronic components that can be formed in the substrate 51 include transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs, etc.), resistors, diodes, and other suitable components. One such microelectronic component is labeled with the number 50 in Figure 1(a). Various processes are performed to form various microelectronic components, including deposition, etching, implantation, photolithography, Annealing and other suitable processes. Before depositing the metal interconnect layers, the microelectronic components fabricated in the semiconductor substrate 51 are covered with a metal front dielectric layer 59. The microelectronic components are interconnected using one or more of the metal interconnect layers 10, 20, 30, 40, 22, 23, and 24. An interlayer dielectric (ILD) 25 electrically isolates the metal interconnect layers 10, 20, 30, 40, 22, 23, and 24 from each other. The metal interconnect layers 10, 20, 30, 40, 22, 23, and 24 may sometimes be referred to herein as metal layers 10, 20, 30, 40, 22, 23, and 24.

[0020] In some examples, metal layers 10, 20, 30, 40, 22, 23, and 24 have layers 11, 13, 15, 17, 33, 35, and 37 disposed on their respective top sides. In some examples, metal layers 10, 20, 30, 40, 22, 23, and 24 have layers 12, 14, 16, 18, 34, 36, and 38 disposed on their respective bottom sides. In some examples, layers 12, 14, 16, 18, 34, 36, and 38 comprise titanium nitride or a titanium / titanium nitride bilayer, which prevents oxidation of the metal interconnect layers to be deposited in subsequent steps. In other examples, at least one of layers 11, 13, 15, 17, 33, 35, and 37 forms a capacitor with the metal interconnect layer beneath them. (See Figure 1(b) above.) Figure 6 An example of this type of capacitor is described in the document.

[0021] Metal layers 24 and 40 are located at the same lateral level, which is referred to herein as the MET 1 level. Before metal layers 24 and 40 are individual units, a single metal layer (not shown) is deposited on a pre-metal dielectric layer 59, and then the single metal layer is patterned to form metal layers 24 and 40. Some of the metal layers present at the MET 1 level are coupled to microelectronic components fabricated in the pre-metal dielectric layer 59 via via structures. For example, block 50 is connected to metal layer 40 via structure 6. Metal layers 23 and 30 are disposed at a second level (or “MET 2 level”) of metal layers. From a fabrication perspective, a single metal layer is first deposited at the MET 2 level and then patterned to form metal layers 23 and 30. Some of the metal layers present at the MET 2 level can be coupled to block 50 via connections formed by a combination of one or more via structures and metal layers. For example, metal layer 30 is coupled to block 50 through via structure 5 coupled to metal layer 40, and metal layer 40 is further coupled to block 50 through via structure 6.

[0022] Metal layers 22 and 20 are disposed in ILD 25 and exist at the same lateral level, which may be referred to as the third level of the metal layers (or "MET 3 level"). From a manufacturing perspective, a single metal layer is deposited at the MET 3 level and then patterned to form metal layers 22 and 20. Some of the metal layers present at the MET 3 level can be coupled to block 50 through connections formed by a combination of one or more via structures and metal layers. For example, metal layer 20 is coupled to block 50 through via structure 4 coupled to metal layer 30, and metal layer 30 is further coupled to block 50 through via structure 5, metal layer 40, and via structure 6. As described in further detail below, the methods described in this disclosure refer to the patterning of metal layers at MET 1, 2, and 3 levels.

[0023] Metal layer 10 is disposed within ILD 25 and exists at a lateral level as the fourth level (or "MET 4 level") of metal layers. Metal layer 10 can be coupled to block 50 via connections formed by combinations of one or more via structures and metal layers. For example, metal layer 10 is coupled to block 50 via via structure 3 coupled to metal layer 20, which is further coupled to block 50 via via structure 4, metal layer 30, via structure 5, metal layer 40, and via structure 6. Metal layer 10 is coupled to a top metal layer (not shown) via via structure 2. The top metal layer is further coupled to other layers that can be coupled to a power source (not shown) and act as a voltage source for the microelectronic components (represented here as block 50). The example depicted in Figure 1(a) shows four levels of metal layers, such as MET 1, 2, 3, and 4 levels. However, in other examples, the number of levels can vary. Metal layers 22, 23, and 24 appear to be floating. However, in actual implementations, metal layers 23 and 24 can be coupled to one of the other metal interconnect layers via a via structure not explicitly shown in FIG1(a).

[0024] Referring now to Figure 1(b), which depicts region 100 marked in Figure 1(a), region 100 shows portions of layer 15 (Figure 1(a)) as layers 104, 106, 108, and 110 in Figure 1(b). Region 100 also shows portions of layer 35 (Figure 1(a)) as layers 114 and 111 in Figure 1(b). Region 100 also shows portions of metal layers 23 and 30 as metal layers 112 and 102, respectively. Region 100 also depicts a portion of ILD 25 from Figure 1(a) as ILD 125 in Figure 1(b).

[0025] As described above, layer 15 of FIG. 1(a) forms a capacitor with the underlying metal layer 30. FIG. 1(b) depicts the layers present in layer 15 that realize this capacitor. For example, layers 108 and 102 form the top and bottom plates of the capacitor, respectively, and layers 104 and 106 act as the dielectric of the capacitor. In one example, layer 104 comprises silicon dioxide and layer 106 comprises silicon nitride. In other examples, layers 104 and 106 may comprise other dielectrics, such as aluminum oxide, hafnium oxide, and zirconium oxide. In one example, layer 108 comprises titanium nitride, and metal layer 102 comprises an aluminum and copper alloy. In some examples, layer 108 is also referred to as the capacitor metal layer and comprises tantalum / tantalum nitride or tungsten / tungsten nitride. In some examples, layers 104 and 106 may be formed of the same dielectric material and are on the front Figure 6 An example of such an embodiment is described in the document.

[0026] In examples where layer 106 comprises silicon nitride, the thickness of layer 106 is between 1000 angstroms and 1600 angstroms, and the refractive index is between 2.3 and 2.9. In examples where layer 108 comprises titanium nitride, the thickness of layer 108 is between 1000 angstroms and 1600 angstroms. In some examples, layer 104 protects metal layer 102 during the etching of layer 106.

[0027] The desired capacitance and breakdown voltage of the resulting capacitor can be achieved by selecting the thicknesses of layers 106 and 108 and various other parameters. For example, for layer 106, which comprises silicon nitride with a thickness between 1200 and 1400 angstroms and a refractive index between 2.3 and 2.9 angstroms; and for layer 108, which comprises titanium nitride with a thickness between 1000 and 1600 angstroms, the resulting capacitor has a breakdown voltage of approximately 120V, which is well-suited for automotive applications with 48V electrical systems.

[0028] As described in detail below, after patterning and etching layers 106 and 108, an anti-reflective coating is deposited on the exposed portions. (See below for details.) Figure 4 As explained, the anti-reflective coating helps pattern the metal interconnect layers to form metal layers 102 and 112. The anti-reflective coating also facilitates the fabrication of other structures, such as via structures that connect to metal layer 102 along with other metal layers and circuit components. The anti-reflective coating helps achieve small critical dimensions (CD) during the photolithography step and, in some examples, can be stripped at a later point in the fabrication process flow. In the example of Figure 1(b), anti-reflective coatings 110 and 111 comprise silicon oxynitride. In some examples, the refractive index of the silicon oxynitride in anti-reflective coatings 110 and 111 is between 1.7 and 2.1, and the thickness is between 200 and 400 angstroms. In some examples, the refractive index of the silicon oxynitride is approximately 1.9. This example can have a capacitance density of approximately 0.4 femto-farads per square micrometer.

[0029] Now for reference Figure 4 An illustrative method 400 is shown. Method 400 describes manufacturing steps that can be performed to form the capacitor described in FIG. 1(b). Method 400 also describes the use of an anti-reflective coating, which facilitates the patterning of the underlying metal interconnect layers. In one example, the patterning forms patterned metal layers, such as metal layers 102 and 112 in FIG. 1(b). Method 400 is described concurrently with FIG. 5(a)–5(l).

[0030] Method 400 begins with step 402, which includes obtaining a substrate having one or more metal interconnect layers deposited over a substrate. Refer now to Figure 5(a) depicting metal interconnect layer 502. For illustration, metal interconnect layer 502 can be considered to be present at MET 2 level, and in this example, metal interconnect layer 502 is deposited on an interlayer dielectric layer similar to ILD 25 (not explicitly shown in Figure 5(a)). For simplicity, Figures 5(a)–5(l) depict the fabrication steps performed on metal interconnect layer 502, and do not explicitly show the different layers that may exist beneath metal interconnect layer 502. Metal interconnect layer 502 can be formed using sputtering or chemical vapor deposition (CVD) processes. In some examples, metal interconnect layer 502 may comprise an alloy of aluminum and copper.

[0031] Then, method 400 moves to step 404 (Figure 5(b)), which involves forming a first dielectric layer 504 on the metal interconnect layer 502 using a CVD technique. In one example, the first dielectric layer 504 comprises silicon dioxide. In other examples, the first dielectric layer 504 comprises silicon nitride. Method 400 further proceeds to step 406 (Figure 5(c)), which involves forming a second dielectric layer 506 on the first dielectric layer 504 using a CVD technique. In one example, the second dielectric layer 506 may comprise silicon nitride. Method 400 describes the use of two dielectric layers (layers 504, 506). However, in some examples, a single dielectric layer may be used. In such examples, the single dielectric layer may comprise silicon nitride. (The preceding text appears to be incomplete and requires further context.) Figure 6 This example is described in [the document / article].

[0032] Then, method 400 proceeds to step 408 (FIG. 5(d)), which includes forming a capacitor metal layer 508 on the second dielectric layer 506 using sputtering or CVD technology. In one example, the capacitor metal layer 508 comprises titanium nitride. Method 400 further proceeds to step 410, which includes patterning and etching the capacitor metal layer 508 and the second dielectric layer 506 onto the first dielectric layer 504 to leave portions of the capacitor metal layer 508 and the second dielectric layer 506 on the first dielectric layer 504. The patterning and etching described in step 410 may include a first deposition of photoresist 510 on the capacitor metal layer 508 (FIG. 5(e)). The photoresist 510 is illuminated in a photolithography process, such that portions of the photoresist 510 are exposed (FIG. 5(f)) and then stripped (FIG. 5(g)). The exposed portions of the capacitor metal layer 508 and the second dielectric layer 506 not covered by the photoresist 510 are etched, with the etching stopping at the first dielectric layer 504. The second dielectric layer 506 and the capacitor metal layer 508 are etched to form layers 106 and 108, respectively (Fig. 5(g)). The photoresist 510 is shown being stripped in Fig. 5(h).

[0033] Then, method 400 proceeds to step 412 (Figure 5(l)), which includes forming an antireflective coating 512 using sputtering, CVD, or related techniques to cover exposed portions of the capacitor metal layer 508, the first dielectric layer 504, and the second dielectric layer 506 (the vertical portion of layer 106). In one example, the antireflective coating 512 comprises silicon oxynitride. This antireflective coating 512 facilitates the patterning of the metal interconnect layer 502 and connects the metal interconnect layer 502 to other circuit components. The composition and various parameters associated with the antireflective coating 512 can be selected independently of the various parameters associated with the layers constituting the resulting capacitor (i.e., the first dielectric layer 504, the second dielectric layer 506, and the capacitor metal layer 508). The characteristics of the resulting capacitor and the antireflective coating 512 can thus be optimized independently.

[0034] In some examples, method 400 further includes step 414, which involves patterning the metal interconnect layer 502 (FIG. 5(j)) to form metal layers 102, 112. As described above, the presence of the anti-reflective coating 512 enables the metal interconnect layer 502 to be patterned by not reflecting the light used during photolithography. Prior to patterning, a dry film or photoresist film is deposited on the surface of the anti-reflective coating 512 using a suitable coating process, followed by curing, deslagging, etc., and then further photolithography and / or etching processes, such as dry etching and / or wet etching processes, to expose the surface of the metal interconnect layer 502 to be etched. The anti-reflective layer 512 forms anti-reflective layers 110, 111 after the metal interconnect layer 502 is etched. Method 400 then proceeds to step 416, which includes forming an interlayer dielectric 125 (FIG. 5(k)) in contact with the anti-reflective layers 110 and 111 in one example using a CVD process. In other examples, the anti-reflective layers 110 and 111 can be etched away before the interlayer dielectric 125 is deposited.

[0035] In some examples, metal layers 102, 112, and 108 can be connected to other metal interconnect layers, thereby electrically connecting to other electrical components in the integrated circuit. As described above, this electrical connection is achieved using via structures, which can be formed by patterning and etching the interlayer dielectric 125. In fact, in some examples, method 400 may further proceed to step 418, which includes patterning and etching the interlayer dielectric 125 to form one or more via structures (FIG. 5(l)). The example shown in FIG. 5(l) illustrates via structures 101 and 103 in contact with metal layer 112 and capacitor metal 108, respectively. As described above in FIG. 1(b), layers 104 and 106 of FIG. 1(b) can be formed of the same dielectric material, and Figure 6 An example of such an embodiment is described in the document.

[0036] Now for reference Figure 6 It depicts region 100 marked in Figure 1(a) and includes a capacitor formed by a combination of layers 602, 606, and 608. Layer 602 is a metal layer serving as the first plate of the generated capacitor; layer 608 is the second plate of the generated capacitor; layer 606 is a dielectric layer and includes silicon nitride. Figure 6 In the manufacturing process of part 100, layers 606 and 608 are patterned and etched to form the resulting capacitor; after etching, layer 606 partially covers layer 602. (Comparison) Figure 6 In the example of Figure 1(b), layer 106 has been etched down to layer 104, where layer 104 protects metal layer 102, but... Figure 6 In the example, a layer 606 (which may include silicon nitride) remains on layer 602 after etching. Layers 608, 606, and 602 are similar to layers 108, 106, and 102 of FIG. 1(b), respectively, and the descriptions of layers 108, 106, and 102 apply to layers 608, 606, and 602, respectively.

[0037] Anti-reflective coatings 610 and 611 are formed over the exposed portions of layers 608 and 606, and as shown in the example of FIG1(b) and the manufacturing process above, other circuit components (not shown) are manufactured to connect to them. Figure 6 When there are one or more layers (such as layer 602), the anti-reflective coatings 610 and 611 are useful. During the photolithography step, the anti-reflective coatings 610 and 611 help reduce the critical dimension and can be stripped at a later point in the process flow. During the process flow, with Figure 6 One or more layers of portion 100 form an interlayer dielectric 625. Antireflective coatings 610 and 611 are similar to antireflective coatings 110 and 111, respectively, and the descriptions of antireflective coatings 110 and 111 apply to antireflective coatings 610 and 611, respectively.

[0038] Now for reference Figure 2 This illustrates schematic diagrams depicting the reflectivity of antireflective coatings based on various examples. Figure 2 In the example, photoresist (not explicitly shown) is deposited on silicon oxynitride (or an anti-reflective coating), wherein the anti-reflective coating is formed by first depositing silicon oxynitride, then etching away the silicon oxynitride, and then redepositing silicon oxynitride of varying thicknesses. Figure 2 In the example, the silicon oxynitride layer above the silicon nitride corresponds to Figure 6 For example, silicon oxynitride and silicon nitride can be considered as anti-reflective coating 610.

[0039] for Figure 2 For example, silicon oxynitride has a refractive index of 1.9 and a dielectric constant k (the imaginary part of the wave vector) of 0.45. Figure 2The y-axis represents the reflectivity of the photoresist, and the x-axis represents the thickness of the silicon oxynitride.

[0040] Figure 2 Each curve in the diagram represents a specific thickness of silicon nitride beneath silicon oxynitride, where: for curve 202, the silicon nitride thickness is 300 angstroms; for curve 204, it is 250 angstroms; for curve 206, it is 200 angstroms; for curve 208, it is 150 angstroms; and for curve 210, it is 100 angstroms. Figure 2 The specific example described herein achieves minimum reflectivity using 150 angstroms silicon nitride and silicon oxynitride. Figure 2 This illustrates that reflectivity can depend on various parameters of the antireflective coating 610, and does not imply any particular set of optimal values.

[0041] Figure 3 The reflectivity of antireflective coatings is shown according to various examples. Figure 3 In this example, a photoresist film is deposited on silicon oxynitride deposited on silicon dioxide. The silicon dioxide is above the metal layer. This example corresponds to the example in Figure 1(b), where the silicon dioxide layer 104 can be considered part of the antireflective layer 110. Figure 3 In the illustrated example, an anti-reflective coating is formed by first depositing a low-density silicon oxynitride with a refractive index of 1.68, then etching away the deposited silicon oxynitride, and then depositing silicon oxynitride of different thicknesses and refractive indices. Figure 3 The y-axis represents the reflectivity value at the photoresist, the x-axis represents the thickness value of silicon oxynitride (LDSiON), and each curve represents various values ​​of refractive index and dielectric constant k.

[0042] For curve 302, silicon oxynitride has a refractive index of 1.68 and a dielectric constant k of 0.007. For curve 304, silicon oxynitride has a refractive index of 1.79 and a dielectric constant k of 0.13. For curve 306, silicon oxynitride has a refractive index of 1.79 and a dielectric constant k of 0.224. For curve 308, silicon oxynitride has a refractive index of 1.87 and a dielectric constant k of 0.3. For curve 310, silicon oxynitride has a refractive index of 1.9 and a dielectric constant k of 0.45. For curve 312, silicon oxynitride has a refractive index of 1.92 and a dielectric constant k of 0.53.

[0043] draw Figure 3 Elliptic curve 314 in the figure indicates the values ​​of refractive index, thickness, and dielectric constant k of silicon oxynitride to minimize reflectivity (for Figure 3 (Specific parameters shown). For example, for thicknesses ranging from approximately 250 angstroms to 350 angstroms, a refractive index between 1.87 and 1.92 yields relatively low reflectivity. Figure 3This illustrates how reflectivity depends on various parameters of the antireflective coating 110, and does not imply any particular set of optimal values.

[0044] In the foregoing discussion and claims, the term "comprising" is used in an open-ended manner and can therefore be interpreted as "including but not limited to...". The term "coupled" means an indirect or direct connection. Thus, if a first device is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices and connections. Similarly, devices coupled between a first component or location and a second component or location can be a direct connection or an indirect connection via other devices and connections. Elements or features "configured" to perform a task or function can be configured by the manufacturer at the time of manufacture (e.g., programmed or structurally designed) to perform a function and / or can be configured (or reconfigured) by the user after manufacture to perform a function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, the construction and / or layout of hardware components, interconnection of the device, or combinations thereof. Furthermore, the use of the phrase "grounded" or similar in the foregoing discussion means including rack ground, ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection suitable for or appropriate to the teachings of this disclosure. Unless otherwise stated, “about,” “approximately,” or “roughly” preceding a value means + / - 10% of that value.

[0045] The foregoing discussion is intended to illustrate the principles and various embodiments of this disclosure. Once fully understood, those skilled in the art will clearly see many changes and modifications. The following claims are intended to be construed as encompassing all such changes and modifications.

Claims

1. A method for use in an integrated circuit, comprising: A substrate is obtained having a metal interconnect layer deposited on the substrate; A first dielectric layer is formed on the metal interconnect layer; The second dielectric layer is formed directly on the first dielectric layer; A capacitor metal layer is formed on the second dielectric layer; The capacitor metal layer and the second dielectric layer are patterned and etched, the patterning and etching extending into the first dielectric layer, so as to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; An anti-reflective coating is formed to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; as well as The metal interconnect layers are patterned to form a first metal layer and a second metal layer, the first metal layer forming the plate of a capacitor.

2. The method of claim 1, wherein the thickness of the second dielectric layer is between 1000 angstroms and 1600 angstroms.

3. The method of claim 1, wherein the second dielectric layer comprises silicon nitride and has a refractive index between 2.3 and 2.

9.

4. The method according to claim 1, further comprising: Forming an interlayer dielectric in contact with the antireflective coating; as well as The interlayer dielectric is patterned and etched to form a via structure.

5. The method of claim 1, wherein the thickness of the capacitor metal layer is between 1000 angstroms and 1400 angstroms.

6. The method of claim 1, wherein the capacitor metal layer comprises titanium nitride.

7. The method of claim 1, wherein the thickness of the first dielectric layer is between 100 angstroms and 200 angstroms.

8. The method of claim 1, wherein the antireflective coating comprises silicon oxynitride.

9. The method of claim 8, wherein the refractive index of the antireflective coating is between 1.7 and 2.

1.

10. The method of claim 8, wherein the thickness of the antireflective coating is between 100 angstroms and 400 angstroms.

11. A method for using an integrated circuit, comprising: A substrate is obtained having a metal layer deposited on the substrate; A first dielectric layer is formed on the metal layer; A silicon nitride layer is formed directly on the first dielectric layer; A titanium nitride layer is formed on the silicon nitride layer; The titanium nitride layer and the silicon nitride layer are patterned and etched to form a capacitor dielectric, leaving a portion of the silicon nitride layer above the metal layer; An anti-reflective coating is formed to cover the exposed portions of the titanium nitride layer and the silicon nitride layer; as well as The metal layer is patterned.

12. The method of claim 11, wherein the thickness of the silicon nitride layer is between 1000 angstroms and 1600 angstroms.

13. The method of claim 12, wherein the refractive index of the silicon nitride layer is between 2.3 and 2.

9.

14. The method of claim 12, wherein the thickness of the titanium nitride layer is between 1000 angstroms and 1400 angstroms.

15. The method of claim 11, wherein forming the antireflective coating comprises forming silicon oxynitride.

16. The method of claim 15, wherein the refractive index of the silicon oxynitride is between 1.7 and 2.

1.

17. An integrated circuit, comprising: Substrate; The first metal layer and the second metal layer are located at the same lateral level above the substrate; A first dielectric layer is disposed on the first metal layer; The second dielectric layer is disposed directly on the first dielectric layer; A first anti-reflective coating is disposed on the first dielectric layer; A third dielectric layer is disposed on the second metal layer; A fourth dielectric layer is disposed on the third dielectric layer; A capacitor metal layer is disposed on the fourth dielectric layer; as well as A second anti-reflective coating is disposed on the capacitor metal layer and the third dielectric layer.

18. The integrated circuit of claim 17, wherein the capacitor metal layer, the second dielectric layer, the third dielectric layer, and the second metal layer constitute a capacitor.

19. The integrated circuit of claim 17, wherein the first antireflective coating and the second antireflective coating comprise silicon oxynitride.

Images