Magnetic random access memory and method of forming the same

Abstract

A magnetic random access memory and a method for forming the same, the magnetic random access memory comprising: a substrate, a surface of the substrate being formed with a conductive contact pad; a magnetic storage layer located on the surface of the substrate, the magnetic storage layer comprising at least two sub-storage layers stacked on the surface of the substrate, the magnetic storage layer comprising a plurality of magnetic storage cells connected to the conductive contact pad and penetrating through each of the sub-storage layers vertically, each of the magnetic storage cells comprising a magnetic tunnel junction, and each of the sub-storage layers comprising at least one magnetic tunnel junction. The magnetic random access memory has high performance.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a magnetic random access memory and a method for forming the same. Background Technology

[0002] Magnetic random access memory (MARM) is an integration of silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) technology. It is a non-volatile memory that has the high-speed read and write capabilities of static random access memory and the high integration density of dynamic random access memory.

[0003] Please refer to Figure 1 This is a schematic diagram of the structure of an existing magnetic random access memory.

[0004] The magnetic random access memory includes an access transistor 110 and a magnetic tunnel junction 120. The magnetic tunnel junction 120 includes a fixed layer 121, a tunneling layer 122, and a free layer 123. The drain 111 of the access transistor 110 is connected to the fixed layer 121 of the magnetic tunnel junction 120, and the free layer 123 of the magnetic tunnel junction 120 is connected to the bit line 130. The source 112 of the access transistor 110 is connected to the source line 140.

[0005] When the magnetic random access memory (RAM) is operating normally, the magnetization direction of the free layer 123 can change, while the magnetization direction of the fixed layer 121 remains unchanged. The resistance of the RAM is related to the relative magnetization directions of the free layer 123 and the fixed layer 121. When the magnetization direction of the free layer 123 changes relative to the magnetization direction of the fixed layer 121, the resistance value of the RAM changes accordingly, corresponding to different stored information.

[0006] In existing process technology nodes, the density of magnetic tunnel junctions per unit area in magnetic random access memory is relatively large. During the etching process to form magnetic tunnel junctions, the magnetic tunnel junctions are easily damaged, affecting chip yield. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to avoid damage to the magnetic tunnel structure during the etching process.

[0008] To address the aforementioned problems, the present invention provides a magnetic random access memory (RAM), a substrate having conductive contact pads formed on its surface, and a magnetic storage layer located on the surface of the substrate. The magnetic storage layer includes at least two sub-storage layers stacked on the surface of the substrate. Each magnetic storage layer includes a plurality of magnetic storage cells perpendicularly penetrating each sub-storage layer and connected to the conductive contact pads. Each magnetic storage cell includes a magnetic tunnel junction, and each sub-storage layer includes at least one magnetic tunnel junction.

[0009] Optionally, the magnetic tunnel junctions of the plurality of magnetic storage cells are randomly arranged within each sub-storage layer.

[0010] Optionally, the magnetic tunnel junctions within each sub-storage layer can be arranged in a random or array-like manner.

[0011] Optionally, the magnetic tunnel junctions of adjacent magnetic storage cells are located in different sub-storage layers.

[0012] Optionally, within the same sub-storage layer, the spacing between at least some adjacent magnetic tunnel junctions is greater than the minimum spacing between magnetic random access memory cells.

[0013] Optionally, within the magnetic storage layer, the spacing between adjacent magnetic storage cells is 'a'; within the same sub-storage layer, the minimum spacing between adjacent magnetic tunnel junctions is 'a'. n is the number of sub-storage layers within the magnetic storage layer.

[0014] Optionally, a dielectric layer is filled between adjacent magnetic storage cells of the magnetic storage layer.

[0015] Optionally, each magnetic storage cell further includes a conductive post located in a sub-storage layer above and / or below the magnetic tunnel junction within the magnetic storage cell, and electrically connected to the magnetic tunnel junction.

[0016] Optionally, a plurality of access transistors are also formed in the substrate, which are connected to the memory cells one by one. The access transistors include at least one of planar transistors, buried gate transistors, and ring gate transistors.

[0017] To address the aforementioned problems, the present invention also provides a method for forming a magnetic random access memory, comprising: providing a substrate, wherein a conductive contact pad is formed on the surface of the substrate; forming a magnetic storage layer on the substrate that connects the conductive contact pad, the magnetic storage layer comprising at least two sub-storage layers stacked on the surface of the substrate, the magnetic storage layer comprising a plurality of magnetic storage cells arranged in an array and vertically penetrating each sub-storage layer, the magnetic storage cells comprising magnetic tunnel junctions, and each sub-storage layer comprising at least one magnetic tunnel junction.

[0018] Optionally, the magnetic tunnel junctions of the plurality of magnetic storage cells are randomly arranged within each sub-storage layer.

[0019] Optionally, the magnetic tunnel junctions within each sub-storage layer can be arranged in a random or array-like manner.

[0020] Optionally, the magnetic tunnel junctions of adjacent magnetic storage cells are located in different sub-storage layers.

[0021] Optionally, each magnetic storage cell further includes a conductive post located in a sub-storage layer above and / or below the magnetic tunnel junction within the magnetic storage cell, and electrically connected to the magnetic tunnel junction.

[0022] Optionally, each sub-storage layer is formed layer by layer from the surface of the substrate upwards.

[0023] Optionally, the method for forming each sub-memory layer includes: forming a magnetic tunnel junction structure layer; forming a patterned mask layer on the surface of the magnetic tunnel junction structure layer; etching the magnetic tunnel junction structure layer using the patterned mask layer as a mask to form a magnetic tunnel junction; forming a dielectric layer filling the spaces between the magnetic tunnel junctions; etching the dielectric layer to form vias; and forming conductive pillars filling the vias.

[0024] Optionally, during the formation of different sub-storage layers, patterned mask layers with different patterns are used respectively, and the pattern positions of each patterned mask layer do not overlap.

[0025] Optionally, within the same sub-storage layer, the spacing between at least some adjacent magnetic tunnel junctions is greater than the minimum spacing between magnetic random access memory cells.

[0026] Optionally, within the magnetic storage layer, the spacing between adjacent magnetic storage cells is 'a'; when forming each sub-storage layer, the minimum spacing between adjacent patterns in the patterned mask layer is 'a'. n is the number of sub-storage layers within the magnetic storage layer.

[0027] Optionally, a plurality of access transistors are also formed in the substrate, which are connected to the memory cells one by one. The access transistors include at least one of planar transistors, buried gate transistors, and ring gate transistors.

[0028] In the method for forming a magnetic random access memory of the present invention, a magnetic memory cell array having at least two sub-memory layers is formed, and the magnetic tunnel junctions of adjacent magnetic memory cells are located in different sub-memory layers, thereby increasing the spacing between magnetic tunnel junctions in the same sub-memory layer. When forming magnetic tunnel junctions in the same sub-memory layer, the process window can be increased, the damage to the sidewalls of the magnetic tunnel junction caused by etching ion reflection can be reduced, the performance of the finally formed memory can be improved, and the unit storage density can be further increased.

[0029] Furthermore, the number of sub-storage layers can be reasonably set according to the spacing between the storage cells of the memory to be formed, and the minimum spacing between adjacent magnetic tunnel junctions within the same sub-storage layer can be reasonably adjusted to minimize the damage to the magnetic tunnel junctions during the etching process.

[0030] The magnetic random access memory of the present invention includes at least two sub-memory layers within its magnetic storage layer, and each sub-memory layer includes at least one magnetic tunnel junction. Therefore, for the same memory cell density, the number of magnetic tunnel junctions located in the same layer is reduced, which is beneficial to increasing the process window for forming magnetic tunnel junctions, thereby improving the quality of the formed magnetic tunnel junctions and improving the performance of the memory. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of an existing magnetic random access memory;

[0032] Figures 2 to 3 This is a schematic diagram illustrating the formation process of a magnetic random access memory according to a specific embodiment of the present invention.

[0033] Figures 4 to 13 This is a schematic diagram illustrating the formation process of a magnetic random access memory according to another specific embodiment of the present invention.

[0034] Figures 14 to 15 This is a schematic diagram of the structure of a magnetic random access memory according to another specific embodiment of the present invention;

[0035] Figures 16 to 19 This is a schematic diagram of the structure of a magnetic random access memory according to another specific embodiment of the present invention;

[0036] Figure 20 This is a schematic diagram of the structure of a magnetic random access memory according to another specific embodiment of the present invention;

[0037] Figure 21 This is a schematic diagram of the structure of a magnetic random access memory according to another specific embodiment of the present invention. Detailed Implementation

[0038] The specific embodiments of the magnetic random access memory and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Please refer to Figures 2 to 3 This is a schematic diagram of the formation process of a magnetic random access memory in a specific embodiment of the present invention.

[0040] Please refer to Figure 2 A substrate 200 is provided, and a first metal layer 212 and a dielectric layer 211 are formed on the surface of the substrate 200; a magnetic tunnel junction structure layer 220 is formed on the deposition surface of the first metal layer 212 and the dielectric layer 211.

[0041] Please refer to Figure 3 The magnetic tunnel structure layer 220 (see reference) is formed by exposure etching process. Figure 2The magnetic tunnel junction structure layer 220 is patterned to form an array of magnetic tunnel junction pillars 221. Due to the high storage density requirements of the memory, the distance between adjacent magnetic tunnel junction pillars 221 is small, and the size of the etched trenches is small. Plasma etching is used to etch the magnetic tunnel junction structure layer 220. During the bombardment process, the etching ions are easily reflected onto the sidewalls of adjacent magnetic tunnel junction pillars 221, which can easily damage the magnetic tunnel junction pillars 221, affecting memory performance and chip yield.

[0042] Damage to the magnetic tunnel junction pillars 221 caused by etching ion reflection can be reduced by increasing the spacing between them, but this will result in an increase in chip area and a decrease in memory integration.

[0043] To address the aforementioned problems, this invention proposes a novel magnetic random access memory (RAM) and its formation method. Employing two or more deposition-etching steps, magnetic tunnel junctions (MTJs) are distributed across multiple sub-memory layers. In each deposition-etching step, the number of MMTs required is reduced, thereby increasing the distance between adjacent MMTs, enlarging the etching window, reducing damage to the MMT pillars, improving chip yield and memory performance, and without decreasing memory integration density. Furthermore, with the same etching spacing, forming multiple sub-memory layers increases the memory's storage density.

[0044] The method for forming the magnetic random access memory includes: providing a substrate, wherein conductive contact pads are formed on the surface of the substrate; forming a magnetic storage layer on the substrate that connects the conductive contact pads, including at least two sub-storage layers stacked in a direction perpendicular to the surface of the substrate, wherein magnetic storage cells within the magnetic storage layers include magnetic tunnel junctions, and each sub-storage layer includes at least one magnetic tunnel junction. The novel magnetic random access memory and its formation method are described in detail below with reference to the accompanying drawings.

[0045] Please refer to Figures 4 to 13 This is a schematic diagram illustrating the formation process of a magnetic random access memory according to a specific embodiment of the present invention. In this specific embodiment, a magnetic memory cell array is formed using two deposition-etching steps.

[0046] Please refer to Figure 4 Please provide a substrate 400, on the surface of which a conductive contact pad 412 and a first dielectric layer 411 are formed.

[0047] The substrate 400 is a semiconductor substrate, which can be a single-crystal silicon substrate, a single-crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. Doped regions and semiconductor devices can also be formed within the substrate 400. The material and structure of the substrate 400 can be reasonably selected according to the specific design and actual needs of the memory, and are not limited herein.

[0048] In one embodiment, the substrate 400 includes a substrate and a dielectric layer covering the surface of the substrate. An access transistor is formed on the surface of the substrate, and a conductive structure connected to the access transistor is formed within the dielectric layer. The access transistor can employ any transistor structure, and can be at least one of various types of transistor structures such as buried-gate transistors, gate-around-the-ring field-effect transistors, and planar transistors.

[0049] A conductive contact pad 412 is formed on the surface of the substrate 400. The conductive contact pad 412 is used to connect to the magnetic storage cell to be formed subsequently. The conductive contact pad 412 is also connected to a conductive structure within the substrate 400 to connect to the drain of the access transistor within the substrate 400.

[0050] The first dielectric layer 411 serves as an isolation structure between the conductive contact pads 412. The method for forming the first dielectric layer 411 and the conductive contact pads 412 includes: depositing the first dielectric layer 411 on the surface of the substrate 400, etching the first dielectric layer 411, forming a through-hole in the first dielectric layer 411, filling the through-hole with a conductive material and planarizing it to form the conductive contact pads 412.

[0051] In another specific embodiment, the method for forming the first dielectric layer 411 and the conductive contact pad 412 includes: after depositing a first metal material layer on the surface of the substrate 400, patterning the first metal material layer to form a patterned conductive contact pad 412; after forming a first dielectric material layer covering the substrate 400 and the conductive contact pad 412, planarizing the first dielectric material layer to expose the surface of the conductive contact pad 412 to form the first dielectric layer 411.

[0052] The arrangement density and position of the conductive contact pads 412 are set according to the arrangement position and density of the storage cells of the magnetic random access memory to be formed. In this specific embodiment, the spacing between adjacent conductive contact pads 412 is the lateral spacing between adjacent magnetic storage cells in the memory to be formed.

[0053] Please refer to Figure 5 A first magnetic tunnel junction structure layer 500 is formed on the surface of the first dielectric layer 411 and the conductive contact pad 412.

[0054] The first magnetic tunnel structure layer 500 includes a fixed layer, a tunneling layer, and a free layer stacked from bottom to top. Figure 5 It is not specifically shown in the text.

[0055] Please refer to Figure 6A first patterned mask layer 600 is formed on the surface of the first magnetic tunnel junction structure layer 500. The material of the first patterned mask layer 600 can be a mask material such as photoresist or silicon oxide. The first patterned mask layer 600 is used to define the position and size of the first magnetic tunnel junction within the first sub-memory layer.

[0056] Please refer to Figure 7 Using the first patterned mask layer 600 as a mask, the magnetic tunnel structure layer 500 is etched (see reference). Figure 6 This forms a first magnetic tunnel junction 501 located on the surface of a portion of the conductive contact pad 412.

[0057] In this specific embodiment, the first magnetic tunnel junction 501 is formed only on a portion of the conductive contact pad 412 surface. Therefore, the spacing between adjacent first magnetic tunnel junctions 501 can be greater than the minimum spacing between the final magnetic storage cells to be formed. This reduces the possibility of reflected etching ions damaging the sidewalls of the first magnetic tunnel junction 501 during the etching of the magnetic tunnel junction structure layer 500, thereby improving the quality of the formed first magnetic tunnel junction 501.

[0058] The number of magnetic tunnel junctions in each storage layer can be randomly set according to the number of sub-storage layers of the magnetic storage layer to be formed, so that at least one magnetic tunnel junction is formed in each sub-storage layer. This makes the spacing between at least some adjacent magnetic tunnel junctions in each storage layer greater than the spacing between storage cells, which can reduce the number of magnetic tunnel junctions damaged by ion reflection during the formation of magnetic tunnel junctions to a certain extent.

[0059] To minimize damage to magnetic tunnel junctions, the magnetic tunnel junctions in adjacent memory cells can be located in different sub-memory layers, such that the minimum spacing between magnetic tunnel junctions in each sub-memory layer is greater than the minimum spacing between memory cells.

[0060] In one specific implementation, the number of memory cells to be formed is A. A magnetic memory cell array is formed using n deposition-etching processes. Therefore, the number of magnetic tunnel junctions formed in each iteration can be an integer closest to A / n. In other specific implementations, the number of magnetic tunnel junctions formed each time can be set according to actual conditions, provided that the spacing between at least two magnetic tunnel junctions within each sub-memory layer is greater than the minimum spacing between the memory cells to be formed.

[0061] In this specific embodiment, the number of the first magnetic tunnel junctions 501 formed is A / 2, where A is an even number. In other specific embodiments, if A is an odd number, the number of magnetic tunnel junctions formed in the two instances can be respectively... and

[0062] Please refer to Figure 8 Remove the first patterned mask layer 600 (see reference). Figure 6 A second dielectric layer 800 is filled between adjacent first magnetic tunnel junctions 501.

[0063] The material of the second dielectric layer 800 can be an insulating dielectric material such as silicon oxide or silicon oxynitride. After depositing the second dielectric material layer on the surface of the first dielectric layer 411 and the conductive contact pad 412, the second dielectric material layer is planarized using the first magnetic tunnel junction 501 as a stop layer to form the second dielectric layer 800.

[0064] Please refer to Figure 9 The second dielectric 800 is etched to form a through-hole on the surface of the conductive contact pad 412 between adjacent locations of the first magnetic tunnel junction 501; the through-hole is filled with a first conductive post 900 connecting the conductive contact pad 412. The through-hole exposes the surfaces of other conductive contact pads 412.

[0065] Please refer to Figure 10 A second magnetic tunnel junction structure layer 1000 is formed covering the second dielectric layer 800, the first magnetic tunnel junction 501, and the first conductive pillar 900; a second patterned mask layer 1001 is formed on the surface of the second magnetic tunnel junction structure layer 1000, the second patterned mask layer 1001 being used to define the position and size of the second magnetic tunnel junction located within the second sub-memory layer.

[0066] Please refer to Figure 11 The second patterned mask layer 1001 (see reference) Figure 10 Using a mask, the second magnetic tunnel structure layer 1000 was etched (please refer to...). Figure 10 A second magnetic tunnel junction 1002 is formed; a third dielectric layer 1100 is filled between the second magnetic tunnel junctions 1002.

[0067] In this specific embodiment, the number of the second magnetic tunnel junction 1002 is A / 2.

[0068] The second patterned mask layer 1001 (please refer to) Figure 10 ) and the first patterned mask layer 600 (see reference) Figure 6 The positions of the patterns do not overlap, so that the first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002 do not overlap in the direction perpendicular to the surface of the substrate 400.

[0069] The spacing between adjacent second magnetic tunnel junctions 1002 is relatively large, so the damage caused to the second magnetic tunnel junction 1002 by etching the second magnetic tunnel junction structure layer 1000 to form the second magnetic tunnel junction 1002 can be reduced during the process.

[0070] Please refer to Figure 12 The third dielectric layer 1100 is etched to form a through hole exposing the first magnetic tunnel junction 501, and the through hole is filled with a second conductive pillar 1200.

[0071] The second conductive post 1200 is electrically connected to the first magnetic tunnel junction 501 in the lower layer. Subsequently, bit lines connected to each of the second conductive posts 1200 and the second magnetic tunnel junction 1001 are formed on the surface of the third dielectric layer 1100.

[0072] The first sub-storage layer containing the first magnetic tunnel junction 501 and the second sub-storage layer containing the second magnetic tunnel junction 1001 constitute a magnetic storage layer located on the surface of the substrate 400. Each magnetic storage cell within the magnetic storage layer includes a magnetic tunnel junction and a conductive post connecting the top or bottom of the magnetic tunnel junction.

[0073] Please refer to Figure 13 This is a schematic diagram showing the location of each magnetic storage unit within the magnetic storage layer in this specific embodiment. Figure 12 , for along Figure 13 A schematic cross-sectional view of the secant AA'. Wherein, Figure 13 The circles numbered 1 and 2 represent memory cells with a first magnetic tunnel junction 501 and a second magnetic tunnel junction 1002, respectively. The first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002 are located in different sub-memory layers.

[0074] In this specific embodiment, the magnetic storage cells are arranged in the form of a rectangular array. The magnetic tunnel junctions in each row and column are alternately distributed in the first sub-storage layer and the second sub-storage layer, so that the magnetic tunnel junctions in each sub-storage layer are also arranged in an array.

[0075] Within the magnetic storage layer, the spacing between adjacent magnetic storage cells is 'a' (the distance between the central axes of adjacent storage cells). Taking the second sub-storage layer as an example, adjacent second magnetic tunnel junctions 1002 within the second sub-storage layer have two spacings, d1 and d2, where d2 = 2a. All are greater than a.

[0076] Therefore, by forming the first and second sub-memory layers sequentially through two deposition-etching steps, the minimum spacing between at least some adjacent magnetic tunnel junctions located in the same sub-memory layer can be increased during each etching process to form a magnetic tunnel junction. This reduces the damage to the sidewalls of the magnetic tunnel junctions caused by etching ion reflection and improves the performance of the final memory.

[0077] In other specific embodiments, three or more sub-storage layers can be formed to further reduce the number of magnetic tunnel junctions in each sub-storage layer, thereby increasing the minimum spacing between adjacent magnetic tunnel junctions in each sub-storage layer. During the formation of different sub-storage layers, patterned mask layers with different patterns are used respectively, and the pattern positions used to define the magnetic tunnel junctions in each patterned mask layer do not overlap.

[0078] The number and location of magnetic tunnel junctions in each sub-memory layer can be set randomly; or the number and location of magnetic tunnel junctions in each sub-memory layer can be set according to a certain pattern, so that the distribution of magnetic tunnel junctions in each sub-memory layer is more regular and the density of magnetic tunnel junctions in each sub-memory layer is more uniform. This allows the heat generated by the magnetic tunnel junctions to be evenly distributed in each sub-memory layer during the operation of the memory, avoiding the problem of excessive local temperature rise.

[0079] In a specific embodiment of the present invention, the minimum spacing between adjacent magnetic storage cells within the magnetic storage layer of the memory to be formed is 'a'. When the magnetic tunnel junctions within adjacent storage cells are located in different sub-storage layers, damage to the magnetic tunnel junctions can be minimized. When forming each sub-storage layer, the minimum spacing between adjacent patterns of the patterned mask layer used can be... That is, the minimum spacing between the magnetic tunnel junctions formed is Where n is the number of sub-storage layers included in the magnetic storage layer.

[0080] For example, when a three-layer sub-memory layer is formed using a three-stage deposition-etching process, the minimum spacing between magnetic tunnel junctions within the same layer can be increased to [value missing]. When four sub-storage layers are formed using a four-step deposition-etching process, the minimum spacing between magnetic tunnel junctions located in the same layer can be increased to 2a.

[0081] Please refer to Figure 14 and Figure 15 This is a schematic diagram of a storage cell of a magnetic random access memory formed by three deposition-etching steps in another specific embodiment of the present invention. Figure 15 For along Figure 14 A cross-sectional view of the secant line BB'.

[0082] In this specific embodiment, the magnetic storage layer formed on the substrate 1500 includes three sub-storage layers. The circles numbered 1, 2, and 3 respectively represent storage cells having a first magnetic tunnel junction 1501, a second magnetic tunnel junction 1502, and a third magnetic tunnel junction 1503, which are located sequentially within the first to third sub-storage layers.

[0083] In this specific embodiment, the memory cells are arranged in a diamond array. The magnetic tunnel junctions in each row of memory cells are distributed sequentially in the first sub-memory layer, the second sub-memory layer, and the third sub-memory layer, so that the magnetic tunnel junctions in each sub-memory layer are also arranged in an array, and the number of magnetic tunnel junctions in each sub-memory layer is similar and the distribution is uniform.

[0084] When the minimum spacing between the memory cells of the magnetic random access memory is 'a', a three-stage deposition-etching process is used to create a magnetic memory cell array with three sub-memory layers. Taking the first sub-memory layer as an example, within the first sub-memory layer, adjacent first magnetic tunnel junctions 1501 have three different spacings, namely c1, c2, and c3; when the minimum spacing between adjacent memory cells is 'a', c1 = 3a, c3 = 2a, minimum spacing is It is greater than the minimum spacing 'a' between each magnetic storage cell in the magnetic storage cell array.

[0085] Please refer to Figure 16 , Figure 17 and Figure 18 This is a schematic diagram of a storage cell of a magnetic random access memory formed by four deposition-etching steps in another specific embodiment of the present invention. Figure 17 For along Figure 16 A cross-sectional view of the secant CC'. Figure 18 For along Figure 16 A cross-sectional view of the secant DD'. Figure 18 For along Figure 16 A cross-sectional view of the secant EE'.

[0086] In this specific embodiment, the magnetic storage layer formed on the substrate 1700 includes four sub-storage layers, wherein... Figure 16 The circles numbered 1, 2, 3 and 4 are used to represent memory cells with a first magnetic tunnel junction 1701, a second magnetic tunnel junction 1702, a third magnetic tunnel junction 1703 and a fourth magnetic tunnel junction 1704, respectively. The first magnetic tunnel junction 1701, the second magnetic tunnel junction 1702, the third magnetic tunnel junction 1703 and the fourth magnetic tunnel junction 1704 are located in the first to fourth sub-memory layers in sequence.

[0087] In this specific embodiment, the memory cells are arranged in a rectangular array. The magnetic tunnel junctions within each row of memory cells are distributed at intervals within two sub-memory layers, while the magnetic tunnel junctions within adjacent rows of memory cells are located in different sub-memory layers. For example, the magnetic tunnel junctions of the memory cells in the first row are located in the third and second sub-memory layers, while the magnetic tunnel junctions of the memory cells in the second row are located in the first and fourth sub-memory layers. The distribution of magnetic tunnel junctions in every three rows is consistent with that in the first row. When the minimum spacing between adjacent memory cells is 'a', taking the third sub-memory layer as an example, the minimum spacing e between adjacent third magnetic tunnel junctions 1703 is 2a.

[0088] In other specific embodiments, the arrangement of the memory cells is not limited; they can be arranged in an array according to a certain pattern or randomly distributed. Similarly, the arrangement of the magnetic tunnel layers within each sub-memory layer can also be random or arranged in an array.

[0089] In the formation process of the aforementioned memory, at least two memory cell sub-memory layers are sequentially formed through at least two deposition-etching steps, with each sub-memory layer containing a magnetic tunnel junction of a memory cell. Therefore, the spacing between some adjacent magnetic tunnel junctions within the same sub-memory layer can be increased, thereby reducing damage to the sidewalls of the magnetic tunnel junction caused by reflected etching ions during the etching of the magnetic tunnel junction structure layer, increasing the process window, and improving the performance of the final formed memory.

[0090] Furthermore, as the number of sub-memory layers increases, the minimum spacing between adjacent magnetic tunnel junctions within the same sub-memory layer increases. The number of sub-layers can be rationally set based on the minimum spacing between the memory cells to be formed and the minimum etching spacing required to form high-quality magnetic tunnel junctions, thereby maximizing memory performance without changing the memory's storage density.

[0091] Specific embodiments of the present invention also provide a magnetic random access memory formed using the above method.

[0092] Please refer to Figure 12 and Figure 13 This is a schematic diagram of the structure of a magnetic random access memory according to a specific embodiment of the present invention. Figure 12 For along Figure 13 A cross-sectional view of the secant line AA'.

[0093] The magnetic random access memory includes: a substrate 400, on the surface of which conductive contact pads 412 are formed; a magnetic storage layer located on the surface of the substrate 400, the magnetic storage layer including at least two sub-storage layers stacked on the surface of the substrate, the magnetic storage layer including a plurality of magnetic storage cells vertically penetrating each sub-storage layer and connected to the conductive contact pads, the magnetic storage cells including magnetic tunnel junctions, and each sub-storage layer including at least one magnetic tunnel junction.

[0094] The magnetic tunnel junction comprises stacked fixed layers, tunneling layers, and free layers.

[0095] The substrate 400 also contains a plurality of access transistors, which are connected one-to-one with the memory cells. The access transistors include at least one of planar transistors, buried gate transistors, and ring gate transistors.

[0096] In this specific embodiment, a first dielectric layer 411 is formed between adjacent conductive contact pads 412. The first dielectric layer 411 is made of insulating material and serves as an isolation layer between the conductive contact pads 412. The magnetic storage layer includes two sub-storage layers. A first magnetic tunnel junction 501 is formed in the first sub-storage layer, and a second magnetic tunnel junction 1002 is formed in the second sub-storage layer. The first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002 belong to different storage cells.

[0097] The first sub-storage layer also includes a first conductive post 900 connected to the conductive contact pad 412 and the second magnetic tunnel junction 1002, and a second dielectric layer 800 is formed between the first conductive post 900 and the first magnetic tunnel junction 501.

[0098] The second sub-storage layer also includes a second conductive post 1200 connected to the first magnetic tunnel junction 501, and a third dielectric layer 1100 is formed between the second conductive post 1200 and the second magnetic tunnel junction 1002.

[0099] Figure 13 In the diagram, circles numbered 1 and 2 represent the memory cells containing the first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002, respectively. In this specific embodiment, the magnetic memory cells are arranged in a rectangular array. Magnetic tunnel junctions in each row and column are spaced apart in the first and second sub-memory layers, ensuring that the magnetic tunnel junctions within each sub-memory layer are also arranged in an array. Within each sub-memory layer, adjacent magnetic tunnel junctions have two spacings, d1 and d2. When the minimum spacing between adjacent memory cells is a, d1 = 2a.

[0100] Please refer to Figure 14 and Figure 15This is a schematic diagram of the structure of a magnetic random access memory according to another specific embodiment of the present invention. Figure 15 For along Figure 14 A cross-sectional view of the secant line BB'.

[0101] In this specific embodiment, the magnetic random access memory includes a substrate 1500 and a magnetic storage layer formed on the substrate 1500. The magnetic storage layer includes three sub-storage layers from the surface of the substrate 1500 upwards. A first magnetic tunnel junction 1501 is formed in the bottom first sub-storage layer, a second magnetic tunnel junction 1502 is formed in the second sub-storage layer located on the surface of the first sub-storage layer, and a third magnetic tunnel junction 1503 is formed in the third sub-storage layer located on the surface of the second sub-storage layer. The first magnetic tunnel junction 1501, the second magnetic tunnel junction 1502, and the third magnetic tunnel junction 1503 are located in different storage cells. Each sub-storage layer also has conductive pillars formed, which connect to the magnetic tunnel junctions in the upper or / lower sub-storage layer. The conductive pillars and magnetic tunnel junctions in the same sub-storage layer are isolated by a dielectric layer.

[0102] In this specific embodiment, the memory cells are arranged in a diamond array. The magnetic tunnel junctions in each row of memory cells are distributed sequentially in the first sub-memory layer, the second sub-memory layer, and the third sub-memory layer, so that the magnetic tunnel junctions in each sub-memory layer are also arranged in an array, and the number of magnetic tunnel junctions in each sub-memory layer is similar and the distribution is uniform.

[0103] Figure 15 In this embodiment, numbers 1, 2, and 3 represent the memory cells containing the first magnetic tunnel junction 1501, the second magnetic tunnel junction 1502, and the third magnetic tunnel junction 1503, respectively. Within each sub-memory layer, adjacent magnetic tunnel junctions have three spacings: c1, c2, and c3. When the minimum spacing between adjacent memory cells is a, c1 = 3a. c3 = 2a, minimum spacing is All are greater than the minimum spacing 'a' between storage cells within the storage cell array.

[0104] Please refer to Figure 16 , Figure 17 and Figure 19 This is a schematic diagram of a storage unit of a magnetic random access memory according to another specific embodiment of the present invention. Figure 17 For along Figure 16 A cross-sectional view of the secant CC'. Figure 18 For along Figure 16 A cross-sectional view of the secant DD'. Figure 19 For along Figure 16 A cross-sectional view of the secant EE'.

[0105] In this specific embodiment, the magnetic storage layer formed on the substrate 1700 of the magnetic random access memory includes four subarray layers, wherein... Figure 16 The circles numbered 1, 2, 3 and 4 represent the memory cells containing the first magnetic tunnel junction 1701, the second magnetic tunnel junction 1702, the third magnetic tunnel junction 1703 and the fourth magnetic tunnel junction 1704, respectively. The first magnetic tunnel junction 1701, the second magnetic tunnel junction 1702, the third magnetic tunnel junction 1703 and the fourth magnetic tunnel junction 1704 are located in the first to fourth sub-memory layers in sequence.

[0106] In this specific embodiment, the memory cells are arranged in a rectangular array. The magnetic tunnel junctions within each row of memory cells are distributed at intervals within two sub-memory layers, while the magnetic tunnel junctions within adjacent rows of memory cells are located in different sub-memory layers. For example, the magnetic tunnel junctions of the memory cells in the first row are located in the third and second sub-memory layers, while the magnetic tunnel junctions of the memory cells in the second row are located in the first and fourth sub-memory layers. The distribution of magnetic tunnel junctions in every three rows is consistent with that in the first row.

[0107] When the minimum spacing between adjacent memory cells is a, taking the third sub-memory layer as an example, the minimum spacing between adjacent third magnetic tunnel junctions 1703 is e = 2a, which is greater than the minimum spacing between adjacent memory cells.

[0108] In other specific embodiments of the magnetic random access memory, the magnetic memory cell array includes n stacked sub-memory layers, with a spacing of 'a' between adjacent magnetic memory cells. When the magnetic tunnel junctions within adjacent memory cells are located in different sub-memory layers, the minimum spacing between adjacent magnetic tunnel junctions within the same sub-memory layer is [missing information].

[0109] In other specific embodiments of the present invention, the number of magnetic tunnel junctions in each storage layer can be randomly set according to the number of sub-storage layers of the magnetic storage layer to be formed, so that at least one magnetic tunnel junction is formed in each sub-storage layer, thereby making the spacing between at least some adjacent magnetic tunnel junctions in each storage layer greater than the spacing between storage cells, which can reduce the number of magnetic tunnel junctions damaged by ion reflection during the formation of magnetic tunnel junctions to a certain extent.

[0110] To minimize damage to magnetic tunnel junctions, the magnetic tunnel junctions within adjacent memory cells can be located in different sub-memory layers. This ensures that the minimum spacing between magnetic tunnel junctions within each sub-memory layer is greater than the minimum spacing between memory cells. When the distribution of magnetic tunnel junctions within each sub-memory layer is relatively regular and the density of magnetic tunnel junctions is relatively uniform, the heat generated by the magnetic tunnel junctions during memory operation is evenly distributed across all sub-memory layers, avoiding the problem of excessively rapid local temperature rise.

[0111] In other specific embodiments, the arrangement of the memory cells is not limited; the memory cells can be arranged in an array according to a certain pattern or randomly distributed. Similarly, the arrangement of the magnetic tunnel layers within each sub-memory layer can also be random or arranged in an array.

[0112] Compared to magnetic random access memory (MRMemory) where all magnetic tunnel junctions are on the same layer, the magnetic tunnel junctions of the present invention are distributed in at least two sub-memory layers. The increased spacing between at least some of the magnetic tunnel junctions within the same sub-memory layer effectively improves the process window for forming the magnetic tunnel junctions and reduces the damage to the sidewalls of the magnetic tunnel junctions caused by the reflection of etching ions. This, in turn, helps to improve the quality of the formed magnetic tunnel junctions and enhance the performance of the magnetic random access memory.

[0113] Please refer to Figure 20 This is a schematic diagram of the memory structure according to another specific embodiment of the present invention.

[0114] In this specific embodiment, a gate-ring transistor is formed within the substrate 2000 of the memory, serving as an access transistor.

[0115] Specifically, the substrate 2000 includes a substrate 2001 and access transistors 2002 formed on the substrate 2001, and an isolation layer 2003 located between the access transistors 2002.

[0116] The access transistor 2002 is a vertical gate all around FET, including a source 2004, a channel region 2005 and a drain 2006 arranged vertically upward from the surface of the substrate 2001, a gate 2007 disposed around the channel region 2005, and a gate dielectric layer 2008 located between the gate 2007 and the channel region 2005.

[0117] The substrate 2000 also includes a dielectric layer 2009 covering the isolation layer 2003 and the access transistor 2002, and a first electrical contact portion 2010 connecting the drain 2006 is formed in the dielectric layer 2009.

[0118] A conductive contact pad 2013 is formed on the surface of the substrate 2000, and the conductive contact pad 2013 is connected to the first electrical contact 2010. The conductive contact pad 2013 is formed within a dielectric layer 2012.

[0119] A storage layer 2020 is formed above the substrate 2000. The storage layer 2020 includes a first sub-storage layer 2021 and a second sub-storage layer 2022. The storage layer 2020 includes storage cells that vertically penetrate each sub-storage layer. Each storage cell includes magnetic tunnel junctions 2031 and 2032 and conductive pillars 2033 above and / or below the magnetic tunnel junctions. In other embodiments, the storage layer 2020 may also include three or more sub-storage layers.

[0120] An access transistor 2002 is formed in the substrate 2000 below each memory cell, and each memory cell is electrically connected to the drain 2006 of the access transistor 2002 below it.

[0121] The storage cells within the storage layer 2020 can be arranged in a certain array pattern, such as a diamond array or a rectangular array.

[0122] In this specific embodiment, the magnetic tunnel junctions of the storage cells can be randomly distributed or arranged in an array within the first sub-storage layer 2021 and the second sub-storage layer 2022. In one specific embodiment, the magnetic tunnel junctions 2031 in the first sub-storage layer 2021 are distributed in the form of rectangular array cells; the magnetic tunnel junctions 2032 in the second sub-storage layer 2022 are distributed in the form of rectangular array cells.

[0123] In other specific embodiments, the magnetic tunnel junctions 2031 in the first sub-storage layer 2021 are distributed in the form of a rhombus array cell; the magnetic tunnel junctions 2032 in the second sub-storage layer 2022 are distributed in the form of a rhombus array cell.

[0124] In other specific embodiments, the magnetic tunnel junctions 2031 in the first sub-storage layer 2021 and the magnetic tunnel junctions 2032 in the second sub-storage layer 2022 can also be randomly distributed.

[0125] This specific embodiment only provides one example structure of the access transistor 2002. In other embodiments, the access transistor 2002 may also have a gate-around structure, for example, the access transistor 2002 may also be a FinFET or a Lateral Gate All AroundFET.

[0126] The FinFET includes a raised fin formed on the surface of a substrate, a gate spanning the fin, the gate surrounding the top and sidewalls of a channel region; and a source and drain located within the fin on either side of the gate.

[0127] The planar all-around gate structure includes a channel region suspended above the substrate surface, a source and a drain located on the substrate surface and respectively connecting the two sides of the channel region, and a gate surrounding the channel region.

[0128] In other specific embodiments, access transistors with other structures, such as buried gate transistors, can also be used to reduce the size of the storage transistors.

[0129] In this specific embodiment, a second medium layer 2024 is also formed on the surface of the storage layer 2020, and a third contact portion 2023 connecting each storage cell is formed in the second medium layer 2024; a bit line 2030 is formed on the surface of the second medium layer 2023, which is connected to the third contact portion 2023.

[0130] The spacing between memory cells is limited not only by the process window for etching to form magnetic tunnel junctions, but also by the size of the access transistors beneath the memory cells. In the specific embodiment described above, the magnetic tunnel junctions of each memory cell are distributed across multiple sub-memory layers, each formed independently. Therefore, provided that the magnetic tunnel junctions within each memory cell do not overlap in the vertical direction, the spacing between the magnetic tunnel junctions within each sub-memory layer can be set according to the minimum process window limit, thereby increasing the minimum spacing between the final memory cells and thus improving the memory's storage density.

[0131] Furthermore, the access transistors within the substrate are gate-around transistors, which can significantly reduce the size of the gate-around transistors, thereby reducing the minimum spacing between each memory cell and increasing the memory's storage density.

[0132] In other specific embodiments, a buried gate transistor can also be formed in the substrate of the memory as an access transistor, the gate of the access transistor is located in the substrate, and the source and drain of the access transistor are located on both sides of the gate and the bottom of the access transistor is higher than the top of the gate.

[0133] Please refer to Figure 21 This is a schematic diagram of the memory structure according to another specific embodiment of the present invention.

[0134] Specifically, the substrate 2100 includes a substrate 2101, which includes an active region and an isolation structure 2102 surrounding the active region. In one embodiment, the isolation structure 2102 may be a shallow trench isolation structure.

[0135] The access transistor is formed within the active region of the substrate 2101. The access transistor includes a gate 2103 buried within the substrate 2101, a source 2105 and a drain 2106 located on either side of the gate 2103 within the substrate 2101, with their bottoms higher than the top of the gate 2103. An isolation layer 2107 is formed on the top of the gate 2103, flush with the surface of the substrate 2101. A gate dielectric layer 2104 is formed between the gate 2103 and the substrate 2101.

[0136] In this specific embodiment, two adjacent transistors are formed in each active region, that is, two gates 2104 are formed buried in the substrate 2101, and adjacent transistors share the same source. Specifically, the source 2105 is located between two adjacent gates 2104, and the drain 2106 is located outside the gate 2104.

[0137] The substrate 2100 further includes a first dielectric layer 2108 covering the surface of the substrate 2101, and the conductive contact pad 2013 is formed within the first dielectric layer 2108. A first electrical contact 2109 connecting the drain 2106 and a second electrical contact 2110 connecting the gate 2103 are also formed within the first dielectric layer 2108, the second electrical contact 2110 being used to connect the source line.

[0138] The conductive contact pad 2113 on the surface of the substrate 2100 is connected to the first electrical contact portion 2109. A storage layer 2120 is formed above the substrate 2100. The storage layer 2120 includes a first sub-storage layer 2121 and a second sub-storage layer 2122. The storage layer 2120 includes storage cells that vertically penetrate each sub-storage layer. The magnetic storage cells include magnetic tunnel junctions 2131 and 2132 and conductive pillars 2133 above and / or below the magnetic tunnel junctions. In other specific embodiments, the storage layer 2120 may also include three or more sub-storage layers.

[0139] In another specific embodiment, only one access transistor may be formed in each active region of the substrate 2101, including a gate buried in the active region, a source and a drain located on both sides of the gate, the drain being connected to the conductive contact pad 2113 to be electrically connected to the magnetic tunnel junction 2131 and the magnetic tunnel junction 2132.

[0140] In this specific embodiment, a second medium layer 2124 is also formed on the surface of the storage layer 2020, and a third contact portion 2123 connecting each storage cell is formed in the second medium layer 2124; a bit line 2130 is formed on the surface of the second medium layer 2123 and is connected to the third contact portion 2123.

[0141] The access transistors within the substrate are buried-gate transistors, which can significantly reduce the size of the transistors, thereby reducing the minimum spacing between memory cells and increasing the memory density. Furthermore, adjacent transistors can share a source electrode, further reducing the minimum spacing between memory cells.

[0142] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A magnetic random access memory, characterized in that, include: A substrate, wherein a conductive contact pad is formed on the surface of the substrate; A magnetic storage layer located on the surface of the substrate, the magnetic storage layer comprising at least two sub-storage layers stacked on the surface of the substrate, the magnetic storage layer comprising a plurality of magnetic storage cells vertically penetrating each sub-storage layer, the magnetic storage cells being connected one-to-one with the conductive contact pads, the magnetic storage cells comprising magnetic tunnel junctions, each sub-storage layer comprising at least one magnetic tunnel junction, and the magnetic tunnel junctions of adjacent magnetic storage cells being located in different sub-storage layers.

2. The magnetic random access memory according to claim 1, characterized in that, The magnetic tunnel junctions of the multiple magnetic storage cells are randomly arranged within each sub-storage layer.

3. The magnetic random access memory according to claim 1, characterized in that, The magnetic tunnel junctions within each sub-storage layer are arranged in a random or array-like manner.

4. The magnetic random access memory according to claim 1, characterized in that, Within the same sub-storage layer, the spacing between at least some adjacent magnetic tunnel junctions is greater than the minimum spacing between magnetic random access memory cells.

5. The magnetic random access memory according to claim 1, characterized in that, Within the magnetic storage layer, the spacing between adjacent magnetic storage cells is 'a'; within the same sub-storage layer, the minimum spacing between adjacent magnetic tunnel junctions is 'a'. a and n are the number of sub-storage layers within the magnetic storage layer.

6. The magnetic random access memory according to claim 1, characterized in that, A dielectric layer is filled between adjacent magnetic storage cells of the magnetic storage layer.

7. The magnetic random access memory according to claim 1, characterized in that, Each magnetic storage cell also includes a conductive post, which is located in a sub-storage layer above and / or below the magnetic tunnel junction within the magnetic storage cell and is electrically connected to the magnetic tunnel junction.

8. The magnetic random access memory according to claim 1, characterized in that, The substrate also contains a plurality of access transistors, which are connected one-to-one with the memory cells. The access transistors include at least one of planar transistors, buried gate transistors, and ring gate transistors.

9. A method for forming a magnetic random access memory, characterized in that, include: A substrate is provided, wherein a conductive contact pad is formed on the surface of the substrate; A magnetic storage layer is formed on the substrate to connect the conductive contact pad. The magnetic storage layer includes at least two sub-storage layers stacked on the surface of the substrate. The magnetic storage layer includes a plurality of magnetic storage cells that vertically penetrate each sub-storage layer. The plurality of magnetic storage cells are arranged in an array. Each magnetic storage cell includes a magnetic tunnel junction. Each sub-storage layer includes at least one magnetic tunnel junction. The magnetic tunnel junctions of adjacent magnetic storage cells are located in different sub-storage layers.

10. The method for forming a magnetic random access memory according to claim 9, characterized in that, Each magnetic storage cell also includes a conductive post, which is located in a sub-storage layer above and / or below the magnetic tunnel junction within the magnetic storage cell and is electrically connected to the magnetic tunnel junction.

11. The method for forming a magnetic random access memory according to claim 9, characterized in that, Each sub-storage layer is formed layer by layer from the surface of the substrate upwards.

12. The method for forming a magnetic random access memory according to claim 11, characterized in that, The method for forming each sub-memory layer includes: forming a magnetic tunnel junction structure layer; forming a patterned mask layer on the surface of the magnetic tunnel junction structure layer; etching the magnetic tunnel junction structure layer using the patterned mask layer as a mask to form a magnetic tunnel junction; forming a dielectric layer filling the spaces between the magnetic tunnel junctions; etching the dielectric layer to form vias; and forming conductive pillars filling the vias.

13. The method for forming a magnetic random access memory according to claim 11, characterized in that, During the formation of different sub-storage layers, patterned mask layers with different patterns are used respectively, and the pattern positions of each patterned mask layer do not overlap.

14. The method for forming a magnetic random access memory according to claim 13, characterized in that, Within the same sub-storage layer, the spacing between at least some adjacent magnetic tunnel junctions is greater than the minimum spacing between magnetic random access memory cells.

15. The method for forming a magnetic random access memory according to claim 12, characterized in that, Within the magnetic storage layer, the spacing between adjacent magnetic storage cells is 'a'; when forming each sub-storage layer, the minimum spacing between adjacent patterns in the patterned mask layer is 'a'. a and n are the number of sub-storage layers within the magnetic storage layer.

16. The method for forming a magnetic random access memory according to claim 9, characterized in that, The substrate also contains a plurality of access transistors, which are connected one-to-one with the memory cells. The access transistors include at least one of planar transistors, buried gate transistors, and ring gate transistors.

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