Tracking instruction execution

Abstract

A method of tracking instruction execution on a processor of an integrated circuit chip in real time while the processor continues to execute instructions during clock cycles of the processor is disclosed. The method includes monitoring instruction execution of the processor by counting a number of consecutive instructions that are used consecutively in time to form an instruction count and counting a number of consecutive clock cycles of the processor during which no instructions are used to form a stall count; generating a trace message that includes the instruction count and the stall count; and outputting the trace message.

Description

Technical Field

[0001] This invention relates to tracking instruction execution on a processor such as a CPU (Central Processing Unit) on an integrated circuit chip. Background Technology

[0002] In the past, embedded systems with multiple core devices (processors, memory, etc.) were integrated into printed circuit boards (PCBs) and connected to the PCB via buses. Communication within the embedded system was transmitted through these buses. This arrangement facilitated monitoring of the core devices because monitoring tools such as oscilloscopes and logic analyzers could be attached to the PCB buses, allowing direct access to the core devices.

[0003] Market demand for smaller products and advancements in semiconductor technology have led to the development of System-on-Chip (SoC) devices. In an SoC, multiple core devices of an embedded system are integrated onto a single chip. In an SoC, communication within the embedded system is transmitted via an internal bus, making it impossible to directly connect monitoring tools to the system bus. The resulting reduced access and the increasing amount of data transmitted around the chip (due to the integration of multiple processing cores and higher internal clock frequencies resulting from SoC technology advancements) diminish the ability of external monitoring tools to monitor for security breaches, vulnerabilities, and security issues within industry-required timeframes. Furthermore, when multiple core devices are embedded on the same chip, the behavior of each individual core device differs from its isolated behavior due to its interactions with other core devices and real-time events such as triggers and alarms.

[0004] Therefore, the development of SoC devices necessitates the development of monitoring technologies, leading to the integration of monitoring functions onto the SoC. It is now known that on-chip monitoring circuitry tracks the execution of programs running on core devices such as the CPU. Trace data is typically output for off-chip analysis. However, this trace data provides limited temporal details about the execution of programs on the core processor. More detailed trace data is needed. Summary of the Invention

[0005] According to a first aspect, a method is provided for real-time tracking of instruction execution on a processor of an integrated circuit chip, while the processor continues to execute instructions during the processor's clock cycle. The method includes: at a tracking circuit on the integrated circuit chip, monitoring the processor's instruction execution by: counting the number of consecutive instructions that are time-continuously stopped to form an instruction count; and counting the number of subsequent consecutive clock cycles of the processor during which no instructions are stopped to form a delay count; generating a tracking message including the instruction count and the delay count; and outputting the tracking message.

[0006] The method may further include comparing the delay count with a threshold delay count; and generating and outputting a trace message only when the delay count is equal to or exceeds the threshold delay count.

[0007] The method may include: if the delay count is less than a threshold delay count, then: resetting the delay counter to count 0; counting another number of consecutively disabled instructions; counting the number of subsequent consecutive clock cycles of the processor during which no instructions are disabled to form another delay count; comparing the other delay count with the threshold delay count; and only if the other delay count is equal to or exceeds the threshold delay count: generating a trace message including the other instruction count and the other delay count, the other instruction count being the sum of the instruction count, the delay count, and the other number of consecutively disabled instructions; and outputting the trace message.

[0008] The method may include incrementing the instruction count by a delay count to form an increased instruction count, wherein another number of consecutively disabled instructions is counted starting from the increased instruction count to form the other instruction count.

[0009] The method may include resetting an instruction counter to count 0, wherein the counting of the additional number of consecutively disabled instructions starts from 0, and the method further includes adding the instruction count, the delay count, and the additional number of consecutively disabled instructions to form the additional instruction count.

[0010] The method may include: if the other delay count is less than the threshold delay count, then iteratively executing the above method, and generating and outputting a trace message only when the iterative delay count is equal to or exceeds the threshold delay count.

[0011] According to a second aspect, a method is provided for real-time tracking of instruction execution on a processor of an integrated circuit chip, wherein the processor continues to execute multiple instructions simultaneously during a processor clock cycle, and the processor is capable of terminating more than one instruction in each clock cycle. The method includes: at a tracking circuit on the integrated circuit chip: monitoring the processor's instruction execution by the following steps: counting the number of instructions terminated in each clock cycle to form a clock cycle count; and counting the number of consecutive clock cycles of the processor during which no instructions are terminated to form a delay count; generating a tracking message including the clock cycle count and the delay count; and outputting the tracking message.

[0012] The method may further include counting the number of unused instructions executed to form an unused count.

[0013] The tracking message can further include the unused count.

[0014] The method may further include using run-length encoding to encode the counts in the trace message.

[0015] This method may include encoding the counts in the tracking message using Elias Gamma codes.

[0016] According to a third aspect, an integrated circuit chip is provided, comprising: a processor configured to execute instructions during a clock cycle of the processor; a trace circuit configured to trace the instruction execution of the processor in real time, the trace circuit comprising: an instruction counter configured to count the number of consecutive instructions that are time-continuously stopped to form an instruction count; a delay counter configured to count the number of subsequent consecutive clock cycles of the processor during which no instructions are stopped to form a delay count; a message generator configured to generate a trace message including the instruction count and the delay count; and an output device configured to output the trace message.

[0017] The integrated circuit chip may further include a comparator configured to compare a delay count with a threshold delay count.

[0018] According to a fourth aspect, an integrated circuit chip is provided, comprising: a processor configured to invalidate more than one instruction in each clock cycle of the processor; a tracking circuit configured to track the instruction execution of the processor in real time, the tracking circuit comprising: a clock cycle counter configured to count the number of instructions invalidated in each clock cycle to form a clock cycle count; a delay counter configured to count the number of consecutive clock cycles in which no instructions are invalidated during a period of the processor to form a delay count; a message generator configured to generate a tracking message including the clock cycle count and the delay count; and an output device configured to output the tracking message.

[0019] The integrated circuit chip may further include another counter configured to count the number of unused instructions executed to form an unused count. Attached Figure Description

[0020] The invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

[0021] Figure 1 This is a schematic diagram of an exemplary monitoring architecture on an integrated circuit chip device;

[0022] Figure 2 This is a schematic diagram of an exemplary monitoring architecture on an integrated circuit chip device;

[0023] Figure 3 This is a schematic diagram of an exemplary monitoring architecture for tracking processors;

[0024] Figure 4 A method for tracing processor instruction execution is shown;

[0025] Figure 5 This demonstrates another method for tracing processor instruction execution;

[0026] Figure 6 This is a schematic diagram of an exemplary monitoring architecture for tracking superscalar processors; and

[0027] Figure 7 A method for tracking instruction execution in a superscalar processor is shown. Detailed Implementation

[0028] The following disclosure describes a monitoring architecture suitable for implementation on an integrated circuit chip. The integrated circuit chip can be a System-on-a-Chip (SoC) or a Multi-Chip Module (MCM).

[0029] Figures 1 to 3 and Figure 6 These are schematic diagrams of an exemplary monitoring architecture and the components within that architecture. The structure is presented in the form of functional blocks. Some functional blocks used to perform functions well-known in the art have been appropriately omitted in certain places within these diagrams. Figure 4 , Figure 5 and Figure 7 These are flowcharts illustrating the methods of a tracer processor. Each flowchart depicts the sequence in which the methods of that flowchart can be executed. However, the flowcharts are not intended to limit the described methods to the order in which they are implemented. The steps of the method may be performed in a different order than that depicted in the flowcharts.

[0030] Figure 1 The overall structure of an exemplary monitoring architecture for SoC 100 is shown. Monitoring circuitry 101 is arranged as monitoring system circuitry 102. Figure 2 An exemplary system circuit including core devices and communication interfaces is shown. The core devices 201, 202, and 203 of the SoC are connected to monitoring circuitry 101. Although... Figure 2 Three core devices are shown, but any number of core devices can be appropriately integrated into a surveillance architecture. Exemplary core devices include a DSP (Digital Signal Processor), video processor, application processor, CPU, graphics processor, system memory, bus, system interconnect, RTOS (Real-Time Operating System), software, data, custom circuitry, and data engine. However, any component of the SoC is suitable as... Figure 2 The core devices on the chip are integrated into the monitoring architecture. These core devices can be emulators or simulators of other devices on the chip. For example, a core device can emulate the processor.

[0031] The monitoring circuitry can monitor the operation of the core device and, optionally, can also manipulate its operation. The monitoring circuitry is connected to communication interface 204. Communication interface 204 can be configured to communicate with entities outside the chip. For example, monitoring circuitry 101 can communicate with an external analyzer via communication interface 204. Communication interface 204 can also be configured to communicate with other entities on the chip. For example, monitoring circuitry 101 can communicate with an on-chip analyzer via communication interface 204. Although... Figure 2 One communication interface is shown, but any number of communication interfaces can be integrated onto the SoC. The implemented communication interface is selected based on the type of connection to be established. Exemplary communication interfaces include: JTAG, parallel trace input / output, and a high-speed serial interface based on Aurora; and reuse of system interfaces such as USB, Ethernet, RS232, PCIe, and CAN. Within monitoring circuitry 101, different monitoring circuitry may exist associated with each core device. Alternatively or additionally, some monitoring circuitry may be associated with two or more core devices.

[0032] The following description focuses on Figure 2 The core device is a processor, and this processor is monitored by the tracking circuit of monitoring circuit 101 in this example. The processor can be, for example, a CPU, GPU, or DSP.

[0033] refer to Figure 3 The architecture shown includes processor 301 with processing logic 302 that executes programs (also called instructions). These executable instructions are stored in memory 303. The processor is clocked at a clock rate. Therefore, processor 301 executes instructions during processor clock cycles. The clock rate can be set by an internal clock 304 of the processor. The processor may take a single clock cycle to complete the execution of an instruction. The processor may take several clock cycles to complete the execution of an instruction. Using pipelining, the processor can perform intermediate execution of several instructions simultaneously. However, the processor begins execution of at most one instruction per clock cycle. The processor retires at most one instruction per clock cycle. As used herein, the term "retire" is used in conjunction with an instruction to indicate that the processor has completed the execution of that instruction.

[0034] The trace circuit 308 tracks the instruction execution of the processor 301. This is done without interference. The trace circuit 308 monitors the processor 301 without interrupting its operation. In other words, the trace circuit tracks the processor without requiring the processor to stop or modify its instruction execution. The processor can continue to operate normally. Therefore, the processor can continue to execute instructions and output to other circuits on and / or outside the chip. The trace circuit tracks the processor 301 and outputs trace data in real time.

[0035] The trace circuit 308 includes an instruction counter 307. The instruction counter 307 receives processor outputs from the processor 301. The instruction counter 307 can also receive a clock input 305 from a clock 309. The clock 309 is internal to the trace circuit 308. The clock 309 can receive its clock signal from the processor clock 304. The instruction counter 307 counts the number of consecutive instructions that are time-continuously disabled to form an instruction count. When the instruction counter detects that the processor has not disabled an instruction during a time gap, it responds by stopping the count. The instruction counter can then output its instruction count to the message generator 310.

[0036] The tracking circuit 308 also includes a stall counter 311. The stall counter 311 receives processor outputs from the processor 301. The stall counter 311 also receives a clock input 312 from the clock 309. The stall counter 311 also receives an output 313 from the instruction counter 307. This output identifies when the instruction counter has stopped counting. The stall counter counts the number of consecutive clock cycles during which no instructions are stopped, forming a stall count. The stall counter begins counting immediately after the end of a sequential series of stopped instructions counted by the instruction counter. The stall counter starts counting when it receives a signal 313 from the instruction counter indicating that it has stopped counting. When the stall counter recognizes that an instruction has stopped, it responds by stopping counting. The stall counter 311 is clocked by the clock 309 at the same clock rate as the processor 301. This can be achieved by the clock 309 receiving a signal from the processor's clock 304. Therefore, the number of clock cycles counted by the stall counter 311 is the same as the number of processor clock cycles that have been delayed. The delay counter 311 outputs its delay count to the message generator 310.

[0037] Message generator 310 generates a trace message that includes instruction counts and delay counts. Output unit 314 outputs the trace message from trace circuit 308. This trace message can then be output to communication interface 306. Communication interface 306 can then output the trace message externally and / or route the trace message on-chip, as referenced above. Figure 2 The communication interface 204 is described above.

[0038] Therefore, refer to Figure 4 , Figure 3The trace circuit 308 monitors instruction execution of the processor 301 as follows: At step 401, the instruction counter 307 counts the number of consecutive instructions that are time-continuously stopped to form an instruction count. Immediately following this, at step 402, a delay counter counts the number of subsequent consecutive clock cycles of the processor during which no instructions are stopped to form a delay count. At step 403, a message generator generates a trace message that includes the instruction count and the delay count. At step 404, the output device 314 outputs the trace message.

[0039] The instruction counter continues to receive processor output from processor 301. After outputting its instruction count to message generator 310, the instruction counter resets its count to 0. Then, when instruction counter 307 receives the next deactivated instruction from processor 301, it starts counting again and repeats. Figure 4 The delay counter continues to receive processor output from processor 301. After outputting its delay count to message generator 310, the delay counter resets its count to 0. Then, upon receiving the next signal 313 from the instruction counter that identifies it has stopped counting, the delay counter 311 starts counting again.

[0040] therefore, Figure 3 The device and Figure 4 This method enables on-chip monitoring circuitry to track processor instruction execution and output timing data that identifies how many consecutive instructions the processor disables and how long the processor delays before resuming instruction execution. The processor may delay due to, for example, a cache miss, an unexpected branch in the instruction, a missing instruction, or an incomplete instruction. The timing data, along with other monitoring data, is then analyzed. This can be used to reconstruct the program execution flow. It can be used to identify changes that can be made to the instruction set and / or processor operation to optimize processor performance and make instruction execution more efficient. Other monitoring data can be any monitoring data known to those skilled in the art. For example, actual processor output, detailed register access information, etc.

[0041] Figure 3 Other optional components within the tracking circuit are also shown, indicated by dashed outlines of those components in the figure. The circuit includes a comparator 315. Comparator 315 receives a delay count as a first input from a delay counter 311. Comparator 315 receives a threshold delay count as a second input from a memory 316. The comparator compares the delay count with the threshold delay count. The comparator output is sent to a controller 317. Controller 317 has a control output 318 to an instruction counter 307. Controller 317 also has a control output 319 to the delay counter 311.

[0042] Now refer to Figure 5 The operation of these additional components is described. At step 501, instruction counter 307 counts the number of consecutive instructions that are time-continuously stopped to form an instruction count. Immediately following this, at step 502, delay counter counts the number of subsequent consecutive clock cycles of the processor to form a delay count during which no instructions are stopped. Comparator 315 receives the delay count from the delay counter and also receives a threshold delay count from memory 316. Comparator 315 compares the delay count with the threshold delay count and outputs the result to controller 317.

[0043] At step 503, controller 317 controls instruction counter 307 to output its instruction count only when the delay count is equal to or exceeds the threshold delay count, and controller 317 controls delay counter 311 to output its delay count. The message generator receives both the instruction count and the delay count, and continues generating a trace message at step 506. The trace message is then output at step 507. At step 503, if the delay count is less than the threshold delay count, then at step 504, controller 317 controls the delay counter to discard the delay count. In other words, controller 317 controls the delay counter to reset its delay count to 0. At step 505, the controller controls the instruction counter to increment its instruction count by the delay count to form an increased instruction count.

[0044] The instruction count and delay count are not output from the instruction counter and delay counter to the message generator. Therefore, no message containing the instruction count and delay count is generated and output. Instead, the method returns to step 501 and continues. Figure 5 The flowchart is further iterated. This time, starting from the incrementing instruction count, the instruction counter counts the number of consecutively stopped instructions to form another instruction count. Immediately following, at step 502, starting from count 0, the delay counter counts the number of subsequent consecutive clock cycles of the processor during which no instructions are stopped to form another delay count. The delay counter outputs this other delay count to a comparator. The comparator then compares this other delay count with a threshold delay count and outputs the result to controller 317. Controller 317 only controls instruction counter 307 to output its other instruction count and delay counter 311 to output its other delay count if the other delay count is equal to or exceeds the threshold delay count. The message generator receives both the other instruction count and the other delay count and continues to generate a trace message at step 506. The trace message is output at step 507.

[0045] However, if the other delay count is less than the threshold delay count, then at step 504, the controller controls the delay counter to reset the delay count to 0, and at step 505, the controller controls the instruction counter to increment the instruction count by the delay count. No trace message containing the other instruction count and the other delay count is generated. Then it is repeated again. Figure 5 The process.

[0046] Figure 5 The process is repeated iteratively until the iteration delay count equals or exceeds the threshold delay count. Once this occurs, the controller controls the instruction counter to output the associated iteration instruction count, and the controller controls the delay counter to output the iteration delay count. The message generator receives these counts and generates a trace message containing the iteration instruction count and the iteration delay count. At step 507, this trace message is output.

[0047] The instruction counter continues to receive processor output from processor 301. After outputting its iterative instruction count to message generator 310, the instruction counter resets its count to 0. Then, when instruction counter 307 receives the next deactivated instruction from processor 301, it starts counting again and repeats. Figure 5 The delay counter also continues to receive processor output from processor 301. After outputting its iterative delay count to message generator 310, the delay counter resets its count to 0. Then, the delay counter 311 restarts counting when it receives the next signal 313 from the instruction counter, indicating that it has stopped counting.

[0048] In the above method, if it is determined that the delay count is less than the delay count threshold, the delay counter is reset to 0, and the instruction counter is incremented by the delay count. In an alternative embodiment, after step 503, if the delay count is less than the delay count threshold, the controller 317 controls the adder ( Figure 3(Not shown in the diagram) The instruction count and delay count are added together. Then, both the delay counter and the instruction counter are reset to 0. The method then returns to step 501, in which the instruction counter starts counting from count 0 for the number of consecutively stopped instructions. At step 502, the delay counter starts counting from count 0 for the number of subsequent consecutive clock cycles of the processor during which no instructions are stopped. If at step 503, the next delay count is less than the delay count threshold, the controller 317 controls the adder to add the instruction count and delay count of the current iteration of the method to the result of the previous iteration. The controller then resets the counts of the instruction counter and the delay counter to 0 and repeats the method. When the iteration delay count from step 502 is equal to or exceeds the threshold delay count, the controller 317 controls the adder to output its current result to the message generator. The message generator generates a trace message containing the current result of the adder as the iteration instruction count. The trace message also contains the iteration delay count.

[0049] In an alternative implementation, at step 501, instruction counter 307 counts the number of consecutively disabled instructions and the number of consecutive delayed clock cycles. In other words, instruction counter 307 increments by 1 for each disabled instruction and by 1 for each delayed clock cycle. At step 502, after a series of consecutively disabled instructions, delay counter 311 counts the number of subsequent consecutive clock cycles of the processor to form a delay count during which no instructions are disabled. Comparator 315 compares the delay count to a threshold delay count. If the delay count is less than the threshold delay count, controller 317 resets the delay counter to 0. Controller 317 takes no action on instruction counter 307. At step 501, instruction counter continues to count the number of consecutively disabled instructions and the number of consecutive delayed clock cycles. After a series of consecutively disabled instructions, at step 502, delay counter 311 counts from 0 for the number of subsequent consecutive clock cycles of the processor to form an iterative delay count during which no instructions are disabled. If, at step 503, the next delay count is less than a delay count threshold, controller 317 resets the delay counter to 0 and takes no action on the instruction counter. This process is repeated. When the iterative delay count from step 502 equals or exceeds the threshold delay count, controller 317 controls the delay counter to output the iterative delay count to the message generator. Controller 317 also controls the instruction counter to output its instruction count to a subtractor. Figure 3(Not shown in the image), the subtractor subtracts the iteration delay count from the instruction count to form the iteration instruction count. The subtractor outputs the iteration instruction count to the message generator. The message generator generates a trace message that contains the iteration instruction count and the iteration delay count.

[0050] The threshold delay count can be stored in memory 316 during manufacturing. Alternatively, the threshold delay count can be configurable. For example, the threshold delay count can be dynamically reconfigured by the entity analyzing the trace messages.

[0051] When the processor delays over multiple cycles that are less than a threshold delay count, regarding Figure 5 The described method does not output trace messages. Instead, the delay is treated as a disabled instruction, and the trace circuit continues to count disabled instructions. This is in contrast to not using a threshold. Figure 4 Compared to other methods, this reduces the number of trace messages generated and output, and is therefore a more efficient tracing method. Appropriately, the threshold delay count is dynamically configured by the entity analyzing the trace messages, or on behalf of the entity analyzing the trace messages, based on the processor actions that entity is attempting to capture.

[0052] Figure 3 The description herein describes a processor capable of starting to execute at most one instruction per clock cycle and capable of suspending at most one instruction per clock cycle. However, the concepts described herein also apply to processors capable of suspending more than one instruction per clock cycle. Figure 6A simplified version of this processor 601 is shown. Processor 601 includes processing logic 1 602, processing logic 2 603, processing logic 3 604, and processing logic 4 605. Each of these processing logic components executes instructions stored in memory 606 during a processor clock cycle. Each processing logic outputs the instructions it executes to buffer 617. Each processing logic is capable of starting to execute one instruction within the same clock cycle as another processing logic begins executing another instruction. Each processing logic is capable of invalidating one instruction within the same clock cycle as another processing logic invalidates an instruction. Buffer 617 reorders invalidated instructions such that they are invalidated from processor 601 in the same order as they began execution. For example, buffer 617 may have four channels 0, 1, 2, and 3. Buffer 617 reorders the execution of invalidations from processing logics 1, 2, 3, and 4 such that the invalidated instructions on channels 0, 1, 2, and 3 are respectively in the same order as the instructions input to the processing logic. The clock rate can be a clock rate set by the processor's internal clock 607. Although four processing logic components are shown, processor 601 may have two, three, or more processing logic components capable of simultaneously initiating instruction execution, executing instructions, and deactivating instructions. Buffer 617 has the same number of channels as the number of processing logic components.

[0053] and Figure 3 Similarly, trace circuit 608 tracks the instruction execution of processor 601. Trace circuit 608 monitors processor 601 without interference (i.e., without interrupting the processor's operation).

[0054] The tracking circuit 608 includes a clock cycle counter 609. The clock cycle counter 609 receives processor output from the processor 601. The clock cycle counter 609 also receives a clock input 610 from a clock 611. The clock 611 is internal to the tracking circuit 608. The clock 611 can receive its clock signal from the processor clock 607. The clock cycle counter counts the number of instructions that are aborted in each clock cycle of the processor to form a clock cycle count. The maximum number of instructions aborted in each clock cycle of the processor is the number of instructions that the processor can abort in the same clock cycle. Figure 6 In the example, processor 601 can deselect four instructions in the same clock cycle, so the clock cycle count is 0, 1, 2, 3, or 4. Clock cycle counter 609 is clocked by clock 611 at the same clock rate as processor 601. This is achieved by clock 611 receiving a signal from processor clock 607. Therefore, the number of instructions deselected by the clock cycle counter in each clock cycle is the number of instructions deselected by the processor in each processor clock cycle. The clock cycle counter outputs its clock cycle count to message generator 612.

[0055] The tracking circuit 608 also includes a delay counter 613. The delay counter receives processor output from the processor 601. The delay counter also receives clock input 614 from the clock 611. The delay counter counts the number of consecutive clock cycles of the processor to form a delay count, during which no instruction is invalidated. The delay counter identifies when there is a clock cycle without instruction invalidation and starts counting from 0. When the delay counter identifies a cycle where an instruction has been invalidated, it stops counting. The delay counter 613 is clocked by the clock 611 at the same clock rate as the processor 601. This can be achieved by the clock 611 receiving a signal from the processor's clock 607. Therefore, the number of clock cycles counted by the delay counter 613 is the same as the number of processor clock cycles that have been delayed. The delay counter 613 outputs its delay count to the message generator 612.

[0056] Message generator 612 generates a trace message that includes clock cycle counts and delay counts. Output device 615 outputs the trace message from trace circuit 608. The trace message can then be output to communication interface 616. Communication interface 616 can then output the trace message externally and / or route the trace message on-chip, as referenced above. Figure 2 The communication interface 204 is described above.

[0057] Therefore, refer to Figure 7 , Figure 6 The trace circuit 608 monitors instruction execution of the processor 601 as follows: At step 701, a clock cycle counter 609 counts the number of instructions stopped during a processor clock cycle to form a clock cycle count. Immediately following this, at step 702, a delay counter counts consecutive clock cycles of the processor to form a delay count during which no instructions are stopped. If the processor stops one or more instructions during a clock cycle immediately after the clock cycle counter analyzes the clock cycle to form a clock cycle count, the delay counter outputs a delay count that identifies no delay. For example, the delay count value can be 0. As another example, the delay count value can be 1. At step 703, a message generator generates a trace message that includes the clock cycle count and the delay count. At step 704, an output device 615 outputs the trace message.

[0058] The clock cycle counter continues to receive processor output from processor 601. After outputting its instruction count to message generator 612, clock cycle counter 609 resets its count to 0. Then, clock cycle counter 609 starts counting again at the next clock cycle of the processor and repeats. Figure 7 The method.

[0059] therefore, Figure 6 The device and Figure 7 This method enables on-chip monitoring circuitry to track processor instruction execution and output timing data that identifies how many instructions were paused in each processor cycle and how many clock cycles the processor delayed before resuming instruction execution. Then, as per [the relevant information]... Figure 3 Analyze the time series data as described.

[0060] Figure 3 and Figure 6 The tracking circuit may optionally further include an unused counter 800. This is shown in dashed outline in the figure. The unused counter receives processor output from processors 301 and 601. The unused counter also receives clock input from clocks 309 and 611. The unused counter 800 is clocked by clocks 309 and 611 at the same clock rate as processors 301 and 601. The unused counter counts missed stopping opportunities. In other words, the unused counter counts the number of times an instruction could have been stopped but was not. For more information on... Figure 5 The described method involves, after a series of consecutive instructions that are temporally terminated, an undetermined counter counting the number of subsequent consecutive clock cycles during which no instructions are terminated. If this count is greater than or equal to a threshold delay count, the undetermined counter discards the count and resets to 0. If the count is less than the threshold delay count, the undetermined counter outputs this count as an undetermined count to the message generator. (For more information...) Figure 7 The described method uses an unused counter to count the number of instructions that could have been stopped but were not during a clock cycle. Figure 6 In the example, four instructions can be deactivated per clock cycle. Therefore, if 4, 3, 2, 1, or 0 instructions are deactivated, the deactivated count of the deactivated counter will be 0, 1, 2, 3, 4. The deactivated counter outputs this deactivated count to the message generator. The message generator includes the deactivated count in the trace message, which is then output.

[0061] Message generators 310 and 612 can generate and output a trace message that includes a single instruction count / clock cycle count, a single delay count, and optionally a single unused count. Alternatively, message generator 310 can receive several groups of instruction counts / clock cycle counts and delay counts (and optional unused counts) from several iterations of the method described herein, concatenate these groups of counts in the payload of a single trace message, and then output the trace message. For example, the trace message may have a maximum payload length. Upon receiving a group of instruction counts / clock cycle counts and delay counts (and optional unused counts), the message generator adds that group to the payload of the trace message. If the maximum payload length is not exceeded, the message generator does not output the trace message. Instead, it waits to receive another group of counts. Upon receiving the next group of counts, the message generator adds that group to the payload of the trace message. This process is repeated until no further groups of counts will be included in the payload without exceeding the maximum payload length. At this point, the message generator outputs the trace message to outputs 314 and 615.

[0062] Message generators 310 and 612 can encode count values ​​from the tracking circuit counter in a compressed format within the tracking message. For example, it can use run-length encoding. Alternatively, the message generator can use Elias Gamma coding to encode the count values. Elias Gamma coding is particularly efficient when encoding small numbers. In cases of frequent processor delays, the methods described herein generate tracking messages encoding small count values ​​at a high rate. Encoding efficiency is especially important in such situations to help minimize the time spent reporting tracking data.

[0063] The message generator can generate token sets representing tracking data. For example, in Figure 4 or Figure 5 In this method, the message generator can generate a group consisting of token pairs. The first token is an Elias gamma-encoded instruction count. The second token is an Elias gamma-encoded delay count. Figure 7 In this method, the message generator can generate a group consisting of token pairs. The first token is an Elias gamma-encoded clock cycle count. The second token is an Elias gamma-encoded delay count. In either case, the group may additionally include a third token, which is an Elias gamma-encoded unused count.

[0064] Figures 1 to 3 and Figure 6 Each component of the SoC shown can be implemented in dedicated hardware. Alternatively, Figures 1 to 3 and Figure 6Each component of the SoC shown can be implemented in software. Some components can be implemented in software, while others can be implemented in dedicated hardware.

[0065] The described SoC is suitably integrated within a computing-based device. The computing-based device can be an electronic device. Suitably, the computing-based device includes one or more processors for processing computer-executable instructions to control the operation of the device to implement the methods described herein. The computer-executable instructions can be provided using any computer-readable medium (e.g., memory). The methods described herein can be executed by software in a machine-readable form on a tangible storage medium. Software can be provided at the computing-based device to implement the methods described herein. For example, tracking circuitry may include counting logic to perform the counting operations described herein.

[0066] The above description portrays system circuitry and tracking circuitry as being contained within the same SoC. In alternative embodiments, system circuitry and tracking circuitry are included between two or more integrated circuit chips in the MCM. In an MCM, integrated circuit chips are typically stacked or placed adjacent to each other on an interposer substrate. Some system circuitry may reside on one integrated circuit chip, while other system circuitry may reside on different integrated circuit chips within the MCM. Similarly, tracking circuitry may be distributed across more than one integrated circuit chip in the MCM. Therefore, the methods and apparatus described above in the context of an SoC are also applicable to the context of an MCM.

[0067] Each individual feature described herein, and any combination of two or more such features, is capable of being performed based on the entire specification and on knowledge known to those skilled in the art, regardless of whether such features or combinations of features solve any problem disclosed herein, and is not limited to the scope of the claims. The applicant notes that aspects of the invention can be constituted by any such individual feature or combination of features. In view of the foregoing description, it will be apparent to those skilled in the art that various modifications can be made within the scope of the invention.

Claims

1. A method for real-time tracking of instruction execution on a processor of an integrated circuit chip, wherein the processor continues to execute instructions during the processor's clock cycle, the method comprising: At the tracking circuit on the integrated circuit chip: The execution of the processor's instructions is monitored in the following ways: An instruction counter is used to count the number of consecutive disable instructions to form an instruction count, wherein the consecutive disable instructions are generated consecutively in time, and wherein the instruction counter stops counting when it detects that the processor has no time gap to disable the instructions; and A delay counter is used to count the number of subsequent consecutive clock cycles of the processor during which no instructions are disabled, to form a delay count, wherein the delay counter begins counting immediately after a series of consecutive disabled instructions generated in time has ended, in response to a signal from the instruction counter that the instruction counter has stopped counting. Generate a trace message including the instruction count and the delay count; and Output the aforementioned tracking message.

2. The method according to claim 1, further comprising: The delay count is compared with the threshold delay count; and The tracking message is generated and output only when the delay count is equal to or exceeds the threshold delay count.

3. The method according to claim 2, comprising: If the delay count is less than the threshold delay count, then: Reset the delay count to 0; Another count is made of the consecutively generated deselective instructions; The number of subsequent consecutive clock cycles of the processor during which no instructions are stopped is counted to form another delay count; Compare the other delay count with the threshold delay count; and Only when the other delay count is equal to or exceeds the threshold delay count: Generate a trace message including another instruction count and the other delay count, wherein the other instruction count is the sum of the instruction count, the delay count, and the other number of consecutively generated deactivated instructions; and Output the aforementioned tracking message.

4. The method according to claim 3, comprising: The instruction count is increased by the delay count to form an increased instruction count; wherein, the other number of consecutively generated deactivated instructions is counted starting from the increased instruction count to form the other instruction count.

5. The method according to claim 3, comprising: The method further includes resetting the instruction count to count 0, wherein the other number of consecutively generated deactivated instructions is counted starting from 0, and the method also includes adding the instruction count, the delay count, and the other number of consecutively generated deactivated instructions to form the other instruction count.

6. The method according to claim 3 or 4, comprising: If the other delay count is less than the threshold delay count, the method according to claim 3 is executed iteratively, and a trace message is generated and output only when the iterative delay count is equal to or exceeds the threshold delay count.

7. A method for real-time tracking of instruction execution on a processor of an integrated circuit chip, wherein the processor simultaneously continues to execute multiple instructions during the processor's clock cycle, the processor being capable of interrupting more than one instruction in each clock cycle, the method comprising: At the tracking circuit on the integrated circuit chip: The execution of the processor's instructions is monitored in the following ways: An instruction counter is used to count the number of consecutive disable instructions in each clock cycle to form a clock cycle count, wherein the consecutive disable instructions are generated sequentially in time, and wherein the instruction counter stops counting when it detects that the processor has no time gap to disable instructions; and A delay counter is used to count the number of consecutive clock cycles of the processor during which no instruction is disabled to form a delay count, wherein the delay counter starts counting immediately after a series of consecutive disabled instructions generated in time is completed in response to a signal from the instruction counter that the instruction counter has stopped counting; Generate a trace message including the clock cycle count and the delay count; as well as Output the aforementioned tracking message.

8. The method according to claim 1 or 7, further comprising: The number of unused instructions executed is counted to form an unused count.

9. The method according to claim 8, wherein, The tracking message also includes the unused count.

10. The method according to claim 1 or 7, further comprising: Run-length encoding is used to encode the counts in the tracking messages.

11. The method of claim 10, comprising: The counts in the tracking messages are encoded using Elias Gamma codes.

12. An integrated circuit chip, comprising: A processor configured to execute instructions during the clock cycle of the processor; A tracing circuit configured to track the execution of instructions by the processor in real time, the tracing circuit comprising: An instruction counter is configured to count the number of consecutive disable instructions to form an instruction count, wherein the consecutive disable instructions are generated consecutively in time, and wherein the instruction counter is configured to stop counting when the instruction counter detects that the processor has no time gap to disable the instructions. A delay counter is configured to count the number of subsequent consecutive clock cycles of the processor during which no instruction is disabled to form a delay count, wherein the delay counter is configured to start counting immediately after a series of consecutive disabled instructions generated in time has ended, in response to a signal from the instruction counter that the instruction counter has stopped counting. A message generator configured to generate a trace message including the instruction count and the delay count; and An output device configured to output the trace message.

13. The integrated circuit chip according to claim 12, further comprising: A comparator is configured to compare the delay count with a threshold delay count.

14. An integrated circuit chip, comprising: A processor configured to stop more than one instruction in each clock cycle of the processor; A tracing circuit configured to track the execution of instructions by the processor in real time, the tracing circuit comprising: A clock cycle counter is configured to count the number of consecutive disable instructions in each clock cycle to form a clock cycle count, wherein the consecutive disable instructions are generated consecutively in time, and wherein the clock cycle counter is configured to stop counting when the clock cycle counter detects that the processor has no time gap to disable the instructions. A delay counter is configured to count the number of consecutive clock cycles of the processor during which no instruction is disabled to form a delay count, wherein the delay counter is configured to start counting immediately after a series of consecutive disabled instructions generated in time has ended, in response to a signal from the clock cycle counter that indicates that the clock cycle counter has stopped counting. A message generator configured to generate a trace message including the clock cycle count and the delay count; and An output device configured to output the trace message.

15. The integrated circuit chip according to claim 12 or 14, further comprising: Another counter is configured to count the number of unused instructions executed to form an unused count.

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