Non-volatile memory device, storage device, and memory controller operation method

Abstract

Non-volatile memory devices, memory devices, and memory controller operation methods are provided. The non-volatile memory devices include a command decoder to receive and decode first and second commands, a first control circuit to generate first control information under control of the command decoder decoding the first command, a second control circuit to generate second control information under control of the command decoder decoding the second command, a first memory bank including first memory cells to operate based on the first control information, and a second memory bank including second memory cells to operate based on the second control information. A first time to output data from the first memory bank in response to the first command is different from a second time to output data from the second memory bank in response to the second command.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0046813, filed on April 22, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the inventive concept described herein relate to semiconductor memory devices, and more specifically, to non-volatile memory devices comprising storage media operating in different operating modes, methods of operating a memory controller, and memory devices comprising a non-volatile memory device and a memory controller. Background Technology

[0003] Requests sent by the host to the memory system are categorized based on the purpose of the memory system's operation and the characteristics of the data to be read or written. For example, a host's request might be for the memory system to operate at its highest speed, for the memory system to consume the least amount of power, or for operation with high reliability.

[0004] To maximize performance, the memory system should perform individual operations based on different requests from the host. This requires controlling the memory devices in the memory system by dividing them into multiple regions and controlling each of these regions separately, according to the different requests from the host. Summary of the Invention

[0005] Embodiments of the inventive concept provide a non-volatile memory device, a method of operating a memory controller, and a storage device including a non-volatile memory device and a memory controller.

[0006] According to some example embodiments, a non-volatile memory device may include: a command decoder that receives and decodes a first command and a second command; a first control circuit that generates first control information under the control of the command decoder that decodes the first command; a second control circuit that generates second control information under the control of the command decoder that decodes the second command; a first memory bank including first memory cells that operate based on the first control information; and a second memory bank including second memory cells that operate based on the second control information. The first time at which data is output from the first memory bank in response to the first command may differ from the second time at which data is output from the second memory bank in response to the second command.

[0007] According to some example embodiments, an operation method of a memory controller connected to a memory device may include: dividing a plurality of memory banks of the memory device into memory banks that operate in a first mode and memory banks that operate in a second mode different from the first mode; receiving a first request from a host corresponding to the first mode, and in response to the first request sending a first memory bank address corresponding to a first memory bank in the memory banks operating in the first mode to the memory device; and further receiving a second request from the host corresponding to the second mode, and in response to the second request sending a second memory bank address corresponding to a second memory bank in the memory banks operating in the second mode to the memory device.

[0008] According to some example embodiments, a storage device may include: a non-volatile memory device including a first memory bank, a second memory bank, a first control circuit configured to control the first memory bank in response to a first control information, and a second control circuit configured to control the second memory bank in response to a second control information; and a memory controller configured to send a first read command to the non-volatile memory device in response to a first request from a host to read the first memory bank, and configured to send a second read command to the non-volatile memory device in response to a second request from the host to read the second memory bank. A first time delay from the time the memory controller sends the first read command to the time the memory controller receives data from the first memory bank corresponding to the first read command may be different from a second time delay from the time the memory controller sends the second read command to the time the memory controller receives data from the second memory bank corresponding to the second read command. Attached Figure Description

[0009] The above-mentioned objects and features of the inventive concept, as well as other objects and features, will become apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a non-volatile memory device according to some example embodiments of the inventive concept.

[0011] Figure 2 This is the architecture of a non-volatile memory device based on some example embodiments of the inventive concept.

[0012] Figure 3 It is shown that it includes Figure 1 A block diagram of an example memory cell array in a non-volatile memory device.

[0013] Figure 4 It shows the direction over time. Figure 1 The first and second memory banks provide a graph of write voltage.

[0014] Figure 5It shows the direction over time. Figure 1 The first and second memory banks provide a graph of bit line voltages.

[0015] Figure 6 These are examples illustrating some embodiments based on the inventive concept. Figure 1 A block diagram of a non-volatile memory device.

[0016] Figure 7 It is provided to Figure 6 Timing diagram of signals for a non-volatile memory device.

[0017] Figure 8 These are examples illustrating some embodiments based on the inventive concept. Figure 2 A block diagram of a non-volatile memory device.

[0018] Figure 9 It is shown Figure 6 Block diagram of the memory controller.

[0019] Figure 10 This is a flowchart illustrating a method of operating a memory controller according to some example embodiments of the inventive concept.

[0020] Figure 11 This is a flowchart illustrating a method for changing the type of memory included in a non-volatile memory device, according to some example embodiments of the inventive concept. Detailed Implementation

[0021] Hereinafter, embodiments of the inventive concept will be described in detail and clearly to the extent that those skilled in the art can easily implement the inventive concept.

[0022] Figure 1 This is a block diagram illustrating some example embodiments of a non-volatile memory device according to an inventive concept. The non-volatile memory device 100 may include: a command decoder 110, an address buffer 120, a first control circuit 130, a second control circuit 140, a first memory bank 150, a second memory bank 160, and / or input / output circuitry 170.

[0023] The non-volatile memory device 100 can receive commands CMD and addresses ADDR from an external device (e.g., a memory controller). The non-volatile memory device 100 can write data DQ to one of a first memory bank 150 and a second memory bank 160 based on the commands CMD and ADDR. The non-volatile memory device 100 can read data stored in one of the first memory bank 150 and the second memory bank 160 based on the commands CMD and ADDR, and can output the read data as data DQ.

[0024] In some example embodiments, one or more of the command decoder 110, the first control circuitry 130, the second control circuitry 140, the memory controller, and / or any portion thereof may be included, may include, and / or may be implemented as one or more instances of processing circuitry (such as hardware including logic circuitry), hardware / software combinations (such as a processor executing software), and combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory device) and a processor, the non-transitory computer-readable storage device being, for example, a solid-state drive (SSD) storing a program of instructions, and the processor being configured to execute the program of instructions to implement the functions of one or more of the command decoder 110, the first control circuitry 130, the second control circuitry 140, and the memory controller.

[0025] Command decoder 110 can decode commands (CMDs) received from an external device (e.g., a memory controller). Command decoder 110 can receive addresses (ADDRs). Command decoder 110 can determine whether the received command (CMD) is associated with a first memory bank 150 or a second memory bank 160 by referring to the memory bank address (BA) included in the address (ADDR). Command decoder 110 can select and / or activate one of the first control circuitry 130 and the second control circuitry 140 based on the command (CMD) and the address (ADDR). For example, the command (CMD) may include a read command, write command, activation command, update command, and / or a reclassification command for the first memory bank 150 or the second memory bank 160.

[0026] Address buffer 120 may receive address ADDR from an external device (e.g., a memory controller). Address buffer 120 may provide address ADDR to command decoder 110. Address buffer 120 may provide address ADDR to one of first control circuit 130 and second control circuit 140 under the control of command decoder 110.

[0027] Under the control of command decoder 110, address buffer 120 can provide the received address ADDR as row address RA to row decoder 152 and row decoder 162, and / or can provide the received address ADDR as column address CA to column decoder 153 and column decoder 164.

[0028] The first control circuit 130 can generate first control information under the control of the command decoder 110, and can provide a first control signal CTRL1 based on the first control information to the first memory bank 150. The second control circuit 140 can generate second control information under the control of the command decoder 110, and can provide a second control signal CTRL2 based on the second control information to the second memory bank 160. The first control circuit 130 and the second control circuit 140 can control the operation of the first memory bank 150 and the second memory bank 160 respectively by using the first control signal CTRL1 and the second control signal CTRL2.

[0029] The first control signal CTRL1 may include a first row control signal CTRL1_RA for controlling the row decoder 152, a first column control signal CTRL1_CA for controlling the column decoder 153, and a first read / write control signal CTRL1_RW for controlling the write driver 154 and the sense amplifier 155. The second control signal CTRL2 may include a second row control signal CTRL2_RA for controlling the row decoder 162, a second column control signal CTRL2_CA for controlling the column decoder 163, and a second read / write control signal CTRL2_RW for controlling the write driver 164 and the sense amplifier 165. (Refer to...) Figure 4 and Figure 5 A more comprehensive description is provided of the first row control signal CTRL1_RA, the second row control signal CTRL2_RA, the first column control signal CTRL1_CA, the second column control signal CTRL2_CA, the first read / write control signal CTRL1_RW, and the second read / write control signal CTRL2_RW.

[0030] The first control circuit 130 may include register R1. The second control circuit 140 may include register R2. Registers R1 and R2 may respectively include first control information and second control information associated with the operating modes, operating characteristics, and operating settings of the first memory bank 150 and the second memory bank 160. Here, the operating modes, operating characteristics, and operating settings of the first memory bank 150 may include at least one of the operating speed of the first memory bank 150, the power consumption of the first memory bank 150, and information regarding the reliability of the operation of the first memory bank 150. The first control circuit 130 may generate a first control signal CTRL1 with reference to register R1. The second control circuit 140 may generate a second control signal CTRL2 with reference to register R2.

[0031] In some exemplary embodiments, command decoder 110 may receive update requests for the first memory bank 150 from an external device (e.g., a host). Under the control of command decoder 110 receiving the update request, the first control circuit 130 may store second control information instead of first control information. When command decoder 110 receives a command for a memory cell of the first memory bank 150 from an external device, the memory cell of the first memory bank 150 may operate based on the second control information instead of the first control information.

[0032] The first memory bank 150 may include a memory cell MC that operates based on first control information. The second memory bank 160 may include a memory cell MC that operates based on second control information. The first memory bank 150 and the second memory bank 160 may perform write operations and read operations independently or simultaneously. A write operation may include a set operation that changes the logic value of the memory cell MC from a first logic value "0" to a second logic value "1", and a reset operation that changes the logic value of the memory cell MC from the second logic value "1" to the first logic value "0". Here, the logic values ​​stored in the memory cell MC through the set and reset operations are merely examples.

[0033] The first memory bank 150 and the second memory bank 160 can perform write or read operations based on operation setting information. Here, the operation setting information may include information about one or more signals used to perform write or read operations on the first memory bank 150 and the second memory bank 160. In some example embodiments, the operation setting information may include information about bit line signals, word line signals, set signals, and reset signals. Information about bit line signals, word line signals, set signals, and reset signals may include, but is not limited to, information about the amplitude, pulse duration (or pulse period), and timing of each signal.

[0034] The first memory bank 150 and the second memory bank 160 can operate in different modes. For example, the first memory bank 150 can operate in a mode with low reliability, high power consumption, or high speed; while the second memory bank 160 can operate in another mode with high reliability, low power consumption, or slow speed.

[0035] An example in Figure 1 It is shown that the number of memory cells included in the non-volatile memory device 100 is "2", but the inventive concept is not limited thereto. The number of memory cells included in the non-volatile memory device 100 is not limited to any number.

[0036] The first memory bank 150 may include a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154, and a sense amplifier 155. The second memory bank 160 may include a memory cell array 161, a row decoder 162, a column decoder 163, a write driver 164, and a sense amplifier 165. The second memory bank 160 may be implemented substantially the same as the first memory bank 150. Therefore, the first memory bank 150 and its components will be described below, and descriptions associated with the components of the second memory bank 160 will be omitted to avoid redundancy.

[0037] exist Figure 1 In this context, a description will be given with the first memory bank 150 including a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154, and a sense amplifier 155. However, compared to... Figure 1 In contrast, the first memory bank 150 may simply be referred to as memory cell array 151, and the row decoder 152, column decoder 153, write driver 154, and sense amplifier 155 may be included in any other component.

[0038] Memory cell array 151 may include multiple memory cells MC connected to multiple word lines WL and multiple bit lines BL. Each of the multiple memory cells MC may be connected between one of the multiple word lines WL and one of the multiple bit lines BL. For example, memory cell array 151 may be a cross-point memory cell array. Memory cell array 151 may be controlled in units of multiple tiles (not shown). Memory cell array 151 may include DRAM (Dynamic Random Access Memory) cells, SRAM (Static Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, ReRAM (Resistive Random Access Memory) cells, FeRAM (Ferroelectric Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, MRAM (Magnetic Random Access Memory) cells, etc., but the inventive concept is not limited thereto. Memory cell array 151 will be referred to... Figure 3 To provide a more comprehensive description.

[0039] The row decoder 152 can be connected to the memory cell array 151 via multiple word lines WL. The row decoder 152 can receive a row address RA from the address buffer 120. The row decoder 152 can select at least one of the multiple word lines WL based on the row address RA. The row decoder 152 can apply a selection voltage and / or selection current to the selected word line, and can apply a non-selection voltage and / or non-selection current to the unselected word lines.

[0040] Column decoder 153 can be connected to data line DL. Column decoder 153 can be connected to memory cell array 151 via multiple bit lines BL. Column decoder 153 can receive column address CA from address buffer 120. Column decoder 153 can select at least one of the multiple bit lines BL based on column address CA.

[0041] In a write operation, write driver 154 can write data into memory cell MC. In this case, write driver 154 can write data by performing a set or reset operation to change the resistance value of memory cell MC. During a set or reset operation, write driver 154 can apply a write pulse to memory cell MC. Write driver 154 can be connected to multiple data lines DL.

[0042] The sensing amplifier 155 can generate a first read signal with respect to a memory cell in the first memory bank 150, having an amplitude or pulse period determined according to first control information. The first control circuit 130 can load the value of the amplitude or pulse period of the first read signal from at least one memory cell included in the first memory bank 150.

[0043] During a read operation, the sense amplifier 155 can read data from the memory cell MC. In this case, the sense amplifier 155 can read data by determining a range of resistance values ​​for the memory cell MC. The sense amplifier 155 can be connected to multiple data lines DL. The sense amplifier 155 can also be referred to as a "read circuit".

[0044] The input / output circuit 170 can exchange data DQ with one of the first memory bank 150 and the second memory bank 160. Furthermore, the input / output circuit 170 can exchange data DQ with an external device (e.g., a memory controller).

[0045] The input / output circuit 170 can transmit data DQ from one of the first memory bank 150 and the second memory bank 160 to an external device, and can also transmit data DQ from an external device to one of the first memory bank 150 and the second memory bank 160.

[0046] Figure 2 This is the architecture of a non-volatile memory device based on some example embodiments of the inventive concept. Figure 2 Reference Figure 1 The non-volatile memory device 200 may include a first memory bank 211 to a sixteenth memory bank 226 and peripheral circuitry PERI. The non-volatile memory device 200 may be a cross-point non-volatile memory device. The first memory bank 211 to the sixteenth memory bank 226 and the peripheral circuitry PERI may be formed on a semiconductor substrate. Hereinafter, it is assumed that the first memory bank 211 is... Figure 1 The first storage unit is 150.

[0047] like Figure 1 The first memory bank 150, the first memory bank 211 may include a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154 and a sense amplifier 155. However, the first memory bank 211 may also include a first control circuit 130.

[0048] The first memory bank 211 is divided into a first region 230, a second region 240, and a third region 250. The first memory bank 211 may include a memory cell array 151 in the first region 230 to the third region 250. The memory cell array 151 may be placed in the first region 230 and the third region 250. Circuitry for controlling the memory cell array 151 (e.g., a first control circuit 130) may be placed in the second region 240.

[0049] The first memory bank 211 may include a row decoder 152, a column decoder 153, a write driver 154, a sense amplifier 155, and a first control circuit 130 in the second region 240.

[0050] The second memory bank 212 through the sixteenth memory bank 226 may have the same structure and configuration as the first memory bank 211. Each of the second memory bank 212 through the sixteenth memory bank 226 may include components from the first memory bank 150.

[0051] The first storage bank 211 through the sixteenth storage bank 226 can perform write or read operations independently of each other. For example, the first storage bank 211 through the sixteenth storage bank 226 can perform write or read operations based on different operation setting information. For another example, each of the first storage bank 211 through the sixteenth storage bank 226 can be classified as a storage bank that performs write or read operations based on first operation setting information, or a storage bank that performs write or read operations based on second operation setting information. For example, the first storage bank 211 can perform write or read operations based on the first operation setting information, and the second storage bank 212 through the sixteenth storage bank 226 can perform write or read operations based on the second operation setting information.

[0052] Reference Figure 2 The number of memory cells included in the non-volatile memory device 200 is "16", but the inventive concept is not limited to this. That is, the number of memory cells included in the non-volatile memory device 200 is not limited to any number.

[0053] The peripheral circuit PERI can receive address ADDR, command CMD, and control signal CTRL from an external device (e.g., a memory controller). The peripheral circuit PERI can exchange data DQ with the external device (e.g., a memory controller) in response to the received signals. The peripheral circuit PERI may include a command decoder 260, an address buffer 270, and input / output circuitry 280. The command decoder 260, address buffer 270, and input / output circuitry 280 can respectively interact with… Figure 1 The command decoder 110, address buffer 120, and input / output circuitry 170 are essentially the same. The command decoder 260, address buffer 270, and input / output circuitry 280 can be connected to components in the second region 240.

[0054] Regarding the first memory bank 211 to the sixteenth memory bank 226, the manufacturing process, the electrical signals supplied to the first memory bank 211 to the sixteenth memory bank 226, and the degree of degradation according to the use of the first memory bank 211 to the sixteenth memory bank 226 can differ from each other. Thus, the differences between the optimized signals (e.g., read signals and write signals) used to operate the first memory bank 211 to the sixteenth memory bank 226 can be increased. Furthermore, since a memory bank is selected and operated based on a memory bank address, the characteristic differences between components within that memory bank can be smaller than the characteristic differences between components in different memory banks. Characteristic differences can depend on the degree of variation in hold time, temperature, the transmission path of control signals, or the pulses supplied to the write driver. In the inventive concept, because the first memory bank 211 to the sixteenth memory bank 226 included in the non-volatile memory device 200 operate according to their respective operating settings, the performance of the non-volatile memory device 200 can be optimized.

[0055] Figure 3 It is shown that it includes Figure 1 A block diagram illustrating an example of a memory cell array in a non-volatile memory device. An example is shown in... Figure 3 As shown in the figure: the memory cell array 151 includes memory cells MC arranged in a two-dimensional structure, but the memory cells MC can be arranged in a three-dimensional structure.

[0056] Memory cells MC can be arranged in rows and columns. Memory cells MC in a row can be connected to the first word line WL1 to the i-th word line WLi. Memory cells MC in a column can be connected to the first bit line BL1 to the j-th bit line BLj. Here, according to some example embodiments, the number of word lines "i", the number of bit lines "j", and the number of memory cells can be varied.

[0057] Each memory cell MC may be connected to one word line and one bit line. According to some example embodiments, each memory cell MC may include a variable resistance element "R" and a selection element "D". Here, the variable resistance element "R" may be referred to as a "variable resistance material", and the selection element "D" may be referred to as a "switching element".

[0058] In some example embodiments, the variable resistor element "R" may be connected between one of the first word lines WL1 to the i-th word line WLi and the selection element "D", and the selection element "D" may be connected between the variable resistor element "R" and one of the first bit lines BL1 to the j-th bit lines BLj. However, the inventive concept is not limited thereto. For example, the selection element "D" may be connected between one of the first word lines WL1 to the i-th word line WLi and the variable resistor element "R", and the variable resistor element "R" may be connected between the selection element "D" and one of the first bit lines BL1 to the j-th bit lines BLj.

[0059] According to some example embodiments, the variable resistive element "R" can have one of a plurality of resistive states by an electrical pulse applied thereto. In some example embodiments, the variable resistive element "R" may include a phase change material whose crystal (or crystalline) state changes according to the magnitude of the voltage or the amount of current. Phase change materials may include a variety of materials such as GaSb, InSb, InSe, Sb₂Te₃, GeTe, GeSbTe (also known as GST), GaSetE, InSbTe, SnSb₂Te₄, InSbGe, AgInSbTe, (GeSN)SbTe, GeSb(SeTe), and / or Te. 81 Ge 15 Sb2S2.

[0060] Phase change materials can exist in an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. The phase of a phase change material can be changed by Joule heating generated according to the amount of current. Data can be written using the phase change of a phase change material.

[0061] The selection element "D" can be connected between one of the first word lines WL1 to the i-th word line WLi and one of the first bit lines BL1 to the j-th bit line BLj, and can control the supply of voltage or current to the variable resistor element "R" based on signals (e.g., word line signals and bit line signals) applied to the word lines and bit lines connected to the selection element "D". In some example embodiments, the selection element "D" can be a PN junction diode or a PIN junction diode. The anode of the diode can be connected to the variable resistor element "R", and the cathode of the diode can be connected to one of the first word lines WL1 to the i-th word line WLi. In this case, the diode can be turned on when the voltage difference between the anode and cathode of the diode is greater than the threshold voltage of the diode, and thus current can be supplied to the variable resistor element "R". One example is... Figure 3 As shown in the diagram, the selection element "D" is a diode, but the inventive concept is not limited thereto. For example, the selection element "D" can be implemented with a switchable element (e.g., a transistor).

[0062] As in some exemplary embodiments of the inventive concept, the memory cell array 151 can be implemented using a three-dimensional (3D) memory array. The three-dimensional memory array can be formed monolithically as one or more physical layers of the memory cell array having active regions arranged on circuitry associated with the operation of the silicon substrate and the memory cells. The circuitry associated with the operation of the memory cells can be located in and / or on the substrate. The term "monolithically" means that each level of the array is directly deposited on each bottom level of the array. The 3D memory array can be configured such that switching elements and variable resistive elements, including at least one memory cell, are arranged vertically according to a vertical direction.

[0063] Figure 4 It shows the direction over time. Figure 1 The first and second memory banks provide a graph of the write voltage. (Refer to...) Figure 1 describe Figure 4 . Figure 4 Only the write voltage is shown, but Figure 4 The same principle can be applied to the read voltage of the first memory bank 150 and the second memory bank 160.

[0064] The write voltage of the first memory bank 150 may be the voltage provided to the memory cells included in the first memory bank 150 for write operations of the first memory bank 150. The write voltage of the second memory bank 160 may be the voltage provided to the memory cells included in the second memory bank 160 for write operations of the second memory bank 160.

[0065] exist Figure 4In response to a first control signal CTRL1, a first control circuit 130 can perform a write operation on memory cells included in the first memory bank 150 based on a write voltage of the first memory bank 150 having an amplitude of "W1–Vss". In response to a second control signal CTRL2, a second control circuit 140 can perform a write operation on memory cells included in the second memory bank 160 based on a write voltage of the second memory bank 160 having an amplitude of "W2–Vss". That is, the first memory bank 150 and the second memory bank 160 can operate based on write voltages of different amplitudes. (Refer to...) Figure 4 Because the write voltage of the second memory bank 160 is less than that of the first memory bank 150, the power consumption of the second memory bank 160 can be less than that of the first memory bank 150. Thus, the non-volatile memory device 100 can be configured with memory banks that have different power consumption levels.

[0066] Reference Figure 4 The pulse duration of the write voltage of the first memory bank 150 can be T1, and the pulse duration of the write voltage of the second memory bank 160 can be T2. T1 and T2 can be different from each other. Here, T1 and T2 can be different from each other because of the difference between the activation time, deactivation time, application time and non-application time of the write voltage of the first memory bank 150 and the second memory bank 160.

[0067] For example, when T1 and T2 are different from each other, T1 can be greater than T2. ​​The pulse duration of the write voltage of the first memory bank 150 can be greater than the pulse duration of the write voltage of the second memory bank 160, therefore, the first memory bank 150 can operate with higher reliability than the second memory bank 160. Conversely, the pulse duration of the write voltage of the second memory bank 160 can be shorter than the pulse duration of the write voltage of the first memory bank 150, therefore, the second memory bank 160 can operate faster than the first memory bank 150.

[0068] The second memory bank 160 can be activated simultaneously with the execution of a write / read operation on the first memory bank 150. In some example embodiments, in response to the first read / write control signal CTRL1_RW in the first control signal CTRL1, the first write driver 154 of the first memory bank 150 can provide write pulses to the memory cells included in the first memory bank 150 and can provide voltages across the memory cells of the first memory bank 150. The first control circuit 130 can perform a read operation on the memory cells of the first memory bank 150 based on the voltages across the memory cells of the first memory bank 150. When a read operation is performed on the memory cells of the first memory bank 150, in response to the second read / write control signal CTRL2_RW in the second control signal CTRL2, the second write driver 164 can provide write pulses to the memory cells included in the second memory bank 160 and can provide voltages across the memory cells of the second memory bank 160.

[0069] Figure 5 It shows the direction over time. Figure 1 The first and second memory banks provide a graph of bit line voltages. Figure 5 Reference Figure 1 Describe it. Figure 5 Only the bit line voltages of the first memory bank 150 and the second memory bank 160 are shown, but Figure 5 The same principle can be applied to the word line voltage of the first memory bank 150 and the second memory bank 160.

[0070] In response to the first row control signal CTRL1_RA in the first control signal CTRL1 output from the first control circuit 130, Figure 1 The column decoder 153 in the first memory bank 150 can discharge the bit lines connected to the memory cells in the first memory bank 150 in standby mode. Here, discharging the bit lines can mean applying a ground voltage Vss or a discharge voltage to the bit lines. The column decoder 153 can precharge the bit lines connected to the memory cells in the first memory bank 150 at time t10 after receiving a read request from an external device. Here, precharging the bit lines can mean applying a voltage greater than "0" to the bit lines (e.g., ...). Figure 5 The pre-charge voltage Vpre is used instead of the ground voltage Vss or the discharge voltage.

[0071] At time t11 when the precharge operation is completed, the first control circuit 130 may perform a read operation on the memory cell in the first memory bank 150. For example, in the read operation, a read voltage Vread (=2Vpre) greater than the precharge voltage Vpre may be applied to the bit line connected to the memory cell in the first memory bank 150.

[0072] At time t12 when the read operation is completed, a recovery operation can be performed. That is, the voltage of the bit line connected to the memory cell in the first memory bank 150 can be restored to the precharge voltage Vpre. However, in some other embodiments, the recovery operation may be omitted.

[0073] At time t13 when the recovery operation is completed, the ground voltage Vss can be applied to the bit lines connected to the memory cells in the first memory bank 150. That is, the voltage of the bit lines connected to the memory cells in the first memory bank 150 can be restored to the standby state voltage. As a result, in the standby state, since the bit lines connected to the memory cells in the first memory bank 150 are maintained at the standby state voltage, potential current leakage can be significantly reduced, and the power consumption of the first memory bank 150 can be reduced.

[0074] In response to the second row control signal CTRL2_RA in the second control signal CTRL2 output from the second control circuit 140, Figure 1 The row decoder 162 and column decoder 163 in the second memory bank 160 can precharge word lines and bit lines that are not connected to memory cells in the second memory bank 160 when they are not in standby mode. That is, the precharge operation can be performed without being in standby mode.

[0075] At time t14, the second control circuit 140 may perform a read operation on a memory cell in the second memory bank 160. For example, in a read operation, a read voltage Vread (=2Vpre) greater than the precharge voltage Vpre may be applied to the bit line connected to the memory cell in the second memory bank 160.

[0076] At time t15 when the read operation is completed, a precharge voltage Vpre can be applied to the bit line connected to the memory cell in the second memory bank 160. That is, the memory cell in the second memory bank 160 can immediately enter a standby state without a separate recovery operation.

[0077] Thus, even in standby mode, the bit lines and word lines connected to the memory cells in the second memory bank 160 can maintain a precharged state through the precharge voltage. That is, no separate precharge operation is required for the second memory bank 160. After the standby state, write operations can be performed at high speed in response to requests from external devices (e.g., a host) regarding the memory cells in the second memory bank 160.

[0078] Figure 6 These are examples illustrating some embodiments based on the inventive concept. Figure 1 A block diagram of a storage device 1000, also referred to as a "memory system". Storage device 1000 may include a memory controller 1100 and a non-volatile memory device 1200.

[0079] The memory controller 1100 may allow the non-volatile memory device 1200 to perform read or write operations. For example, the memory controller 1100 may provide the non-volatile memory device 1200 with a command CMD, an address ADDR, and a data DQ, causing the non-volatile memory device 1200 to perform a write operation.

[0080] Memory controller 1100 provides a physical connection between an external device (e.g., a host) and non-volatile memory device 1200. Memory controller 1100 can control non-volatile memory device 1200 in response to signals received from the external device. Memory controller 1100 can provide an interface connection with non-volatile memory device 1200 according to the bus format of the external device. In particular, memory controller 1100 can decode commands provided from the external device. Memory controller 1100 can access non-volatile memory device 1200 based on the decoding result.

[0081] The memory controller 1100 may include a buffer memory 1121. The buffer memory 1121 may store a mapping table in which the first memory address of a memory bank operating in a first mode is mapped to the first mode, and the second memory address of a memory bank operating in a second mode is mapped to the second mode.

[0082] The non-volatile memory device 1200 may include a first control circuit 1211, a second control circuit 1212, a first memory bank 1231, and a second memory bank 1232. The non-volatile memory device 1200 can be used with... Figure 1 The non-volatile memory device 100 is substantially the same. That is, the first control circuit 1211 and the second control circuit 1212 may be substantially the same as the first control circuit 130 and the second control circuit 140, and the first memory bank 1231 and the second memory bank 1232 may be substantially the same as the first memory bank 150 and the second memory bank 160.

[0083] Under the control of memory controller 1100, non-volatile memory device 1200 can store data and / or provide the data stored therein to memory controller 1100. Non-volatile memory device 1200 can be provided as a storage medium for memory device 1000. For example, non-volatile memory device 1200 can be implemented using phase-change memory (PCM). Non-volatile memory device 1200 may include multiple memory devices. In this case, memory devices can be connected to memory controller 1100 on a channel-by-channel basis.

[0084] The memory controller 1100 may receive a first request corresponding to a first mode from an external device (e.g., a host). The memory controller 1100 may determine whether the first request corresponding to the first mode is associated with the first memory bank 1231 based on a mapping table stored in the buffer memory 1121. When the first request corresponding to the first mode is associated with the first memory bank 1231, the memory controller 1100 may select the first memory bank 1231.

[0085] In some example embodiments, the memory controller 1100 may access the first memory bank 1231 based on a first request that includes operational characteristics of the first memory bank 1231 from an external device (e.g., a host). In this case, the memory controller 1100 may determine the address of the first memory bank 1231 that is the target of access (e.g., the access target memory address) based on the first request that includes the operational characteristics of the first memory bank 1231. In this way, the memory controller 1100 can access the first memory bank 1231.

[0086] In some example embodiments, the first control circuit 1211 may receive an update request for the first memory bank 1231 from an external device (e.g., a host) via the memory controller 1100, and then may receive a read request from the external device. Here, the update request may refer to a request to update the amplitude value, duration value, and timing of pulses used for operations on the first memory bank 1231. If, after receiving an update request for the first memory bank 1231 from the external device (e.g., the host), a read request is received from the external device via the memory controller 1100, the first control circuit 1211 may perform a read operation on the memory cells of the first memory bank 1231 by using read / write pulses different from those used before receiving the update request. The first control circuit 1211 may load the amplitude value and pulse duration value of a read / write pulse different from those used before receiving the update request from at least one memory cell included in the first memory bank 1231.

[0087] In some example embodiments, the memory controller 1100 may receive a reclassification request for a memory bank from an external device (e.g., a host). Here, a reclassification request may refer to a request to change the operating characteristics of the memory bank (e.g., the amplitude and duration values ​​of read / write pulses). For example, when a first operating characteristic corresponds to a first memory bank 1231 and a second operating characteristic corresponds to a second memory bank 1232, in response to a reclassification request from the external device, the memory controller 1100 may update the first memory bank 1231 to be set to the second operating characteristic, and may update the second memory bank 1232 to be set to the first operating characteristic. Furthermore, to update the first memory bank 1231, the memory controller 1100 may reference a third operating characteristic different from the first and second operating characteristics; in response to a reclassification request from the external device, the memory controller 1100 may update the first memory bank 1231 to be set to the third operating characteristic. In response to a reclassification request from the external device, the memory controller 1100 may map the memory bank address of the first memory bank 1231 to a second mode in a mapping table.

[0088] In some example embodiments, the memory controller 1100 may activate or access the second memory bank 1232 while performing a read or write operation on the first memory bank 1231. The memory controller 1100 may access the second memory bank 1232 simultaneously with accessing the first memory bank 1231. When performing a read operation on the first memory bank 1231, the memory controller 1100 may receive a second request corresponding to a second mode from an external device, which is different from the first request corresponding to the first memory bank 1231. The memory controller 1100 may determine whether the second request corresponding to the second mode is associated with the second memory bank 1232 based on a mapping table stored in a buffer memory. When the second request corresponding to the second mode is associated with the second memory bank 1232, the memory controller 1100 may access the second memory bank 1232 while performing a read operation on the first memory bank 1231.

[0089] In some example embodiments, the memory controller 1100 and / or the non-volatile memory device 1200 may be packaged according to any of a variety of different packaging technologies. Examples of such packaging technologies may include: PoP (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Waffle Package, Wafer Package, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Scale Construction Package (WFP), and Wafer-Scale Process Stacked Package (WSP), etc.

[0090] Figure 7 It is provided to Figure 6 Timing diagram of signals for a non-volatile memory device. Refer to... Figure 1 and Figure 6 right Figure 7 Describe the timing of sending and receiving commands (CMD) and address (ADDR), as well as the timing of outputting and receiving data (DQ). Figure 7 As shown in the image.

[0091] The command CMD may include a selection command BK1 SEL for the first memory bank 1231, a selection command BK2 SEL for the second memory bank 1232, a read command BK1 RD for the first memory bank 1231, and a read command BK2 RD for the second memory bank 1232. The address ADDR may include the row address BK1 RA of the first memory bank 1231, the row address BK2 RA of the second memory bank 1232, the column address BK1 CA of the first memory bank 1231, and the column address BK2 CA of the second memory bank 1232. The data DQ may include read data DATA1 from the first memory bank 1231 and read data DATA2 from the second memory bank 1232.

[0092] At time t20, the memory controller 1100 can send a selection command BK1 SEL for the first memory bank 1231 and the row address BK1 RA of the first memory bank 1231 to the non-volatile memory device 1200, and the non-volatile memory device 1200 can receive the selection command BK1 SEL for the first memory bank 1231 and the row address BK1 RA of the first memory bank 1231. At time t21, the memory controller 1100 can send a selection command BK2 SEL for the second memory bank 1232 and the row address BK2 RA of the second memory bank 1232 to the non-volatile memory device 1200, and the non-volatile memory device 1200 can receive the selection command BK2 SEL for the second memory bank 1232 and the row address BK2 RA of the second memory bank 1232. When the memory controller 1200 sends the selection commands BK1 SEL and BK2 SEL, the first memory bank 1231 and the second memory bank 1232 can be selected in parallel. Parallel selection refers to the independent selection of other memory banks that is not affected by the selection of the memory controller 1200. For example, the first memory bank 1231 and the second memory bank 1232 can be selected simultaneously by the memory controller 1200.

[0093] At time t22, the memory controller 1100 may send a read command BK1 RD for the first memory bank 1231 and the column address BK1 CA of the first memory bank 1231 to the non-volatile memory device 1200, and the non-volatile memory device 1200 may receive BK1 RD and the column address BK1 CA of the first memory bank 1231. At time t23, the memory controller 1100 may send a read command BK2 RD for the second memory bank 1232 and the column address BK2 CA of the second memory bank 1232 to the non-volatile memory device 1200, and the non-volatile memory device 1200 may receive the read command BK2 RD for the second memory bank 1232 and the column address BK2 CA of the second memory bank 1232.

[0094] At time t24, the first storage bank 1231 can output read data DATA1 from at least one memory cell in the first storage bank 1231, and the memory controller 1100 can receive read data DATA1. At time t25, the second storage bank 1232 can output read data DATA2 from at least one memory cell in the second storage bank 1232, and the memory controller 1100 can receive read data DATA2.

[0095] In some example embodiments, the first control signal CTRL1 may include the value of a delay time interval BK1Latency from time t22 when a read command BK1 RD for the first memory bank 1231 is received by the non-volatile memory device 1200 to time t24 when read data DATA1 is output from the first memory bank 1231. The second control signal CTRL2 may include the value of a delay time interval BK2Latency from time t23 when a read command BK2 RD for the second memory bank 1232 is received by the non-volatile memory device 1200 to time t25 when data DATA2 is output from the second memory bank 1232. (As in...) Figure 6 As shown, because there is a difference between "the time interval from time t20 when the first control circuit 1211 receives the selection command BK1 SEL for the first memory bank 1231 to time t24 when the first memory bank 1231 outputs data DATA1" and "the time interval from time t21 when the second control circuit 1212 receives the selection command BK2 SEL for the second memory bank 1232 to time t25 when the second memory bank 1232 outputs read data DATA2", the value of the time delay interval BK1 Latency of the first memory bank 1231 and the value of the time delay interval BK2 Latency of the second memory bank 1232 can be different from each other.

[0096] In some example embodiments, the time at which read data DATA1 is output from the first memory bank 1231 in response to read command BK1 RD may differ from the time at which read data DATA2 is output from the second memory bank 1232 in response to read command BK2 RD. In other embodiments, the signal applied to the first memory bank 1231 may be determined by first control information in register R1 of the first control circuit 1211, causing data to be output from the first memory bank 1231 with a first delay. The signal applied to the second memory bank 1232 may be determined by second control information in register R2 of the second control circuit 1212, causing data to be output from the second memory bank 1232 with a second delay.

[0097] Figure 8 These are examples illustrating some embodiments based on the inventive concept. Figure 2 A block diagram of a non-volatile memory device. The memory controller can be... Figure 6 The memory controller. Non-volatile memory devices may include... Figure 2 The architecture of non-volatile memory devices.

[0098] Memory controller 2100 can be with Figure 6 The memory controller 1100 is basically the same. Although in Figure 8Not shown, but memory controller 2100 may include buffer memory (e.g., Figure 6 (Buffer memory 1121).

[0099] Non-volatile memory device 2200 is available Figure 2 The architecture implementation. The first storage bank 2210 to the sixteenth storage bank 2226 can be connected with... Figure 2 The first memory bank 2210 to the sixteenth memory bank 2226 are basically the same. That is, the first memory bank 2210 to the sixteenth memory bank 2226 are divided into a first region 2230, a second region 2240, and a third region 2250. The command decoder 2260, the address buffer 2270, and the input / output circuit 2280 can be respectively connected to... Figure 2 The command decoder 260, address buffer 270, and input / output circuit 280 are basically the same.

[0100] The memory controller 2100 can divide the first memory bank 2210 to the sixteenth memory bank 2226 into multiple categories. For example, the memory controller 2100 can divide the first memory bank 2210 to the sixteenth memory bank 2226 into a first category and a second category. The first category may include the first memory bank 2210 to the eighth memory bank 2218, and the second category may include the ninth memory bank 2219 to the sixteenth memory bank 2226. In this case, memory banks included in the same category can operate in the same mode, have the same operating characteristics, and can operate according to the same operating settings. The memory controller 2100 can set the core control operation of the memory bank differently for each category. Here, the core control operation may refer to the operation of setting up the circuitry to generate control signals for controlling the memory bank.

[0101] The memory controller 2100 can receive requests from an external device (e.g., a host) and can identify the received requests. In this case, the received request can be identified based on the operating characteristics corresponding to the request. For example, the received request may correspond to operating characteristics for reducing or minimizing power consumption, operating characteristics for faster operation, or operating characteristics for higher reliability. The memory controller 2100 can select the relevant memory bank in response to the identified request. In this way, the non-volatile memory device 2200 can achieve optimal performance.

[0102] The memory controller 2100 can change the category of the first memory bank 2210 through the sixteenth memory bank 2226. To change the category, an external device (e.g., a host) can send a reclassification request to the memory controller 2100, and the memory controller 2100 can change the category of the first memory bank 2210 through the sixteenth memory bank 2226 in response to the reclassification request. For example, in response to the reclassification request, the memory controller 2100 can again divide the first memory bank 2210 through the sixteenth memory bank 2226 into a third category and a fourth category. Here, the third category may include the thirteenth memory bank 2223 through the sixteenth memory bank 2226, and the fourth category may include the first memory bank 2211 through the twelfth memory bank 2222. The operating characteristics of the memory bank included in the third category may correspond to the operating characteristics of the memory bank included in the first category, and the operating characteristics of the memory bank included in the fourth category may correspond to the operating characteristics of the memory bank included in the second category.

[0103] Similar to Figure 3 An example in Figure 9 While it is shown that the number of memory cells included in the non-volatile memory device 2200 is "16", the inventive concept is not limited to this. That is, the number of memory cells included in the non-volatile memory device 2200 is not limited to any number.

[0104] Figure 9 It is shown Figure 6 Block diagram of the memory controller. Figure 9 Reference Figure 6 Provide a description. (Refer to...) Figure 1 and Figure 9 The memory controller 1100 may include a processor 1110, an SRAM 1120, a ROM 1130, a host interface 1140, and a memory interface 1150.

[0105] The processor 1110 can control the overall operation of the memory controller 1100 and can perform various logical operations. For example, the processor 1110 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), etc., and the number of processors may be two or more (e.g., a multi-core processor).

[0106] SRAM 1120 can be used as a cache memory, working memory, and / or buffer memory of memory controller 1100 (e.g., Figure 6The SRAM 1120 can also be used as a cache memory for the processor 1110. The SRAM 1120 can store code and instructions that the processor 1110 will execute. The SRAM 1120 can store data processed by the processor 1110.

[0107] ROM 1130 may store various information for the operation of memory controller 1100 in the form of firmware. In some example embodiments, various information for controlling non-volatile memory device 1200 (e.g., flash translation layer and mapping table) may be stored in SRAM 1120, ROM 1130 or a separate buffer memory and may be managed or driven by processor 1110.

[0108] Host interface 1140 can communicate with an external host under the control of processor 1110. Host interface 1140 can send requests (e.g., read / write requests and reclassification requests) from the host to processor 1110 via bus 1160. In some example embodiments, host interface 1140 may include at least one of a variety of interfaces, such as Double Data Rate (DDR) interface, Low Power DDR (LPDDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, High Speed ​​PCI (PCI-e) interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, External SATA (eSATA) interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE) interface, Mobile Industrial Processor Interface (MIPI), High Speed ​​Non-Volatile Memory (NVM-e) interface, and Universal Flash Memory (UFS) interface.

[0109] The memory interface 1150, under the control of the processor 1110, can act as a communication intermediary between the non-volatile memory device 1200 and the memory controller 1100. That is, the memory controller 1100 can communicate with the non-volatile memory device 1200 via the memory interface 1150. In some example embodiments, the memory controller 1100 can provide various signals (e.g., CMD, ADDR, and DQ) to the non-volatile memory device 1200 via the memory interface 1150.

[0110] Bus 1160 provides a communication path between components of memory controller 1100. Components of memory controller 1100 can exchange data with each other based on the bus format of bus 1160. For example, the bus format may include one or more of various protocols, such as USB, SCSI, PCIe, ATA, PATA, SATA, IDE, and UFS.

[0111] Figure 9 The memory controller 1100 shown is an example, and the inventive concept is not limited thereto. The memory controller 1100 may also include various components such as an error correction code (ECC) engine, a random number generator, and buffer management circuitry.

[0112] Figure 9 The memory controller 1100 can be used for Figure 6 The storage device is described, but Figure 8 The memory controller 2100 can be configured to work with Figure 9 It is the same as the memory controller 1100.

[0113] Figure 10 This is a flowchart illustrating a method of operating a memory controller according to some example embodiments of the inventive concept. Figure 10 Reference Figure 8 Describe it.

[0114] In operation S110, the memory controller 2100 may divide a plurality of memory banks included in the non-volatile memory device 2200 into memory banks operating in a first mode and memory banks operating in a second mode different from the first mode. In some other example embodiments, the memory controller 2100 may again divide the plurality of memory banks into memory banks operating in the first mode, memory banks operating in the second mode, and memory banks operating in a third mode different from the first and second modes. Although not in Figure 9 As shown in the figure, as referenced Figure 6 As described, the memory controller 2100 may include a buffer memory that stores a mapping table in which the address of a first memory bank operating in a first mode is mapped to the first mode, and the address of a second memory bank operating in a second mode is mapped to the second mode.

[0115] In operation S120, the memory controller 2100 may receive a first request corresponding to a first mode from the host, and in response to the first request, may send the address of a first memory bank corresponding to a first memory bank operating in the first mode to the non-volatile memory device 2200. The memory controller 2100 may determine whether the first request corresponds to a first mode or a second mode.

[0116] In operation S130, the memory controller 2100 may also receive a second request corresponding to the second mode from the host, and may, in response to the second request, send the address of the second memory bank corresponding to the second memory bank operating in the second mode to the non-volatile memory device 2200. The memory controller 2100 may determine whether the second request corresponds to the first mode or the second mode.

[0117] In some example embodiments, after selecting a first bank of memory in the non-volatile memory device 2200, the memory controller 2100 may send a third request to the non-volatile memory device 2200 for reading the first bank. Here, a second request may be sent to the non-volatile memory device 2200 between the first request and the third request.

[0118] In some example embodiments, the memory controller 2100 may receive a write request corresponding to a first mode from the host, and may select a first memory bank among the memory banks operating in the first mode in response to the write request. The memory controller 2100 may determine the memory bank address as the target of access based on the write request corresponding to the first mode. The memory controller 2100 may access the first memory bank corresponding to the memory bank address as the target of access. However, the inventive concept is not limited thereto. For example, as in a write request, the memory controller 2100 may receive the memory bank address as the target of access from the host. The memory controller 2100 may perform a read / write operation on a memory cell included in one of the first memory banks.

[0119] The memory controller 2100 may receive a second read / write request from the host, the second read / write request including commands different from those included in the first read / write request. When a read / write operation is performed on a memory cell included in one of the first memory banks, the memory controller 2100 may access one of the second memory banks based on the second read / write request.

[0120] Figure 11 This is a flowchart illustrating a method for changing the type of memory included in a non-volatile memory device, according to some example embodiments of the inventive concept. Figure 11 Reference Figure 8 Describe it.

[0121] In operation S210, the memory controller 2100 may receive a reclassification request from the host.

[0122] In operation S220, the memory controller 2100 may map one of the first memory bank addresses to a second mode in response to a reclassification request. However, the inventive concept is not limited thereto. For example, the memory controller 2100 may map one of the first memory bank addresses to a third mode different from the first and second modes in response to a reclassification request.

[0123] The non-volatile memory device according to some example embodiments of the inventive concept can support different operating settings for different requests from the host to each memory bank (or to each individual memory bank), thereby optimizing performance.

[0124] According to some example embodiments of the inventive concept, a storage device including a non-volatile memory device can change the type of storage medium included in the non-volatile memory device and can update the values ​​of the operating settings for the storage medium.

[0125] Although described with reference to specific examples and accompanying drawings, modifications, additions, and substitutions to the exemplary embodiments may be made differently by those skilled in the art based on the description. For example, the described techniques may be performed in a different order than the described methods, and / or components such as the described systems, architectures, devices, circuits, etc., may be connected or combined in a manner different from the methods described above, or the results may be appropriately achieved through other components or equivalents.

[0126] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be clear to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept set forth in the claims.

Claims

1. A non-volatile memory device, comprising: The command decoder is configured to receive and decode the first and second commands. The first control circuit is configured to generate first control information under the control of a command decoder that decodes the first command; The second control circuit is configured to generate second control information under the control of a command decoder that decodes the second command; The first storage bank includes a first memory cell that operates based on first control information; The second storage bank includes a second memory cell that operates based on second control information, wherein the first time required to output data from the first storage bank in response to a first command is different from the second time required to output data from the second storage bank in response to a second command; A first read circuit is configured to generate a first read signal for a first memory cell, wherein the first read signal has a first amplitude determined according to first control information; and The second read circuit is configured to generate a second read signal for a second memory cell, wherein the second read signal has a second amplitude determined according to second control information, the second amplitude being different from the first amplitude.

2. The non-volatile memory device according to claim 1, wherein, While the first memory cell of the first storage bank operates based on the first control information, the second memory cell of the second storage bank operates based on the second control information.

3. The non-volatile memory device according to claim 1, wherein, The first memory unit and the second memory unit are phase-change random access memory units.

4. A non-volatile memory device, comprising: The command decoder is configured to receive and decode the first and second commands. The first control circuit is configured to generate first control information under the control of a command decoder that decodes the first command; The second control circuit is configured to generate second control information under the control of a command decoder that decodes the second command; The first storage bank includes a first memory cell that operates based on first control information; The second storage bank includes a second memory cell that operates based on second control information, wherein the first time required to output data from the first storage bank in response to a first command is different from the second time required to output data from the second storage bank in response to a second command; A first read circuit is configured to generate a first read signal for a first memory cell, wherein the first read signal has a first pulse period determined according to first control information; and The second read circuit is configured to generate a second read signal for a second memory cell, wherein the second read signal has a second pulse period determined according to second control information, and the second pulse period is different from the first pulse period.

5. The non-volatile memory device according to claim 4, wherein, The first control circuit is configured to load the value of the first pulse period from at least one third memory cell included in the first memory bank.

6. A non-volatile memory device, comprising: The command decoder is configured to receive and decode the first and second commands. The first control circuit is configured to generate first control information under the control of a command decoder that decodes the first command; The second control circuit is configured to generate second control information under the control of a command decoder that decodes the second command; The first storage bank includes a first memory cell that operates based on first control information; The second storage bank includes a second memory cell that operates based on second control information, wherein the first time required to output data from the first storage bank in response to a first command is different from the second time required to output data from the second storage bank in response to a second command, and The command decoder is configured to receive update requests for the first storage bank from the host. The first control circuit is configured to store second control information instead of the first control information under the control of the command decoder that receives the update request, and The first memory cell of the first memory bank is configured to operate based on the second control information rather than the first control information in response to a third command received from the host by the command decoder for the first memory cell of the first memory bank.

7. A non-volatile memory device, comprising: The command decoder is configured to receive and decode the first and second commands. The first control circuit is configured to generate first control information under the control of a command decoder that decodes the first command; The second control circuit is configured to generate second control information under the control of a command decoder that decodes the second command; The first storage bank includes a first memory cell that operates based on first control information; The second storage bank includes a second memory cell that operates based on second control information, wherein the first time required to output data from the first storage bank in response to a first command is different from the second time required to output data from the second storage bank in response to a second command; The first column decoder is configured to operate in response to first control information, wherein the first column decoder is configured as follows: In standby mode, the bit lines connected to the first memory cell are discharged, and After receiving a read request from the host, the bit lines connected to the first memory cell are precharged; and The second column decoder is configured to precharge bit lines that are not connected to the second memory cell in standby mode in response to the second control information.

8. A method of operating a memory controller connected to a memory device, the method comprising: The memory device is divided into multiple memory banks that operate in a first mode and memory banks that operate in a second mode that is different from the first mode; Receive a first request from the host corresponding to the first mode, and in response to the first request send the address of the first memory bank corresponding to the first memory bank in the memory bank operating in the first mode to the memory device. and It also receives a second request from the host corresponding to the second mode, and in response to the second request sends the address of the second memory bank corresponding to the second memory bank operating in the second mode to the memory device, and The partitioning steps include: mapping the address of the first memory bank corresponding to the first memory bank to the first mode, mapping the address of the second memory bank corresponding to the second memory bank to the second mode, and storing the mapping result in the buffer memory of the memory controller.

9. The method according to claim 8, further comprising: Receive a third request from the host; and The plurality of storage units are divided into storage units operating in a first mode, storage units operating in a second mode, and storage units operating in a third mode.

10. The method of claim 8, further comprising: Receive a reclassification request from the host; and In response to the reclassification request, the address of the first storage bank corresponding to the first storage bank is mapped to the second mode.

11. The method according to claim 8, wherein: The step of receiving the first request from the host includes determining whether the first request corresponds to a first mode or a second mode, and The step of receiving a second request from the host includes determining whether the second request corresponds to the first mode or the second mode.

12. The method according to claim 8, further comprising: After selecting the first storage bank in response to the first request, a third request for reading the first storage bank is sent to the memory device, wherein, The second request is sent to the memory device between the first request and the third request.

13. A storage device, comprising: A non-volatile memory device includes a first memory bank, a second memory bank, a first control circuit configured to control the first memory bank in response to the first control information, and a second control circuit configured to control the second memory bank in response to the second control information, wherein the first memory bank includes a first memory cell operating based on the first control information, and the second memory bank includes a second memory cell operating based on the second control information; and The memory controller is configured as follows: In response to a first request from the host to read the first memory bank, a first read command is sent to the non-volatile memory device, and In response to a second request from the host to read the second memory, a second read command is sent to the non-volatile memory device, wherein... The first time delay from the time the memory controller sends the first read command to the time the memory controller receives the data of the first memory bank corresponding to the first read command is different from the second time delay from the time the memory controller sends the second read command to the time the memory controller receives the data of the second memory bank corresponding to the second read command, and The non-volatile memory device also includes: A first read circuit is configured to generate a first read signal for a first memory cell, wherein the first read signal has a first amplitude determined according to first control information; and The second read circuit is configured to generate a second read signal for a second memory cell, wherein the second read signal has a second amplitude determined according to second control information, the second amplitude being different from the first amplitude.

14. The storage device according to claim 13, wherein, The first control circuit determines the signal to be applied to the first memory bank through the first control information, causing the first memory bank to output the data of the first memory bank with a first time delay, and The second control circuit determines the signal to be applied to the second memory bank through the second control information, so that the second memory bank outputs the data of the second memory bank with a second delay.

15. The storage device according to claim 14, wherein, The memory controller is configured as follows: Before sending the first read command to the non-volatile memory device, a first select command for selecting the first memory bank is also sent to the non-volatile memory device. and Before sending the second read command to the non-volatile memory device, a second select command for selecting the second memory bank is also sent to the non-volatile memory device, wherein... The time interval between the first selection command and the first read command is different from the time interval between the second selection command and the second read command.

16. The storage device according to claim 15, wherein, The memory controller is configured as follows: The memory controller sends a first selection command and a second selection command to the non-volatile memory device, and selects the first memory bank and the second memory bank in parallel.

17. The storage device according to claim 14, wherein, After the memory controller receives an update request for the first memory bank from the host, it receives the first request again. The first control circuit determines the signal to be applied to the first memory bank through the second control information, so that the first memory bank outputs the data of the first memory bank with a second delay.

18. The storage device according to claim 13, wherein, The third delay, from the time the host receives the first request to the time the data in the first storage unit is output to the host, is different from the fourth delay, from the time the host receives the second request to the time the data in the second storage unit is output to the host.

Images