Method for forming a semiconductor device

Abstract

A method of forming a semiconductor device includes forming a dummy gate stack over a semiconductor substrate, the dummy gate stack having a dummy gate electrode and a dummy gate dielectric layer; forming a spacer element over sidewalls of the dummy gate stack; partially removing the dummy gate electrode to form a recess; partially removing the spacer element to enlarge the recess; removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer; doping the spacer element after removing the remaining portion of the dummy gate electrode; removing the dummy gate dielectric layer; and forming a metal gate stack in the recess.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method including gate replacement. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in successive generations of ICs. Each generation has smaller and more complex circuits than the previous one.

[0003] As integrated circuits evolve, functional density (i.e., the number of interconnected components per chip area) generally increases while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, these advances have also increased the complexity of processing and manufacturing integrated circuits. As feature sizes continue to decrease, manufacturing processes continue to become more difficult. Consequently, forming reliable semiconductor devices at increasingly smaller sizes is challenging. Summary of the Invention

[0005] An embodiment of the present invention includes a method for forming a semiconductor device, comprising forming a dummy gate stack on a semiconductor substrate, the dummy gate stack having a dummy gate electrode and a dummy gate dielectric layer; forming a spacer element on a sidewall of the dummy gate stack; partially removing the dummy gate electrode to form a groove; partially removing the spacer element to expand the groove; removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer; doping the spacer element after removing the remaining portion of the dummy gate electrode; removing the dummy gate dielectric layer; and forming a metal gate stack in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the components may be enlarged or reduced to clearly illustrate the technical features of the embodiments of the present invention.

[0007] 1A-1K are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0008] Figure 2 is a cross-sectional view illustrating a semiconductor device structure according to some embodiments.

[0009] Figure 3 is a cross-sectional view illustrating a semiconductor device structure according to some embodiments.

[0010] Figure 4 FIG. 1 is a graph illustrating a distribution of dopant concentration in a spacer element of a semiconductor device structure according to some embodiments.

[0011] Figure 5 FIG. 1 is a graph illustrating a distribution of dopant concentration in a spacer element of a semiconductor device structure according to some embodiments.

[0012] Description of reference numerals:

[0013] 100~Semiconductor substrate

[0014] 102~Fin-like structure

[0015] 104~Gate Stack

[0016] 106~Dummy gate dielectric layer

[0017] 108~Dummy gate electrode

[0018] 110~Spacer element

[0019] 112~Source / drain structure

[0020] 114~Etching stop layer

[0021] 116~Dielectric layer

[0022] 118, 118'~ groove

[0023] 120~Oxide layer

[0024] 122~Defect

[0025] 123~Doping Operation

[0026] 124~Dopant

[0027] 126~Gate dielectric layer

[0028] 128~Work function layer

[0029] 130~Conductive filling layer

[0030] 132~Metal Gate Stack

[0031] H1~Depth

[0032] H2~Height

[0033] T1, T2~thickness

[0034] P1~lower part

[0035] P2~upper part

[0036] R~part

[0037] W1, W2, W3~width

[0038] L~imaginary plane

[0039] θ~angle DETAILED DESCRIPTION

[0040] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.

[0041] In addition, spatially relative terms may be used, such as "below," "beneath," "lower," "above," "upper," and similar terms. These spatially relative terms are used to facilitate describing the relationship between one element or feature and another element or feature in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used will also be interpreted based on the rotated orientation.

[0042] A person of ordinary skill in the art will understand that the word "substantially" is used here, for example in "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective "substantially" can be removed. When applicable, the word "substantially" can also include embodiments of "completely", "entirely", "all", etc. When applicable, the word "substantially" can also relate to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. In addition, words such as "substantially parallel" or "substantially perpendicular" are to be interpreted as not excluding minor deviations from a specific arrangement, and can include, for example, deviations of up to 10°. The word "substantially" does not exclude "entirely", for example, a composition "substantially free" of Y can be completely free of Y.

[0043] The word "about" in conjunction with a specific distance or size should be interpreted as not excluding slight deviations from the specific distance or size and may include deviations of up to 10%, for example. The word "about" with respect to a value x may mean x ± 5 or 10%.

[0044] Several embodiments of the present invention have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Different embodiments may replace or eliminate some of the stages described. Additional components may be incorporated into the semiconductor device structure. Different embodiments may replace or eliminate some of the components described below. Although some embodiments discuss operations in a particular order, these operations may be performed in another logical order.

[0045] 1A-1K are cross-sectional views showing various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1A As shown, a semiconductor substrate 100 is received or provided. In some embodiments, semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, semiconductor substrate 100 includes silicon or other elemental semiconductor materials such as germanium. Semiconductor substrate 100 can be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer can be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0046] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a structure with the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition is defined as follows, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of these is greater than or equal to zero, and their sum equals 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates may also be used, including Group II and VI compound semiconductors.

[0047] In some embodiments, semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. SOI substrates can be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another suitable method, or a combination thereof. In some other embodiments, semiconductor substrate 100 comprises a multilayer structure. For example, semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0048] In some embodiments, one or more fin structures are formed. Figure 1A , one of the fin structures (fin structure 102) is shown. In some embodiments, a plurality of recesses (or trenches) (not shown) are formed in semiconductor substrate 100. As a result, a plurality of fin structures, including fin structure 102, are formed between the recesses. In some embodiments, one or more photolithography and etching processes are used to form the recesses.

[0049] In some embodiments, an isolation feature (not shown) is formed in the recess to surround the lower portion of the fin structure 102. The isolation feature is used to define and electrically isolate device elements formed in and / or on the semiconductor substrate 100. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0050] In some embodiments, each isolation component has a multi-layer structure. In some embodiments, the isolation component is made of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, one or more other suitable materials, or a combination thereof. In some embodiments, a shallow trench isolation liner (not shown) is formed to reduce crystallization defects at the interface between the semiconductor substrate 100 and the isolation component. Similarly, a shallow trench isolation liner can also be used to reduce crystallization defects at the interface between the fin structure and the isolation component. In some other embodiments, a shallow trench isolation liner is not formed. In these cases, the isolation component may be in direct contact with the fin structure.

[0051] In some embodiments, a dielectric material layer is disposed over semiconductor substrate 100. The dielectric material layer covers the fin structures, including fin structure 102, and fills the recesses between the fin structures. In some embodiments, the dielectric material layer is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin coating process, one or more other suitable processes, or a combination thereof.

[0052] In some embodiments, a planarization process is then used to thin the dielectric material layer until the fin structure 102 (or the hard mask element on the fin structure 102) is exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, a dry grinding process, one or more other suitable processes, or a combination thereof. The dielectric material layer is then etched back to below the top of the fin structure 102. As a result, an isolation feature is formed. The fin structure includes the fin structure 102 protruding from the top surface of the isolation feature.

[0053] According to some embodiments, Figure 1A As shown, a gate stack 104 is formed on a semiconductor substrate 100. Gate stack 104 covers a portion of fin structure 102. In some embodiments, each gate stack 104 extends across multiple fin structures including fin structure 102. In some embodiments, gate stack 104 surrounds the side surfaces and top surface of fin structure 102 and further extends above semiconductor substrate 100. In some embodiments, the portion of fin structure 102 below gate stack 104 serves as the channel region of a transistor to be formed.

[0054] In some embodiments, the gate stack 104 is a dummy gate stack and will be replaced by a new gate stack such as a metal gate stack. Figure 1A As shown, each gate stack 104 includes a dummy gate dielectric layer 106 and a dummy gate electrode 108 .

[0055] In some embodiments, a gate dielectric material layer is deposited on the semiconductor substrate 100 to form the dummy gate dielectric layer 106, covering the fin structures 102 and the isolation features between the fin structures. In some embodiments, the gate dielectric material layer is made of or includes silicon oxide. In some embodiments, the gate dielectric material layer is deposited using a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, one or more other suitable processes, or a combination thereof.

[0056] According to some embodiments, Figure 1AAs shown, a gate electrode layer for forming a dummy gate electrode 108 is then formed on the gate dielectric material layer to cover a portion of the fin structure 102. In some embodiments, the gate electrode layer is made of a semiconductor material such as polysilicon. In some embodiments, the gate electrode layer is deposited on the gate dielectric material layer using a chemical vapor deposition process or one or more other suitable processes. In some embodiments, the gate electrode layer is made of polysilicon.

[0057] Then, according to some embodiments, a patterned hard mask layer (not shown) is formed on the gate electrode layer. The patterned hard mask layer is used to pattern the gate electrode layer into a dummy gate electrode 108. In some embodiments, as shown in FIG. Figure 1A As shown, the gate dielectric material layer is also patterned to form a dummy gate dielectric layer 106 .

[0058] In some embodiments, the patterned hard mask layer includes a first hard mask layer and a second hard mask layer. The first hard mask layer is located between the gate electrode layer and the second hard mask layer. In some embodiments, the first hard mask layer is made of silicon nitride. In some embodiments, the second hard mask layer is made of silicon oxide. In some embodiments, the second hard mask layer is thicker than the first hard mask layer. In some embodiments, the patterned hard mask layer includes two or more material layers. In some embodiments, these material layers are made of different materials. In some embodiments, some material layers are made of different materials. In some other embodiments, the patterned hard mask layer includes only a single material layer.

[0059] According to some embodiments, Figure 1A As shown, spacer elements 110 are then formed on the sidewalls of the gate stack 104. The spacer elements 110 can be used to protect the gate stack 104 and / or assist in the subsequent process of forming the source / drain structure. In some embodiments, the spacer elements 110 are made of one or more spacer materials. The spacer material may include silicon nitride, silicon oxynitride, silicon oxide, one or more other suitable materials, or a combination thereof. Each spacer element 110 may include a single dielectric layer. Alternatively, each spacer element 110 may include multiple dielectric layers. The multiple dielectric layers may be made of different materials.

[0060] In some embodiments, a dielectric material layer is deposited over the semiconductor substrate 100 and the gate stack 104. The dielectric material layer can be deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, a spin coating process, one or more other suitable processes, or a combination thereof. Subsequently, an etching process, such as an anisotropic etching process, is used to partially remove the dielectric material layer. As a result, the remaining portions of the dielectric material layer on the sidewalls of the gate stack 104 form spacer elements 110.

[0061] According to some embodiments, Figure 1A As shown, source / drain structures 112 are formed on the portion of the fin structure 102 near the gate stack 104. In some embodiments, the source / drain structures 112 also serve as a stress source for applying strain or stress to the channel region between the source / drain structures 112, thereby improving carrier mobility.

[0062] In some embodiments, the fin structure 102 is partially removed to form a recess adjacent to the spacer element 110. In some embodiments, the recess extends laterally such that a portion of the recess is directly below the gate stack 104. Figure 1A As shown, an epitaxial growth process is then performed to form the source / drain structure 112. The epitaxial growth process may include a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy (MBE) process, one or more other suitable processes, or a combination thereof.

[0063] In some embodiments, the source / drain structures 112 are doped with one or more suitable dopants. For example, the source / drain structures 112 are SiGe source / drain components doped with boron (B), indium (In), or other suitable dopants. Alternatively, in some other embodiments, the source / drain structures 112 are Si source / drain components doped with phosphorus (P), arsenic (As), antimony (Sb), or other suitable dopants.

[0064] In some embodiments, the source / drain structure 112 is doped in situ during its epitaxial growth. In other embodiments, the source / drain structure 112 is not doped during its growth. Instead, after the source / drain structure 112 is formed, the source / drain structure 112 is doped in a subsequent process. In some embodiments, doping can be achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, one or more other suitable processes, or a combination thereof. In some embodiments, the source / drain structure 112 is further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

[0065] According to some embodiments, Figure 1B As shown, an etch stop layer 114 is deposited as shown. Figure 1A 1. The structure shown. An etch stop layer 114 extends over the sidewalls and top of the gate stack 104. The etch stop layer 114 may be used to assist in the subsequent formation of conductive contacts to the source / drain structure 112. The etch stop layer 114 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or combinations thereof. The etch stop layer 114 may be deposited using a chemical vapor deposition process, an atomic layer deposition process, a flowable chemical vapor deposition (FCVD) process, a spin coating process, one or more other suitable processes, or combinations thereof.

[0066] According to some embodiments, Figure 1B As shown, a dielectric layer 116 is then deposited over the etch stop layer 114 . The dielectric layer 116 covers the source / drain structures 112 , the spacer elements 110 , the fin structure 102 , and the gate stack 104 .

[0067] The dielectric layer 116 may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k dielectric material, a porous dielectric material, one or more other suitable materials, or a combination thereof. In some embodiments, the dielectric layer 116 is deposited using a chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a spin-on coating process, one or more other suitable processes, or a combination thereof.

[0068] According to some embodiments, Figure 1C As shown, a planarization process is used to partially remove the dielectric layer 116 and the etch stop layer 114. The planarization process can be performed until the dummy gate electrode 108 is exposed. Alternatively, the planarization process can be performed until the hard mask element on the dummy gate electrode 108 is exposed. In some embodiments, the planarization process includes a chemical mechanical polishing process, a grinding process, an etching process, a dry polishing process, one or more other suitable processes, or a combination thereof.

[0069] According to some embodiments, Figure 1D As shown, the dummy gate electrode 108 is partially removed in the first etching operation to form recesses 118. Each recess 118 is surrounded by the spacer element 110 and the dummy gate electrode 108 remaining between the spacer elements 110. Each recess 118 has a depth H1. The depth H1 may be in the range of about 10 nm to about 100 nm. The depth H1 depends on the height of the dummy gate. Figure 1D As shown, before partially removing the dummy gate electrode 108, each gate stack 104 has a height H2. The height H2 may be in the range of about 20 nm to about 200 nm. The ratio of the depth H1 to the height H2 (H1 / H2) may be in the range of about 0.1 to about 0.95. In some other embodiments, the ratio of the depth H1 to the height H2 (H1 / H2) may be in the range of about 1 / 3 to about 2 / 3.

[0070] In some embodiments, the first etching operation involves the use of plasma. In some embodiments, the reactive gas used to generate the plasma for the first etching operation includes HBr, Cl2, other similar gases, one or more other suitable gases, or a combination thereof.

[0071] According to some embodiments, Figure 1E As shown, the spacer element 110 is partially removed to enlarge the groove 118 to form a groove 118' (larger). The upper portion of the groove 118' becomes larger than Figure 1D The upper portion of the groove 118 shown in FIG.

[0072] In some embodiments, the second etching operation laterally etches the spacer elements 110. In some embodiments, the first etching operation etches the spacer elements 110 at a lower rate than the second etching operation etches the spacer elements 110. In some embodiments, the second etching operation is performed in situ in the same process chamber as the first etching operation without breaking vacuum.

[0073] In some embodiments, as Figure 1E As shown, a portion of the etch stop layer 114 is also removed when the spacer elements 110 are partially removed. The second etch operation partially etches the etch stop layer 114. The recess 118' is enlarged and extends into the etch stop layer 114.

[0074] During the second etching operation or when removing from the process chamber Figure 1E After the structure is exposed to air, an oxide layer 120 (e.g., a native oxide layer) may be grown on the surface portion of the dummy gate electrode 108. Each oxide layer 120 may have a thickness ranging from about 0.1 nm to about 5 nm. In some other embodiments, the oxide layer 120 may have a thickness ranging from about 1 nm to about 3 nm.

[0075] In some embodiments, as Figure 1E As shown, the conditions of the second etching operation are fine-tuned to laterally etch the upper portion of spacer element 110. In some embodiments, the second etching operation involves the use of a plasma. In some embodiments, the reactive gas used to generate the plasma for the second etching operation includes CHF3, HBr, O2, Ar, He, N2, other similar gases, one or more other suitable gases, or a combination thereof. In some embodiments, the volume concentration of CHF3 ranges from approximately 5% to approximately 90%. In some embodiments, the volume concentration of HBr ranges from approximately 5% to approximately 50%. In some embodiments, the volume concentration of O2 ranges from approximately 5% to approximately 50%. In some embodiments, the plasma is generated using a continuous mode. The operating power for generating the plasma may range from approximately 200 W to approximately 2000 W. In some other embodiments, the plasma is generated using a pulsed mode, which includes an "on" state and an "off" state. The operating power for generating the plasma may range from approximately 200 W to approximately 800 W. For example, the operating power is approximately 500 W.

[0076] Due to the lateral etching of the spacer elements 110, each groove 118' has a larger opening. In some embodiments, each groove 118' has a sloped sidewall. In some other embodiments, each groove 118' has a curved sidewall. In some embodiments, each groove 118' has a width that gradually increases from the bottom of the groove 118' to the top of the groove 118'.

[0077] In some embodiments, the second etching operation results in defects being formed in the spacer elements 110. Figure 1E As shown, each spacer element 110 has a lower portion P1 and an upper portion P2. In some embodiments, defects 122 are formed in upper portion P2 due to the second etching operation. The remaining portion of dummy gate electrode 108 protects lower portion P1 of spacer element 110 from damage during the second etching operation. Lower portion P1 is substantially free of defects 122 caused by the second etching operation.

[0078] In some embodiments, defects 122 are primarily formed near the surface portion of upper portion P2. In some embodiments, the density of defects 122 decreases gradually from the inner surface of upper portion P2 toward the outer surface of upper portion P2 adjacent to etch stop layer 114. Figure 1E As shown, the portion of the upper portion P2 adjacent to the etch stop layer 114 is substantially free of defects 122 caused by the second etching operation.

[0079] Then, according to some embodiments, as Figure 1F As shown, the oxide layer 120 is removed. A cleaning process may be used to remove the oxide layer 120. For example, dilute hydrofluoric acid (DHF) may be used to remove the oxide layer 120.

[0080] According to some embodiments, Figure 1G As shown, the remaining portion of the dummy gate electrode 108 is removed to expose the dummy gate dielectric layer 106. In some embodiments, a third etching operation is used to remove the remaining portion of the dummy gate electrode 108. In some embodiments, the second etching operation has a higher etching rate for the spacer elements 110 than the third etching operation has for the spacer elements 110. In some embodiments, the spacer elements 110 are substantially not removed during the third etching operation.

[0081] In some embodiments, the third etching operation involves the use of a plasma. In some embodiments, the third etching operation uses a reactive gas comprising HBr, Cl2, other similar gases, one or more other suitable gases, or a combination thereof. In some other embodiments, one or more other etching operations are performed before, during, between, and / or after the first, second, and third etching operations.

[0082] According to some embodiments, Figure 1H As shown, the spacer element 110 is doped with one or more dopants using a doping operation 123. The dopants are used to lower the dielectric constant of the spacer element to reduce RC delay. After the doping operation 123, both the lower portion P1 and the upper portion P2 of the spacer element 110 are doped with dopants 124.

[0083] According to an embodiment of the present invention, the spacer element 110 is doped with a dopant 124 after forming the source / drain structure 112. Prior to the doping operation 123, the spacer element 110 can have a strong resistance to withstand the process of forming the source / drain structure 112. For example, the spacer element 110 can protect the gate stack 104 from damage during the etching process that forms the recess where the source / drain structure 112 will be formed. After forming the source / drain structure 112, a doping operation is performed to reduce the dielectric constant of the spacer element 110. Consequently, RC delay is reduced, and the reliability and performance of the semiconductor device structure are improved.

[0084] In some embodiments, the doping operation 123 is an ion implantation process. In some embodiments, the spacer element 110 is doped with a halide-containing dopant. In some embodiments, the spacer element 110 is doped with fluorine. In some embodiments, the implanted composition includes free radicals generated from F, SiF3, XeF2, SF6, SiF4, Si2F6, SiF2, one or more other halide-containing sources, or a combination thereof. A range of about 10 13 ions / cm 2 to about 10 15 ions / cm 2 The ion implantation process can be performed using an implantation dose in a range of about 0.1 KeV to about 20 KeV. The implantation energy level can be varied depending on the implant type.

[0085] Many variations and / or modifications may be made to the embodiments of the present invention. Dopants other than halide dopants may also be used. In some embodiments, the dopant for the implanted spacer element 110 includes fluorine, nitrogen, oxygen, carbon, one or more other suitable dopants, or a combination thereof.

[0086] In some embodiments, the atomic concentration of the dopant 124 (e.g., fluorine) gradually decreases from the inner surface of the spacer element 110 toward the outer surface of the spacer element 110 adjacent to the etch stop layer 114. Because the dopant 124 enters the spacer element 110 from the inner surface of the spacer element 110 (i.e., the sidewalls of the recess 118'), the portion of the spacer element 110 adjacent to the inner surface may have a greater atomic concentration of the dopant 124 than the portion of the spacer element 110 adjacent to the outer surface.

[0087] In some embodiments, due to the blocking effect of the dummy gate dielectric layer 106, the portion of the spacer element 110 adjacent to the dummy gate dielectric layer 106 (eg, portion R) has a lower dopant concentration than the other portion directly exposed to the doping operation 123. In some embodiments, as Figure 1H As shown, a portion R of the spacer element 110 adjacent to the dummy gate dielectric layer 106 is substantially free of the dopant 124 .

[0088] However, the present invention is not limited thereto. Some dopants may diffuse downward to the portion blocked by the dummy gate dielectric layer 106. In some embodiments, the entire spacer element 110 has a substantially uniform dopant concentration.

[0089] According to some embodiments, Figure 1I As shown, the dummy gate dielectric layer 106 is removed. As a result, the fin structure 102 is partially exposed. In some embodiments, the dummy gate dielectric layer 106 is removed using an etching process. In some embodiments, due to defects 122 in the upper portion P2 of the spacer element 110, the upper portion P2 has a lower resistance to the etchant used to remove the dummy gate dielectric layer 106 than the lower portion P1. In some embodiments, when etching the dummy gate dielectric layer 106, the upper portion P2 of the spacer element 110 is partially removed. As a result, as shown in FIG. Figure 1I As shown, the upper portion P2 of each spacer element 110 becomes thinner than the underlying lower portion P1. The etched upper portion P2 may have a greater atomic concentration of the dopant 124 than the remaining portion of the upper portion P2.

[0090] like Figure 1I As shown, the lower portion P1 has a thickness T1, and the upper portion P2 has a thickness T2. In some embodiments, thickness T1 is greater than thickness T2. Thickness T1 may range from about 1 nm to about 20 nm. In some other embodiments, thickness T1 may range from about 3 nm to about 20 nm. Thickness T2 may range from about 1 nm to about 20 nm. In some other embodiments, thickness T2 may range from about 2.5 nm to about 19.5 nm.

[0091] In some embodiments, the lower portion P1 of the spacer element 110 has a first atomic concentration of the dopant 124 (e.g., fluorine), and the upper portion P2 of the spacer element 110 has a second atomic concentration of the dopant 124 (e.g., fluorine). In some embodiments, the first atomic concentration of the dopant 124 is greater than the second atomic concentration of the dopant 124.

[0092] According to some embodiments, Figure 1JAs shown, a metal gate stack is deposited to fill the recess 118' surrounded by the spacer element 110. The metal gate stack may include a gate dielectric layer 126, a work function layer 128, and a conductive fill layer 130. One or more other layers may be formed between the metal gate stack layers. For example, a barrier layer may be formed between the gate dielectric layer 126 and the work function layer 128. A barrier layer may be formed between the work function layer 128 and the conductive fill layer 130. In some embodiments, the enlargement and / or widening of the recess 118' makes filling the metal gate stack easier.

[0093] In some embodiments, the gate dielectric layer 126 is made of or includes a high-k dielectric material. The gate dielectric layer 126 may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, a hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or combinations thereof.

[0094] In some embodiments, a gate dielectric layer 126 is deposited over the dielectric layer 116 along the sidewalls and bottom of the recess 118'. The gate dielectric layer 126 can be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof. In some embodiments, forming the gate dielectric layer 126 involves a thermal process. During the thermal process, the spacer elements 110 are also heated. This activates the dopants 124 in the spacer elements 110, further reducing the dielectric constant of the spacer elements 110. Additional subsequent thermal processes also help activate the dopants 124 in the spacer elements 110.

[0095] Work function layer 128 can be used to provide a desired work function for the transistor to enhance device performance, including improving threshold voltage. In some embodiments, work function layer 128 is used to form an NMOS device. Work function layer 128 is an n-type work function layer. An n-type work function layer can provide a suitable work function value for the device, for example, equal to or less than approximately 4.5 eV.

[0096] The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

[0097] In some embodiments, a PMOS device is formed using the work function layer 128. The work function layer 128 is a p-type work function layer that can provide a suitable work function value for the device, such as equal to or greater than about 4.8 eV.

[0098] The p-type work function layer may include metal, metal carbide, metal nitride, other suitable materials, or combinations thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or combinations thereof.

[0099] The work function layer 128 can be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer 128 can be fine-tuned to adjust the work function level. For example, a titanium nitride layer can be used as a p-type work function layer or an n-type work function layer, depending on the thickness and / or composition of the titanium nitride layer.

[0100] The work function layer 128 may be deposited on the gate dielectric layer 126 by using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0101] In some embodiments, a barrier layer is formed before the work function layer 128 to provide a connection between the gate dielectric layer 126 and the subsequently formed work function layer 128. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 126 and the subsequently formed work function layer 128. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0102] In some embodiments, the conductive fill layer 130 is made of, or includes, a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. The conductive fill layer 130 may be deposited on the work function layer 128 using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other suitable processes, or a combination thereof.

[0103] In some embodiments, a barrier layer is formed on the work function layer 128 before forming the conductive fill layer 130. The barrier layer can be used to prevent the subsequently formed conductive fill layer 130 from diffusing into or penetrating the work function layer 128. The barrier layer can be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The barrier layer can be deposited using an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0104] According to some embodiments, Figure 1K As shown, a planarization process is performed to remove portions of the metal gate stack outside the recesses (or trenches) between the spacer elements 110. As a result, metal gate stacks 132 are formed. Each metal gate stack 132 includes a gate dielectric layer 126, a work function layer 128, and a conductive fill layer 130.

[0105] like Figure 1K As shown, one of the metal gate stacks 132 has a lower portion having a width W1, a middle portion having a width W3, and an upper portion having a width W2. In some embodiments, width W2 is greater than width W3, and width W3 is greater than width W1.

[0106] like Figure 1K As shown, an angle θ is formed between the sidewall surface of the spacer element 110 and an imaginary plane L extending from the inner surface of the spacer element 110 toward the top of the metal gate stack 132. In some embodiments, the angle θ should be carefully controlled to fall within a suitable range. In some embodiments, the angle θ is in a range of about 0.5 degrees to about 20 degrees.

[0107] The upper portion P2 of the spacer element 110 may have a lower portion and an upper portion. Figure 1K As shown, the lower portion has a substantially uniform thickness, such as thickness T2. Figure 1K As shown, the upper portion tapers gradually in a direction towards the top of the spacer element 110 .

[0108] According to some embodiments, Figure 4A diagram showing the distribution of dopant concentration in a spacer element of a semiconductor device structure. In some embodiments, Figure 4 Show Figure 1K A graph showing the atomic concentration profile of the dopant 124 in the spacer element 110 is shown. The horizontal axis represents the distance from the inner surface of the spacer element 110 (adjacent the metal gate stack 132) to the outer surface of the spacer element 110 (adjacent the etch stop layer 114 and at a distance T1). The vertical axis represents the atomic concentration of the dopant 124 in the spacer element 110 at the corresponding distance. As shown in Figures 4 and 1K, the atomic concentration of the dopant 124 in the spacer element 110 decreases from the inner surface of the spacer element 110 to the outer surface of the spacer element 110. In some embodiments, the portion of the spacer element 110 adjacent to the outer surface of the spacer element 110 is substantially free of the dopant 124.

[0109] According to some embodiments, Figure 5 A diagram showing the distribution of dopant concentration in a spacer element of a semiconductor device structure. In some embodiments, Figure 5 Show Figure 1K A profile of the atomic concentration of the dopant 124 in the spacer element 110 is shown. As shown in Figures 5 and 1K, the atomic concentration of the dopant 124 in the spacer element 110 gradually decreases from the inner surface of the spacer element 110 to the outer surface of the spacer element 110. In some embodiments, the portion of the spacer element 110 adjacent to the inner surface of the spacer element 110 has a higher atomic concentration of the dopant 124 than the portion of the spacer element 110 adjacent to the outer surface of the spacer element 110.

[0110] Many variations and / or modifications may be made to the embodiments of the present invention. According to some embodiments, Figure 2 is a cross-sectional view of a semiconductor device structure. In some embodiments, the planarization process for forming the metal gate stack 132 further removes the upper portion of the upper portion P2 of the spacer element 110. As a result, a structure such as Figure 2 The structure shown.

[0111] Many variations and / or modifications may be made to the embodiments of the present invention. According to some embodiments, Figure 3 is a cross-sectional view of a semiconductor device structure. In some embodiments, the planarization process for forming the metal gate stack 132 further removes the upper portion P2 of the spacer element 110. As a result, a Figure 3 The structure shown.

[0112] An embodiment of the present invention relates to a gate replacement process. A dummy gate stack having a dummy gate electrode and a dummy gate dielectric layer is partially removed to form a groove between the spacer elements. The spacer element is then partially removed to have a wider upper portion, which facilitates the subsequent formation of a metal gate stack. Thereafter, the dummy gate electrode is removed to expose the dummy gate dielectric layer. A doping operation is then used to dope the spacer element with one or more dopants that can reduce the dielectric constant of the spacer element. Thereafter, the dummy gate dielectric layer is removed and a metal gate stack is formed in the groove. Before the doping operation, the spacer element may have a stronger resistance to withstand the process of forming a source / drain structure next to the dummy gate stack. After the source / drain structure is formed, a doping operation is performed to reduce the dielectric constant of the spacer element. As a result, RC delay is reduced and the reliability and performance of the semiconductor device structure are improved.

[0113] According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a dummy gate stack on a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming a spacer element on the sidewall of the dummy gate stack and partially removing the dummy gate electrode to form a groove. The method also includes partially removing the spacer element to expand the groove and removing the remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer element and removing the dummy gate dielectric layer after removing the remaining portion of the dummy gate electrode. The method also includes forming a metal gate stack in the groove. In one embodiment, doping the spacer element includes implanting the spacer element with halogen-containing dopant ions. In one embodiment, the spacer element is doped with fluorine. In one embodiment, when removing the dummy gate dielectric layer, the upper portion of the spacer element is partially removed, so that the upper portion of the spacer element becomes thinner than the lower portion of the spacer element. In one embodiment, the method further includes forming a source / drain structure on the semiconductor substrate, the source / drain structure being located adjacent to the dummy gate stack, forming a dielectric layer over the source / drain structure and the dummy gate stack, and planarizing the dielectric layer to expose the dummy gate stack. In one embodiment, the method further includes forming an etch stop layer over the source / drain structure and the dummy gate stack before forming the dielectric layer. In one embodiment, a portion of the etch stop layer is removed when the spacer element is partially removed to expand the recess. In one embodiment, forming the metal gate stack includes forming a gate dielectric layer over the dielectric layer, the gate dielectric layer extending along the sidewalls and bottom of the recess, forming a work function layer over the gate dielectric layer, forming a conductive fill layer over the work function layer to fill the recess, and planarizing the conductive fill layer, the work function layer, and the gate dielectric layer to expose the dielectric layer. In one embodiment, the dummy gate dielectric layer is removed after doping the spacer element. In one embodiment, the method further includes heating the spacer element after doping the spacer element.

[0114] According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a dummy gate electrode on a semiconductor structure and forming a spacer element on a sidewall of the dummy gate electrode. The method also includes partially removing the dummy gate electrode to form a recess and partially removing the spacer element so that the upper portion of the recess is wider. The method also includes removing the remaining portion of the dummy gate electrode and implanting the spacer element with at least one dopant. In addition, the method includes forming a metal gate stack in the recess. In one embodiment, the at least one dopant includes fluorine, nitrogen, oxygen, carbon, or a combination thereof. In one embodiment, the method also includes forming a source / drain structure adjacent to the dummy gate electrode before implanting the spacer element. In one embodiment, the method also includes removing a native oxide grown on the dummy gate electrode after partially removing the spacer element and before removing the remaining portion of the dummy gate electrode. In one embodiment, a dummy gate dielectric layer is exposed after removing the remaining portion of the dummy gate electrode, and the method also includes removing the dummy gate dielectric layer after implanting the spacer element and before forming the metal gate stack.

[0115] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a metal gate stack on the semiconductor substrate. The semiconductor device also includes a spacer element on the sidewall of the metal gate stack. The spacer element is doped with fluorine. In one embodiment, the atomic concentration of fluorine gradually decreases along a direction from the inner surface of the spacer element adjacent to the metal gate stack toward the outer surface of the spacer element. In one embodiment, the spacer element has a lower portion and an upper portion, and the lower portion is thicker than the upper portion. In one embodiment, the lower portion has a first atomic concentration of fluorine, the upper portion has a second atomic concentration of fluorine, and the first atomic concentration is greater than the second atomic concentration. In one embodiment, the upper portion of the spacer element has a first portion and a second portion, the first portion is located between the second portion and the semiconductor substrate, the first portion has a substantially uniform thickness, and the second portion gradually becomes thinner along a direction toward the top of the spacer element.

[0116] The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can preferably understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the inventive concept and scope of the embodiments of the present invention. Various changes, replacements or modifications may be made to the embodiments of the present invention without departing from the inventive concept and scope of the embodiments of the present invention, and therefore the scope of protection of the present invention shall be subject to that defined by the claims. In addition, although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been described in detail herein.

Claims

1. A method for forming a semiconductor device, comprising: forming a dummy gate stack on a semiconductor substrate, wherein the dummy gate stack comprises a dummy gate electrode and a dummy gate dielectric layer; forming spacer elements on sidewalls of the dummy gate stack; Partially removing the dummy gate electrode to form a groove; partially removing the spacer element to enlarge the recess; removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer; doping the spacer element after removing the remaining portion of the dummy gate electrode; removing the dummy gate dielectric layer, wherein the dummy gate dielectric layer is removed after doping the spacer elements; as well as A metal gate stack is formed in the recess, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall proximate the metal gate stack, and the lower portion has a lower sidewall proximate the metal gate stack, the upper sidewall and the lower sidewall are substantially vertical, and the lower sidewall is recessed relative to the upper sidewall. 2 . The method for forming a semiconductor device according to claim 1 , wherein doping the spacer element comprises implanting the spacer element with a halide-containing dopant ion. 3 . The method for forming a semiconductor device according to claim 1 , wherein the spacer element is doped with fluorine.

4. The method for forming a semiconductor device as claimed in claim 1, wherein when removing the gate dielectric layer, a portion of the upper portion of the spacer element is partially removed, so that the upper portion of the spacer element becomes thinner than a lower portion of the spacer element.

5. The method for forming a semiconductor device according to claim 1 , further comprising: forming a source / drain structure on the semiconductor substrate, wherein the source / drain structure is located next to the dummy gate stack; forming a dielectric layer on the source / drain structure and the dummy gate stack; as well as The dielectric layer is planarized to expose the dummy gate stack.

6. The method for forming a semiconductor device according to claim 5, further comprising: Before forming the dielectric layer, an etch stop layer is formed on the source / drain structure and the dummy gate stack. 7 . The method for forming a semiconductor device according to claim 6 , wherein a portion of the etch stop layer is removed when the spacer element is partially removed to expand the recess.

8. The method for forming a semiconductor device according to claim 5 , wherein forming the metal gate stack comprises: forming a gate dielectric layer on the dielectric layer, wherein the gate dielectric layer extends along sidewalls and a bottom of the groove; forming a work function layer on the gate dielectric layer; forming a conductive filling layer on the work function layer to fill the groove; and The conductive filling layer, the work function layer, and the gate dielectric layer are planarized to expose the dielectric layer.

9. The method for forming a semiconductor device according to claim 1 , further comprising: After doping the spacer elements, the spacer elements are heated.

10. The method for forming a semiconductor device according to claim 1, wherein an upper portion of the spacer element has a first dopant concentration, a lower portion of the spacer element has a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration.

11. A method for forming a semiconductor device, comprising: forming a dummy gate electrode on a semiconductor structure; forming a spacer element on a sidewall of the dummy gate electrode; Partially removing the dummy gate electrode to form a groove; Partially removing the spacer element so that an upper portion of the groove becomes wider; removing a remaining portion of the dummy gate electrode, wherein a dummy gate dielectric layer is exposed after the remaining portion of the dummy gate electrode is removed; implanting the spacer element with at least one dopant; forming a metal gate stack in the groove; as well as The dummy gate dielectric layer is removed after implanting the spacer element and before forming the metal gate stack, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall adjacent to the metal gate stack, and the lower portion has a lower sidewall adjacent to the metal gate stack, the upper sidewall and the lower sidewall are substantially vertical, and the lower sidewall is recessed relative to the upper sidewall. 12 . The method for forming a semiconductor device according to claim 11 , wherein the at least one dopant comprises fluorine, nitrogen, oxygen, carbon, or a combination thereof.

13. The method for forming a semiconductor device according to claim 11, further comprising: Before implanting the spacer element, a source / drain structure is formed next to the dummy gate electrode.

14. The method for forming a semiconductor device according to claim 11, further comprising: After partially removing the spacer element and before removing the remaining portion of the dummy gate electrode, a native oxide grown on the dummy gate electrode is removed. 15 . The method for forming a semiconductor device according to claim 11 , wherein an upper portion of the spacer element has a first dopant concentration, a lower portion of the spacer element has a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration. 16 . The method of forming a semiconductor device according to claim 15 , wherein the lower portion of the spacer element is substantially free of the at least one dopant.

17. A method for forming a semiconductor device, comprising: forming a dummy gate electrode on a semiconductor structure; forming a spacer element on a sidewall of the dummy gate electrode; removing an upper portion of the dummy gate electrode to form a groove; removing a portion of an upper portion of the spacer element; After removing a portion of the upper portion of the spacer element, removing a remaining portion of the dummy gate electrode, wherein a dummy gate dielectric layer is exposed after removing the remaining portion of the dummy gate electrode; introducing at least one dopant into the spacer element; forming a metal gate stack in the groove; as well as The dummy gate dielectric layer is removed after introducing the at least one dopant into the spacer element and before forming the metal gate stack, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall proximate the metal gate stack, the lower portion has a lower sidewall proximate the metal gate stack, the upper sidewall and the lower sidewall are substantially vertical, and the lower sidewall is recessed relative to the upper sidewall. 18 . The method of forming a semiconductor device according to claim 17 , wherein the at least one dopant reduces a dielectric constant of the spacer element. 19 . The method for forming a semiconductor device according to claim 17 , wherein the at least one dopant comprises fluorine, nitrogen, oxygen, carbon, or a combination thereof.

20. The method for forming a semiconductor device according to claim 17, wherein when removing the dummy gate electrode layer, another portion of the upper portion of the spacer element is partially removed so that each upper portion of the spacer element becomes thinner than each lower portion of the spacer element.

21. A semiconductor device comprising: a semiconductor substrate; a metal gate stack located on the semiconductor substrate; as well as A spacer element is located on a sidewall of the metal gate stack, wherein the spacer element is doped with a dopant that reduces a dielectric constant of the spacer element, and an atomic concentration of the dopant decreases along an inner surface of the spacer element adjacent to the metal gate stack toward an outer surface of the spacer element, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall adjacent to the metal gate stack, and the lower portion has a lower sidewall adjacent to the metal gate stack, the upper sidewall and the lower sidewall are substantially vertical, and the lower sidewall is recessed relative to the upper sidewall. 22 . The semiconductor device of claim 21 , wherein the atomic concentration of the dopant gradually decreases along the inner surface of the spacer element adjacent to the metal gate stack toward the outer surface of the spacer element.

23. The semiconductor device of claim 21, wherein the lower portion has a first atomic concentration of the dopant, the upper portion has a second atomic concentration of the dopant, and the first atomic concentration of the dopant is greater than the second atomic concentration of the dopant.

24. The semiconductor device of claim 23, wherein the upper portion of the spacer element comprises a first portion and a second portion, the first portion being located between the second portion and the semiconductor substrate, the first portion having a substantially uniform thickness, and the second portion tapering toward a top of the spacer element.

25. The semiconductor device of claim 21, wherein the lower portion of the spacer element has a lower portion and an upper portion, the upper portion having a first atomic concentration of the dopant, the lower portion having a second atomic concentration of the dopant, and the first atomic concentration of the dopant is greater than the second atomic concentration of the dopant. 26 . The semiconductor device of claim 25 , wherein the lower portion of the lower portion of the spacer element is substantially free of the dopant.

27. The semiconductor device of claim 21, wherein the dopant comprises a halide.

28. The semiconductor device of claim 21, wherein the dopant comprises fluorine.

29. The semiconductor device of claim 21, wherein the spacer element is a single-layer spacer.

30. A semiconductor device comprising: a semiconductor substrate; a metal gate stack located on the semiconductor substrate; as well as A spacer element is located on a sidewall of the metal gate stack, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall proximate the metal gate stack, and the lower portion has a lower sidewall proximate the metal gate stack, the upper sidewall and the lower sidewall are substantially perpendicular, and the lower sidewall is recessed relative to the upper sidewall, wherein the spacer element is doped with a dopant that reduces a dielectric constant of the spacer element, the lower portion has a first atomic concentration of the dopant, and the upper portion has a second atomic concentration of the dopant, and the first atomic concentration of the dopant is greater than the second atomic concentration of the dopant.

31. The semiconductor device of claim 30, wherein the lower portion of the spacer element has an upper portion and a lower portion, and the lower portion is substantially free of the dopant.

32. The semiconductor device of claim 30 , wherein the lower portion of the spacer element has an inner portion and an outer portion, the inner portion is located between the outer portion and the metal gate stack, the inner portion has an inner atomic concentration of the dopant, the outer portion has an outer atomic concentration of the dopant, and the inner atomic concentration of the dopant is greater than the outer atomic concentration of the dopant.

33. The semiconductor device of claim 30, wherein the lower portion of the spacer element has an inner portion and an outer portion, the inner portion is located between the outer portion and the metal gate stack, and the outer portion is substantially free of the dopant.

34. A semiconductor device comprising: a semiconductor substrate; a metal gate stack located on the semiconductor substrate; as well as A spacer element is disposed on a sidewall of the metal gate stack, wherein the spacer element is doped with a dopant that reduces a dielectric constant of the spacer element, the spacer element having a lower portion and a higher portion, the higher portion having a first atomic concentration of the dopant, the lower portion having a second atomic concentration of the dopant, and the first atomic concentration of the dopant being greater than the second atomic concentration of the dopant, wherein the lower portion of the spacer element is thicker than the higher portion, the higher portion having an upper sidewall proximate the metal gate stack, and the lower portion having a lower sidewall proximate the metal gate stack, the upper sidewall and the lower sidewall being substantially vertical, and the lower sidewall being recessed relative to the upper sidewall. 35 . The semiconductor device of claim 34 , wherein the high portion of the spacer element has an inner portion and an outer portion, the inner portion is located between the outer portion and the metal gate stack, and the inner portion has a greater atomic concentration of the dopant than the outer portion. The semiconductor device of claim 35 , wherein the exterior portion is substantially free of the dopant.

37. The semiconductor device of claim 34, wherein the dopant comprises fluorine, carbon, or a combination thereof.

38. A semiconductor device comprising: a semiconductor substrate; a metal gate stack located on the semiconductor substrate; as well as A spacer element is located on a sidewall of the metal gate stack, wherein the spacer element is doped with fluorine, wherein the spacer element has a lower portion and an upper portion, the lower portion is thicker than the upper portion, the upper portion has an upper sidewall adjacent to the metal gate stack, and the lower portion has a lower sidewall adjacent to the metal gate stack, the upper sidewall and the lower sidewall are substantially vertical, and the lower sidewall is recessed relative to the upper sidewall. 39 . The semiconductor device of claim 38 , wherein an atomic concentration of fluorine gradually decreases along an inner surface of the spacer element adjacent to the metal gate stack toward an outer surface of the spacer element.

40. The semiconductor device of claim 38, wherein the lower portion has a first atomic concentration of fluorine, the upper portion has a second atomic concentration of fluorine, and the first atomic concentration of fluorine is greater than the second atomic concentration of fluorine.

41. The semiconductor device of claim 40, wherein the upper portion of the spacer element has a first portion and a second portion, the first portion being located between the second portion and the semiconductor substrate, the first portion having a substantially uniform thickness, and the second portion tapering in a direction toward a top of the spacer element.

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