A semiconductor packaging structure and its manufacturing process

Abstract

The present invention relates to a novel semiconductor package structure and its manufacturing process. The package structure includes a circuit inner core (1), and the circuit inner core (1) includes an upper metal plate (1.1) and a lower metal plate (1.2). Plastic (2) is filled between the upper metal plate (1.1) and the lower metal plate (1.2). A base island (3) and inner leads (4) are arranged on the front surface of the upper metal plate (1.1), and outer leads (5) are arranged on the back surface of the lower metal plate (1.2). A chip (7) is arranged on the base island (3), and the chip (7) and bonding wires (8) are encapsulated by a plastic encapsulant (9). In the present invention, the plastic encapsulant is directly filled in the circuit inner core, without the use of a glass fiber layer, and there is no need to implant a conductive substance in the holes after opening the holes, which simplifies the manufacturing process, reduces the manufacturing cost, and at the same time, due to its relatively stable structure, it is not easy to warp when the temperature changes.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure and a manufacturing process thereof, belonging to the technical field of semiconductor packaging. Background Art

[0002] The manufacturing process flow of a traditional substrate packaging structure is as follows:

[0003] Step 1: Refer to Figure 13 , take a substrate made of a glass fiber material;

[0004] Step 2: Refer to Figure 14 , open holes at the required positions on the glass fiber substrate;

[0005] Step 3: Refer to Figure 15 , coat a layer of copper foil on the back of the glass fiber substrate;

[0006] Step 4: Refer to Figure 16 , fill conductive substances at the positions where holes are drilled on the glass fiber substrate;

[0007] Step 5: Refer to Figure 17 , coat a layer of copper foil on the front of the glass fiber substrate;

[0008] Step 6: Refer to Figure 18 , coat a photoresist film on the surface of the glass fiber substrate;

[0009] Step 7: Refer to Figure 19 , expose and develop the photoresist film to open windows at the required positions;

[0010] Step 8: Refer to Figure 20 , etch the part where the window opening is completed;

[0011] Step 9: Refer to Figure 21 , strip the photoresist film on the substrate surface;

[0012] Step 10: Refer to Figure 22 , coat a solder mask (commonly known as green paint) on the surface of the copper foil circuit layer;

[0013] Step 11: Refer to Figure 23 , open windows in the areas of the solder mask where subsequent chip mounting and wire bonding operations are required;

[0014] Step 12: Refer to Figure 24 , electroplate in the areas where windows are opened in Step 11 to form base islands and pins relatively;

[0015] Step 13: Complete subsequent related processes such as chip mounting, wire bonding, encapsulation, and cutting.

[0016] The above traditional substrate packaging structure has the following deficiencies and defects:

[0017] 1. In the manufacture of traditional substrates, holes need to be drilled in a fiberglass substrate, conductive substances are implanted into the holes, and copper foil is coated on the fiberglass substrate. Its manufacturing process is very complex and the cost is relatively high.

[0018] 2. The traditional substrate has a layer of fiberglass material, which also incurs an additional cost for the fiberglass. Fiberglass itself is a foaming substance, so it is prone to absorbing moisture and humidity over time and in different environments, directly affecting the reliability and safety performance or the reliability level.

[0019] 3. In traditional substrates, upper and lower conducting metal posts are only provided at the places where electrical connections are required, so the metal posts are not evenly distributed, which may cause the substrate to warp easily when the temperature changes. Summary of the Invention

[0020] The technical problem to be solved by the present invention is to provide a semiconductor packaging structure and its manufacturing process for the above-mentioned existing technology. Plastic is directly filled in the inner core of the circuit, without using a fiberglass layer, and there is no need to implant conductive substances into the holes after drilling. The manufacturing process is simplified, the production cost is reduced, and at the same time, due to its relatively stable structure, it is not prone to warping when the temperature changes.

[0021] The technical solution adopted by the present invention to solve the above problems is: a semiconductor packaging structure, which includes an inner core of the circuit. The inner core of the circuit includes an upper metal plate and a lower metal plate. The upper metal plate and the lower metal plate are connected by a plurality of metal posts. Plastic is filled between the upper metal plate and the lower metal plate, and the metal posts are coated with the plastic. A base island and inner leads are arranged on the front surface of the upper metal plate, and outer leads are arranged on the back surface of the lower metal plate. A chip is arranged on the base island, and the chip is encapsulated with molding compound. The metal posts have two forms, namely connecting metal posts and virtual metal posts. The connecting metal posts play the roles of electrical connection and mechanical support, and the virtual metal posts only play the role of mechanical support.

[0022] Optionally, the plurality of metal posts are arranged in an array.

[0023] Optionally, the outer periphery of the upper metal plate and the lower metal plate is coated with green paint.

[0024] Optionally, the upper surface of the green paint coated on the outer periphery of the upper metal plate is flush with the upper surfaces of the base island and the inner leads; the lower surface of the green paint coated on the outer periphery of the lower metal plate is flush with the lower surfaces of the outer leads.

[0025] Optionally, the connecting metal pillars in the base island area are connected to the top and bottom of the connecting metal pillars through an upper metal plate and a lower metal plate respectively, and the connecting metal pillars in the pin area are connected to the top and bottom of the connecting metal pillars through an upper metal plate and a lower metal plate respectively.

[0026] Optionally, the connecting metal pillars in the base island area are connected to the virtual metal pillars only through the upper metal plate at the top or the lower metal plate at the bottom; the connecting metal pillars and the virtual metal pillars in the pin area are connected only through the upper metal plate at the top or the lower metal plate at the bottom.

[0027] Optionally, the virtual metal pillars in the base island area are connected to the virtual metal pillars only through the upper metal plate at the top or the lower metal plate at the bottom; the virtual metal pillars in the pin area are connected to the virtual metal pillars only through the upper metal plate at the top or the lower metal plate at the bottom.

[0028] Optionally, the connecting metal pillars in the base island area are not connected by the lower metal plate between the bottom of the connecting metal pillars.

[0029] A manufacturing process of a semiconductor packaging structure, the process comprising the following steps:

[0030] Step 1: Take a circuit inner core, the circuit inner core includes an upper metal plate and a lower metal plate, and the upper metal plate and the lower metal plate are connected by a plurality of metal pillars;

[0031] Step 2: Fill plastic between the upper metal plate and the lower metal plate of the circuit inner core;

[0032] Step 3: Chemically etch partial areas on the surfaces of the upper metal plate and the lower metal plate until the plastic and partial metal pillars are exposed;

[0033] Step 4: Coat green paint on the peripheries of the upper metal plate and the lower metal plate after the etching in Step 3 is completed;

[0034] Step 5: Expose and develop the green paint on the surfaces of the upper metal plate and the lower metal plate to remove partial green paint, so as to expose the graphic areas on the upper metal plate and the lower metal plate that need to be electroplated subsequently;

[0035] Step 6: Form corresponding base islands and inner pins on the front of the upper metal plate by electroplating, and form outer pins on the back of the lower metal plate;

[0036] Step 7: Implant a chip on the base island formed in Step 6;

[0037] Step 8: Encapsulate the periphery of the chip with a molding compound;

[0038] Step 9: Cut to obtain a single semiconductor packaging structure.

[0039] Optionally, the upper metal plate and the lower metal plate in step one are flat metal plates; there are two forms of metal columns, namely connecting metal columns and virtual metal columns. The connecting metal columns play the roles of electrical connection and mechanical support, and the virtual metal columns only play the role of mechanical support in the subsequent formed packaging structure.

[0040] Compared with the prior art, the advantages of the present invention are as follows:

[0041] 1. The present invention directly fills plastic in the inner core of the circuit, without using a glass fiber layer, without the need to open holes and implant conductive substances in the holes, simplifies the manufacturing process, reduces the production cost, improves the safety and reliability of the package, and reduces the environmental pollution caused by glass fiber materials;

[0042] 2. In the packaging structure of the present invention, metal columns are evenly distributed. Some are used to connect the base island with the outer pins or the inner pins with the outer pins, and some are virtual metal columns. Although they are not used for electrical connection, they still play a supporting role. Therefore, its structure is relatively stable and is not prone to warping when the temperature changes. Description of the Drawings

[0043] Figure 1 It is a schematic cross-sectional view of Embodiment 1 of a semiconductor packaging structure of the present invention.

[0044] Figure 2 It is a schematic cross-sectional view of Embodiment 2 of a semiconductor packaging structure of the present invention.

[0045] Figures 3 to 12 It is a schematic flow chart of a manufacturing process of a semiconductor packaging structure of the present invention.

[0046] Figures 13 to 24 It is a schematic flow chart of a manufacturing process of a traditional substrate packaging structure.

[0047] Among them:

[0048] Inner core of the circuit 1

[0049] Upper metal plate 1.1

[0050] Lower metal plate 1.2

[0051] Metal column 1.3

[0052] Connecting metal column 1.3a

[0053] Virtual metal column 1.3b

[0054] Plastic 2

[0055] Base island 3

[0056] Inner pin 4

[0057] Outer pin 5

[0058] Bonding material or solder 6

[0059] Chip 7

[0060] Bonding wire 8

[0061] Molding compound 9

[0062] Green paint 10. Detailed implementation mode

[0063] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0064] Embodiment 1:

[0065] As Figure 1 shown, a semiconductor package structure involved in the present invention includes an inner circuit core 1, the inner circuit core 1 includes an upper metal plate 1.1 and a lower metal plate 1.2, the upper metal plate 1.1 and the lower metal plate 1.2 are electrically and mechanically connected through a plurality of metal columns 1.3 arranged in an array, plastic 2 is filled between the upper metal plate 1.1 and the lower metal plate 1.2, the metal columns 1.3 are coated in the plastic 2, a base island 3 and inner leads 4 are arranged on the front surface of the upper metal plate 1.1, outer leads 5 are arranged on the back surface of the lower metal plate 1.2, a chip 7 is arranged on the base island 3 through a bonding material or solder 6, the chip 7 is electrically connected to the inner leads 4 through a bonding wire 8, and the chip 7 and the bonding wire 8 are encapsulated with a molding compound 9;

[0066] The upper metal plate 1.1 and the lower metal plate 1.2 are coated with green paint 10;

[0067] The upper surface of the green paint 10 coated on the periphery of the upper metal plate 1.1 is flush with the upper surfaces of the base island 3 and the inner leads 4;

[0068] The lower surface of the green paint 10 coated on the periphery of the lower metal plate 1.2 is flush with the lower surfaces of the outer leads 5;

[0069] The metal columns 1.3 have two forms, namely connecting metal columns 1.3a and virtual metal columns 1.3b, the connecting

[0070] metal columns 1.3a are used to connect the base island 3 to the outer leads 5 or the inner leads 4 to the outer leads 5, playing the role of electrical connection and mechanical support, and the virtual metal columns 1.3b only play the role of mechanical support;

[0071] The plastic 2 is a thermosetting plastic, and can be phenolic plastic, epoxy plastic, amino plastic, unsaturated polyester, alkyd plastic, etc.;

[0072] The connecting metal columns 1.3a in the area of the base island 3 are connected by the upper metal plate 1.1 and the lower metal plate 1.2 respectively between the top and the bottom of the connecting metal columns 1.3a;

[0073] The connecting metal posts 1.3a in the pin area (including the inner pin area and the outer pin area) are connected to the top and bottom of the connecting metal posts 1.3a through the upper metal plate 1.1 and the lower metal plate 1.2 respectively;

[0074] The connecting metal posts 1.3a in the base island 3 area are connected to the top of the virtual metal posts 1.3b through the upper metal plate 1.1 or to the bottom through the lower metal plate 1.2;

[0075] The connecting metal posts 1.3a in the pin area (including the inner pin area and the outer pin area) are connected to the top of the virtual metal posts 1.3b through the upper metal plate 1.1 or to the bottom through the lower metal plate 1.2;

[0076] The virtual metal posts 1.3b in the base island 3 area are connected to the top of the virtual metal posts 1.3b through the upper metal plate 1.1 or to the bottom through the lower metal plate 1.2;

[0077] The virtual metal posts 1.3b in the pin area (including the inner pin area and the outer pin area) are connected to the top of the virtual metal posts 1.3b through the upper metal plate 1.1 or to the bottom through the lower metal plate 1.2.

[0078] Embodiment 2:

[0079] As Figure 2 shown, the difference between Embodiment 2 and Embodiment 1 is that: the connecting metal posts 1.3a in the base island 3 area are not connected to the bottom of the connecting metal posts 1.3a through the lower metal plate 1.2; the connecting metal posts 1.3a in the pin area (including the inner pin area and the outer pin area) are not connected to the bottom of the connecting metal posts 1.3a through the lower metal plate 1.2.

[0080] Its manufacturing process is as follows:

[0081] Step 1, referring to Figure 3 , take a circuit inner core, the circuit inner core includes an upper metal plate and a lower metal plate, the upper metal plate and the lower metal plate are flat metal plates, and the upper metal plate and the lower metal plate are electrically and mechanically connected through a plurality of metal posts; Figure 4 is a schematic diagram when the upper metal plate and the metal posts are not combined. A plurality of metal posts are arranged in an array between the upper metal plate and the lower metal plate. The metal posts have two forms, namely connecting metal posts and virtual metal posts. The connecting metal posts play the roles of electrical connection and mechanical support, and the virtual metal posts only play the role of mechanical support in the subsequent formed packaging structure;

[0082] Step 2, referring to Figure 5, plastic is coated around the inner core of the circuit by one-time injection molding. The lower surface of the upper metal plate, the upper surface of the lower metal plate, and the metal posts are coated in the plastic. The upper surface of the upper metal plate and the lower surface of the lower metal plate are exposed outside the plastic. The plastic is a thermosetting plastic, which can be phenolic plastic, epoxy plastic, amino plastic, unsaturated polyester, alkyd plastic, etc.;

[0083] Step three, refer to Figure 6 , a photoresist material that can be exposed and developed is pasted or printed on the front of the upper metal plate and the back of the lower metal plate to protect the subsequent etching of the metal layer process operation; the photoresist material can be a photoresist film or a photoresist. The photoresist material on the surface of the metal plate is exposed and developed by an exposure and development device to remove part of the photoresist material to expose the graphic area of the metal plate that needs to be etched. The exposed and developed area on the metal plate is chemically etched until the plastic and the virtual metal posts are exposed. The etching solution can be copper chloride or ferric chloride or other chemicals that can be used for chemical etching. Remove the photoresist film on the surface of the metal plate. The method of removing the photoresist film can be to soften it with a chemical solution and then wash it with high-pressure water. After the etching is completed, the connecting metal posts play the role of electrically connecting the inner pins and the outer pins and the mechanical support role. The virtual metal posts do not play the role of electrical connection and only play the role of mechanical support; Step four, refer to Figure 7 , apply green paint to the periphery of the upper metal plate and the lower metal plate that have completed etching in step three. The green paint completely coats the upper metal plate, the lower metal plate, and the plastic and virtual metal posts exposed by etching in step three;

[0084] Step five, refer to Figure 8 , use an exposure and development device to expose and develop the green paint on the surface of the metal plate to remove part of the green paint to expose the graphic area of the metal plate that needs to be electroplated;

[0085] Step six, refer to Figure 9 , electroplate the surface metal layer in the window areas on the front and back of the metal plate after step five. After the surface metal layer is electroplated, the corresponding base islands and inner pins are formed on the front of the upper metal plate, and the outer pins are formed on the back of the lower metal plate;

[0086] Step seven, refer to Figure 10 , apply a bonding substance or solder on the surface of the base island formed in step six, and then implant the chip on the bonding substance or solder. Perform wire bonding operation between the front of the chip and the front of the inner pins. The material of the metal wire is gold, silver, copper, aluminum or alloy material, and the shape of the metal wire can be filamentous or ribbon-shaped;

[0087] Step eight, refer to Figure 11, the periphery of the chip that has completed the wire bonding operation in Step Seven is encapsulated with encapsulant. The encapsulation method can be die potting, spraying, or film laminating, and the epoxy resin with or without filler can be used.

[0088] Step Nine, refer to Figure 12 , the semi-finished product that has completed the encapsulation in Step Eight is subjected to a cutting operation to separate the originally arrayed encapsulation bodies, thereby obtaining the semiconductor package structure.

[0089] In addition to the above embodiments, the present invention also includes other embodiments. Any technical solutions formed by equivalent transformation or equivalent substitution shall fall within the protection scope of the claims of the present invention.

Claims

1. A semiconductor package structure, characterized in that: It includes a circuit inner core (1), and the circuit inner core (1) includes an upper metal plate (1.1) and a lower metal plate (1.2). The upper metal plate (1.1) and the lower metal plate (1.2) are connected by a plurality of metal columns (1.3). All the metal columns between the upper metal plate and the lower metal plate are arranged in an array. Plastic (2) is filled between the upper metal plate (1.1) and the lower metal plate (1.2), and the metal columns (1.3) are coated in the plastic (2). A base island (3) and inner pins (4) are arranged on the front surface of the upper metal plate (1.1), and outer pins (5) are arranged on the back surface of the lower metal plate (1.2). A chip (7) is arranged on the base island (3), and the periphery of the chip (7) is encapsulated with plastic encapsulant (9). The metal columns (1.3) have two forms, namely connecting metal columns (1.3a) and virtual metal columns (1.3b). The connecting metal columns (1.3a) play the roles of electrical connection and mechanical support, and the virtual metal columns (1.3b) only play the role of mechanical support.

2. The semiconductor package structure according to claim 1, wherein: The peripheries of the upper metal plate (1.1) and the lower metal plate (1.2) are coated with green paint (10).

3. A semiconductor package structure according to claim 2, wherein: The upper surface of the green paint (10) coated on the periphery of the upper metal plate (1.1) is flush with the upper surfaces of the base island (3) and the inner pins (4); the lower surface of the green paint (10) coated on the periphery of the lower metal plate (1.2) is flush with the lower surfaces of the outer pins (5).

4. A semiconductor package structure according to claim 1, characterized in that: Between the connecting metal columns (1.3a) in the base island (3) region, the top and the bottom are connected by the upper metal plate (1.1) and the lower metal plate (1.2) respectively. Between the connecting metal columns (1.3a) in the pin region, the top and the bottom are connected by the upper metal plate (1.1) and the lower metal plate (1.2) respectively.

5. A semiconductor package structure according to claim 1, wherein: Between the connecting metal columns (1.3a) and the virtual metal columns (1.3b) in the base island (3) region, only the top or the bottom is connected; between the connecting metal columns (1.3a) and the virtual metal columns (1.3b) in the pin region, only the top or the bottom is connected.

6. A semiconductor package structure according to claim 1, characterized in that: Between the virtual metal columns (1.3b) in the base island (3) region, only the top or the bottom is connected; between the virtual metal columns (1.3b) in the pin region, the top or the bottom is connected.

7. A semiconductor package structure according to claim 1, wherein: Between the bottom of the connecting metal columns (1.3a) in the base island (3) region, they are not connected by the lower metal plate (1.2).

8. A manufacturing process of a semiconductor package structure, characterized in that The process includes the following steps: Step 1: Take a circuit inner core. The circuit inner core includes an upper metal plate and a lower metal plate. The upper metal plate and the lower metal plate are connected by a plurality of metal columns. All the metal columns between the upper metal plate and the lower metal plate are arranged in an array. Step 2: Fill plastic between the upper metal plate and the lower metal plate of the circuit inner core. Step 3: Chemically etch partial regions on the surfaces of the upper metal plate and the lower metal plate until the plastic and partial metal columns are exposed. Step 4: Coat green paint on the peripheries of the upper metal plate and the lower metal plate after the etching in Step 3 is completed. Step Five: Expose and develop the green paint on the surfaces of the upper metal plate and the lower metal plate to remove part of the green paint, so as to expose the graphic areas on the upper metal plate and the lower metal plate where electroplating operations need to be carried out subsequently; Step Six: Form corresponding base islands and inner leads on the front surface of the upper metal plate by electroplating, and form outer leads on the back surface of the lower metal plate; Step Seven: Implant chips on the base islands formed in Step Six; Step Eight: Encapsulate the periphery of the chips with encapsulant; Step Nine: Cut to obtain single semiconductor package structures.

9. The manufacturing process of a semiconductor packaging structure according to claim 8, characterized in that: In Step One, the upper metal plate and the lower metal plate are flat metal plates; there are two forms of metal columns, namely connecting metal columns and virtual metal columns. The connecting metal columns play the roles of electrical connection and mechanical support, and the virtual metal columns only play the role of mechanical support in the subsequently formed package structure.

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