Chip and Method for Forming the Same

Abstract

A chip and a method for forming the same, the chip comprising: a substrate including a storage region and a peripheral region; a memory array formed in the storage region; at least one antifuse device formed in the peripheral region, the antifuse device being configured to repair storage defects caused by failed memory cells in the memory array; the antifuse device comprising: a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectric layer; a doped region in the substrate on one side of the gate structure in a direction parallel to the surface of the substrate, at least a part of an edge of the doped region being aligned with an edge of the gate or located below the gate. The antifuse device is more easily broken down.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and in particular, to a chip and a method for forming the same. Background Art

[0002] DRAM chips manufactured using semiconductor processes will inevitably produce defective storage cells. Redundant storage cells are usually formed on DRAM chips. By using the redundant storage cells to permanently replace the defective storage cells, the DRAM chips can be repaired.

[0003] When repairing DRAM chips, one-time programming (OTP) devices such as fuses or antifuses are required. As the feature size of semiconductor processes decreases, the thickness of the gate dielectric layer of the MOS transistor structure has become very thin, making the MOS structure available as an antifuse device.

[0004] In the prior art, the formation process of the antifuse device is relatively complex, and the resistance during the breakdown process is large, making it difficult to achieve a large breakdown current and affecting the repair efficiency of the chip. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to improve the repair efficiency of the chip by increasing the breakdown current of the antifuse device.

[0006] To solve the above problems, the present invention provides a chip, including: a substrate, the substrate including a storage area and a peripheral area; a storage array formed in the storage area; an antifuse device formed in the peripheral area, the antifuse device being used to repair storage defects caused by failed storage cells in the storage array; the antifuse device being connected to the storage array; the antifuse device including: a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectric layer; a doped region in the substrate on one side of the gate structure in a direction parallel to the surface of the substrate, at least a part of the edge of the doped region being aligned with the edge of the gate or located below the gate.

[0007] Optionally, the storage array includes: a main storage array and a redundant storage array, the redundant storage cells in the redundant storage array being used to replace the failed storage cells in the main storage array for data storage; the at least one antifuse device constitutes a programmable module for recording information of the failed storage cells in the main storage array or / and the redundant storage cells in the redundant storage array.

[0008] Optionally, the substrate in the peripheral area includes an active region and an isolation region surrounding the active region; the gate structure covers part of the active region and part of the isolation region, only exposing part of the active region located on one side of the gate.

[0009] Optionally, a doped well is formed in the substrate under the gate structure of the antifuse device, and the doping type of the doped well is opposite to that of the doped region.

[0010] To solve the above problems, the technical solution of the present invention further provides a method for forming a chip, including: providing a substrate including a storage area and a peripheral area; forming a storage array in the storage area; forming at least one antifuse device in the peripheral area, the antifuse device including: a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectric layer; a doped region in the substrate on one side of the gate structure in a direction parallel to the surface of the substrate, and at least a part of the edge of the doped region is aligned with the edge of the gate or located under the gate.

[0011] Optionally, it further includes: forming peripheral circuit transistors in the peripheral area.

[0012] Optionally, the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the storage array are formed simultaneously.

[0013] Optionally, the formation methods of the peripheral circuit transistor, the antifuse device, and the storage array include: forming the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the storage array in the peripheral area; forming sidewalls on both sides of the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line; using the same mask to simultaneously remove the sidewalls on both sides of the bit line and the gate of the antifuse device.

[0014] Optionally, the formation method of the peripheral circuit transistor includes: performing light doping ion implantation on the substrate on both sides of the gate in the peripheral area before forming the sidewalls; after removing the sidewalls on both sides of the gate of the antifuse device, using the gate of the peripheral circuit transistor and the sidewalls on both sides, and the gate of the antifuse device as masks to perform heavy doping ion implantation on the substrate in the peripheral area to form the source / drain of the peripheral circuit transistor and the doped region of the antifuse device.

[0015] Optionally, the formation methods of the peripheral circuit transistor, the antifuse device, and the storage array include: forming the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the storage array; performing light doping ion implantation on the substrate on both sides of the gate in the peripheral area; forming sidewalls on both sides of the peripheral circuit transistor; using the gate of the peripheral circuit transistor and the sidewalls on both sides, and the gate of the antifuse device as masks to perform heavy doping ion implantation on the substrate in the peripheral area to form the source / drain of the peripheral circuit transistor and the doped region of the antifuse device.

[0016] The peripheral region of the chip of the present invention includes antifuse devices, and the antifuse devices adopt a MOS structure. A doped region is directly formed with the gate as a mask, so that the doped region is aligned with the edge of the gate or located below the gate, thereby shortening the current path between the doped region and the gate, reducing the resistance on the current path, and being beneficial to increasing the breakdown current.

[0017] During the formation process of the chip of the present invention, after simultaneously removing the gate of the antifuse device and the sidewalls on both sides of the bit line, the doped region of the antifuse device is formed, reducing the distance between the doped region and the gate. There is no need to add additional process steps, nor is it necessary to perform additional ion implantation on the active region below the gate of the antifuse device to reduce the resistance on the breakdown circuit path. Thus, process steps can be saved, and moreover, the antifuse device is more easily broken down, thereby improving the repair efficiency when using the antifuse device to repair the chip. Description of the Drawings

[0018] Figures 1 to 4 is a schematic structural diagram of the formation process of an antifuse device according to a specific embodiment of the present invention;

[0019] Figures 5 to 9 is a schematic structural diagram of the formation process of a memory according to a specific embodiment of the present invention. Specific Embodiments

[0020] The following will make a detailed description of the specific embodiments of the antifuse device and its formation method, the memory and its formation method provided by the present invention with reference to the drawings.

[0021] Please refer to Figures 1 to 4 , which is a schematic structural diagram of the formation process of an antifuse device according to a specific embodiment of the present invention.

[0022] Please refer to Figure 1 and Figure 2 , wherein Figure 2 is a schematic cross-sectional view along the secant line AA' in Figure 1 .

[0023] A substrate 100 is provided, and a gate structure is formed on the surface of the substrate 100. The gate structure includes a gate dielectric layer 103 located on the surface of the substrate 100 and a gate 104 located on the surface of the gate dielectric layer 103.

[0024] The substrate 100 may be a semiconductor substrate, such as a single crystal silicon substrate, a single crystal germanium substrate, etc. The substrate 100 may also be an N-type or P-type semiconductor substrate.

[0025] The substrate 100 includes an active region 102 and an isolation region 101 surrounding the active region 102. The isolation region 101 may be a shallow trench isolation structure formed within the substrate 100. A doped well may be formed within the active region 102, and the doped well may be a part of the self-doping of the substrate 100 or a doped well formed by ion implantation or diffusion of the substrate 100.

[0026] The method for forming a gate structure on the surface of the substrate 100 includes: sequentially forming a gate dielectric material layer covering the surface of the substrate 100 and a gate material layer covering the surface of the gate dielectric material layer, forming a patterned mask layer on the surface of the gate material layer, and etching the gate material layer and the gate dielectric material layer to the surface of the substrate 100 using the patterned mask layer as a mask to form the gate 104 and the gate dielectric layer 103.

[0027] The material of the gate dielectric layer 103 may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials such as hafnium oxide and zirconium oxide; the gate layer 104 may be at least one of conductive materials such as polysilicon, titanium, copper, tungsten, and metal silicide.

[0028] The gate structure covers a part of the active region 102 and may cover one end of the active region 102. In this specific embodiment, the width of one end of the active region 102 is smaller than that of the other end, the gate structure covers the end with a smaller width of the active region 102, and a part is located on the surface of the isolation region 101.

[0029] As an antifuse device, the thickness and dielectric constant of the gate dielectric layer 103 determine the breakdown voltage of the antifuse device. In the specific embodiment of the present invention, for the convenience of process compatibility with other MOS transistors in the circuit, the gate dielectric layer 103 may be formed simultaneously with the gate dielectric layers 103 of some transistors formed in other regions on the substrate 100, using the same material and thickness, such as being substantially the same as the gate dielectric layer of the low-voltage transistor in the peripheral region. Due to the different doping concentrations in the channel regions under the gate dielectric layers in different regions and other growth environments of the gate dielectric layers, even if they are formed in the same formation process, there may be slight differences in the thicknesses of the gate dielectric layers on different regions, so it is "substantially the same". In this specific embodiment, the material of the gate dielectric layer 103 is silicon oxide, and the thickness range may be 2 nm to 4 nm.

[0030] Please refer to Figure 3 and Figure 4 , a doped region 105 is formed within the substrate 100 on one side of the gate structure along the direction parallel to the surface of the substrate 100, and at least a part of the edge of the doped region 105 is aligned with the edge of the gate 104 or is located under the gate 104.

[0031] The doping region 105 can be formed by ion implantation. Using the gate 104 as a mask, the substrate 100 is ion implanted to form the doping region 105 in part or all of the uncovered active region 102. The doping type of the doping region 105 is opposite to that of the doping well in the active region 102. In this specific embodiment, the active region 102 has a P-type doping well, and the doping region 105 is N-type doping.

[0032] The doping region 105 serves as a conductive contact region and has a relatively high doping concentration to reduce resistance. In this specific embodiment, the doping region 105 is formed in a region where the width of the active region 102 is larger, which can increase the contact area of the doping region 105, thereby increasing the size of the electrical contact portion formed on the surface of the doping region 105 subsequently and reducing the contact resistance between the electrical contact portion and the doping region 105. In a specific embodiment, the doping concentration range of the doping region 105 is 1e20 - 5e21 cm ,

[0033] ,

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[0034] , As doping can be used, the ion implantation energy can be 20 keV - 50 keV, and the implantation dose can be 1e15 - 5e15 cm -2 , and the relatively high doping concentration can further reduce the resistance of the doping region 105.

[0033] Since the periphery of the active region 102 is the isolation region 101, during ion implantation, the isolation region 101 will also be implanted, but no conductive doping region will be formed.

[0034] Since the ion implantation uses the gate 104 as a mask, the edge of the formed doping region 105 is aligned with the edge of the gate 104, or can be partially located under the gate 104. When a breakdown voltage is applied to the gate 104, the current flows from the gate 104 to the doping region 105. Since the distance between the doping region 105 and the gate 104 is relatively close, the resistance on the carrier movement path can be reduced, thereby increasing the breakdown current and improving the breakdown efficiency of the antifuse device. There is no need to perform additional ion implantation on the active region under the gate 104 to reduce the resistance.

[0035] The method for forming the antifuse device in the above specific embodiment adopts a MOS structure and directly uses the gate as a mask to form a doping region, so that the doping region is aligned with the gate edge or located under the gate, thereby shortening the current path between the doping region and the gate, reducing the resistance on the current path, and being beneficial to increasing the breakdown current.

[0036] The specific embodiment of the present invention also provides an antifuse device formed by the above method.

[0037] Please refer toFigure 3 and Figure 4 , which is an anti-fuse device according to a specific embodiment of the present invention.

[0038] The anti-fuse device includes: a substrate 100; a gate structure located on the surface of the substrate 100, the gate structure including a gate dielectric layer 103 located on the surface of the substrate 100 and a gate 104 located on the surface of the gate dielectric layer 103; a doped region 105 in the substrate on one side of the gate structure, at least a part of the edge of the doped region 105 being aligned with the edge of the gate structure or located below the gate structure.

[0039] The substrate 100 includes an active region 102 and an isolation region 101 surrounding the active region 102. The isolation region 101 may be a shallow trench isolation structure formed in the substrate 100. A doped well may be formed in the active region 102, and the doped well may be a part of the self-doping of the substrate 100 or a doped well formed by ion implantation or diffusion of the substrate 100.

[0040] The material of the gate dielectric layer 103 may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials such as hafnium oxide and zirconium oxide; the gate layer 104 may be at least one of conductive materials such as polysilicon, titanium, copper, tungsten, and metal silicide. The gate structure covers a part of the active region 102 and may cover one end of the active region 102. In this specific embodiment, one end of the active region 102 has a smaller width than the other end, and the gate structure covers the end with the smaller width of the active region 102 and is partially located on the surface of the isolation region 101.

[0041] As an anti-fuse device, the thickness and dielectric constant of the gate dielectric layer 103 determine the breakdown voltage of the anti-fuse device. In the specific embodiment of the present invention, for the convenience of process compatibility with other MOS transistors in the circuit, the gate dielectric layer 103 may have the same material and thickness as the gate dielectric layer 103 of some transistors formed in other regions on the substrate 100, such as being substantially the same as the gate dielectric layer of the low-voltage transistors in the peripheral region. Due to the different doping concentrations in the channel regions under the gate dielectric layers in different regions and other growth environments of the gate dielectric layers, even if they are formed in the same formation process, there may be slight differences in the thicknesses of the gate dielectric layers on different regions, so it is "substantially the same". In this specific embodiment, the material of the gate dielectric layer 103 is silicon oxide, and the thickness range may be 2 nm to 4 nm.

[0042] The doping type of the doped region 105 is opposite to the doping type of the doped well in the active region 102. In this specific embodiment, the active region 102 has a P-type doped well, and the doped region 105 is N-type doped.

[0043] The heavily doped region 105 serves as a conductive contact region with a relatively high doping concentration to reduce resistance. In this specific embodiment, the doped region 105 is formed in the region where the width of the active region 102 is larger, which can increase the contact area of the doped region 105, thereby increasing the size of the electrical contact portion formed on the surface of the doped region 105 subsequently and reducing the contact resistance between the electrical contact portion and the doped region 105. Moreover, the doping concentration range of the doped region 105 is 1e20 - 5e21 cm -3 , and the relatively high doping concentration can further reduce the resistance of the doped region 105.

[0044] The edge of the doped region 105 is aligned with the edge of the gate 104 or can be partially located under the gate 104. When a breakdown voltage is applied to the gate 104, the current flows from the gate 104 to the doped region 105. Since the distance between the doped region 105 and the gate 104 is relatively short, the resistance on the carrier movement path can be reduced, thereby increasing the breakdown current and making it easier for the antifuse device to be broken down.

[0045] This specific embodiment of the present invention also provides a chip having the antifuse device described in the above specific embodiment. The chip includes a storage area and a peripheral area; a memory array formed in the storage area; and at least one antifuse device formed in the peripheral area. A memory array is formed in the storage area, and the memory array includes a main memory array and a redundant memory array. The memory cells in the main memory array are used to store data. When a certain memory cell in the memory array fails, the failed memory cell will be unable to store data or the stored data will be incorrect, resulting in a storage defect in the memory. The redundant memory cells in the redundant memory array are used to replace the failed memory cells in the main memory array for data storage.

[0046] The at least one antifuse device forms a non-volatile programmable module. By performing a breakdown operation on the fuse device, the state of the corresponding antifuse device can be changed to program the programmable module. By programming the programmable module, information related to the failed memory cells in the main memory array can be recorded. For example, information related to the address of the failed memory cells can be recorded; or information related to the redundant memory cells used to replace the failed memory cells for data storage can be recorded. For example, it can be information related to the address of the redundant memory cells. After the chip is powered on, it can first read the information recorded in the programmable module to obtain information related to the failed memory cells and the redundant memory cells, and then perform data storage or reading operations, thereby repairing the storage defect caused by the failed memory cells.

[0047] During the programming process of the anti-fuse device in the specific embodiment of the present invention, the resistance when breaking through the gate dielectric layer is small. Under the same programming voltage, a larger programming current can be formed. Therefore, the programming voltage can be appropriately reduced, the power consumption can be reduced, and the programming efficiency can be improved.

[0048] Please refer to Figures 5 to 8 It is a schematic structural diagram of the formation process of a chip according to a specific embodiment of the present invention.

[0049] Please refer to Figure 5 , a substrate 200 is provided, and the substrate 200 includes a storage area II and a peripheral area I.

[0050] The chip can be a memory chip, and the memory can be various types of memories such as SRAM memory, DRAM memory, or MRAM memory. In this specific embodiment, the chip is a DRAM memory chip.

[0051] The storage area II of the substrate 200 is used to form a storage array, and the storage array includes a main storage array and a redundant storage array. The redundant storage units in the redundant storage array are used to store data instead of the failed storage units when the storage units in the main storage array fail.

[0052] The peripheral area I is used to form a peripheral control circuit. In this specific embodiment, the peripheral area I is used to form an anti-fuse device, and the anti-fuse device is used to repair the memory. Other peripheral transistors for forming the peripheral control circuit are also formed on the peripheral area I.

[0053] A shallow trench isolation structure 201 is also formed in the substrate 200 as an isolation structure between active regions. The anti-fuse device, peripheral circuit transistors, and storage array are all formed on the active regions.

[0054] In this specific embodiment, two word lines 211 of the storage unit and a gate dielectric layer 212 between the word lines and the substrate 200 are formed in the active region of the storage area II of the substrate 200. The word lines 211 are buried in the active region of the storage area II and cross the active region. A drain 214 is also formed between adjacent word lines 211 in the storage area II, and two source electrodes 213 are formed on the other side of the word lines 211.

[0055] In other specific embodiments, storage units with other structures can also be formed in the storage area II. Before forming the bit lines of the storage array, other semiconductor device structures can also be formed in the storage area II.

[0056] Please refer to Figure 6, the gate 222 of the antifuse device and the gate 232 of the peripheral transistor are formed in the peripheral region I, and the bit line 215 of the memory array is formed in the memory region II.

[0057] Before specifically forming the gate 232 and the gate 222, it further includes forming a gate dielectric material layer covering the surface of the peripheral region I.

[0058] In this specific embodiment, the gate 232, the gate 222, and the bit line 215 are formed simultaneously, specifically including: forming a gate material layer on the peripheral region I and the memory region II, and patterning the gate material layer to respectively form the gate 232, the gate 222, and the bit line 215. While forming the gate 232 and the gate 222, the gate dielectric material layer is etched to form a gate dielectric layer 231 under the gate 232 and a gate dielectric layer 221 under the gate 222. The bit line 215 is located on the surface of the drain 214.

[0059] The gate dielectric layer 221 and the gate 222 cover part of the active region and part of the isolation region 201, and only part of the active region for forming the antifuse device is exposed on one side of the gate 222.

[0060] In other specific embodiments, the gate on the peripheral region I and the bit line on the memory region II can also be formed separately.

[0061] After forming the gate 232 and the gate 222, the peripheral region I can be lightly doped with ions using the gate 232 and the gate 222 as masks to form the lightly doped region 233 of the peripheral circuit transistor, and at the same time, a lightly doped region 223 is also formed on one side of the gate 222. During the process of the lightly doped ion implantation, a protective layer can also be formed on the memory region II to prevent ion implantation into the active region of the memory region II.

[0062] Please refer to Figure 7 , sidewalls 224 are formed on both sides of the gate 222 of the antifuse device, sidewalls 234 are formed on both sides of the gate 232 of the peripheral circuit transistor, and sidewalls 216 are formed on both sides of the bit line 215.

[0063] The sidewall 234, sidewall 224, and sidewall 216 are formed simultaneously. The specific method includes: forming a sidewall material layer covering the peripheral region I and the storage region II, where the sidewall material layer covers the tops and sidewalls of the gate 222, gate 232, and bit line 215; using a maskless etching process to etch the sidewall material layer and remove the sidewall material layer located on the tops of the gate 222, gate 232, and bit line 215 and on the surface of the substrate 200, thereby forming the sidewall 224 covering the sidewall of the gate 222, the sidewall 234 covering the sidewall of the gate 232, and the sidewall 215 covering the sidewall of the bit line 215. Forming each sidewall simultaneously is conducive to reducing process steps.

[0064] Please refer to Figure 8 , and simultaneously remove the sidewalls 216 and 224 on both sides of the bit line 215 and the gate 222 of the antifuse device (please refer to Figure 7 ).

[0065] Since a capacitor connecting the source 213 needs to be formed above the storage region II subsequently, an electrical connection portion needs to be formed on the surface of the source 213 to connect the lower electrode of the capacitor. Therefore, sufficient lateral space needs to be left on the surface of the source 213, and thus, the sidewalls on both sides of the bit line 215 need to be removed. In this specific embodiment, when removing the sidewalls 216 on both sides of the bit line 215, the sidewalls 224 on both sides of the gate 222 of the antifuse device are removed simultaneously without adding additional process steps.

[0066] The method for removing the sidewall 216 and the sidewall 224 includes: covering a mask layer on the storage region II and the peripheral region I, using the same mask plate to pattern the mask layer on the storage region II and the peripheral region I, exposing the gate 222 of the antifuse device and the sidewalls 224 on both sides thereof, as well as the bit line 215 in the storage region and the sidewalls 216 on both sides thereof; then using an anisotropic or isotropic etching process to remove the sidewall 216 and the sidewall 224 simultaneously.

[0067] Please refer to Figure 9 , using the gate 232 and the sidewalls 234 on both sides thereof and the gate 222 as masks, performing heavy doping ion implantation on the peripheral region I to form the source / drain 235 of the peripheral circuit transistor and the doping region 225 of the antifuse device. At least part of the edge of the doping region 225 is aligned with the edge of the gate 222 or is located below the gate 222.

[0068] Before the heavy-doped ion implantation is performed, the spacers on both sides of the gate 222 of the antifuse device are removed. Therefore, the formed doped region 225 completely replaces the lightly doped region 233 formed in the previous step, shortening the distance between the doped region 225 and the gate 222, reducing the resistance on the breakdown current path, and making the formed antifuse device more easily broken down.

[0069] During the formation process of the above-mentioned memory, the spacers on both sides of the gate 222 of the antifuse device and the spacers 216 on both sides of the bit line 215 are removed simultaneously. Therefore, no additional process steps are required, and no additional ion implantation is needed for the active region under the gate 222 of the antifuse device to reduce the resistance on the breakdown circuit path, thus saving process steps and making the antifuse device more easily broken down.

[0070] In another specific embodiment, it is also possible to perform a lightly doped ion implantation on the substrate on both sides of the gate of the peripheral region after forming the gate of the antifuse device, the gates of the peripheral circuit transistors, and the bit lines of the memory array; then form spacers only on both sides of the peripheral circuit transistors; and then use the gates of the peripheral circuit transistors and the spacers on both sides, and the gate of the antifuse device as masks to perform a heavy-doped ion implantation on the substrate of the peripheral region to form the source / drain regions and the doped region of the antifuse device. Since spacers are only formed on both sides of the gates of the peripheral circuit transistors, the step of removing the spacers on both sides of the gate of the antifuse device and the bit lines is no longer required, thus further saving process steps.

[0071] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A chip, characterized in that, Comprising: A substrate, the substrate including a storage area and a peripheral area; A memory array formed within the storage area; At least one antifuse device formed within the peripheral area, the antifuse device being configured to repair storage defects caused by failed memory cells within the memory array; The antifuse device comprising: A gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectric layer; A doped region within the substrate on one side of the gate structure in a direction parallel to the surface of the substrate; The antifuse device adopts a MOS structure, and the doped region is directly formed using the gate structure as a mask, such that at least a portion of the edge of the doped region is aligned with the edge of the gate or is located below the gate; the substrate of the peripheral area includes an active region and an isolation region surrounding the active region; the gate structure covers a portion of the active region and a portion of the isolation region, only exposing a portion of the active region located on one side of the gate.

2. The chip according to claim 1, wherein The memory array includes: a main memory array and a redundant memory array, and redundant memory cells within the redundant memory array are used to replace failed memory cells within the main memory array for data storage; the at least one antifuse device constitutes a programmable module for recording information of failed memory cells within the main memory array or / and redundant memory cells within the redundant memory array.

3. The chip according to claim 1, characterized in that, A doped well is formed within the substrate under the gate structure of the antifuse device, and the doping type of the doped well is opposite to that of the doped region.

4. A method for forming a chip, characterized in that, Comprising: Providing a substrate, the substrate including a storage area and a peripheral area; Forming a memory array within the storage area; Forming at least one antifuse device within the peripheral area, the antifuse device including: a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectric layer; a doped region within the substrate on one side of the gate structure in a direction parallel to the surface of the substrate, at least a portion of the edge of the doped region being aligned with the edge of the gate or being located below the gate; forming peripheral circuit transistors within the peripheral area; The forming method of the peripheral circuit transistors, antifuse devices, and memory array includes: forming the gate of the antifuse device, the gate of the peripheral circuit transistors, and the bit lines of the memory array within the peripheral area; simultaneously forming sidewalls on both sides of the gate of the antifuse device, the gate of the peripheral circuit transistors, and the bit lines; using the same mask to simultaneously remove the sidewalls on both sides of the bit lines and the gate of the antifuse device; The forming method of the peripheral circuit transistors, antifuse devices, and memory array further includes: before forming the sidewalls, performing a light doping ion implantation on the substrate on both sides of the gate within the peripheral area; after removing the sidewalls on both sides of the gate of the antifuse device, using the gate of the peripheral circuit transistors and the sidewalls on both sides thereof, and the gate of the antifuse device as a mask, performing a heavy doping ion implantation on the substrate within the peripheral area to form the source / drain electrodes of the peripheral circuit transistors and the doped region of the antifuse device.

5. The method for forming a chip according to claim 4, wherein The gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the memory array are formed simultaneously.

6. The method for forming a chip according to claim 4, wherein The method for forming the peripheral circuit transistor, the antifuse device, and the memory array includes: forming the gate of the antifuse device, the gate of the peripheral circuit transistor, and the bit line of the memory array; performing light doping ion implantation on the substrate on both sides of the gate in the peripheral region; forming sidewalls on both sides of the peripheral circuit transistor; using the gate of the peripheral circuit transistor, the sidewalls on both sides, and the gate of the antifuse device as masks to perform heavy doping ion implantation on the substrate in the peripheral region to form the source / drain of the peripheral circuit transistor and the doped region of the antifuse device.

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