semiconductor packaging

Abstract

A semiconductor package includes: a package substrate; a lower semiconductor chip located on the package substrate; an intermediate layer located on the lower semiconductor chip, the intermediate layer including a plurality of segments spaced apart from each other; an upper semiconductor chip located on the intermediate layer; and a molding member covering the lower semiconductor chip and the intermediate layer.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] The entire text of Korean Patent Application No. 10-2019-0043784, entitled “Semiconductor Package,” filed in the Korean Intellectual Property Office on April 15, 2019, is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor package including an intermediate layer. Background Art

[0004] Recently, the demand for portable devices in the electronic product market has rapidly increased. Therefore, there is a continuous demand for miniaturization and weight reduction of electronic components in electronic products.

[0005] Semiconductor packages including such electronic components are needed to process large amounts of data while reducing the size of such electronic components. Consequently, there is also a need for highly integrated, single-package semiconductor chips mounted on such semiconductor packages. Therefore, interlayers have been used to efficiently arrange semiconductor chips within the limited structure of semiconductor packages. Summary of the Invention

[0006] According to an aspect of an embodiment, a semiconductor package is provided, comprising: a package substrate; a lower semiconductor chip disposed on the package substrate; an intermediate layer disposed on the lower semiconductor chip and comprising a plurality of segments spaced apart from each other; an upper semiconductor chip disposed on the intermediate layer; and a molding member covering the lower semiconductor chip and the intermediate layer.

[0007] According to an aspect of an embodiment, a semiconductor package is provided, comprising: a package substrate; a lower semiconductor chip disposed on the package substrate; an intermediate layer disposed on the lower semiconductor chip and divided into a plurality of regions by grooves formed in an upper surface of the intermediate layer; an upper semiconductor chip disposed on the intermediate layer; bonding wires connecting the package substrate to the intermediate layer; and a molding member covering the lower semiconductor chip, the intermediate layer, and the bonding wires, wherein a thermal expansion coefficient of the molding member is greater than a thermal expansion coefficient of the intermediate layer.

[0008] According to an aspect of an embodiment, a semiconductor package is provided, comprising: a package substrate; a lower semiconductor chip disposed on the package substrate; an intermediate layer disposed on the lower semiconductor chip and divided into a plurality of regions by grooves formed in side surfaces of the intermediate layer; an upper semiconductor chip disposed on the intermediate layer; bonding wires connecting the package substrate to the intermediate layer; and a molding member covering the lower semiconductor chip, the intermediate layer, and the bonding wires, wherein a thermal expansion coefficient of the molding member is greater than a thermal expansion coefficient of the intermediate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1A to 1D Diagrams illustrating semiconductor packages according to exemplary embodiments.

[0011] Figures 2A to 9B Diagrams illustrating semiconductor packages according to exemplary embodiments.

[0012] Figure 10 A flowchart illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0013] Figures 11A to 11E Cross-sectional views illustrating various stages in a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0014] Figure 12 A schematic diagram illustrating a semiconductor module including a semiconductor package according to an exemplary embodiment is shown.

[0015] Figure 13 A schematic diagram illustrating a system for semiconductor packaging according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0016] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0017] Figures 1A to 1D is a diagram showing a semiconductor package according to an exemplary embodiment. Specifically, Figure 1A is a cross-sectional view of the semiconductor package 10, Figure 1B is a plan view of the semiconductor package 10, Figure 1C is a perspective view of the intermediate layer 300 in the semiconductor package 10, and Figure 1D FIG. 4 is a bottom view of the upper semiconductor chip 400 in the semiconductor package 10 .

[0018] For ease of explanation, Figure 1BThe molding member MB and the upper semiconductor chip 400 are omitted to show the top view of the intermediate layer 300 on the lower semiconductor chip 200. In addition, for convenience, only the upper semiconductor chip 400 is shown in FIG. Figure 1B and Figure 1C 3. In FIG. 3, the redistribution layer structure 320 is shown on a single segment of the intermediate layer 300, and the redistribution layer structure 320 may be formed on each segment of the intermediate layer 300 (eg, Figure 1A ).also, Figure 1A The cross section of FIG reflects a cross section through elements 321 and 325 in two adjacent segments of the intermediate layer 300 and is, for convenience, shown from FIG. Figure 1A The element 323 connecting the elements 321 and 325 is omitted.

[0019] Reference Figures 1A to 1D The semiconductor package 10 may include: a package substrate 100; a lower semiconductor chip 200 located on the package substrate 100; an intermediate layer 300 located on the lower semiconductor chip 200; and an upper semiconductor chip 400 located on the intermediate layer 300. The intermediate layer 300 may include a plurality of segments (i.e., a plurality of portions spaced apart from each other (e.g., Figure 1C )), as will be explained in more detail below.

[0020] Specifically, the package substrate 100 may be a supporting substrate. For example, the package substrate 100 may include a main body 110, a lower protective layer, and an upper protective layer. The package substrate 100 may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, or the like. For example, in the semiconductor package 10, the package substrate 100 may be a PCB.

[0021] A wiring 140 may be formed in the package substrate 100. The wiring 140 may be electrically connected to the lower semiconductor chip 200 through, for example, at least one of a pillar structure, a solder bump, a solder ball, and a solder layer connected to an upper electrode pad 120 formed in the upper surface of the package substrate 100.

[0022] In addition, external connection terminals 150 may be provided on the lower electrode pads 130 formed in the lower surface of the package substrate 100. The package substrate 100 may be electrically connected to a module substrate or a system board of an electronic product through the external connection terminals 150.

[0023] For example, multiple layers or a single layer of wiring 140 may be formed in the body portion 110, and the external connection terminals 150 may be electrically connected to the lower semiconductor chip 200 through the wiring 140. The lower and upper protective layers may protect the body portion 110 and may include, for example, solder resist.

[0024] When package substrate 100 is a PCB, body portion 110 may include a thermosetting polymer. For example, body portion 110 may be formed by compressing a polymer material (e.g., thermosetting resin, epoxy resin (e.g., flame retardant 4 (FR-4), bismaleimide triazine (BT), Ajinomoto buildup film (ABF)), or phenolic resin) to a predetermined thickness to thin it, applying copper foil to both sides of the polymer material, and forming wiring 140 as a path for electrical signal transmission through a patterning process. In addition to upper electrode pad 120 and lower electrode pad 130, solder resist may be applied to the entire lower and upper surfaces of body portion 110 to form a lower protective layer and an upper protective layer. Due to characteristics of the material constituting the package substrate 100 (eg, due to the thermosetting polymer used in the body portion 110 of the package substrate 100 ), the thermal expansion coefficient of the package substrate 100 may be relatively large compared to that of a comparative semiconductor substrate.

[0025] Generally speaking, PCBs can be classified into single-layer PCBs having wiring 140 formed only on one side and double-layer PCBs having wiring 140 formed on both sides. For example, by using an insulator (e.g., prepreg), the number of copper foil layers can be three or more, and a PCB having a multi-layer structure can be implemented by forming three or more wirings 140 according to the number of copper foil layers to be formed. However, the package substrate 100 is not limited to the above-mentioned printed circuit board structures and materials.

[0026] The lower semiconductor chip 200 may be implemented as a single logic chip (eg, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, a system on chip, etc.) However, the lower semiconductor chip 200 is not limited thereto.

[0027] In addition, the lower semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 formed in a lower surface of the semiconductor substrate 210. The chip pad 220 may be connected to a logic device of the lower semiconductor chip 200 through a wiring structure.

[0028] The semiconductor substrate 210 constituting the lower semiconductor chip 200 may have an active surface and an inactive surface opposite the active surface. The active surface of the semiconductor substrate 210 may be a surface facing the upper surface of the package substrate 100. A plurality of active devices and / or passive devices may be formed on the active surface of the semiconductor substrate 210. In addition, a chip pad 220 may be formed on the active surface of the semiconductor substrate 210.

[0029] The chip pads 220 can be directly connected to the upper electrode pads 120 provided in the upper surface of the package substrate 100 through the connection terminals 230. The chip pads 220 and the upper electrode pads 120 can be used as terminals for signal transmission between the lower semiconductor chip 200 and the package substrate 100. The number of the chip pads 220 and the upper electrode pads 120 and the arrangement of the chip pads 220 and the upper electrode pads 120 are shown by way of example and are not limited thereto.

[0030] The connection terminals 230 may be provided on the chip pads 220. The connection terminals 230 may electrically connect the lower semiconductor chip 200 to the package substrate 100. Through the connection terminals 230, at least one of a control signal, a power supply signal, and a ground signal for operating the lower semiconductor chip 200 may be externally provided, a data signal to be stored in the lower semiconductor chip 200 may be externally provided, or data stored in the lower semiconductor chip 200 may be externally provided. For example, the connection terminals 230 may be flip-chip connections, e.g., the connection terminals 230 may include at least one of a pillar structure, a solder bump, a solder ball, and a solder layer.

[0031] For example, the semiconductor substrate 210 may include a silicon wafer containing silicon (Si) (e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon). In another example, the semiconductor substrate 210 may include a semiconductor element (e.g., germanium) or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). In the semiconductor package 10 according to an embodiment, the semiconductor substrate 210 may be a silicon wafer. The silicon wafer may have a relatively small thermal expansion coefficient of approximately 7.6 ppm / K compared to the thermal expansion coefficient of the package substrate 100.

[0032] The semiconductor substrate 210 may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate 210 may include a buried oxide (BOX) layer. The semiconductor substrate 210 may include a conductive region (e.g., an impurity-doped well or an impurity-doped structure). In addition, the semiconductor substrate 210 may have various device isolation structures (e.g., a shallow trench isolation (STI) structure).

[0033] The intermediate layer 300 may be located between the lower semiconductor chip 200 and the upper semiconductor chip 400. For example, the intermediate layer 300 may be located on the inactive surface of the semiconductor substrate 210 of the lower semiconductor chip 200. The intermediate layer 300 may include a base substrate 310 and a redistribution layer structure 320 formed in the base substrate 310. For example, Figure 1AAs shown, the redistribution layer structure 320 may be formed in the upper surface of the base substrate 310 to have an upper surface as high as the upper surface of the base substrate 310 .

[0034] The base substrate 310 may include a silicon wafer including silicon (Si) (e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon). In other words, both the base substrate 310 and the semiconductor substrate 210 may include a silicon wafer, and therefore, the thermal expansion coefficient of the base substrate 310 is relatively smaller than the thermal expansion coefficient of the package substrate 100.

[0035] Reference Figure 1A and Figure 1B The redistribution layer structure 320 may include an upper surface pad 321 electrically connected to the upper semiconductor chip 400, a bonding pad 325 electrically connected to the bonding wire BW, and a redistribution layer 323 electrically connecting the upper surface pad 321 to the bonding pad 325. For example, Figure 1B As shown, the redistribution layer structure 320 may include a plurality of upper surface pads 321, a plurality of bonding pads 325, and a plurality of redistribution layers 323 electrically connecting each upper surface pad 321 to a corresponding bonding pad 325. Here, the upper surface pads 321 may be formed to be exposed from the molding member MB, for example, a portion of the molding member MB may be removed to expose the upper surface of the upper surface pads 321. Although Figure 1B and Figure 1C The redistribution layer structure 320 is shown as being formed only on a single segment of the intermediate layer 300, however this is for the sake of explanation, and the redistribution layer structure 320 may also be formed in other segments of the intermediate layer 300, for example, Figure 1A Two adjacent segments or all segments of the intermediate layer 300 are shown.

[0036] For example, the middle layer 300 may further include a circuit region. For example, a buffer circuit capable of controlling the capacitive load of the upper semiconductor chip 400 may be formed in the circuit region of the middle layer 300. In some embodiments, the circuit region may include a semiconductor integrated circuit comprising at least one of the following: a transistor, a diode, a capacitor, and a resistor. In another example, the circuit region may be omitted.

[0037] In some embodiments, the intermediate layer 300 may be disposed in a region between the lower semiconductor chip 200 and the upper semiconductor chip 400 so as to overlap the lower semiconductor chip 200 and the upper semiconductor chip 400, respectively. Figure 1A For example, in a plan view, a portion of the intermediate layer 300 may overlap with the lower semiconductor chip 200, and the entire portion of the intermediate layer 300 may overlap with the upper semiconductor chip 400 ( Figure 1AFor example, in a plan view, the outermost edge of the intermediate layer 300 may extend beyond the edge of the lower semiconductor chip 200 ( Figure 1B ), and the edge of the upper semiconductor chip 400 may extend beyond the outermost edge of the intermediate layer 300 ( Figure 1A ).

[0038] like Figure 1B and Figure 1C As shown, according to an embodiment, the intermediate layer 300 may include a plurality of segments 300a. Figure 1B As shown, the intermediate layer 300 may include a plurality of discrete portions spaced apart from each other in the X and Y directions in a matrix pattern, for example. For example, in a plan view, the intermediate layer 300 may include 2N segments (N is a natural number), and the 2N segments (i.e., segments) may be arranged on the lower semiconductor chip 200 in a bilaterally symmetrical structure with spaces between the lower semiconductor chips 200. Therefore, a portion of the upper surface of the lower semiconductor chip 200 corresponding to the empty space formed between adjacent 2N segments (e.g., segments) (e.g., portions spaced apart from each other) may not overlap with the intermediate layer 300, that is, the lower semiconductor chip 200 may overlap with the empty space between the portions 300a of the intermediate layer 300 ( Figure 1B ).

[0039] Specifically, the segments 300a (i.e., portions 300a (segments 300a and portion 300a will be used interchangeably hereinafter)) of the intermediate layer 300 may be spaced apart from each other by a first distance DX in a first direction (i.e., the X direction) and spaced apart from each other by a second distance DY in a second direction (i.e., the Y direction). Each of the segments 300a (i.e., portions 300a) may be configured to have the same or different shapes and the same or different dimensions (e.g., area in the XY plane and thickness in the Z direction). The first distance DX and the second distance DY may also be configured to have the same or different lengths.

[0040] In the semiconductor package 10 according to the embodiment, since the intermediate layer 300 may include the plurality of segments 300a (ie, portions 300a), the spaces between the plurality of segments 300a (ie, portions 300a) may be filled with the molding member MB. Figures 1A to 1CThe intermediate layer 300 may include segments 300a arranged in rows and columns in the X and Y directions, for example, in a matrix pattern on the lower semiconductor chip 200, with portions of the molding member MB completely filling the spaces between adjacent segments 300a in the X and Y directions. Thus, the segments 300a of the intermediate layer 300 with portions of the molding member MB between them provide an intermediate layer composed of different materials with different coefficients of thermal expansion. As will be explained in more detail later, the coefficient of thermal expansion of the intermediate layer 300 may be different from (e.g., lower than) the coefficient of thermal expansion of the molding member MB.

[0041] The upper semiconductor chip 400 may be located on the intermediate layer 300 and include, for example, a volatile memory chip and / or a non-volatile memory chip. In another example, the upper semiconductor chip 400 may include a high-bandwidth memory chip. The volatile memory chip may include, for example, a dynamic random-access memory (DRAM), a static random access memory (SRAM), a thyristor random access memory (TRAM), a zero-capacitor random access memory (ZRAM), etc. The non-volatile memory chip may include, for example, a flash memory, a magnetic random access memory (MRAM), a spin-transfer torque random access memory (STT-MRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), etc.

[0042] In some embodiments, the upper semiconductor chip 400 may include a stack of multiple memory chips capable of merging data with each other. In this case, each memory chip slice constituting the upper semiconductor chip 400 may include a semiconductor substrate having an active surface and an inactive surface facing each other, a memory device formed on the active surface, and through silicon vias (TSVs). In a packaging system in which multiple memory chips are integrated into one package, the number of memory chip slices constituting the upper semiconductor chip 400 may vary depending on the purpose of the semiconductor package 10. That is, the number of memory chip slices constituting the upper semiconductor chip 400 is not limited to a specific number.

[0043] The upper semiconductor chip 400 may include a semiconductor substrate stack 410 and a chip pad 420 formed in a lowermost surface of the semiconductor substrate stack 410. The chip pad 420 may be connected to a memory device of the upper semiconductor chip 400 through a wiring structure.

[0044] The chip pads 420 can be directly connected to the upper surface pads 321 provided in the upper surface of the middle layer 300 through the connection terminals 430. The chip pads 420 and the upper surface pads 321 can be used as terminals for signal transmission between the upper semiconductor chip 400 and the middle layer 300. The number of the chip pads 420 and the upper surface pads 321 and their arrangement are shown by way of example only and are not limited thereto.

[0045] The connection terminals 430 may be provided on the chip pad 420. Due to the height of the connection terminals 430, the upper semiconductor chip 400 may be spaced apart from the molding member MB. The connection terminals 430 may electrically connect the upper semiconductor chip 400 to the intermediate layer 300. Through the connection terminals 430, at least one of a control signal, a power supply signal, and a ground signal for operating the upper semiconductor chip 400 may be externally supplied, a data signal to be stored in the upper semiconductor chip 400 may be externally supplied, or data stored in the upper semiconductor chip 400 may be provided to the outside.

[0046] In addition, the terminal area 400R ( Figure 1D ) is equal to the number of segments (i.e., portions) of the intermediate layer 300. In the terminal region 400R, the chip pads 420 are arranged in groups on the lower surface of the upper semiconductor chip 400 (i.e., the surface facing the intermediate layer 300). The terminal region 400R can be configured to correspond to (e.g., overlap) the region in which the segments of the intermediate layer 300 are disposed. For example, each terminal region 400R and the corresponding portion of the intermediate layer 300 have the same size and shape so as to completely overlap each other. That is, in the manufacturing process of the upper semiconductor chip 400, the chip pads 420 can be designed taking into account the redistribution layer structure 320 of the intermediate layer 300.

[0047] The adhesive member DAF may be configured to adhere to the lower semiconductor chip 200 and the intermediate layer 300. The adhesive member DAF may include a die attach film. Die attach films can be categorized into inorganic adhesives and polymer adhesives. Polymers can generally be categorized into thermosetting resins and thermoplastic resins, and hybrid polymers can be made by mixing these two components.

[0048] Bonding wires BW may electrically connect the package substrate 100 to the intermediate layer 300, for example, via bonding pads 325. The bonding wires BW may include, for example, at least one of gold (Au), silver (Ag), copper (Cu), and aluminum (Al). In some embodiments, the bonding wires BW may be connected using either a thermocompression connection method or an ultrasonic connection method, or may be connected using a thermosonic connection method that is a combination of these methods.

[0049] The molding member MB may protect the lower semiconductor chip 200 and the intermediate layer 300 from external influences (eg, contamination and impact). To implement such protection, the molding member MB may be formed to have a thickness that covers at least the lower semiconductor chip 200 and the intermediate layer 300.

[0050] For example, if Figure 1A As shown, the molding member MB may, for example, continuously extend from the upper surface of the body portion 110 of the package substrate 100 along, for example, the entire side surface of the lower semiconductor chip 200 and the intermediate layer 300 to a height higher than the upper surface of the intermediate layer 300 (relative to the bottom of the package substrate 100). For example, as Figure 1A As further shown, the molding member MB may extend along the entire side surface of each of the segments 300a of the intermediate layer 300 to, for example, completely fill the space between adjacent segments 300a of the segments 300a of the intermediate layer 300. For example, Figure 1A As further shown, the molding member MB may at least partially cover the upper surface of the middle layer 300. For example, the molding member MB may at least partially expose the upper surface of the upper surface pad 321 on the upper surface of the middle layer 300. The width of the molding member MB (for example, the distance between the outermost surfaces of the molding member MB along the X direction) may be substantially the same as the width of the semiconductor package 10, for example, along the X direction, because the molding member MB may cover the entirety of the package substrate 100.

[0051] For example, the molding member MB may include epoxy molding compound. The epoxy molding compound may have a thermal expansion coefficient of approximately 10 ppm / K to approximately 30 ppm / K. However, the molding member MB is not limited to epoxy molding compound and may include various materials, such as epoxy-based materials, thermosetting materials, thermoplastic materials, and ultraviolet (UV) curable materials.

[0052] For example, after an appropriate amount of molding material is injected onto the package substrate 100 through an injection process, the molding member MB can be formed into the outer shape of the semiconductor package 10 through a curing process. Optionally, the outer shape of the semiconductor package 10 can be formed by applying pressure to the molding material during a pressing process using a press. Process conditions (e.g., the delay time between injecting the molding material and pressing the molding material, the amount of molding material to be injected, the pressing temperature and pressure, etc.) can be set taking into account physical properties (e.g., the viscosity of the molding material, etc.). Depending on the molding material, the thermal expansion coefficient of the molding member MB may vary.

[0053] An underfill (UF) may be formed between the package substrate 100 and the lower semiconductor chip 200. During the electrical connection between the connection terminals 230 and the lower semiconductor chip 200, a gap may be formed between the package substrate 100 and the lower semiconductor chip 200. This gap may cause problems with the connection reliability between the lower semiconductor chip 200 and the package substrate 100, and therefore, an underfill (UF) may be injected to strengthen the connection. In some cases, a molded underfill (MUF) process may be used instead of the UF underfill.

[0054] A typical semiconductor package may include a package base, a semiconductor chip, an intermediate layer, a molding member, and the like. In such a typical semiconductor package, the materials constituting the package base, semiconductor chip, intermediate layer, and molding member may differ from one another, and each component may have a different coefficient of thermal expansion. Therefore, when temperature changes occur during the process of manufacturing the semiconductor package, each component may contract or expand differently from one another, causing deformation (e.g., warping) in the semiconductor package. This deformation of the semiconductor package is referred to as warping.

[0055] For example, in typical semiconductor packages, the package substrate, which has a relatively large coefficient of thermal expansion, may shrink at room temperature, exerting tensile stress on the semiconductor chip and the interlayers above it. Furthermore, at high temperatures, the package substrate, which has a relatively large coefficient of thermal expansion, may expand, exerting compressive stress on the semiconductor chip and the interlayers above it. Consequently, stress concentration caused by tensile or compressive stress may cause warping of the semiconductor package, thereby reducing the productivity and reliability of the semiconductor package.

[0056] In contrast, according to embodiments, the semiconductor package 10 includes an intermediate layer 300 having a plurality of segments 300a (i.e., portions 300a) spaced apart from one another, with the molding member MB interposed between the segments 300a. This reduces warping of the semiconductor package 10. Specifically, components with a large coefficient of thermal expansion (i.e., portions of the molding member MB) and components with a small coefficient of thermal expansion (i.e., segments 300a of the intermediate layer 300) can be appropriately (e.g., alternately) arranged on the same plane, thereby reducing warping of the semiconductor package 10.

[0057] Specifically, when the package substrate 100, which has a relatively large coefficient of thermal expansion, contracts at room temperature, the molding member MB, which also has a large coefficient of thermal expansion and fills the spaces between the segments 300 a of the intermediate layer 300 , also contracts. Consequently, the overall structure of the alternating segments 300 a in the intermediate layer 300 and portions of the molding member MB may contract. Specifically, the shrinkage of the molding member MB reduces the spaces between adjacent segments 300 a, thereby eliminating tensile stress on the lower semiconductor chip 200 and the intermediate layer 300. Consequently, warping of the semiconductor package 10 may be reduced.

[0058] Similarly, when the package substrate 100, which has a relatively large coefficient of thermal expansion, expands at high temperatures, the molding member MB, which also has a large coefficient of thermal expansion and fills the spaces between the segments 300 a of the intermediate layer 300 , also expands. Consequently, the overall structure of alternating segments 300 a in the intermediate layer 300 and portions of the molding member MB expands. Specifically, the expansion of the molding member MB results in larger spaces between adjacent segments 300 a, thereby relieving compressive stress on the lower semiconductor chip 200 and the intermediate layer 300 . Consequently, warping of the semiconductor package 10 can be reduced.

[0059] Therefore, the semiconductor package 10 according to the embodiment can minimize stress concentration caused by warpage, thereby improving productivity and reliability of the semiconductor package 10.

[0060] Figures 2A to 9B 1 is a diagram showing a semiconductor package according to an exemplary embodiment. Figures 1A to 1D Therefore, for ease of explanation, only the components and materials described above with respect to the semiconductor package 10 (see Figure 1A ) is different.

[0061] Reference Figure 2A and Figure 2B , Figure 2A is a cross-sectional view of the semiconductor package 20, and Figure 2Bis a plan view of the semiconductor package 20. For ease of explanation, Figure 2B The molding member MB and the upper semiconductor chip 400 are omitted.

[0062] like Figure 2A and Figure 2B As shown together, the semiconductor package 20 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 302 including a plurality of segments spaced apart from each other, an upper semiconductor chip 400, and first and second bonding wires BW1 and BW2. The first bonding wires BW1 may electrically connect the package substrate 100 to the intermediate layer 302, and the second bonding wires BW2 may electrically connect the segments of the intermediate layer 302 to each other.

[0063] Specifically, a second bonding pad 327 may be provided on each segment of the intermediate layer 302, and second bonding wires BW2 may be formed to connect the second bonding pads 327 of adjacent segments of the intermediate layer 302. The second bonding wires BW2 can electrically connect the multiple segments of the intermediate layer 302 to each other to implement various wiring designs for signal transmission with the upper semiconductor chip 400. The number of second bonding pads 327 and second bonding wires BW2, and the arrangement of the second bonding pads 327 and second bonding wires BW2 are shown for illustrative purposes only and are not intended to be limiting.

[0064] Reference Figure 3A and Figure 3B , Figure 3A is a cross-sectional view of the semiconductor package 30, and Figure 3B is a plan view of the semiconductor package 30. For ease of explanation, Figure 3B The molding member MB and the upper semiconductor chip 400 are omitted.

[0065] like Figure 3A and Figure 3B As shown together, the semiconductor package 30 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 303 consisting of two segments, and an upper semiconductor chip 400. In the semiconductor package 30, the intermediate layer 303 may be divided into, for example, only two segments. That is, the intermediate layer 303 may still include 2N segments (N is 1), and the two segments may be arranged in a symmetrical structure in a plan view.

[0066] In addition, the intermediate layer 303 may be configured such that the two segments are arranged to be spaced apart from each other by a second distance DY in the second direction (Y direction).The two segments may be configured to have the same area or different areas.

[0067] Furthermore, a second redistribution layer 329 may be formed on the intermediate layer 303 to implement various wiring designs for signal transmission with the upper semiconductor chip 400. The number of the second redistribution layers 329 and the arrangement of the second redistribution layers 329 are illustrative and not limiting.

[0068] Reference Figure 4A and Figure 4B , Figure 4A is a cross-sectional view of the semiconductor package 40, and Figure 4B is a plan view of the semiconductor package 40. For ease of explanation, Figure 4B The first molding member MB1 and the upper semiconductor chip 400 are omitted.

[0069] like Figure 4A and Figure 4B As shown together, the semiconductor package 40 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 304 including a plurality of segments, an upper semiconductor chip 400, and a first molding member MB1 and a second molding member MB2. The first molding member MB1 may be formed, for example, only on the lower semiconductor chip 200 and the outer portion of the intermediate layer 304. The second molding member MB2 may be formed in the space between the plurality of segments of the intermediate layer 304 ( Figure 4A and Figure 4B ).

[0070] Specifically, in the semiconductor package 40, the molding member may include at least two portions having different coefficients of thermal expansion. In some embodiments, the semiconductor package 40 may include a first molding member MB1 and a second molding member MB2 having different coefficients of thermal expansion. For example, the coefficient of thermal expansion of the first molding member MB1 may be smaller than the coefficient of thermal expansion of the second molding member MB2. In other words, by taking into account the coefficients of thermal expansion of the first molding member MB1 and the second molding member MB2, the tensile and compressive stresses applied to the semiconductor package 40 can be effectively controlled to minimize warpage.

[0071] Reference Figure 5A and Figure 5B , Figure 5A is a cross-sectional view of the semiconductor package 50, and Figure 5B is a plan view of a semiconductor package 50. For ease of explanation, Figure 5B The first molding member MB1 and the upper semiconductor chip 400 are omitted.

[0072] like Figure 5A and Figure 5BAs shown, the semiconductor package 50 may include a package substrate 100 , a lower semiconductor chip 200 , an intermediate layer 305 including a plurality of segments, an upper semiconductor chip 400 , a first molding member MB1 , and third and fourth molding members MB3 and MB4 filling spaces between the segments of the intermediate layer 305 .

[0073] In detail, the semiconductor package 50 may include third and fourth molding members MB3 and MB4 formed in the space between the segments of the intermediate layer 305 , and a first molding member MB1 formed on the lower semiconductor chip 200 and outer portions of the intermediate layer 305 .

[0074] The third molding member MB3 may include a conductive material. For example, the third molding member MB3 may include a metal (e.g., copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), and combinations thereof), a metal paste containing the metal, or a metal tape containing the metal. The third molding member MB3 may be used to dissipate heat generated in the lower semiconductor chip 200.

[0075] The fourth molding member MB4 may include an insulating material. That is, the fourth molding member MB4 may prevent a short circuit between the third molding member MB3 and the intermediate layer 305 .

[0076] Furthermore, in the semiconductor package 50, the molding member may include at least three portions having different coefficients of thermal expansion. In some embodiments, the semiconductor package 50 may include a first molding member MB1, a third molding member MB3, and a fourth molding member MB4 having different coefficients of thermal expansion. That is, by taking into account the coefficients of thermal expansion of the first molding member MB1, the third molding member MB3, and the fourth molding member MB4, the tensile and compressive stresses applied to the semiconductor package 50 can be effectively controlled to minimize warpage.

[0077] Reference Figures 6A to 6C , Figure 6A is a cross-sectional view of a semiconductor package 60, Figure 6B is a plan view of the semiconductor package 60, and Figure 6C is a perspective view of the middle layer 306. For ease of explanation, Figure 6B The molding member MB and the upper semiconductor chip 400 are omitted.

[0078] like Figures 6A to 6C As shown together, the semiconductor package 60 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 306 divided into a plurality of regions by grooves 306G formed on side surfaces of the intermediate layer 306, and an upper semiconductor chip 400. That is, the plurality of regions of the intermediate layer 306 may be partially connected to each other while being only partially separated by the grooves 306G.

[0079] In detail, the semiconductor package 60 may include an intermediate layer 306, and the intermediate layer 306 is divided into a plurality of regions by grooves 306G formed on the side surface of the intermediate layer 306. The number of the grooves 306G may be 2N (N is a natural number), and the grooves 306G may be arranged to face each other in a plan view. In addition, one end of the groove 306G may intersect with the edge of the intermediate layer 306. For example, Figure 6C As shown, each of the grooves 306G may extend through the entire thickness of the intermediate layer 306, for example, along the Z direction. Figure 6C As further shown in FIG, each of the grooves 306G may extend only partially along the Y direction, for example, and thus the length of one groove 306G, for example, along the Y direction, may be smaller than the distance between two facing grooves 306G, for example, along the Y direction. Figure 6B As shown, a portion of the upper surface of the lower semiconductor chip 200 overlapping the groove 306G may be opened from the intermediate layer 306 , eg, the lower semiconductor chip 200 may be exposed through the groove 306G.

[0080] In the semiconductor package 60 , the intermediate layer 306 may include a groove 306G on a side surface, and the groove 306G may be filled with the molding member MB. The thermal expansion coefficient of the intermediate layer 306 may be different from the thermal expansion coefficient of the molding member MB.

[0081] Furthermore, a second redistribution layer 329 may be formed on the intermediate layer 306 to implement various wiring designs for signal transmission with the upper semiconductor chip 400. The number of second redistribution layers 329 and the arrangement of the second redistribution layers 329 are illustrative and not limiting.

[0082] Reference Figures 7A to 7C , Figure 7A is a cross-sectional view of a semiconductor package 70, Figure 7B is a plan view of the semiconductor package 70, and Figure 7C is a perspective view of the middle layer 307. For ease of explanation, Figure 7B The molding member MB and the upper semiconductor chip 400 are omitted.

[0083] like Figures 7A to 7C As shown, the semiconductor package 70 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 307 divided into a plurality of regions by grooves 307G formed on an upper surface of the intermediate layer 307, and an upper semiconductor chip 400. That is, the grooves 307G may only partially extend into the intermediate layer 307 along the Z direction.

[0084] In detail, the semiconductor package 70 may include an intermediate layer 307, and the intermediate layer 307 is divided into the plurality of regions by a groove 307G formed on the upper surface of the intermediate layer 307. The groove 307G may extend parallel to the edge of the intermediate layer 307, and the depth of the groove 307G may be greater than half the thickness of the intermediate layer 307, for example, along the Z direction. In addition, both ends of the groove 307G may be spaced apart from the edge of the intermediate layer 307.

[0085] For example, the groove 307G may be linear and continuous along the entire length of the groove 307G (eg, along the Y direction). Figure 7C In another example, the groove 307G may include a plurality of grooves, and at least two of the grooves 307G may be formed to intersect each other. That is, the plurality of grooves 307G may be formed, each extending in the first direction (X direction) and the second direction (Y direction).

[0086] In the semiconductor package 70 , the intermediate layer 307 may include a groove 307G on the upper surface, and the groove 307G may be filled with the molding member MB. The thermal expansion coefficient of the intermediate layer 307 may be different from the thermal expansion coefficient of the molding member MB.

[0087] The molding member MB may include a first molding member and a second molding member. That is, the molding member may include a second molding member filling the groove 307G and a first molding member formed on the outer portion of the lower semiconductor chip 200 and the intermediate layer 307, for example, as previously described with reference to Figure 4A and Figure 4B The thermal expansion coefficient of the first molding member and the thermal expansion coefficient of the second molding member may be different from each other.

[0088] Reference Figures 8A to 8C , Figure 8A is a cross-sectional view of a semiconductor package 80, Figure 8B is a plan view of the semiconductor package 80, and Figure 8C is a perspective view of the middle layer 308. For ease of explanation, Figure 8B The molding member MB and the upper semiconductor chip 400 are omitted.

[0089] like Figures 8A to 8C As shown, the semiconductor package 80 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 308 divided into a plurality of regions by grooves 308G formed on an upper surface of the intermediate layer 308, and an upper semiconductor chip 400. That is, the grooves 308G may only partially extend into the intermediate layer 308 along the Z direction.

[0090] Specifically, the semiconductor package 80 may include an intermediate layer 308, which is divided into the plurality of regions by a groove 308G formed on an upper surface of the intermediate layer 308. The groove 308G may extend parallel to an edge of the intermediate layer 308, and the depth of the groove 308G may be greater than half the thickness of the intermediate layer 308, for example, along the Z direction. Furthermore, one end of the groove 308G may intersect with an edge of the intermediate layer 308; for example, the length of the groove 308G along the Y direction may be equal to the length of the intermediate layer 308 along the Y direction.

[0091] For example, the groove 308G may be linear and continuous, for example, along the Y direction. In another example, the groove 308G may include a plurality of grooves, and at least two of the grooves 308G may be formed to intersect each other. In other words, the plurality of grooves 308G may be formed, each extending in the first direction (X direction) and the second direction (Y direction).

[0092] In the semiconductor package 80 , the intermediate layer 308 may include a groove 308G on the upper surface, and the groove 308G may be filled with the molding member MB. The thermal expansion coefficient of the intermediate layer 308 may be different from the thermal expansion coefficient of the molding member MB.

[0093] The molding member MB may include a second molding member filling the groove 308G and a first molding member formed on the lower semiconductor chip 200 and the outer portion of the intermediate layer 308. Thermal expansion coefficients of the first and second molding members may be different from each other.

[0094] Reference FIG. 9A to FIG. 9B , Figure 9A is a cross-sectional view of a semiconductor package 90, and Figure 9B is a plan view of a semiconductor package 90. For ease of explanation, Figure 9B The molding member MB and the upper semiconductor chip 400 are omitted.

[0095] like Figure 9A and Figure 9B As shown, semiconductor package 90 may include a package substrate 100, a lower semiconductor chip 200, an intermediate layer 300 including a plurality of segments, and an upper semiconductor chip 400. In addition, semiconductor package 90 may include a lower semiconductor chip 209 electrically connected to package substrate 100 via a third bonding wire BW3.

[0096] In the semiconductor package 90, the second adhesive member DAF2 may be adhered to the lower semiconductor chip 209 and the package substrate 100. The second adhesive member DAF2 may be substantially the same as the first adhesive member DAF 1. That is, the second adhesive member DAF2 may include a die attach film.

[0097] In the semiconductor package 90, the thickness of the first bonding member DAF1 may be formed to be greater than or equal to the thickness for looping the third bonding wire BW3 to prevent mechanical deformation of the third bonding wire BW3. That is, the level of the upper surface of the first bonding member DAF1 may be higher than the level of the uppermost surface of the third bonding wire BW3.

[0098] Figure 10 is a flowchart illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0099] Reference Figure 10 , a method S10 for manufacturing a semiconductor package may include: a first step S110 of preparing a package substrate; a second step S120 of mounting a lower semiconductor chip on the package substrate; a third step S130 of attaching an intermediate layer including a plurality of segments to the lower semiconductor chip; a fourth step S140 of forming bonding wires for connecting the package substrate to the intermediate layer and then forming a molding member; a fifth step S150 of mounting an upper semiconductor chip to the intermediate layer; and a sixth step S160 of forming external connection terminals on a lower portion of the package substrate.

[0100] The semiconductor package manufacturing method S10 may include the exemplary process steps S110 to S160 described above. If some embodiments are implemented in other ways, certain process steps may be performed in a different order than the above-described process steps. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order to the above-described order.

[0101] Will refer to Figures 11A to 11E The technical features of the first step S110 to the sixth step S160 are elaborated in detail. Figures 11A to 11E are cross-sectional views of various stages in a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0102] Reference Figure 11A , a package substrate 100 may be prepared. The package substrate 100 may include a main body portion 110 as a supporting substrate. The package substrate 100 may be a PCB. Wiring 140 may be formed on the package substrate 100, and the wiring 140 may be electrically connected to the upper electrode pad 120 on the upper surface of the package substrate 100 and the lower electrode pad 130 on the lower surface of the package substrate 100.

[0103] Reference Figure 11B , a lower semiconductor chip 200 may be mounted on the package substrate 100 .

[0104] The semiconductor substrate 210 constituting the lower semiconductor chip 200 may have an active surface and an inactive surface. The active surface of the semiconductor substrate 210 may be disposed to face the upper surface of the package substrate 100. A chip pad 220 may be formed on the active surface of the semiconductor substrate 210.

[0105] The chip pad 220 may be directly connected to the upper electrode pad 120 disposed on the upper surface of the package substrate 100 through the connection terminal 230. The chip pad 220 and the upper electrode pad 120 may be used as terminals for signal transmission between the lower semiconductor chip 200 and the package substrate 100.

[0106] Reference Figure 11C , an intermediate layer 300 including a plurality of segments may be attached to the lower semiconductor chip 200. The intermediate layer 300 may be attached to the upper surface of the lower semiconductor chip 200 using an adhesive member DAF. For example, each segment (i.e., portion) of the intermediate layer 300 may be attached to a different portion of the lower semiconductor chip 200 using a separate adhesive member DAF so that the plurality of segments of the intermediate layer 300 may be spaced apart from each other by a predetermined distance on the lower semiconductor chip 200 to define rows and columns on the lower semiconductor chip 200.

[0107] In a plan view, a portion of the intermediate layer 300 may overlap with the lower semiconductor chip 200. For example, each of the plurality of segments of the intermediate layer 300 may overlap with a portion of the lower semiconductor chip 200. In addition, the outermost edge of the intermediate layer 300 may protrude beyond the edge of the lower semiconductor chip 200 in a horizontal direction. For example, at least some of the plurality of segments of the intermediate layer 300 may extend beyond the edge of the lower semiconductor chip 200 to overhang the edge of the lower semiconductor chip 200.

[0108] Reference Figure 11D After forming bonding wires BW for connecting the package substrate 100 and the middle layer 300, a molding member MB may be formed to cover the lower semiconductor chip 200, the middle layer 300, and the bonding wires BW. A portion of the molding member MB may, for example, completely fill the space between adjacent segments of the middle layer 300.

[0109] In detail, the bonding wires BW may electrically connect the package substrate 100 to the intermediate layer 300. After forming the bonding wires BW, an appropriate amount of molding material may be injected onto the package substrate 100, and the molding member MB may be formed through a curing process of the molding material.

[0110] A photolithography process and an etching process may be performed to form the opening MBH for opening the upper surface pad of the redistribution layer structure 320 of the intermediate layer 300. The photolithography process and the etching process may be performed according to any convenient process.

[0111] Reference Figure 11E , an upper semiconductor chip 400 may be mounted on the intermediate layer 300. The upper semiconductor chip 400 may include a semiconductor substrate stack 410 and a chip pad 420 formed on the lowermost surface of the semiconductor substrate stack 410.

[0112] The chip pad 420 may be directly connected to the redistribution layer structure 320 disposed in the upper surface of the intermediate layer 300 through the connection terminal 430. The chip pad 420 and the redistribution layer structure 320 may be used as terminals for signal transmission between the upper semiconductor chip 400 and the intermediate layer 300.

[0113] Refer again Figure 1A , the semiconductor package 10 according to the embodiment may be completed by forming the external connection terminals 150 on the lower portion of the package substrate 100 .

[0114] Figure 12 is a schematic diagram illustrating a semiconductor module including a semiconductor package according to an exemplary embodiment.

[0115] Reference Figure 12 The semiconductor module 1000 may include a module substrate 1010, a control chip 1020 mounted on the module substrate 1010, and a plurality of semiconductor packages 1030 mounted on the module substrate 1010. A plurality of input / output terminals 1050 that can be inserted into a socket of a mainboard may be provided on one side of the module substrate 1010. The plurality of semiconductor packages 1030 may include a reference Figures 1A to 9B Any one of the semiconductor packages 10 to 90 according to the embodiments is illustrated.

[0116] Figure 13 is a schematic diagram illustrating a system of semiconductor packaging according to an exemplary embodiment.

[0117] Reference Figure 13 , the system 1100 may include a controller 1110 , an input / output device 1120 , a memory 1130 , an interface 1140 , and a bus 1150 .

[0118] System 1100 may be a mobile system or a system for sending or receiving information. In some embodiments, the mobile system may include, for example, a portable computer, a web tablet computer, a mobile phone, a digital music player, or a memory card.

[0119] The controller 1110 may be used to control the execution programs in the system 1100 and may include, for example, a microprocessor, a digital signal processor, a microcontroller, etc.

[0120] The input / output device 1120 can be used to input or output data of the system 1100. The system 1100 can be connected to an external device (such as a personal computer or a network) using the input / output device 1120 and can exchange data with the external device. The input / output device 1120 may include, for example, a touch pad, a keyboard, or a display.

[0121] The memory 1130 may store data used for the operation of the controller 1110 or may store data processed by the controller 1110. The memory 1130 may include a reference Figures 1A to 9B Any one of the semiconductor packages 10 to 90 according to the embodiments is illustrated.

[0122] The interface 1140 may be a data transmission path between the system 1100 and external devices. The controller 1110 , the input / output device 1120 , the memory 1130 , and the interface 1140 may communicate with each other through a bus 1150 .

[0123] In summary and review, embodiments provide a semiconductor package that utilizes an interlayer to effectively arrange semiconductor chips within a limited structure of the semiconductor package while simultaneously controlling warpage. Specifically, embodiments provide a semiconductor package including an interlayer having a plurality of segments and a molding member that fills spaces between the segments to mitigate warpage.

[0124] Exemplary embodiments have been disclosed herein, and although specific terms are employed, these terms are intended to be construed in a generic and illustrative sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Accordingly, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A semiconductor package comprising: packaging substrate; a lower semiconductor chip, located on the packaging substrate; an intermediate layer located on the lower semiconductor chip, the intermediate layer including a plurality of segments spaced apart from each other; an upper semiconductor chip located on the intermediate layer; as well as a molding member covering the lower semiconductor chip and the intermediate layer, wherein the molding member fills spaces between adjacent segments of the plurality of segments of the intermediate layer, the molding member having a thermal expansion coefficient greater than a thermal expansion coefficient of the intermediate layer, The thermal expansion coefficient of the packaging substrate is greater than the thermal expansion coefficient of the intermediate layer. 2 . The semiconductor package according to claim 1 , wherein the intermediate layer comprises 2N segments arranged in a bilaterally symmetrical structure in a plan view, where N is a natural number. 3 . The semiconductor package according to claim 1 , wherein a portion of an upper surface of the lower semiconductor chip does not overlap with the intermediate layer.

4. The semiconductor package according to claim 1, wherein In a plan view, an outermost edge of the intermediate layer extends beyond an edge of the lower semiconductor chip. 5 . The semiconductor package according to claim 1 , wherein each of the lower semiconductor chip and the intermediate layer comprises a silicon wafer as a base.

6. The semiconductor package according to claim 1, wherein: A portion of the upper surface of the intermediate layer includes a pad area exposed by the molding member, The intermediate layer and the upper semiconductor chip are connected to each other through a connecting member in the pad area, and The upper semiconductor chip is spaced apart from the molding member.

7. The semiconductor package according to claim 6, wherein: The number of terminal areas in the upper semiconductor chip in which the connection members are arranged is equal to the number of the plurality of segments of the intermediate layer, and Each of the terminal regions overlaps with a corresponding one of the plurality of segments of the intermediate layer. 8 . The semiconductor package according to claim 1 , wherein the lower semiconductor chip comprises a single logic chip, and the upper semiconductor chip comprises a stack formed of a plurality of memory chips.

9. The semiconductor package according to claim 1, wherein the molding member comprises: a first molding member filling spaces between the plurality of segments of the intermediate layer; as well as A second molding member covers the lower semiconductor chip, the intermediate layer, and the first molding member, wherein a thermal expansion coefficient of the first molding member is greater than a thermal expansion coefficient of the second molding member. 10 . The semiconductor package according to claim 9 , wherein the first molding member includes a metal material, and an insulating film is provided between the intermediate layer and the first molding member.

11. The semiconductor package according to claim 1 , further comprising: a first bonding wire connecting the package substrate to the intermediate layer; as well as A second bonding wire connects the segments of the intermediate layer to each other. 12 . The semiconductor package according to claim 1 , wherein the lower semiconductor chip is positioned on the package substrate in a flip-chip manner, and bonding wires connect the lower semiconductor chip to the package substrate. 13 . The semiconductor package according to claim 1 , wherein the intermediate layer is attached to the lower semiconductor chip using an adhesive member.

14. A semiconductor package comprising: packaging substrate; a lower semiconductor chip, located on the packaging substrate; an intermediate layer located on the lower semiconductor chip, the intermediate layer comprising a plurality of regions separated from each other by grooves in an upper surface of the intermediate layer; an upper semiconductor chip located on the intermediate layer; bonding wires connecting the package substrate to the intermediate layer; as well as a molding member covering the lower semiconductor chip, the intermediate layer, and the bonding wires, wherein a thermal expansion coefficient of the molding member is greater than a thermal expansion coefficient of the intermediate layer, The molding member comprises: a first molding member filling the groove; as well as A second molding member covers the lower semiconductor chip, the intermediate layer, the first molding member, and the bonding wires, wherein a thermal expansion coefficient of the first molding member is greater than a thermal expansion coefficient of the second molding member.

15. The semiconductor package according to claim 14, wherein In a plan view, an edge of the intermediate layer extends beyond an edge of the lower semiconductor chip. The semiconductor package according to claim 14 , wherein an end portion of the groove is spaced apart from an edge of the intermediate layer. The semiconductor package according to claim 14 , wherein an end of the groove meets an edge of the intermediate layer.

18. A semiconductor package comprising: packaging substrate; a lower semiconductor chip, located on the packaging substrate; an intermediate layer located on the lower semiconductor chip, the intermediate layer including a plurality of regions separated from each other by grooves extending from a side surface of the intermediate layer; an upper semiconductor chip located on the intermediate layer; bonding wires connecting the package substrate to the intermediate layer; as well as a molding member covering the lower semiconductor chip, the intermediate layer, and the bonding wires, the molding member having a thermal expansion coefficient greater than a thermal expansion coefficient of the intermediate layer; The end of the groove meets the edge of the middle layer. 19 . The semiconductor package according to claim 18 , wherein the groove includes 2N segments arranged to face each other in a plan view, where N is a natural number. 20 . The semiconductor package according to claim 18 , wherein a portion of an upper surface of the lower semiconductor chip overlapping the groove is exposed by the intermediate layer.

21. The semiconductor package according to claim 18, wherein In a plan view, an edge of the intermediate layer extends beyond an edge of the lower semiconductor chip.

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