Silicon carbide semiconductor device

Abstract

The present invention provides a silicon carbide semiconductor device capable of preventing dielectric breakdown. A first portion of the gate polysilicon layer is disposed on a first surface of the front side of the semiconductor substrate with a gate insulating film interposed therebetween in the edge termination region, forming a gate channel. The first portion of the gate polysilicon layer faces the edge p<supgt;++< / supgt; type contact region in the depth direction Z. An end portion on the chip end side of the first portion of the gate polysilicon layer is located within the plane of the edge p<supgt;++< / supgt> type contact region. The field oxide film extends from the chip end toward the chip center side and terminates on the first surface of the front side of the semiconductor substrate at a position closer to the chip end side than the first portion of the gate polysilicon layer, and is disposed separately from the gate polysilicon layer. Therefore, no step caused by the field oxide film is generated on the surface of the gate polysilicon layer, and the entire surface of the gate polysilicon layer is flat. An end portion on the chip center side of the field oxide film is located at a position closer to the chip end side than the edge p<supgt;++< / supgt> type contact region and is located on the p-type base region.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device. Background Art

[0002] Conventionally, a trench gate type SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate composed of a three-layer structure of metal-oxide-semiconductor) using silicon carbide (SiC) as a semiconductor material has a structure in which a gate polysilicon (poly-Si) layer constituting a gate channel extends on a field oxide film directly below a gate metal layer in an edge termination region. The structure of the edge termination region of an existing semiconductor device will be described.

[0003] Figure 13 FIG. is a top view showing the layout of an existing silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate. Figure 14 is an enlarged view showing Figure 13 the rectangular frame AA of Figure 13 The rectangular frame AA of FIG. has a pair of diagonal vertices including a vertex AA1 on the corner side of the semiconductor substrate 150 and a vertex AA2 on the center side of the semiconductor substrate 150. A portion surrounded by the rectangular frame AA is a part of the edge termination region 102 of the semiconductor substrate (semiconductor chip) 150. Figure 15 FIG. is a sectional view showing Figure 14 the sectional structure at the cut line BB-BB' of Figure 16 FIG. is a sectional view showing Figure 13 the sectional structure at the cut line CC-CC' of

[0004] Figures 13 to 16 The existing silicon carbide semiconductor device 110 shown in FIG. is a vertical MOSFET having a trench gate structure including a gate metal layer 113 and a gate polysilicon layer 114 in an edge termination region 102 surrounding an active region 101. In the active region 101, respective portions constituting a MOS gate structure are provided on the front side of the semiconductor substrate 150. In the active region 101, a source pad 111 and a gate pad 112 are separately provided on a first surface 153a described later on the front of the semiconductor substrate 150. The source pad 111 has a substantially rectangular planar shape with a part thereof recessed inward.

[0005] The source pad 111 occupies a major part of the surface area of the active region 101 and extends from the active region 101 to the edge termination region 102. In Figure 13In [the figure], the outer periphery 111a of the source pad 111 is indicated by a dotted line finer than the field oxide film 121 described later. The gate pad 112 is disposed in the concave portion of the source pad 111 and has a substantially rectangular planar shape with three sides surrounded by the source pad 111. In the edge termination region 102, on the front surface of the semiconductor substrate 150, a gate insulating film 137 extends from the inner wall of the trench 136 that forms the MOS gate structure in the active region 101.

[0006] On the gate insulating film 137 on the front surface of the semiconductor substrate 150, at the second surface 153b described later, a field oxide film 121 is provided. The field oxide film 121 extends from the end of the semiconductor substrate 150 (hereinafter referred to as the chip end) toward the active region 101 side (hereinafter referred to as the chip center side) and terminates within the edge termination region 102 on the first surface 153a of the front surface of the semiconductor substrate 150. The field oxide film 121 is disposed on the first surface 153a of the front surface of the semiconductor substrate 150 directly below the gate metal layer 113, directly below the gate pad 112, and directly below the metal layer (hereinafter referred to as the gate connection metal layer) 113a that connects the gate pad 112 and the gate metal layer 113.

[0007] The gate polysilicon layer 114 is provided on the gate insulating film 137 on the front surface of the semiconductor substrate 150 on the chip center side relative to the field oxide film 121. The gate polysilicon layer 114 extends from the gate insulating film 137 onto the field oxide film 121 along the chip end side, is disposed directly below the gate metal layer 113, directly below the gate pad 112, and directly below the gate connection metal layer 113a, and terminates within the plane of the first surface 153a of the front surface of the semiconductor substrate 150. The first portion 114a of the gate polysilicon layer 114 directly below the gate metal layer 113 is a gate runner that is connected to the gate electrode 138 at the end of the trench 136.

[0008] The first portion 114a of the gate polysilicon layer 114 surrounds the periphery of the active region 101. The end 114a' on the chip center side of the first portion 114a of the gate polysilicon layer 114 is located on the chip center side relative to the end 121a' on the chip center side of the first portion 121a of the field oxide film 121 directly below the gate metal layer 113. The end 114b' of the second portion 114b of the gate polysilicon layer 114 directly below the gate pad 112 terminates at a position farther from the gate pad 112 relative to the end 121b' of the second portion 121b of the field oxide film 121 directly below the gate pad 112.

[0009] The end 114c' of the third part 114c of the gate polysilicon layer 114, directly under the gate connection metal layer 113a, terminates at a position farther from the gate pad 112 than the end 121c' of the third part 121c of the field oxide film 121, directly under the gate connection metal layer 113a. The trench 136 is formed in a strip shape in the active region 101 along the first direction X parallel to the front surface of the semiconductor substrate 150 and extends from the active region 101 to the edge termination region 102. The end of the trench 136 faces the end 114a' on the chip center side of the first part 114a of the gate polysilicon layer 114 in the depth direction Z.

[0010] The gate electrode 138 is disposed in the trench 136 via the gate insulating film 137. In Figure 13 it, the end 114a' on the chip center side of the first part 114a of the gate polysilicon layer 114, the end on the chip end side of the first part 114a, and the ends 114b', 114c' of the second and third parts 114b, 114c are represented by thick solid lines. The end on the chip end side of the first part 121a of the field oxide film 121 is located at the chip end. In Figure 13 it, the end 121a' on the chip center side of the first part 121a of the field oxide film 121 and the ends 121b', 121c' of the second and third parts 121b, 121c of the field oxide film 121 are represented by dotted lines thicker than the outer periphery 111a of the source pad 111.

[0011] On the first part 114a of the gate polysilicon layer 114, a gate metal layer 113 is provided on the interlayer insulating film 122. The gate metal layer 113 surrounds the periphery of the active region 101. The gate metal layer 113 is electrically connected to the first part 114a of the gate polysilicon layer 114 via the contact hole 122a of the interlayer insulating film 122 and is electrically connected to the gate pad 112 via the gate connection metal layer 113a. The portion directly under the gate metal layer 113 becomes a three-layer structure formed by sequentially laminating the gate insulating film 137, the first part 121a of the field oxide film 121, and the first part 114a of the gate polysilicon layer 114 on the front surface of the semiconductor substrate 150.

[0012] Moreover, the end 114a' of the first portion 114a of the gate polysilicon layer 114 extends more toward the chip center side than the end 121a' on the chip center side of the first portion 121a of the field oxide film 121. Therefore, in the above three-layer structure, the portion adjacent to the chip center side becomes a double-layer structure formed by sequentially laminating only the gate insulating film 137 and the first portion 114a of the gate polysilicon layer 114 on the front surface of the semiconductor substrate 150. In the first portion 114a of the gate polysilicon layer 114, a step 115 corresponding to the thickness of the field oxide film 121 is generated between the portion on the field oxide film 121 and the portion on the gate insulating film 137.

[0013] Due to this step 115, the surface of the first portion 114a of the gate polysilicon layer 114 is recessed toward the semiconductor substrate 150 at the portion closer to the chip center side than the first portion 121a of the field oxide film 121. The surfaces of the second portion 114b and the third portion 114c of the gate polysilicon layer 114 are also the same as the surface of the first portion 114a of the gate polysilicon layer 114, and a step 115 corresponding to the thickness of the field oxide film 121 is generated between the portion on the field oxide film 121 and the portion on the gate insulating film 137. The gate polysilicon layer 114 and the field oxide film 121 are covered with the interlayer insulating film 122.

[0014] The gate polysilicon layer 114 is electrically connected by contacting the gate metal layer 113 through the contact hole 122a of the interlayer insulating film 122. In Figure 14 , Figure 15 , reference numeral 141 is the gate metal layer 113, and shows the portion from the end on the chip end side of the gate metal layer 113 to the end on the chip center side. Reference numeral 142 is the contact hole 122a of the interlayer insulating film 122. A contact portion between the gate metal layer 113 and the gate polysilicon layer 114 is formed in this contact hole 122a. Reference numeral 143 is the portion between the gate metal layer 113 and the source pad 111.

[0015] The boundary between reference numeral 143 and reference numeral 144 is the end position of the source pad 111. The boundary between reference numeral 144 and reference numeral 145 is the position of the end 121a' on the chip center side of the first portion 121a of the field oxide film 121. Reference numeral 145 is the portion of the structure formed by sequentially laminating the gate insulating film 137 and the gate polysilicon layer 114 on the front surface of the semiconductor substrate 150. Reference numeral 146 is the portion from the end 114a' on the chip center side of the first portion 114a of the gate polysilicon layer 114 to the end on the chip center side of the interlayer insulating film 122 covering the first portion 114a of the gate polysilicon layer 114.

[0016] The semiconductor substrate 150 is an n + -type starting substrate (not shown) on which an n -An epitaxial substrate formed by sequentially epitaxially growing an n-type semiconductor layer 151 and a p-type semiconductor layer 152. The n - -type semiconductor layer 151 forms an n - -type drift region 131. The p-type semiconductor layer 152 is etched to remove a part on the chip end side, so that it remains in a mesa (tablet) shape in the center of the chip. By removing the part of the p-type semiconductor layer 152 on the chip end side, a step 153 is formed on the front surface of the semiconductor substrate 150 in the edge termination region 102. The side surface of the remaining mesa-shaped p-type semiconductor layer 152 is exposed at the step edge 153c of the step 153.

[0017] The front surface of the semiconductor substrate 150 is bounded by this step 153, and the second surface 153b closer to the chip end side than the first surface 153a on the chip center side is recessed toward the drain electrode (not shown). The p-type semiconductor layer 152 forms a p-type base region 132. That is, the p-type base region 132 extends from the active region 101 to the step edge 153c of the step 153 in the edge termination region 102. The step edge 153c of the step 153 is a surface connecting the first surface 153a on the front surface of the semiconductor substrate 150 closer to the chip center side than the step 153 and the recessed second surface 153b closer to the chip end side than the step 153.

[0018] In the part of the edge termination region 102 of the p-type semiconductor layer 152 (p-type base region 132), at the contact hole 122b of the interlayer insulating film 122, a p ++ -type contact region 135 (hereinafter referred to as the edge p ++ -type contact region 135') extends from the active region 101. The edge p ++ -type contact region 135' extends further toward the chip end side than the first part 114a of the gate polysilicon layer 114 and terminates at a position closer to the chip center side than the step edge 153c of the step 153. The edge p ++ -type contact region 135' also extends directly below the gate pad 112.

[0019] The distance d101 from the step edge 153c of the step 153 to the edge p ++ -type contact region 135' is 15 μm. The end on the chip end side of the first part 114a of the gate polysilicon layer 114 and the edge p ++The distance d102 between the ends on the chip end side of the type contact region 135’ is 2 μm. The distance d103 from the end on the chip end side of the first part 114a of the gate polysilicon layer 114 to the end 121a’ on the chip center side of the first part 121a of the field oxide film 121 is 73 μm. The distance d104 from the gate metal layer 113 to the source pad 111 is 10 μm. The width d105 of the gate metal layer 113 is 36 μm.

[0020] In the n - type semiconductor layer 151, a p - type region 163 is selectively formed by ion implantation in a surface area of a portion of the second surface 153b that forms the front surface of the semiconductor substrate 150. - The p - type region 163 is electrically connected to the source electrode 139 and constitutes a breakdown voltage structure such as a junction termination extension (JTE) structure. The p - type region 163 surrounds the periphery of the active region 101. Between the p + type region 163 and the active region 101, p

[0021] p + type regions 162a’ and 162b’ that face each other and are adjacent to each other in the depth direction Z are provided at a position closer to the drain electrode than the p-type base region 132. - type region 162a’ contacts the p + type region 163 and the p + type region 162b’. The p - type region 162b’ contacts the p + type region 163 and the p-type base region 132. The p + type regions 162a’ and 162b’ surround the periphery of the active region 101. The p + type regions 162a’ and 162b’ extend under the gate pad 112. The p + type regions 162a’ and 162b’ are formed simultaneously with the p + type regions 161, 162a, and 162b of the active region 101 have the following function: depleting when the MOSFET is turned off to relieve the electric field applied to the bottom surface of the trench 136.

[0022] At a position closer to the drain electrode than the p-type base region 132, a plurality of p + type regions 161 are provided separately from the p-type base region 132. + type region 161 faces the bottom surface of the trench 136 in the depth direction Z. Between adjacent trenches 136, with the trenches 136 and p +The p-type region 161 is separately provided with p + -type regions 162a and 162b. The p + -type region 162a is separately provided at a position closer to the drain electrode than the p-type base region 132. The p + -type region 162b is provided between the p-type base region 132 and the p + -type region 162a, and is in contact with the p-type base region 132 and the p + -type region 162a.

[0023] Within the contact hole 122b of the interlayer insulating film 122, the source electrode 139 makes an ohmic contact with the n + -type source region 134 and the p ++ -type contact region 135. Within the contact hole 122b of the interlayer insulating film 122, the source electrode 139 is connected to the source pad 111. On the back side of the semiconductor substrate 150, an n + -type drain region and a drain electrode are provided. The symbol 123 is a passivation protective film. The symbol 133 is provided inside the n - -type drift region 131, and is an n-type region that forms a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the expansion resistance of carriers.

[0024] As such an existing SiC-MOSFET, a device has been proposed in which a gate polysilicon layer is provided on a gate insulating film between a gate metal layer in an edge termination region and the gate insulating film that extends from an active region to directly below the gate metal layer on the front surface of a semiconductor substrate (for example, refer to Patent Documents 1 to 3 below). In Patent Document 1 below, as a structure in which a p-type region for extracting charges (holes) is arranged at a corner (vertex of a rectangle) of an active region, an electric field caused by charges generated in the edge termination region is not applied to the field oxide film between the p-type base region and the gate channel, thereby preventing insulation breakdown of the field oxide film.

[0025] In Patent Document 2 below, by arranging a p-type surface field reduction region along the depth direction so as to face the step edge between the active region and the breakdown voltage structure of the edge termination region, a structure is provided in which no electric field concentration occurs between the active region and the breakdown voltage structure, thereby suppressing a breakdown voltage drop. In Patent Document 3 below, the thickness of the portion of the interlayer insulating film on the active region is made thinner than the thickness of the portion of the interlayer insulating film on the edge termination region, and the thickness of the portion of the interlayer insulating film on the edge termination region is designed to be a thickness that does not affect the electric field distribution in the edge termination region, thereby flattening the source pad and preventing fluctuations in breakdown voltage characteristics or breakdown voltage defects caused by such fluctuations.

[0026] Prior Art Documents

[0027] Patent Documents

[0028] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-206873

[0029] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2018-117016

[0030] Patent Document 3: Japanese Unexamined Patent Application Publication No. 2014-175314 SUMMARY OF THE INVENTION

[0031] TECHNICAL PROBLEM

[0032] However, in the existing silicon carbide semiconductor device 110 (see Figures 13 to 16 ), in a reliability test in which a voltage of 1200 V is applied between the drain and source at a high temperature (e.g., about 175°C) and the voltage is applied in such a manner that a negative bias is applied between the gate and source, it was confirmed that the semiconductor device was damaged at a measurement time of about 500 hours with respect to a target measurement time of 1000 hours. Therefore, a cross-sectional analysis using emission microscopy (EMS: Emission Micro Scope) was performed on the silicon carbide semiconductor device 110 that caused the over-damage.

[0033] As a result of the cross-sectional analysis based on the emission microscopy, light emission 170 indicating the generation of leakage current was observed in a portion 145 of a double-layer structure in which a gate insulating film 137 and a gate polysilicon layer 114 are sequentially laminated on the front surface of a semiconductor substrate 150, at an end 121a' on the chip center side of a first portion 121a of a field oxide film 121 and at ends 121b', 121c' of a second portion 121b and a third portion 121c of the field oxide film 121 adjacent to the chip center side, and it was confirmed that the gate insulating film 137 was insulation-damaged at the portion of the light emission 170 ( Figure 14 , Figure 15 ).

[0034] It is speculated that the reason for the damage in the portion 145 of the double-layer structure is that when a voltage is applied under the above-described predetermined conditions, electric field concentration occurs at an end 114a' on the chip center side of a first portion 114a and at ends 114b', 114c' of a second portion 114b and a third portion 114c of the gate polysilicon layer 114. When turned off, a part of the hole current generated in the edge terminal region 102 and extracted through the edge p ++ -type contact region 135' to the source electrode 139 becomes leakage current and is injected into the gate insulating film 137 at the electric field concentration portion, thereby causing insulation damage.

[0035] In order to solve the above problems of the prior art, an object of the present invention is to provide a silicon carbide semiconductor device capable of preventing insulation damage.

[0036] Technical Solution

[0037] In order to solve the above problems and achieve the purpose of the present invention, the silicon carbide semiconductor device of the present invention has the following characteristics. In the active area, an insulating gate structure having a three-layer structure of metal-oxide film-semiconductor of an insulated gate bipolar transistor is provided on the front side of a semiconductor substrate composed of silicon carbide. The first conductive semiconductor layer constitutes the semiconductor substrate and constitutes the drift region of the insulated gate bipolar transistor. The second conductive semiconductor layer is arranged between the front side of the semiconductor substrate and the first conductive semiconductor layer to constitute the semiconductor substrate, and constitutes the base region of the insulated gate bipolar transistor.

[0038] The trench is arranged on the front side of the semiconductor substrate and extends along a first direction parallel to the front side of the semiconductor substrate. The gate electrode of the insulated gate bipolar transistor is arranged inside the trench through an insulating film. In the terminal area surrounding the active area, a second conductive type high concentration area having an impurity concentration higher than the impurity concentration of the second conductive type semiconductor layer is arranged on the surface area of ​​the front side of the semiconductor substrate. The second conductive type high concentration area forms a second conductive type junction having an impurity concentration different from that of the second conductive type semiconductor layer. A first gate polysilicon layer is arranged on the front side of the semiconductor substrate through the insulating film.

[0039] The first gate polysilicon layer is opposite to the second conductive type high concentration region in the depth direction through the insulating film, and surrounds the active region in a rectangular manner. The first gate polysilicon layer is electrically connected to the gate electrode at the end of the trench. In the terminal area, a field oxide film is provided on the front surface of the semiconductor substrate through the insulating film. The field oxide film extends from the outside to the inside, and surrounds the first gate polysilicon layer in a rectangular manner. Among the four sides of the field oxide film, at least the portion parallel to the second direction terminates at a position further outward than the first gate polysilicon layer, and the second direction is a direction orthogonal to the first direction.

[0040] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the portion of the field oxide film along at least one of the two sides parallel to the first direction extends inward in the second direction to the same position as the inner end of the first gate polysilicon layer.

[0041] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, a portion of the field oxide film parallel to the first direction extends inwardly in the second direction to the same position as an inner end of the first gate polysilicon layer.

[0042] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the second conductivity type high concentration region terminates at a position closer to the inside than the second conductivity type semiconductor layer. The inner end of at least the portion of the field oxide film parallel to the second direction is at a position closer to the outside than the second conductivity type junction, and faces the second conductivity type semiconductor layer across the insulating film in the depth direction.

[0043] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the outer end of the first gate polysilicon layer is located within the plane of the second conductivity type high concentration region.

[0044] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the silicon carbide semiconductor device is flat over the entire surface of the first gate polysilicon layer.

[0045] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the silicon carbide semiconductor device further includes a second gate polysilicon layer and a gate pad. In the active region, the second gate polysilicon layer is disposed on the front surface of the semiconductor substrate across the insulating film and is connected to the first gate polysilicon layer. The gate pad is disposed above the second gate polysilicon layer across the interlayer insulating film and is electrically connected to the second gate polysilicon layer. The field oxide film is not disposed between the front surface of the semiconductor substrate and the second gate polysilicon layer.

[0046] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, based on the above invention, the insulating film is a high temperature oxide film or a thermal oxide film, and the field oxide film is a silicon oxide film. The thickness of the field oxide film is thicker than the thickness of the insulating film.

[0047] Technical Effects

[0048] According to the silicon carbide semiconductor device of the present invention, the following effects are achieved: Since no step caused by the field oxide film is generated on the surface of the gate polysilicon layer, no electric field concentration occurs near the inner end of the gate polysilicon layer, and thus dielectric breakdown can be prevented. Brief Description of the Drawings

[0049] Figure 1 is a top view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as viewed from the front side of the semiconductor substrate.

[0050] Figure 2 is an enlarged view showing Figure 1 the rectangular frame A.

[0051] Figure 3 is a sectional view showing the sectional structure of the cutting line B-B'. Figure 2

[0052] Figure 4 is a sectional view showing the sectional structure of the cutting line C-C'. Figure 1

[0053] Figure 5 is a sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment.

[0054] Figure 6 is a sectional view showing the structure of the silicon carbide semiconductor device according to the third embodiment.

[0055] Figure 7 is a top view showing the layout of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front side of the semiconductor substrate.

[0056] Figure 8 is a sectional view showing Figure 7 the sectional structure of the cutting line D-D'.

[0057] Figure 9 is a top view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front side of the semiconductor substrate.

[0058] Figure 10 is a top view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front side of the semiconductor substrate.

[0059] Figure 11 is a top view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front side of the semiconductor substrate.

[0060] Figure 12 is a top view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front side of the semiconductor substrate.

[0061] Figure 13 is a top view showing the layout of the conventional silicon carbide semiconductor device as viewed from the front side of the semiconductor substrate.

[0062] Figure 14 is an enlarged top view showing Figure 13 the rectangular frame AA.

[0063] Figure 15 is a sectional view showing Figure 14 the sectional structure of the cutting line BB-BB'.

[0064] Figure 16 is a sectional view showing Figure 13 ​​Cross-sectional view of the cross-sectional structure of the cutting line CC-CC'.

[0065] Symbol Explanation

[0066] 1 Active region

[0067] 2 Edge termination region

[0068] 10, 71 to 77 Silicon carbide semiconductor device

[0069] 11 Source pad

[0070] 11a Outer periphery of the source pad

[0071] 12 Gate pad

[0072] 13 Gate metal layer

[0073] 13a Gate connection metal layer

[0074] 14 Gate polysilicon layer

[0075] 14a First part of the gate polysilicon layer directly below the gate metal layer

[0076] 14a' End of the first part of the gate polysilicon layer

[0077] 14b Second part of the gate polysilicon layer directly below the gate pad

[0078] 14b' End of the second part of the gate polysilicon layer

[0079] 14c Third part of the gate polysilicon layer directly below the gate connection metal layer

[0080] 14c' End of the third part of the gate polysilicon layer

[0081] 15 Drain electrode

[0082] 21, 21' Field oxide film

[0083] 21a, 21a', 21b End of the field oxide film on the chip center side

[0084] 22 Interlayer insulating film

[0085] 22a, 22b Contact hole

[0086] 23 Passivation protection film

[0087] 31 n - -type drift region

[0088] 32 p-type base region

[0089] 33 n-type region

[0090] 34 n + n-type source region

[0091] 35 p ++ p-type contact region

[0092] 35’ edge p ++ p-type contact region

[0093] 36 trench

[0094] 37, 37’ gate insulating film

[0095] 38 gate electrode

[0096] 39 source electrode

[0097] 40 n + n-type drain region

[0098] 50 semiconductor substrate

[0099] 51 n - n-type semiconductor layer

[0100] 52 p-type semiconductor layer

[0101] 53 step on the front surface of the semiconductor substrate

[0102] 53a first surface of the front surface of the semiconductor substrate

[0103] 53b second surface of the front surface of the semiconductor substrate

[0104] 53c, 53c’ ledge of the step on the front surface of the semiconductor substrate

[0105] 54 n + n-type starting substrate

[0106] 61, 62a, 62a’, 62b, 62b’ p + p-type region

[0107] 63 p - p-type region

[0108] X first direction parallel to the front surface of the semiconductor substrate (direction in which the trench extends stripwise)

[0109] Y second direction parallel to the front surface of the semiconductor substrate and orthogonal to the first direction

[0110] Z depth direction

[0111] d1 distance from the ledge of the step on the front surface of the semiconductor substrate to the edge p ++ p-type contact region

[0112] The distance between the end on the chip end side of the first part of the d2 gate polysilicon layer and the end on the chip end side of the edge p ++ type contact region

[0113] The distance that the end on the chip center side of the d3 field oxide film extends from the step edge toward the chip center side

[0114] d3’ The distance from the end on the chip center side of the field oxide film to the edge p ++ type contact region

[0115] The distance from the gate metal layer to the source pad, d4

[0116] The width of the gate metal layer, d5 Detailed implementation mode

[0117] Hereinafter, with reference to the drawings, a preferred implementation mode of the silicon carbide semiconductor device of the present invention will be described in detail. In this specification and the drawings, in the layers or regions prefixed with n or p, electrons or holes are respectively indicated as the majority carriers. In addition, + and - marked on n or p respectively indicate that the impurity concentration is higher or lower than that of the layers or regions without + and - marked. It should be noted that in the following description of the implementation mode and the drawings, the same symbols are marked for the same structures, and repeated descriptions are omitted.

[0118] (Embodiment 1)

[0119] The structure of the silicon carbide semiconductor device of Embodiment 1 will be described. Figure 1 It is a top view showing the layout of the silicon carbide semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate. Figure 2 It is an enlarged top view showing Figure 1 The rectangular frame A. The part surrounded by the rectangular frame A is a part of the edge terminal region 2. The rectangular frame A has a vertex A1 on the corner side (one vertex of the semiconductor substrate (semiconductor chip) 50 having a substantially rectangular planar shape) and a vertex A2 on the center side of the semiconductor substrate 50 as a set of diagonal vertices. Figure 3 It is a sectional view showing Figure 2 The sectional structure at the cutting line B - B' of Figure 4 It is a sectional view showing Figure 1 The sectional structure at the cutting line C - C' of

[0120] Figures 1 to 4The silicon carbide semiconductor device 10 of the first embodiment shown is a vertical MOSFET with a trench gate structure having a gate metal layer 13 and a gate polycrystalline silicon (poly-Si) layer 14 in an edge termination region 2 surrounding the active region 1. The active region 1 is a region where current flows when the device is in the on state. The edge termination region 2 is a region between the active region 1 and the end of the semiconductor substrate 50, and is a region for relieving the electric field on the front side of the semiconductor substrate 50 and maintaining the breakdown voltage. A breakdown voltage structure such as a junction termination extension (JTE) structure is disposed in the edge termination region 2. The breakdown voltage is the limit voltage at which the device does not malfunction or break down.

[0121] In the active region 1, a source pad 11 and a gate pad 12 are separately provided on a first surface 53a, which will be described later, on the front side of the semiconductor substrate 50. The source pad 11 has a substantially rectangular planar shape with a part recessed inward. The source pad 11 occupies most of the surface area of the active region 1 and extends from the active region 1 to the edge termination region 2. In Figure 1 the outer periphery 11a of the source pad 11 is represented by a dotted line finer than a field oxide film 21, which will be described later. The gate pad 12 is disposed in the recess of the source pad 11 and has a substantially rectangular planar shape with three sides surrounded by the source pad 11.

[0122] In the active region 1, each part constituting the MOS gate structure is provided on the front side of the semiconductor substrate 50. The semiconductor substrate 50 is an epitaxial substrate in which an n + -type starting substrate 54, an n - -type semiconductor layer 51, and a p-type semiconductor layer 52 are sequentially epitaxially grown. The main surface on the p-type semiconductor layer 52 side of the semiconductor substrate 50 is defined as the front side, and the main surface on the n + -type starting substrate 54 side of the semiconductor substrate 50 (the back surface of the n + -type starting substrate 54) is defined as the back side. The chip size of the semiconductor substrate 50 can be, for example, 3.8 mm × 3.8 mm. The MOS gate structure is composed of a p-type base region 32, an n + -type source region 34, a p ++ -type contact region 35, a trench 36, a gate insulating film 37, and a gate electrode 38.

[0123] The n + -type starting substrate 54 constitutes an n + -type drain region 40. The n - -type semiconductor layer 51 constitutes an n - -type drift region 31. An n-type region 33 and a p - -type drift region 31 can be provided inside the n +Type regions 61, 62a, 62b. The n-type region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type region 33 is provided between the p + type region 61 and the p + type region 62a. The n-type region 33 may extend to the edge terminal region 2, in which case the n-type region 33 terminates at a position, for example, closer to the center (inner side) of the chip than the step edge 53c of the step 53. The p + type regions 61, 62a, 62b have the function of depleting when the MOSFET is turned off and relieving the electric field applied to the bottom surface of the trench 36.

[0124] p + type region 61 is provided separately from the p-type base region 32 at a position closer to the drain electrode 15 than the p-type base region 32. The p + type region 61 faces the bottom surface of the trench 36 in the depth direction. The p + type regions 62a, 62b are provided separately from the trench 36 and the p + type region 61 between adjacent trenches 36. The p + type region 62a is provided separately from the p-type base region 32 at a position closer to the drain electrode 15 than the p-type base region 32. The p + type region 62b is provided between the p-type base region 32 and the p + type region 62a, and contacts the p-type base region 32 and the p + type region 62a.

[0125] The p-type semiconductor layer 52 is formed into a mesa (terrace) shape remaining in the center of the chip by etching away a part on the end (hereinafter referred to as the chip end) side. By removing the part on the chip end (outer side) of the p-type semiconductor layer 52, a step 53 is formed on the front surface of the semiconductor substrate 50 in the edge terminal region 2. The side surface of the p-type semiconductor layer 52 remaining in a mesa shape is exposed at the step edge 53c of the step 53. The front surface of the semiconductor substrate 50 is recessed toward the drain electrode 15 side at a second surface 53b closer to the chip end than the first surface 53a on the chip center side (hereinafter referred to as the active region 1 side) with the step 53 as a boundary.

[0126] The p-type semiconductor layer 52 constitutes the p-type base region 32. That is, the p-type base region 32 extends from the active region 1 to the step edge 53c of the step 53 in the edge terminal region 2. The step edge 53c is a surface that connects the first surface 53a on the chip center side of the front surface of the semiconductor substrate 50, which is closer to the step 53, and the recessed second surface 53b on the chip end side. In the active region 1, between the first surface 53a on the front surface of the semiconductor substrate 50 and the p-type base region 32, n + type source regions 34 and p++ Type contact region 35.

[0127] The trench 36 penetrates through the n- + type source region 34 and the p-type base region 32 and reaches the n- - type drift region 31. The trench 36 is not provided directly under the gate pad 12. The trench 36 extends strip-like from the active region 1 toward the edge termination region 2 along the first direction X parallel to the front surface of the semiconductor substrate 50. The end of the trench 36 faces the end 14a' on the chip center side of the first part 14a of the gate polysilicon layer 14 described later in the depth direction Z. In addition, the end of the trench 36 faces the ends 14b', 14c' of the second and third parts 14b, 14c of the gate polysilicon layer 14 described later in the depth direction Z.

[0128] Inside the trench 36, a gate electrode 38 made of polysilicon is provided via a gate insulating film 37. For example, the gate insulating film 37 can be a high temperature oxidation (HTO: High Temperature Oxide) film or a thermal oxidation film. The gate electrode 38 can be, for example, a polysilicon layer. At the end of the trench 36, the gate electrode 38 is connected to any one of the first part 14a to the third part 14c of the gate polysilicon layer 14. An interlayer insulating film 22 is provided on the entire front surface of the semiconductor substrate 50 so as to cover the gate electrode 38. As the interlayer insulating film 22, for example, NSG (Non doped Silicate Glass) and BPSG (Boro Phospho Silicate Glass) can be laminated in sequence.

[0129] In the contact hole 22b of the interlayer insulating film 22, the source electrode 39 makes an ohmic contact with the n- + type source region 34 and the p- ++ type contact region 35 and is connected to the source pad 11. The source pad 11 is provided on the interlayer insulating film 22 so as to be buried in the contact hole 22b of the interlayer insulating film 22, covering almost the entire part of the first surface 53a of the front surface of the semiconductor substrate 50 in the active region 1 except for the gate pad 12. The gate pad 12 is provided on the interlayer insulating film 22 and covers a part of the first surface 53a of the front surface of the semiconductor substrate 50 in the active region 1. The gate pad 12 is electrically connected to all the gate electrodes 38 via the gate polysilicon layer 14.

[0130] In the edge terminal region 2, on the front surface of the semiconductor substrate 50, a gate insulating film 37 extends from the inner wall of the trench 36 of the active region 1. A field oxide film 21 is provided in contact with the gate insulating film 37 on the second surface 53b of the front surface of the semiconductor substrate 50. The field oxide film 21 extends from the chip end portion toward the chip center side and terminates at a position closer to the chip end portion side than the first portion 14a of the gate polysilicon layer 14 on the first surface 53a of the front surface of the semiconductor substrate 50. The field oxide film 21 is disposed separately from the gate polysilicon layer 14, and the field oxide film 21 surrounds the periphery of the first portion 14a of the gate polysilicon layer 14.

[0131] The end portion 21a on the chip center side of the field oxide film 21 is located at a position closer to the chip center side than the step edge 53c of the step 53, and is located at a position closer to the chip end portion side than the edge p ++ -type contact region 35'. That is, in the portion 44 between the step edge 53c of the step 53 and the edge p ++ -type contact region 35', the end portion 21a on the chip center side of the field oxide film 21 is located on the p-type base region 32 exposed on the first surface 53a of the front surface of the semiconductor substrate 50. Thereby, it is possible to prevent dielectric breakdown of the field oxide film 21 on the p ++ -type contact region 35'.

[0132] In the portion 44 between the step edge 53c of the step 53 and the edge p ++ -type contact region 35', the position of the end portion 21a on the chip center side of the field oxide film 21 can be variously changed according to design conditions. Specifically, the distance d1 from the step edge 53c of the step 53 to the edge p ++ -type contact region 35' is predetermined by design specifications, for example, about 15 μm. In this case, the end portion 21a on the chip center side of the field oxide film 21 terminates at a position more than 0.5 μm away from the step edge 53c of the step 53 toward the chip center side, and terminates at a position less than 15 μm away from the step edge 53c of the step 53 toward the chip center side.

[0133] When the distance d3 by which the end portion 21a on the chip center side of the field oxide film 21 extends from the step edge 53c of the step 53 toward the chip center side is 13 μm, the distance d3' from the end portion 21a on the chip center side of the field oxide film 21 to the edge p ++ -type contact region 35' becomes 2 μm. Further, when the distance d3 is 10 μm, the distance d3' from the end portion 21a on the chip center side of the field oxide film 21 to the edge p ++ -type contact region 35' is 5 μm. The field oxide film 21 may be, for example, silicon oxide (SiO 2) The film. The thickness of the field oxide film 21 can be thicker than the thickness of the gate insulating film 37.

[0134] The gate polysilicon layer 14 is located on the gate insulating film 37 on the front surface of the semiconductor substrate 50 at a position closer to the center of the chip than the field oxide film 21. The gate polysilicon layer 14 is disposed directly below the gate metal layer 13, directly below the gate pad 12, and directly below the metal layer (hereinafter referred to as the gate connection metal layer) 13a that connects the gate pad 12 and the gate metal layer 13, and terminates within the surface of the first surface 53a on the front surface of the semiconductor substrate 50. The entire gate polysilicon layer 14 is located within the surface of the edge p ++ type contact region 35'. It should be noted that in the drawings, it is described as an assumption that the gate insulating film 37 is formed by thermal oxidation. Generally, since the formation process of the field oxide film 21 is an earlier process than the formation process of the gate insulating film 37, when the gate insulating film 37 is an HTO film, the stacking relationship between the field oxide film 21 and the gate insulating film 37 is reversed.

[0135] The first portion 14a of the gate polysilicon layer 14 directly below the gate metal layer 13 is a gate runner that is connected to the gate electrode 38 at the end of the trench 36. The first portion 14a of the gate polysilicon layer 14 is opposed to the entire gate metal layer 13 in the depth direction and surrounds the periphery of the active region 1. The end 14a' of the first portion 14a of the gate polysilicon layer 14 on the chip center side extends toward the chip center side and terminates at a position opposed to the outer periphery 11a of the source pad 11 in the depth direction Z. The end of the first portion 14a of the gate polysilicon layer 14 on the chip end side is located within the surface of the edge p ++ type contact region 35'. For example, the distance d2 between the end of the first portion 14a of the gate polysilicon layer 14 on the chip end side and the end of the edge p ++ type contact region 35' on the chip end side is about 2 μm.

[0136] The second portion 14b of the gate polysilicon layer 14 directly below the gate pad 12 is opposed to the entire gate pad 12 in the depth direction Z. The end 14b' of the second portion 14b of the gate polysilicon layer 14 extends in a direction separated from the gate pad 12 along a direction parallel to the front surface of the semiconductor substrate 50 (the first direction X and the second direction Y), and terminates at a position opposed to the outer periphery 11a of the source pad 11 in the depth direction Z. The third portion 14c of the gate polysilicon layer 14 directly below the gate connection metal layer 13a is opposed to the entire gate connection metal layer 13a in the depth direction Z. The end 14c' of the third portion 14c of the gate polysilicon layer 14 extends along a direction parallel to the front surface of the semiconductor substrate 50 (in Figure 1The middle is in the first direction X), extending from the gate connection metal layer 13a and terminating at a position facing the outer periphery 11a of the source pad 11 in the depth direction Z.

[0137] The planar shape of the inner periphery of the gate polysilicon layer 14 is slightly smaller than the outer periphery 11a of the source pad 11 and has the same planar shape as the outer periphery 11a of the source pad 11. The planar shape of the outer periphery of the gate polysilicon layer 14 is slightly smaller than the rectangle of the inner periphery of the field oxide film 21. In Figure 1 the figure, the end 14a' on the chip center side of the first part 14a of the gate polysilicon layer 14, the end on the chip end side of the first part 14a, and the ends 14b', 14c' of the second and third parts 14b, 14c are represented by thick solid lines. In Figure 1 the figure, the end 21a on the chip center side of the field oxide film 21 is represented by a dotted line thicker than the outer periphery 11a of the source pad 11. The end on the chip end side of the field oxide film 21 is located at the chip end.

[0138] On the first part 14a of the gate polysilicon layer 14, a gate metal layer 13 is provided on the interlayer insulating film 22. The gate metal layer 13 surrounds the periphery of the active region 1. The gate metal layer 13 is electrically connected to the first part 14a of the gate polysilicon layer 14 via the contact hole 22a of the interlayer insulating film 22 and is electrically connected to the gate pad 12 via the gate connection metal layer 13a. The portion directly below the gate metal layer 13 extends over the entire first part 14a of the gate polysilicon layer 14 and forms a double-layer structure in which the gate insulating film 37 and the first part 14a of the gate polysilicon layer 14 are sequentially laminated on the first surface 53a on the front side of the semiconductor substrate 50. That is, in the first part 14a of the gate polysilicon layer 14, the film thickness (thickness) of the insulating film existing between the gate polysilicon layer 14 and the first surface 53a on the front side of the semiconductor substrate 50 becomes the same as the film thickness of the gate insulating film 37 formed inside the trench 36 in the active region 1. The same film thickness only needs to be formed by the same manufacturing process and includes a film thickness deviation of ±10% within the range of in-plane deviation.

[0139] In the second part 14b of the gate polysilicon layer 14, over the entire second part 14b of the gate polysilicon layer 14, it also forms a double-layer structure in which the gate insulating film 37 and the second part 14b of the gate polysilicon layer 14 are sequentially laminated on the first surface 53a on the front side of the semiconductor substrate 50. In the third part 14c of the gate polysilicon layer 14, over the entire third part 14c of the gate polysilicon layer 14, it also forms a double-layer structure in which the gate insulating film 37 and the third part 14c of the gate polysilicon layer 14 are sequentially laminated on the first surface 53a on the front side of the semiconductor substrate 50.

[0140] Thus, the field oxide film 21 is not opposed to the gate polysilicon layer 14 in the depth direction Z. Therefore, the surface of the gate polysilicon layer 14 is flat throughout the gate polysilicon layer 14, and steps 115 ([ Figure 15 , Figure 16 ) based on the field oxide film 121 as in the conventional structure are not generated on the surface of the gate polysilicon layer 14. Since the insulating film between the gate polysilicon layer 14 and the first surface 53a of the front side of the semiconductor substrate 50 is only the gate insulating film 37, when a voltage is applied under the above conditions, electric field concentration does not occur at the end 14a' on the chip center side of the first part 14a of the gate polysilicon layer 14 and the ends 14b', 14c' of the second and third parts 14b, 14c as in the conventional structure.

[0141] The gate polysilicon layer 14 and the field oxide film 21 are covered with the interlayer insulating film 22. The gate polysilicon layer 14 is electrically connected to the gate metal layer 13 through the contact hole 22a of the interlayer insulating film 22. A contact portion between the gate metal layer 13 and the gate polysilicon layer 14 is formed in the contact hole 22a of the interlayer insulating film 22. Figure 3 Symbols 41 to 44, symbol 44', symbols 45 to 49 respectively correspond to Figure 2 symbols 41 to 44, symbol 44', symbols 45 to 49. The distance d4 from the gate metal layer 13 to the source pad 11 is about 10 μm, for example. The width d5 of the gate metal layer 13 is about 36 μm, for example. The distances d1 to d4 between the above-mentioned respective parts and the width d5 of the gate metal layer 13 are determined according to the design specifications and are not related to the chip size of the semiconductor substrate 50.

[0142] In the edge termination region 2, between the first surface 53a of the front side of the semiconductor substrate 50 and the p-type base region 32, a p ++ -type contact region 35 (hereinafter, referred to as the edge p ++ -type contact region 35') extends from the active region 1. The edge p ++ -type contact region 35' extends more toward the chip end side than the first part 14a of the gate polysilicon layer 14 and terminates at a position closer to the chip center side than the end 21a of the field oxide film 21 on the chip center side. The edge p ++ -type contact region 35' makes an ohmic contact with the source electrode 39 through the contact hole 22b of the interlayer insulating film 22.

[0143] The contact portion (electrical contact portion) between the edge p ++ -type contact region 35' and the source electrode 39 is a contact portion for extracting the hole current generated in the edge termination region 2 during turn-off through the edge p ++ -type contact region 35'. For example, the edge p ++The type contact region 35' also extends directly under the gate pad 12. In the n - type semiconductor layer 51, a surface region of a portion of the second surface 53b that forms the front surface of the semiconductor substrate 50 is selectively formed with a p - type region 63 by ion implantation. The p - type region 63 is electrically connected to the source electrode 39 and constitutes a breakdown voltage structure such as a junction termination extension (JTE) structure. The p - type region 63 surrounds the periphery of the active region 1.

[0144] Between the p - type region 63 and the active region 1, p + type regions 62a' and 62b' that are opposed to each other in the depth direction Z and adjacent to each other are provided at a position closer to the drain electrode 15 than the p-type base region 32. The p + type region 62a' contacts the p - type region 63 and the p + type region 62b'. The p + type region 62b' contacts the p - type region 63 and the p-type base region 32. The p + type regions 62a' and 62b' surround the periphery of the active region 1. The p + type regions 62a' and 62b' extend, for example, directly under the gate pad 12. The p + type regions 62a' and 62b' are formed simultaneously with the p + type regions 62a and 62b of the active region 1.

[0145] The front surface of the semiconductor substrate 50 is covered with a passivation protective film 23. The entire back surface of the semiconductor substrate 50 is provided with a drain electrode 15 and is electrically connected to an n + type drain region 40 (n + type starting substrate 54).

[0146] As described above, according to the first embodiment, by terminating the end of the field oxide film on the chip center side at a position closer to the chip end side than the first part of the gate polysilicon layer, no step caused by the field oxide film is generated on the surface of the gate polysilicon layer, and the surface is flat throughout the entire surface of the gate polysilicon layer. Therefore, when a voltage is applied under the above predetermined conditions, no electric field concentration occurs at the end of the first part of the gate polysilicon layer on the chip center side, which occurs in the existing structure. Therefore, a part of the hole current (leakage current) generated in the edge terminal region during turn-off and extracted to the source electrode through the edge p ++ type contact region is not injected into the gate insulating film near the contact portion for extracting the hole current. Therefore, insulation breakdown of the gate insulating film can be prevented.

[0147] (Second Embodiment)

[0148] Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. Figure 5 FIG. is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device 71 according to the second embodiment is different from the silicon carbide semiconductor device 10 according to the first embodiment (see Figures 1 to 4 ) in that a field oxide film covering the front surface of the semiconductor substrate 50 in the edge termination region 2 is not provided. The planar structure of the silicon carbide semiconductor device 71 according to the second embodiment is the same as the structure obtained by removing the field oxide film 21 from Figure 1 , Figure 2 . Figure 5 It corresponds to the cross-sectional structure of the cutting line B-B' of Figure 2 .

[0149] As described above, according to the second embodiment, even if the field oxide film is not provided, no step is generated on the surface of the gate polysilicon layer, so that the same effect as that of the first embodiment can be obtained.

[0150] (Third Embodiment)

[0151] Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. Figure 6 FIG. is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the third embodiment. The silicon carbide semiconductor device 72 according to the third embodiment is different from the silicon carbide semiconductor device 10 according to the first embodiment (see Figures 1 to 4 ) in that the edge 53c' of the step 53 is inclined with respect to the first surface 53a of the front surface of the semiconductor substrate 50 so as to form an obtuse angle. The planar structure of the silicon carbide semiconductor device 72 according to the third embodiment is the same as that of Figure 1 , Figure 2 . Figure 6 It corresponds to the cross-sectional structure at the cutting line B-B' of Figure 2 .

[0152] In the third embodiment, the field oxide film 21' and the gate insulating film 37' are disposed on the edge 53c' of the step 53 and are inclined along the edge 53c'. As a result, the field oxide film 21' can be uniformly deposited on the edge 53c', and the reliability is improved. Therefore, it is possible to prevent the end 21a' of the field oxide film 21' on the chip center side from moving toward the chip center side and being located on the edge p ++ type contact region 35' due to a deviation in the processing accuracy of the field oxide film 21' or the like, or the end 21a' of the field oxide film 21' on the chip center side from moving toward the chip end side and being located on the edge 53c' of the step 53.

[0153] As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained. In addition, according to the third embodiment, by inclining the step edge with respect to the first surface and the second surface of the front surface of the semiconductor substrate so as to form an obtuse angle, between the step edge and the edge p ++ -type contact region, the position of the end portion on the chip center side of the field oxide film extending from the step edge to the first surface of the front surface of the semiconductor substrate can be set with high precision on the p-type base region exposed on the first surface of the front surface of the semiconductor substrate.

[0154] (Fourth Embodiment)

[0155] Next, the structure of the silicon carbide semiconductor device according to the fourth embodiment will be described. Figure 7 FIG. is a plan view showing the layout of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate. Figure 8 FIG. shows Figure 7 The cross-sectional structure of the cutting line D-D'. The silicon carbide semiconductor device 73 according to the fourth embodiment is different from the silicon carbide semiconductor device 10 according to the first embodiment (refer to Figures 1 to 4 ) in that the end portion 21b parallel to the first direction X on the chip center side of the field oxide film 21 is located at the same position as the end portion 14a' on the chip center side of the first portion 14a of the gate polysilicon layer 14.

[0156] Specifically, in the second direction Y parallel to the front surface of the semiconductor substrate 50 and orthogonal to the first direction X, the end portion 21b on the chip center side of the portion of the field oxide film 21 parallel to the first direction X extends toward the chip center side to the same position as the end portion 14a' on the chip center side of the portion of the first portion 14a of the gate polysilicon layer 14 parallel to the first direction X. Therefore, on the portion of the first portion 14a of the gate polysilicon layer 14 parallel to the first direction X, no step caused by the field oxide film 21 is generated on the surface of the first portion 14a of the gate polysilicon layer 14. In Figure 7 , the end portions 21a and 21b on the chip center side of the field oxide film 21 are represented by a thick dotted line thicker than the outer periphery 11a of the source pad 11.

[0157] Thus, at the position parallel to the first direction X of the first portion 14a of the gate polysilicon layer 14, the end portion 21b on the chip center side of the portion parallel to the first direction X of the field oxide film 21 can extend more toward the chip center side than the first portion 14a of the gate polysilicon layer 14 in such a manner that no step caused by the field oxide film 21 is generated on the surface of the first portion 14a of the gate polysilicon layer 14. Therefore, the end portion 21b on the chip center side of the portion parallel to the first direction X of the field oxide film 21 can extend slightly more toward the chip center side than the end portion 14a' on the chip center side of the portion parallel to the first direction X of the first portion 14a of the gate polysilicon layer 14.

[0158] On the other hand, the portion of the first portion 14a of the gate polysilicon layer 14 parallel to the second direction Y is a position opposed to the end of the trench 36 in the depth direction Z. The end portion 21a on the chip center side of the portion parallel to the second direction Y of the field oxide film 21 terminates at a position closer to the chip end side than the portion of the first portion 14a of the gate polysilicon layer 14 parallel to the second direction Y, as in the first embodiment. Therefore, at the portion of the first portion 14a of the gate polysilicon layer 14 parallel to the second direction Y, no step caused by the field oxide film 21 is generated on the surface of the first portion 14a of the gate polysilicon layer 14.

[0159] That is, at the portion of the gate metal layer 13 parallel to the first direction X, directly under the gate metal layer 13, a three-layer structure is formed by sequentially laminating a gate insulating film 37, a field oxide film 21, and the first portion 14a of the gate polysilicon layer 14 on the front surface of the semiconductor substrate 50. At the portion of the gate metal layer 13 parallel to the second direction Y, directly under the gate metal layer 13, a two-layer structure is formed by sequentially laminating a gate insulating film 37 and the first portion 14a of the gate polysilicon layer 14 on the front surface of the semiconductor substrate 50. Therefore, the total film thickness of the insulating films (37, 21) present between the front surface of the semiconductor substrate 50 and the gate polysilicon layer 14 is thicker at the portion parallel to the first direction than at the portion parallel to the second direction Y.

[0160] Thus, when the positions of the end portions 21a and 21b on the chip center side of the field oxide film 21 are different in the first direction X and the second direction Y, steps caused by the field oxide film 21 are generated on the surface of the first portion 14a of the gate polysilicon layer 14 at the corners of the semiconductor substrate 50 (the four vertices of the semiconductor substrate 50 having a substantially rectangular planar shape). In addition to this, due to the arrangement of the gate pads 12, steps caused by the field oxide film 21 are generated on the surface of the third portion 14c of the gate polysilicon layer 14, but the degree of freedom in design is increased for the arrangement of the field oxide film 21.

[0161] In the second part 14b of the gate polysilicon layer 14, similarly to the first embodiment, since there is no field oxide film 21 directly below the second part 14b of the gate polysilicon layer 14, steps caused by the field oxide film 21 are not generated on the surface of the second part 14b of the gate polysilicon layer 14.

[0162] As described above, according to the fourth embodiment, by extending the position of the end portion on the chip center side of the field oxide film toward the chip center side to the same position as the end portion on the chip center side of the first part of the gate polysilicon layer, steps caused by the field oxide film are not generated on the surface of the first part of the gate polysilicon layer, and thus an effect similar to that of the first embodiment can be obtained.

[0163] (Fifth Embodiment)

[0164] Next, the structure of the silicon carbide semiconductor device according to the fifth embodiment will be described. Figures 9 to 12 FIG. is a plan view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front side of the semiconductor substrate. In Figures 9 to 12 , the gate polysilicon layers 14, the end portions 21a, 21b on the chip center side of the field oxide films 21 (only the end portion 21a in Figure 9 ) and the trenches 36 of the silicon carbide semiconductor devices 74 to 77 according to the fifth embodiment are schematically shown, and other components are omitted in the drawing. In addition, the end portions 21a, 21b on the chip center side of the field oxide film 21 are represented by dashed lines.

[0165] The silicon carbide semiconductor devices 74 to 77 according to the fifth embodiment are silicon carbide semiconductor devices showing the positional relationship between the gate polysilicon layers 14 and the end portions 21a, 21b on the chip center side of the field oxide films 21 (only the end portion 21a in Figure 9 ) on each side of the semiconductor substrate 50 having a substantially rectangular planar shape. On each of the four sides of the semiconductor substrate 50, the positional relationship between the gate polysilicon layer 14 and the end portions 21a, 21b on the chip center side of the field oxide film 21 is represented as "retreat" on the side where the first embodiment is applied, and the positional relationship between the gate polysilicon layer 14 and the end portions 21a, 21b on the chip center side of the field oxide film 21 is represented as "advance" on the side where the fourth embodiment is applied.

[0166] That is, regarding the positional relationship between the end portions 21a and 21b on the chip center side of the gate polysilicon layer 14 and the field oxide film 21, the "retreat" in the case of applying Embodiment 1 is the case where the end portion 21a on the chip center side of the field oxide film 21 is located on the chip end side relative to the gate polysilicon layer 14. The "advance" in the case of applying Embodiment 4 is the case where, in the second direction Y, the end portion 21b on the chip center side of the field oxide film 21 is located at the same position as the end portion 14a' on the chip center side of the first portion 14a of the gate polysilicon layer 14.

[0167] Specifically, Figure 9 the silicon carbide semiconductor device 74 of Embodiment 5 shown is the silicon carbide semiconductor device 10 of Embodiment 1 (refer to Figure 1 ). That is, on all four sides of the semiconductor substrate 50, the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "retreat". Although not shown in Figure 9 , the gate polysilicon layer 14 and the field oxide film 21 are arranged separately in the above-described manner (the same applies to the "retreat" part of Figures 10 to 12 ).

[0168] Figure 10 the silicon carbide semiconductor device 75 of Embodiment 5 shown is the silicon carbide semiconductor device 73 of Embodiment 4 (refer to Figure 7 , Figure 8 ). That is, on the two sides of the semiconductor substrate 50 parallel to the first direction X, the positional relationship between the gate polysilicon layer 14 and the end portion 21b on the chip center side of the field oxide film 21 is "advance". Moreover, on the two sides of the semiconductor substrate 50 parallel to the second direction Y, the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "retreat".

[0169] Figure 11 、 Figure 12 In the silicon carbide semiconductor device 76 and semiconductor device 77 of Embodiment 5 shown, on any one of the two sides of the semiconductor substrate 50 parallel to the first direction X, the positional relationship between the gate polysilicon layer 14 and the end portion 21b on the chip center side of the field oxide film 21 is "advance". Moreover, on any one of the two sides of the semiconductor substrate 50 parallel to the first direction X and on the two sides parallel to the second direction Y, the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "retreat".

[0170] On the sides among the four sides of the semiconductor substrate 50 where the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "receded", Embodiment 2 can also be used instead of Embodiment 1. In this case, the field oxide film 21 is not disposed in the silicon carbide semiconductor device 74 of Embodiment 5. In the silicon carbide semiconductor device 75 of Embodiment 5, the field oxide film 21 is disposed only on the two sides of the semiconductor substrate 50 parallel to the first direction X. In the silicon carbide semiconductor devices 76 and 77 of Embodiment 5, the field oxide film 21 is disposed only on any one of the two sides of the semiconductor substrate 50 parallel to the first direction X.

[0171] On the sides among the four sides of the semiconductor substrate 50 where at least the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "receded", Embodiment 3 can be used instead of Embodiment 1. In this case, on the sides among the four sides of the semiconductor substrate 50 where at least the positional relationship between the gate polysilicon layer 14 and the end portion 21a on the chip center side of the field oxide film 21 is "receded", the step edge 53c' of the step 53 can be inclined with respect to the first surface 53a of the front surface of the semiconductor substrate 50 so as to form an obtuse angle.

[0172] As described above, in Embodiment 5, Embodiments 1 to 4 can be applied.

[0173] As mentioned above, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the present invention. For example, the present invention can also be applied to vertical semiconductor devices having a MOS gate, such as planar gate type MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), etc., and has the same effects.

[0174] Industrial Applicability

[0175] As described above, the silicon carbide semiconductor device of the present invention is useful for vertical semiconductor devices having a MOS gate, and is particularly suitable for vertical MOSFETs having a trench gate structure.

Claims

1. A silicon carbide semiconductor device, characterized in that, it comprises: An insulated gate structure, which is disposed on the front side of a semiconductor substrate made of silicon carbide in an active region and has a three-layer structure of metal-oxide-semiconductor of an insulated gate bipolar transistor; A first-conductivity-type semiconductor layer, which constitutes the semiconductor substrate and constitutes the drift region of the insulated gate bipolar transistor; A second-conductivity-type semiconductor layer, which is disposed between the front side of the semiconductor substrate and the first-conductivity-type semiconductor layer, constitutes the semiconductor substrate, and constitutes the base region of the insulated gate bipolar transistor; A trench, which is disposed on the front side of the semiconductor substrate and extends along a first direction parallel to the front side of the semiconductor substrate; The gate electrode of the insulated gate bipolar transistor, which is disposed inside the trench with an insulating film therebetween; A second-conductivity-type high-concentration region, which has an impurity concentration higher than that of the second-conductivity-type semiconductor layer and is disposed in a surface region on the front side of the semiconductor substrate in a terminal region surrounding the active region, and forms a second-conductivity-type junction having an impurity concentration different from that of the second-conductivity-type semiconductor layer; An interlayer insulating film, which is disposed on the entire front side of the semiconductor substrate so as to cover the gate electrode; A first gate polysilicon layer, which is disposed on the front side of the semiconductor substrate with the insulating film therebetween, faces the second-conductivity-type high-concentration region with the insulating film therebetween in the depth direction, surrounds the periphery of the active region in a rectangular shape, and is electrically connected to the gate electrode at an end of the trench and is disposed under the interlayer insulating film; and A field oxide film, which is disposed on the front side of the semiconductor substrate with the insulating film therebetween in the terminal region, extends from the outside to the inside, and surrounds the periphery of the first gate polysilicon layer in a rectangular shape, At least a portion of the four sides of the field oxide film that is parallel to a second direction terminates at a position outside the first gate polysilicon layer, and the second direction is orthogonal to the first direction.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, At least a portion of the field oxide film along at least one of the two sides parallel to the first direction extends inward in the second direction to the same position as the inner end of the first gate polysilicon layer.

3. The silicon carbide semiconductor device according to claim 2, characterized in that, The portion of the field oxide film parallel to the first direction extends inward in the second direction to the same position as the inner end of the first gate polysilicon layer.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The second-conductivity-type high-concentration region terminates at a position inside the second-conductivity-type semiconductor layer, The inner end of at least a portion of the field oxide film parallel to the second direction is at a position outside the second-conductivity-type junction and faces the second-conductivity-type semiconductor layer with the insulating film therebetween in the depth direction.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, Characterized in that, The end portion on the outer side of the first gate polysilicon layer is located within the plane of the second conductivity type high concentration region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 4, Characterized in that, The silicon carbide semiconductor device is flat over the entire surface of the first gate polysilicon layer.

7. The silicon carbide semiconductor device according to any one of claims 1 to 4, Characterized in that, The silicon carbide semiconductor device further includes: A second gate polysilicon layer, which is disposed on the front surface of the semiconductor substrate with the insulating film therebetween in the active region and is connected to the first gate polysilicon layer; and A gate pad, which is disposed on the second gate polysilicon layer with the interlayer insulating film therebetween and is electrically connected to the second gate polysilicon layer, The field oxide film is not disposed between the front surface of the semiconductor substrate and the second gate polysilicon layer.

8. The silicon carbide semiconductor device according to any one of claims 1 to 4, Characterized in that, The insulating film is a high temperature oxide film or a thermal oxide film, The field oxide film is a silicon oxide film, The thickness of the field oxide film is thicker than the thickness of the insulating film.

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