Method of operating a flyback converter, corresponding control circuit, and flyback converter

Abstract

Embodiments of the present disclosure relate to a method of operating a flyback converter, a corresponding control circuit, and a flyback converter. The flyback converter includes two input terminals and two output terminals. A first electronic switch and a primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit includes a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and a secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to a solution for switching the first, second, and third electronic switches to achieve zero-voltage switching of the first electronic switch.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to solutions for operating a flyback converter with active clamping. Background Art

[0002] Electronic converters (e.g., AC / DC or DC / DC switched-mode power supplies) are well known in the art. There are many types of electronic converters, which can be mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic converters are buck, boost, buck-boost, Cuk, SEPIC, and ZETA type converters. In contrast, isolated converters include transformers, such as flyback and forward converters. These types of converters are well known to those skilled in the art.

[0003] For example, Figure 1 An example of a flyback converter 20 with active clamping is shown. In the example considered, the electronic converter 20 includes a first input terminal 200a and a second input terminal 200b for receiving a DC input voltage V in , and a first output terminal 202a and a second output terminal 202b for providing a DC output voltage V out . For example, the input voltage V in can be provided by a DC voltage source 10 such as a battery. Generally, the DC input voltage V in can also be generated from an AC voltage via a rectifier circuit. In turn, the output voltage V out can be used to power an electrical load 30.

[0004] The flyback converter includes a transformer T, and the transformer T includes a primary winding T1 and a secondary winding T2. Specifically, the first terminal of the primary winding T1 (e.g., directly) is connected to the (positive) input terminal 200a, and the second terminal of the primary winding T1 is (e.g., directly) connected to the (negative) input terminal 200b via the current path of an electronic switch S1. The input terminal 200b generally represents ground. Thus, the electronic switch S1 is configured to selectively connect the primary winding to the input terminals 200a and 200b (i.e., the voltage V in ). For example, in the example considered, the electronic switch S1 is implemented using an n-channel field effect transistor (FET) such as an n-channel metal oxide semiconductor field effect transistor (MOSFET) (i.e., NMOS). In this case, the drain terminal of the transistor S1 is connected to the second terminal of the primary winding T1. The second terminal of the primary winding T1 represents the phase node of the flyback converter, and the source terminal of the transistor S1 is connected to the terminal 200b.

[0005] In addition, in the example considered, the electronic switch S3 and the secondary winding T2 are connected in series (e.g., directly) between the output terminals 202a and 202b. For example, the first terminal of the secondary winding T2 can be (e.g., directly) connected to the (positive) output terminal 202a, and the second terminal of the secondary winding T2 can be connected to the (negative) output terminal 202b via the current path of the electronic switch S3. Thus, the electronic switch S3 is configured to selectively connect the secondary winding T2 to the output terminals 202a and 202b. For example, in the example considered, the electronic switch S3 is implemented using an n-channel FET such as an NMOS. In this case, the drain terminal of the transistor S3 can be connected to the second terminal of the secondary winding T2, and the source terminal of the transistor S3 can be connected to the terminal 202b. Those skilled in the art will understand that the switch S3 is typically implemented using a diode.

[0006] In addition, the capacitor C is typically (e.g., directly) connected between the terminals 202a and 202b.

[0007] As is well known, a conventional flyback converter 20 operates using two switching states. When the switch S1 is closed and the switch S3 is open, the primary winding T1 of the transformer T1 is directly connected to the input voltage V in . Thus, the primary current Ipri and the magnetic flux in the transformer T increase, thereby storing energy in the transformer T. Under this condition, the capacitor C supplies energy to the output terminals 202a and 202b (i.e., the load 30). Conversely, when the switch S1 is open and the switch S3 is closed, the primary current Ipri drops to zero while current begins to flow in the secondary winding, and the energy from the transformer core T charges the capacitor C and supplies power to the load 30.

[0008] However, this hard switching of the switch S1 has the disadvantage that the switch S1 is not closed at zero voltage. Thus, flyback converters including an active clamp circuit have been proposed.

[0009] Specifically, in Figure 1In [the circuit], the flyback converter 20 further includes a series connection of a clamping capacitor C2 and an electronic switch S2, and this series connection of the clamping capacitor C2 and the electronic switch S2 is connected in parallel with the primary winding T1 of the transformer T, that is, the electronic switch S2 is configured to selectively connect the capacitor C2 in parallel with the primary winding T1. Specifically, in the example under consideration, the first terminal of the primary winding T1 (e.g., directly) is connected to the first terminal of the capacitor C2, and the second terminal of the primary winding T1 (i.e., the phase node / midpoint between the primary winding T1 and the electronic switch S1) is connected to the second terminal of the capacitor C2 via the current path of the electronic switch S2 (e.g., directly). For example, in the example under consideration, the electronic switch S2 is implemented using an n-channel FET such as an NMOS. In this case, the drain terminal of the transistor S2 can be connected to the second terminal of the capacitor C2, and the source terminal of the transistor S2 can be connected to the phase node / second terminal of the primary winding T1.

[0010] Generally, the electronic switches S1, S2, and S3 are driven via respective drive signals LSGD, HSGD, and SRGD, and the drive signals are generated by a suitable control circuit 210 to, for example, be a function of the output voltage V at terminals 202a and 202b. out For example, such an active clamping circuit (including the capacitor C2 and the switch S2) and the corresponding operation of the flyback converter are described in the document US2011 / 0305048A1. Basically, the active clamping circuit allows the recovery of the energy in the leakage inductance of the transformer T and allows the implementation of soft switching of the electronic switch S1.

[0011] As previously described, in an ideal flyback converter, when the control circuit 210 turns off the electronic switch S1, since the control circuit 210 closes the electronic switch S3, the current Ipri in the primary winding T1 immediately stops, and at the same time, the current starts to flow in the secondary side T2. Anyway, in an actual transformer T, the two windings T1 and T2 are not perfectly coupled, and a leakage inductance remains on the primary side. Basically, such a leakage inductance L S can be simulated by an inductor connected in series with the primary winding T1. Conversely, the magnetizing inductance L of the transformer T M (for simulating the magnetic flux) can be simulated by an inductor connected in parallel with the primary winding T1.

[0012] Therefore, when the control circuit 210 turns off the electronic switch S1, due to the leakage inductance Ls, the primary current Ipri continues to flow in the primary side T1, thereby creating a spike on the primary winding T1. Specifically, the electronic switch S1 has an associated parasitic capacitance C1 (e.g., the parasitic drain-source capacitance of the corresponding FET) connected in parallel with the electronic switch S1. Therefore, the current provided by the leakage inductance L S of the transformer T will charge this capacitance C1. Typically, such a spike is followed by ringing, which decays due to losses in the system until all the energy stored in the leakage inductance L S is dissipated (when the electronic switch S1 has been turned off).

[0013] Basically, the addition of the electronic switch S2 and the capacitor C2 allows the energy in the leakage inductance LS to be shifted to the clamping capacitor C2. Specifically, when the control circuit 210 turns off the electronic switch S1, the phase node (which is between the primary winding T1 and the electronic switch S1, e.g., the drain terminal of the transistor S1) rises as in a normal flyback converter (which does not have active clamping). Anyway, when the voltage on the phase node bypasses the voltage on the clamping capacitor C2, the body diode of the electronic switch S2 (or a similar diode D2 connected in parallel with the electronic switch S2) turns on, and the primary current Ipri also flows into the capacitor C2 until the primary current Ipri drops to zero. By turning on the electronic switch S2, the energy stored on the capacitor C2 can be returned to the system.

[0014] For example, typically, the control circuit 210 is configured to control the active clamping in a complementary mode, i.e., when the electronic switch S1 is closed, the electronic switch S2 is open, and when the electronic switch S1 is open, (usually after a short dead time) the electronic switch S2 is closed.

[0015] The inventors have observed that this complementary control has some drawbacks. For example, since current flows both when the electronic switch S1 is closed and when the electronic switch S2 is closed, the current Ipri generated on the primary side typically has a very high root mean square (RMS) value. SUMMARY OF THE INVENTION

[0016] In view of the foregoing, an object of various embodiments of the present disclosure is to provide a solution for operating a flyback converter with active clamping.

[0017] According to one or more embodiments, the above object is achieved by a method of operating a flyback converter having unique elements specifically set forth in the appended claims. Embodiments also relate to corresponding control circuits and flyback converters.

[0018] The claims form part of the technical teaching of the specification provided herein.

[0019] As previously mentioned, various embodiments of the present disclosure relate to solutions for operating a flyback converter with active clamping.

[0020] In various embodiments, the flyback converter includes a first input terminal and a second input terminal for receiving an input voltage, and a first output terminal and a second output terminal for providing an output voltage. The flyback converter further includes a transformer having a primary winding and a secondary winding, wherein a leakage inductance and a magnetizing inductance are associated with the transformer.

[0021] In various embodiments, a first electronic switch and the primary winding are connected in series between the first input terminal and the second input terminal, wherein an intermediate node between the first electronic switch and the primary winding represents a phase node, and a capacitor is associated with the phase node. For example, the first electronic switch can be an n-channel FET.

[0022] In various embodiments, the active clamping circuit is connected in parallel with the primary winding, wherein the active clamping circuit includes a series connection of a clamping capacitor and a second electronic switch. For example, the second electronic switch can be an n-channel FET.

[0023] In various embodiments, a third electronic switch and the secondary winding are connected in series between the first output terminal and the second output terminal. For example, the third electronic switch can be an n-channel FET or a diode.

[0024] In various embodiments, the control circuit of the electronic converter can thus repeat the following steps for each switching cycle:

[0025] During a first time interval, close the first electronic switch and open both the second electronic switch and the third electronic switch, whereby the primary winding is connected to the input voltage and the current flowing through the primary winding increases, thereby storing energy in the transformer;

[0026] During a subsequent second time interval, open the first electronic switch, the second electronic switch, and the third electronic switch, whereby the current flowing through the primary winding charges the capacitor associated with the phase node;

[0027] During a subsequent third time interval, open the first electronic switch and close both the second electronic switch and the third electronic switch, whereby the clamping capacitor is connected in parallel with the primary winding and the current flowing through the primary winding also charges the clamping capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero.

[0028] During a subsequent fourth time interval, the third electronic switch is closed and both the first and second electronic switches are opened, whereby the current flowing through the primary winding becomes zero and the energy stored in the transformer is released via the current flowing through the secondary winding, where the fourth time interval ends when the current flowing through the secondary winding reaches zero.

[0029] During a subsequent fifth time interval, the first electronic switch is opened and both the second and third electronic switches are closed, whereby the clamping capacitor is connected in parallel with the primary winding, whereby the clamping capacitor and the leakage inductance form a resonant circuit having a given resonant period, and where the fifth time interval ends after one or more half - periods of the resonant period;

[0030] During a subsequent sixth time interval, the second electronic switch is closed and the first and third electronic switches are opened, whereby the current flowing through the primary winding decreases, and where the sixth time interval ends when the current flowing through the primary winding is negative; and

[0031] During a subsequent seventh time interval, the first, second, and third electronic switches are opened, whereby the negative current flowing through the primary winding discharges the capacitance associated with the phase node.

[0032] Typically, the second electronic switch may include a diode. In this case, the second electronic switch can be closed during the third time interval by closing the diode. Similarly, the third electronic switch may include a diode or even consist of a diode. In this case, the third electronic switch can be closed during at least one (or even all) of the third, fourth, and fifth time intervals by closing the diode.

[0033] In various embodiments, the control circuit can control the duration of the sixth time interval by determining a reference value of the current flowing through the primary winding during the sixth time interval and ending / stopping the sixth time interval when the current flowing through the primary winding exceeds a given reference value, the reference value indicating the energy for discharging the capacitance. Alternatively, the control circuit can determine the duration of the sixth time interval as a function of the duty cycle of the flyback converter, the duty cycle corresponding to the ratio between the duration of the first time interval and the duration of the switching period, and ending / stopping the sixth time interval after the determined duration of the sixth time interval.

[0034] In various embodiments, the capacitance value of the clamping capacitor should thus be selected in a suitable manner. For example, in various embodiments, the maximum value of the output voltage and the minimum value of the input voltage are determined / obtained based on the product specifications of the electronic converter, for instance. Next, the minimum clamping time is determined as a function of the maximum value of the output voltage and the minimum value of the input voltage, and the capacitance value of the clamping capacitor is selected such that the half period of the resonance period of the clamping capacitor and the leakage inductance is shorter than the minimum clamping time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, and in which:

[0036] Figure 1 shows an example of a flyback converter including an active clamp;

[0037] Figures 2A to 2D shows Figure 1 an embodiment of the control of a flyback converter;

[0038] Figures 3A to 3E and Figure 4 shows Figure 8 an embodiment of the control of a flyback converter;

[0039] Figure 5A , Figure 5B and Figure 6 shows Figure 8 an embodiment of the control of a flyback converter;

[0040] Figure 7 shows Figure 8 an embodiment of the control of a flyback converter; and

[0041] Figure 8 shows a flyback converter including an active clamp according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In the following description, various specific details are set forth in order to provide a thorough understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0043] References to "an embodiment" or "one embodiment" in the context of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases such as "in an embodiment" or "in one embodiment" that may appear in various aspects of this specification do not necessarily refer to the same embodiment. In addition, a particular configuration, structure, or characteristic may be combined in one or more embodiments in any suitable manner.

[0044] The reference numerals used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

[0045] In the following description of FIGS. 2 to Figure 8 in, components, elements, or assemblies that have been described are designated by the same reference numerals as previously used in these figures. These elements have been described and will not be repeated in the following so as not to make the detailed description of the present invention cumbersome. Figure 1

[0046] Various embodiments of this specification relate to the operation of a flyback converter including an active clamp. The overall architecture of such a flyback converter 20 is shown in Figure 1 in, and its corresponding description, particularly regarding the connection of the flyback converter (transformer T, electronic switches S1 and S3, and capacitor C) to the active clamp (electronic switches S2 and capacitor C2), applies as a whole. In this regard, this specification relates to the control implemented within the control circuit 210. Specifically, such a control circuit can be any suitable analog and / or digital processing circuit, including an application-specific integrated control circuit or a programmable processing unit (e.g., a microprocessor programmed via software instructions).

[0047] As previously mentioned, the control circuit 210 can drive such an active clamp using complementary control, which generally includes four phases that are periodically repeated:

[0048] During a first time interval Δt1, the electronic switch S1 is closed and the electronic switch S2 is open;

[0049] During a second (dead time) interval Δt2, the electronic switch S1 is open and the electronic switch S2 remains open;

[0050] During a third time interval Δt3, the electronic switch S1 remains open and the electronic switch S2 is closed; and

[0051] During a fourth (dead time) interval Δt4, the electronic switch S1 remains open and the electronic switch S2 is open.

[0052] As Figure 2A ​As schematically shown, during the time interval Δt1, the current Ipri in the primary side flows through the transformer T and linearly increases at the following rate:

[0053] dIpri / dt = V in / Lpri

[0054] where Lpri represents the equivalent inductance at the primary side, Lpri = L S +L M .

[0055] As Figure 2B schematically shown, during the time interval Δt2, both of the primary-side electronic switches S1 and S2 are turned off. The current Ipri flows through the primary side of the transformer T and the parasitic capacitor C1 at the phase node (between the transformer T and the electronic switch S1), thereby increasing the voltage Vlsd at this node, and the voltage Vlsd at this node corresponds, for example, to the drain-source voltage of the corresponding lower-side FET S1.

[0056] As Figure 2C schematically shown, during the time interval Δt3, the current Ipri flows through the primary side T1. By providing the leakage inductance LS and the clamping capacitor C2 of the transformer T with appropriate specifications, oscillations can be generated by these components.

[0057] Meanwhile, the difference between the magnetizing current I M flowing through the magnetizing inductance L LM and the leakage current I S flowing through the leakage inductance L LS flows as the secondary current Isec through the secondary side T2 of the transformer T in a proportional form due to the turns ratio n of the transformer T.

[0058] As Figure 2D schematically shown, during the time interval Δt4, when the primary-side current Ipri is negative, by turning off the electronic switch S2 at the end of the interval Δt3, this negative current flows through the transformer T and the parasitic capacitor C1 at the phase node, thereby discharging the parasitic capacitor C1. If the energy in the magnetizing L M and / or the leakage inductance L S is high enough when the electronic switch S2 is turned off at the end of the interval Δt3, the phase node drops to zero, thereby allowing the electronic switch S1 to perform full zero-voltage switching (ZVS) at the start of the subsequent interval Δt1.

[0059] As previously mentioned, such complementary control has several disadvantages. However, the inventors have observed that active clamping can also be driven using non-complementary control.

[0060] Figure 8FIG. 0 shows a flyback converter 30 according to an embodiment of the present disclosure. The flyback converter 30 includes a control circuit 310 for driving an active clamp using non-complementary control.

[0061] Specifically, as Figure 3A schematically shown, by closing the electronic switch S1 (switches S2 and S3 are open) during the time interval Δt1, the current Ipri in the primary side flows through the transformer T and linearly increases. Basically, this stage is not changed compared with Figure 2A the complementary control shown.

[0062] As Figure 3B schematically shown, during the second time interval Δt2’, the control circuit 310 keeps all the electronic switches S1, S2 and S3 open. However, when using an FET to implement the electronic switch S2, at the end of this stage, the current Ipri in the primary side leakage inductance is directed to the clamp capacitor C2 through the body diode of the transistor S2 (or a similar diode D2 connected in parallel with the electronic switch S2) until the current Ipri drops to zero.

[0063] As Figure 3C schematically shown, during the third time interval Δt3a’, the high-side switch S2 remains open (or can remain on during the period when the diode associated with the switch S2 is on), while the rectifier switch S3 is turned on. Basically, during this stage, no current can flow in the primary side (Ipri = 0), and the current flows to the output on the secondary side T2. Basically, this stage corresponds to the flyback stage of a conventional flyback converter.

[0064] As Figure 3D schematically shown, when the current Isec on the secondary side T2 reaches zero, the control circuit 310 turns on the high-side switch S2, thus starting the fourth time interval Δt3b’. Basically, at the beginning of this interval, the voltage on the clamp capacitor C2 is slightly higher than the voltage reflected from the secondary side, whereby the current Isec on the secondary side starts to increase again. Basically, under this condition, resonance may occur again between the clamp capacitor C2 and the leakage inductance L S Meanwhile, the current I M on the magnetizing inductance L LM becomes negative.

[0065] After a preferably long enough time to provide sufficient energy in the magnetizing inductance L M to force soft switching, both the rectifier (S3) and the high-side (S2) electronic switches are turned off, thus terminating the fourth time interval Δt3b’.

[0066] Therefore, as Figure 3ESchematically, by turning off the electronic switch S2 at the end of the interval Δt3b’, when the excitation current I LM is negative, this negative current flows through the transformer T and the parasitic capacitance C1 at the phase node, so that at the start of the subsequent interval Δt1, the parasitic capacitance C1 is discharged and full zero-voltage switching of the electronic switch S1 is allowed.

[0067] In this regard, Figure 4 an embodiment is shown of the waveforms of the secondary-side current Isec, the primary-side current Ipri (also including a part of the excitation current ILM), the voltage Vlsd at the phase node (between the primary winding T1 and the electronic switch S1), and the drive signals LSGD, HSGD, and SRGD for the switches S1, S2, and S3 respectively.

[0068] The inventors have observed that such non-complementary control allows low ringing on the secondary side T2 to be achieved by, for a given input voltage V in and output voltage V out , by tuning the transformer ratio n (the ratio between the windings of the primary winding T1 and the secondary winding T2) and the clamping capacitance C2. However, what the inventors have observed is that it is difficult to provide a match for a wide range of input / output voltages.

[0069] Figure 6 An embodiment of the modified control implemented within the control circuit 310 is shown.

[0070] Specifically, during a first time interval Δt1, the control circuit generates the drive signals LSGD, HSGD, and SRGD so as to close the electronic switch S1 and open the electronic switches S2 and S3. Basically, this phase remains unchanged compared to the control shown in Figure 2A and Figure 3A . Thus, the primary winding T1 is connected to the input voltage V in , and the current Ipri in the primary side T1 increases linearly. As will be described in more detail below, in various embodiments, the control circuit 310 can change the duration of the time interval Δt1 in order to regulate the output voltage V out to a given reference value, which given reference value indicates the requested output voltage.

[0071] During a second time interval Δt2a, the control circuit 310 keeps all the electronic switches S1, S2, and S3 open. Thus, at the end of the interval Δt1, the (positive) current Ipri in the primary-side leakage inductance charges the parasitic capacitance C1, and the voltage Vlsd at the phase node increases.

[0072] When the voltage Vlsd at the phase node reaches a given threshold, the electronic switch S2 closes. Specifically, for this purpose, the control circuit 310 can set the control signal HDGD to directly close the electronic switch S2, or the electronic switch S2 can automatically close via a corresponding diode D2 (e.g., the body diode of a corresponding FET) connected in parallel with the electronic switch S2. For example, using such a diode D2 has the advantage that the control circuit 310 does not necessarily need to monitor the voltage at the phase node.

[0073] Accordingly, during a subsequent third time interval Δt2b, the current Ipri in the primary-side leakage inductance is also supplied to the clamping capacitor C2 until the current Ipri drops to zero. For example, for this purpose, the control circuit 310 can monitor the current Ipri and determine when the current Ipri reaches zero. As Figure 8 shown, the control circuit 310 can have a first input coupled to the transformer T to detect the current Ipri, for example, via a sense resistor (not shown).

[0074] In the embodiment under consideration, during the time interval Δt2b, the control circuit 310 closes the electronic switch S3, thereby allowing current to flow on the secondary side T2 of the transformer T. As will be described in more detail below, the electronic switch S3 can also be implemented only using the diode D3, or the diode D3 can be connected in parallel with the electronic switch S3, such as the body diode of a corresponding FET. Accordingly, the drive signal SRGD may not be required either, so the drive signal SRGD is only optional.

[0075] Accordingly, the time intervals Δt2a and Δt2b basically correspond to the second time interval Δt2’ described with respect to Figure 3B description.

[0076] Correspondingly, in the embodiment under consideration, at the end of the interval Δt2b, the primary-side current Ipri reaches zero, and the secondary-side current Isec reaches its maximum peak value.

[0077] During a subsequent time interval Δt3a’, the electronic switches S1 and S2 are thus turned off, and the electronic switch S3 is closed. Accordingly, the primary-side current Ipri remains zero while the current Isec flows to the output on the secondary side T2. Specifically, the time interval Δt3a’ ends when the secondary-side current Isec reaches zero. For example, for this purpose, the control circuit 310 can monitor the current Isec and determine when the current Isec reaches zero. As can be seen in Figure 8 it, the control circuit 310 can have a second input coupled to the drain of the electronic switch S3 to detect the current Isec, for example, via a sense resistor (not shown).

[0078] Basically, the time interval Δt3a’ corresponds to the flyback phase that has been described with respect to Figure 3C However, compared to the embodiments described with respect to FIGS. 3 and Figure 4 the operation is changed for the following time intervals.

[0079] Specifically, similar to Figure 3D the control circuit 310 then closes the electronic switch S2 during the time interval Δt3c.

[0080] Specifically, as Figure 5A shown, during this switching state, the electronic switch S1 is open, and the electronic switches S2 and S3 are closed. Thus, this switching state more or less corresponds to the switching state described with respect to Figure 3D but it has some substantial differences that will be described in more detail below.

[0081] Specifically, at the start of this interval Δt3c, the voltage on the clamping capacitor C2 is slightly higher than the voltage reflected from the secondary side, whereby the current Isec on the secondary side starts to increase again. In addition, under these conditions, there is a resonance between the clamping capacitor C2 and the leakage inductance LS of the transformer. Specifically, this resonance has a period Tres, which corresponds to:

[0082]

[0083] At the same time, the current I M on the magnetizing inductance L LM becomes negative.

[0084] However, with respect to Figure 3D in the embodiment under consideration, the time interval Δt3c ends after Tres / 2, i.e., after half a period of the oscillation of the clamping capacitor C2 and the leakage inductance L S In various embodiments, the control circuit 310 can determine the end of the time interval Δt3c by determining whether the current Isec reaches zero again, or the duration of the time interval Δt3c can be fixed at Tres / 2.

[0085] Thus, while in Figure 3D the currents at the primary and secondary sides are cut off, in the currently considered embodiment, the time interval Δt3c ends at the moment when the secondary side current Isec reaches zero.

[0086] Thus, at the start of the subsequent time interval Δt3d, the control circuit 310 can open the electronic switch S3 with zero current.

[0087] The corresponding switching state during the interval Δt3d is shown in Figure 5BIt is shown in. Specifically, during the interval Δt3d, the electronic switches S1 and S3 are turned off, and the electronic switch S2 remains closed.

[0088] In various embodiments, the duration of this phase Δt3d is determined by the energy to be stored in the magnetizing inductance LM of the transformer to obtain soft switching of the electronic switch S1 in the next phase.

[0089] The inventors have observed that the energy E used to obtain such soft switching SS can be approximated as

[0090]

[0091] Starting from zero crossing (at the end of the interval Δt3a' / beginning of the interval Δt3c), the current in the exciting inductor L M increases approximately

[0092]

[0093] where n is the turns ratio between the primary winding and the secondary winding, and tclamp is the total clamping time, which corresponds to the sum of the durations of the intervals Δt3c and Δt3d (i.e., tclamp = Δt3c + Δt3d).

[0094] The energy E in the exciting inductor LM LM is:

[0095]

[0096] That is, by combining equations (3) and (4):

[0097]

[0098] Therefore, in order to obtain an energy E in the exciting inductor equal to the energy E SS in the exciting inductor, the total clamping time can be calculated according to equations (2) and (5) as: LM That is, by combining equations (3) and (4):

[0099]

[0100] Therefore, equation (6) can be used to calculate the total clamping duration t clamp . Alternatively, equations (2) and (4) can be used to determine the threshold of the current Ipri at the primary side (which corresponds to the exciting current I during the interval Δt3d LM ), and the control circuit 310 can monitor the primary side current Ipri, and when the primary side current Ipri reaches a given threshold, the control circuit 310 can end the interval Δt3d.

[0101] Thus, at the end of the interval Δt3d, the primary current Ipri is negative and the excitation inductor LM has stored enough energy to discharge the parasitic capacitance C1 associated with the phase node.

[0102] During the subsequent time interval Δt4, the control circuit 310 can thus switch off the electronic switch S2. Thus, during the time interval Δt4 (which essentially corresponds to the situation already Figure 2D and Figure 3E described), the negative primary current Ipri flows through the transformer T and the parasitic capacitance C1 at the phase node, thereby discharging the parasitic capacitance C1. Furthermore, when the voltage Vlsd at the phase node reaches zero, the control circuit 310 can close the electronic switch S1 again, thereby starting the subsequent time interval Δt1. For this purpose, for example, the control circuit 310 can monitor the voltage at the phase node. Usually, the duration of the time interval Δt4 can also be fixed.

[0103] Thus, in the considered embodiment, each switching period has the following switching durations T SW :

[0104] T SW = Δt1 + Δt2a + Δt2b + Δt3a’ + Δt3c + Δt3d + Δt4.

[0105] In the considered embodiment, the electronic switch S3 is closed when the secondary current Isec is positive (intervals Δt2b, Δt3a’ and Δt3c). Thus, the electronic switch S3 can also be implemented using the diode D3 or a diode connected in parallel with the electronic switch S3 (e.g., the body diode of the corresponding FET), where:

[0106] The anode of the diode D3 is connected to the terminal 202b and the cathode is connected to the secondary winding T2 (as Figure 1 shown), or

[0107] The anode of the diode is connected to the secondary winding T2 and the cathode is connected to the terminal 202a.

[0108] Furthermore, as previously mentioned, the start and end of the interval Δt2b can be carried out automatically by connecting the diode D2 (e.g., the body diode of the corresponding FET) in parallel with the electronic switch S2, where the anode is connected to the phase node and the cathode is connected to the capacitor C2.

[0109] Thus, in various embodiments, the control circuit 310 can generate the control signals LSGD and HSGB in order to control the duration Δt1 (electronic switch S1 closed) and the duration t clamp= Δt3c + Δt3d (when electronic switch S2 is closed). Generally, in the considered embodiment, when the secondary side current Isec reaches zero, the control circuit 310 should also determine the end of the interval Δt3a'.

[0110] Specifically, the control circuit 310 can vary the duration Δt1 in order to obtain a given output voltage V out . In fact, in a flyback converter, the ratio between the input voltage and the output voltage V in / V out is proportional to the term D / (1 - D), where D = Δt1 / T SW is the duty cycle.

[0111] Conversely, as described with respect to equation (6), the duration t clamp should also take into account the ratio V in / V out . Thus, instead of measuring the input voltage V in , the duration t clamp can be calculated by multiplying a fixed parameter by D / (1 - D), i.e., the control circuit 310 can determine the duration t clamp as a function of the duty cycle D, which in turn is determined as a function of the duration Δt1.

[0112] In the considered embodiment, the clamping capacitor C2 should thus be customized to store sufficient energy on the primary side T1 to achieve the ZVS condition, but should be small enough to complete the half-resonance with the leakage inductance LS during the phase Δt3c.

[0113] Specifically, as shown in equation (1), the minimum clamping duration is determined by the values of the clamping capacitor C2 and the leakage inductance LS. Generally, the inventors have observed that it is desirable to keep this duration as short as possible so that soft switching can be obtained under the condition of the shortest clamping time, which, as shown in equation (6), occurs under the operating conditions where the input voltage V in has its minimum value and the output voltage V out has its maximum value.

[0114] The inventors have observed that in the case of a synchronous rectifier on the secondary side, this control gives the best results, and this control can even be applied to systems with non-synchronous rectification.

[0115] Figure 7Shows a second embodiment of the drive implemented within the control circuit. Specifically, as previously described, when the secondary side current Isec reaches zero, the control circuit 310 determines the end of the interval Δt3c, for example, by monitoring the secondary side current Isec or by using a fixed duration for the interval Δt3c (corresponding to Tres / 2).

[0116] However, as Figure 7 shown, the control circuit 310 does not necessarily have to terminate the interval Δt3c (interval Δt3c’ in Figure 7 ) after the first half cycle of the resonance Tres. Instead, the control circuit 310 can terminate the interval Δt3c’ after a multiple of Tres / 2, i.e., at a moment corresponding to a plurality of half cycles of the oscillation. In fact, at each of these moments, the secondary side current Isec will be zero. Thus, in various embodiments, the control circuit 310 can determine the end of the time interval Δt3c’ by determining whether the current Isec has reached zero a given number N of times, or the duration of the time interval Δt3c can be fixed at N·Tres / 2, where N is a positive integer. For example, in FIG. 2, the duration of the interval Δt3c’ corresponds to Tres (i.e., N = 2).

[0117] Of course, without prejudice to the principles of the present disclosure, details of the construction and embodiments can vary widely relative to what is described and shown herein by way of example only, without departing from the scope of the present disclosure.

[0118] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments in accordance with the above detailed description. Generally, in the claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which the claim is entitled. Thus, the claims are not limited by the present disclosure.

Claims

1. A method of operating a flyback converter, comprising: During a first time interval of a switching cycle, closing a first electronic switch and opening a second electronic switch and a third electronic switch, the first electronic switch being connected to a primary winding of a transformer between a first input terminal and a second input terminal for receiving an input voltage, the first electronic switch and the primary winding being coupled to each other at a phase node, and a capacitor being associated with the phase node, the second electronic switch and a clamping capacitor being connected to each other as an active clamping circuit, the active clamping circuit being connected in parallel with the primary winding, the third electronic switch and the secondary winding of the transformer being connected between a first output terminal and a second output terminal for providing an output voltage, wherein closing the first electronic switch during the first time interval electrically couples the primary winding to the input voltage and causes the current flowing through the primary winding to increase, thereby storing energy in the transformer; During a subsequent second time interval of the switching cycle, opening the first electronic switch and keeping the second electronic switch open and the third electronic switch open, whereby the current flowing through the primary winding charges the capacitor associated with the phase node; During a subsequent third time interval of the switching cycle, keeping the first electronic switch open and closing the second electronic switch and the third electronic switch, which electrically couples the clamping capacitor to the primary winding, and the current flowing through the primary winding also charges the clamping capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero; During a subsequent fourth time interval of the switching cycle, keeping the first electronic switch open and keeping the third electronic switch closed and opening the second electronic switch, whereby the current flowing through the primary winding is zero and the energy stored in the transformer is released via the current flowing through the secondary winding, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero; During a subsequent fifth time interval of the switching cycle, keeping the first electronic switch open, closing the second electronic switch, and keeping the third electronic switch closed, whereby the clamping capacitor is electrically coupled in parallel with the primary winding, whereby the clamping capacitor and the leakage inductance of the transformer form a resonant circuit having a given resonant period, and wherein the fifth time interval ends after one or more half-cycles of the resonant period; During a subsequent sixth time interval of the switching cycle, keeping the first electronic switch open, keeping the second electronic switch closed, and opening the third electronic switch, whereby the current flowing through the primary winding decreases, and wherein the sixth time interval ends when the current flowing through the primary winding is negative; and During a subsequent seventh time interval of the switching cycle, keep the first electronic switch open and the third electronic switch open, and open the second electronic switch, whereby the negative current flowing through the primary winding discharges the capacitor associated with the phase node.

2. The method according to claim 1, wherein the second electronic switch includes a diode, and wherein closing the second electronic switch during the third time interval includes closing the diode.

3. The method according to claim 1, wherein the third electronic switch includes a diode, and wherein closing the third electronic switch during at least one of the third time interval, the fourth time interval, and the fifth time interval includes closing the diode.

4. The method according to claim 1, comprising: determining a given reference value for the current flowing through the primary winding during the sixth time interval, the given reference value indicating the energy for discharging the capacitor; and ending the sixth time interval when the current flowing through the primary winding exceeds the given reference value.

5. The method according to claim 1, comprising: determining the duration of the sixth time interval as a function of the duty cycle of the flyback converter, the duty cycle corresponding to the ratio between the duration of the first time interval and the duration of the switching cycle; and ending the sixth time interval after the duration of the sixth time interval.

6. The method according to claim 1, comprising: obtaining a maximum value for the output voltage and a minimum value for the input voltage; determining a minimum clamp time as a function of the maximum value for the output voltage and the minimum value for the input voltage; and selecting a capacitance value of the clamp capacitor such that a half period of the resonance period of the clamp capacitor and the leakage inductance is shorter than the minimum clamp time.

7. A control circuit for a flyback converter, the flyback converter comprising: a first input terminal and a second input terminal for receiving an input voltage; a first output terminal and a second output terminal for providing an output voltage; a transformer having a primary winding, a secondary winding, and a leakage inductance; a first electronic switch coupled to the primary winding between the first input terminal and the second input terminal; a phase node between the first electronic switch and the primary winding; a capacitor associated with the phase node; an active clamp connected to the primary winding and including a connection of a clamp capacitor and a second electronic switch; a third electronic switch electrically coupled to the secondary winding between the first output terminal and the second output terminal, the control circuit being configured to: During a first time interval of a switching cycle, the first electronic switch is closed, and the second and third electronic switches are opened, wherein the first electronic switch closed during the first time interval electrically couples the primary winding to the input voltage and causes the current flowing through the primary winding to increase, thereby storing energy in the transformer; During a subsequent second time interval of the switching cycle, the first electronic switch is opened, and the second and third electronic switches are kept open, whereby the current flowing through the primary winding charges the capacitor associated with the phase node; During a subsequent third time interval of the switching cycle, the first electronic switch is kept open, and both the second and third electronic switches are closed, which electrically couples the clamping capacitor to the primary winding, and the current flowing through the primary winding also charges the clamping capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero; During a subsequent fourth time interval of the switching cycle, the first electronic switch is kept open, the third electronic switch is kept closed, and the second electronic switch is opened, whereby the current flowing through the primary winding is zero, and the energy stored in the transformer is released via the current flowing through the secondary winding, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero; During a subsequent fifth time interval of the switching cycle, the first electronic switch is kept open, the second electronic switch is closed, and the third electronic switch is kept closed, whereby the clamping capacitor is electrically coupled in parallel with the primary winding, whereby the clamping capacitor and the leakage inductance form a resonant circuit having a given resonant period, and wherein the fifth time interval ends after one or more half periods of the resonant period; During a subsequent sixth time interval of the switching cycle, the first electronic switch is kept open, the second electronic switch is kept closed, and the third electronic switch is opened, whereby the current flowing through the primary winding decreases, and wherein the sixth time interval ends when the current flowing through the primary winding is negative; and During a subsequent seventh time interval of the switching cycle, the first and third electronic switches are kept open, and the second electronic switch is opened, whereby the negative current flowing through the primary winding discharges the capacitor associated with the phase node.

8. The control circuit according to claim 7, wherein the second electronic switch includes a diode, and wherein the control circuit is configured to close the second electronic switch by closing the diode during the third time interval.

9. The control circuit according to claim 7, wherein the third electronic switch includes a diode, and wherein the control circuit is configured to close the third electronic switch by closing the diode during at least one of the third time interval, the fourth time interval, and the fifth time interval.

10. The control circuit according to claim 7, wherein the control circuit is configured to: when the current flowing through the primary winding exceeds a given reference value, end the sixth time interval, the given reference value indicating the energy for discharging the capacitor.

11. The control circuit according to claim 7, wherein the control circuit is configured to: end the sixth time interval after a duration, the duration being a function of the duty cycle of the flyback converter, the duty cycle corresponding to the ratio between the duration of the first time interval and the duration of the switching period.

12. The control circuit according to claim 7, wherein the control circuit is configured to: detect when the current flowing through the secondary winding reaches zero; and in response to detecting that the current flowing through the secondary winding has reached zero, end the fourth time interval.

13. A flyback converter, comprising: a first input terminal and a second input terminal for receiving an input voltage; a first output terminal and a second output terminal for providing an output voltage; a transformer including a primary winding and a secondary winding, wherein a leakage inductance and a magnetizing inductance are associated with the transformer; a first electronic switch connected to the primary winding between the first input terminal and the second input terminal, wherein the first electronic switch and the primary winding are connected to each other through a phase node, and wherein a capacitor is associated with the phase node; an active clamp circuit connected to the primary winding, the active clamp circuit including a clamp capacitor and a second electronic switch connected in series; a third electronic switch connected to the secondary winding between the first output terminal and the second output terminal; and a control circuit configured to: during a first time interval of a switching period, close the first electronic switch and open the second electronic switch and the third electronic switch, wherein the first electronic switch closed during the first time interval electrically couples the primary winding to the input voltage and causes the current flowing through the primary winding to increase, thereby storing energy in the transformer; during a subsequent second time interval of the switching period, open the first electronic switch and keep the second electronic switch and the third electronic switch open, whereby the current flowing through the primary winding charges the capacitor associated with the phase node; During a subsequent third time interval of the switching cycle, the first electronic switch is kept open, and both the second and the third electronic switches are closed, which electrically couples the clamping capacitor to the primary winding, and the current flowing through the primary winding also charges the clamping capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero; During a subsequent fourth time interval of the switching cycle, the first electronic switch is kept open, the third electronic switch is kept closed, and the second electronic switch is opened, whereby the current flowing through the primary winding becomes zero, and the energy stored in the transformer is released via the current flowing through the secondary winding, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero; During a subsequent fifth time interval of the switching cycle, the first electronic switch is kept open, the second electronic switch is closed, and the third electronic switch is kept closed, whereby the clamping capacitor is electrically coupled in parallel with the primary winding, whereby the clamping capacitor and the leakage inductance form a resonant circuit having a given resonant period, and wherein the fifth time interval ends after one or more half - periods of the resonant period; During a subsequent sixth time interval of the switching cycle, the first electronic switch is kept open, the second electronic switch is kept closed, and the third electronic switch is opened, whereby the current flowing through the primary winding decreases, and wherein the sixth time interval ends when the current flowing through the primary winding is negative; and During a subsequent seventh time interval of the switching cycle, the first electronic switch and the third electronic switch are kept open, and the second electronic switch is opened, whereby the negative current flowing through the primary winding discharges the capacitor associated with the phase node.

14. The flyback converter according to claim 13, wherein: the first electronic switch is an n - channel field - effect transistor; the second electronic switch is an n - channel field - effect transistor; and the third electronic switch is an n - channel field - effect transistor or a diode.

15. The flyback converter according to claim 13, wherein the second electronic switch includes a diode, and wherein the control circuit is configured to close the second electronic switch by closing the diode during the third time interval.

16. The flyback converter according to claim 13, wherein the third electronic switch includes a diode, and wherein the control circuit is configured to close the third electronic switch by closing the diode during at least one of the third time interval, the fourth time interval, and the fifth time interval.

17. The flyback converter according to claim 13, wherein the control circuit is configured to: When the current flowing through the primary winding exceeds a given reference value, which indicates the energy for discharging the capacitor, the sixth time interval ends.

18. The flyback converter according to claim 13, wherein the control circuit is configured to: end the sixth time interval after a duration that is a function of the duty cycle of the flyback converter, the duty cycle corresponding to the ratio between the duration of the first time interval and the duration of the switching period.

19. The flyback converter according to claim 13, wherein the control circuit is configured to: detect when the current flowing through the secondary winding reaches zero; and in response to detecting that the current flowing through the secondary winding has reached zero, end the fourth time interval.

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