Method for writing in an EEPROM memory and corresponding integrated circuit

Abstract

Embodiments of the present disclosure relate to methods for writing in EEPROM memory and corresponding integrated circuits. Methods and integrated circuits for programming non-volatile memory (NVM) are disclosed. In one embodiment, the integrated circuit includes: a memory plane organized into rows and columns of memory words, each memory word including memory cells, and each memory cell including a state transistor having a control gate and a floating gate; and a write circuit device configured to program a selected memory word during a programming phase by applying a first non-zero positive voltage to the control gates of the state transistors of the memory cells that do not belong to the selected memory word.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. 1904337 filed on April 25, 2019, which is incorporated herein by reference. Technical Field

[0003] Embodiments and implementations relate to writing to EEPROM ("Electrically Erasable Programmable Read Only Memory") memory, specifically voltage division programming. Background Art

[0004] Typically, digital data is written to EEPROM memory through a write cycle that includes an erase phase and a program phase.

[0005] EEPROM memory typically comprises a memory plane organized into rows and columns of memory words, each memory word comprising memory cells.

[0006] Conventionally, a memory cell includes a state transistor having a floating gate and a control gate, and an access transistor for transmitting a voltage to a drain of the state transistor.

[0007] The memory cell can have two states defined by the charge of the floating gate, and is therefore capable of recording a bit of digital data (eg, typically "0" in an erased state and "1" in a programmed state).

[0008] The erase operation and the program operation are achieved by injecting positive or negative charge onto the floating gate of the state transistor of the memory cell by means of the Fowler-Nordheim effect.

[0009] In particular, the programming operation involves (by convention) injecting positive charge onto the floating gate of the state transistor of the memory cell.The memory cell being programmed is said to be selected.

[0010] To inject charge onto the floating gate, a potential difference of approximately 13 V is generated between the control gate and drain regions of the state transistor, for example conventionally by applying zero voltage to the control gate and a high amplitude positive voltage (13 V) to the drain.

[0011] In order to reduce the size of the memory cells, so-called voltage-dividing architectures have been proposed, making it possible to reduce the coupling factor and the voltages involved during programming.

[0012] The voltage divider architecture proposes applying a moderate amplitude negative voltage to the control gate of the state transistor and a moderate amplitude positive voltage to the drain region of the state transistor. This enables the same Fowler-Nordheim electric field to be achieved across the state transistor with a lower coupling coefficient and a more moderate voltage.

[0013] That being said, in voltage-dividing architectures, as in more conventional architectures, there is particularly the problem of stray programming of unselected cells.

[0014] In particular, a positive word line voltage is applied to the gates of the access transistors of the memory cells in the memory word of the unselected row, in particular to avoid leakage and breakdown in the access transistors. Now, a stray positive voltage can be transmitted to the drain of the state transistor via the access transistor controlled in this way. This can lead to very weak stray tunnel currents, which repeatedly tend to charge the floating gate of the state transistor, which may eventually change a cell that was initially in an erased state to a programmed state, thereby destroying the stored data item. With regard to these two issues, a compromise with regard to the word line voltage needs to be established, and the compromise may lead to non-optimal programming conditions. Summary of the invention

[0015] The embodiments provide an improved voltage division architecture technique.

[0016] According to one embodiment, a writing method for an electrically erasable programmable read-only memory is proposed, the electrically erasable programmable read-only memory comprising: a memory plane organized into rows and columns of memory words, each memory word comprising a memory cell having a state transistor, the state transistor having a control gate and a floating gate, the writing method comprising a programming phase, the programming phase comprising performing possible voltage division programming on the selected memory cell in the selected memory word. Specifically, if the bits to be written to the selected memory word are all "0", the programming of the memory cells of the selected memory word is not performed during the programming phase. In the opposite case, at least one memory cell is selected in the selected memory word so as to perform voltage division programming therein, hence the term "possibly" is used.

[0017] According to a general feature of this embodiment, during the programming phase, a first non-zero positive voltage is applied to the control gates of the state transistors of the memory cells that do not belong to the selected memory word.

[0018] By applying a first non-zero positive voltage to the control gates of the state transistors of the unselected memory words during programming, the stray voltage transmitted on the drains of the state transistors is insufficient to cause stray programming operations. This improves the robustness of data storage.

[0019] The method according to this embodiment also provides the possibility to establish a better compromise with regard to the word line voltage of the unselected rows and the possibility to use a higher word line voltage for the unselected rows.

[0020] Therefore, programming can be achieved with optimal conditions without suffering from the problem of stray programming of the state transistor. In addition, if the memory cell includes an access transistor, it does not suffer from the problems of leakage, breakdown, gate stress and drain stress of the access transistor.

[0021] Each memory cell may further include an access transistor connected in series with the state transistor and the corresponding bit line, the gates of the access transistors of the same row being coupled to the word line, and according to one implementation mode, during the programming phase, the bit lines other than the bit line of the selected memory cell and the word lines of the unselected rows are brought to a first non-zero positive voltage.

[0022] Specifically, the wordline voltage on the unselected row makes it possible to increase the breakdown voltage limit of the select transistor of the memory cell (via the gated diode effect). Thus, the voltage applied to the selected bitline can be higher, or the leakage current lower for a given selected bitline voltage.

[0023] The wordline voltage on the unselected rows also makes it possible to reduce the gate-drain voltage of the selected transistors, which is beneficial for long-term reliability, especially in terms of gate oxide degradation.

[0024] Furthermore, these advantages also hold true for transistors used in components at the periphery of the memory plane (eg, decoders).

[0025] Furthermore, this implementation has the advantage of pooling some of the voltages involved on the various lines of the memory plane, thereby simplifying the memory, in addition to improving performance.

[0026] According to one implementation:

[0027] The non-zero positive programming voltage is high enough (e.g., 11V) to allow optimal programming of the selected memory cells;

[0028] The word line voltage of the selected row (e.g., 14V) allows the select transistor to pass the non-zero positive programming voltage;

[0029] The first non-zero positive voltage on the bit lines of the unselected memory cells is high enough (eg, 4V) so as not to induce a gate-drain voltage that degrades the access transistor.

[0030] This implementation corresponds to programming in an optimal voltage division architecture. Specifically, compared to conventional voltage division programming operations, this implementation may correspond to increasing the level of the programming voltage towards more positive values, and this reduces the risk of degradation caused by hot carriers. Specifically, the higher voltage level tends to better prevent the state transistor from entering the on state by means of the substrate effect during the programming phase.

[0031] The memory plane may include a source plane or source line coupled to the source region of the state transistor, and according to one implementation, the voltage of the source plane or source line is equal to the first non-zero positive voltage during the programming phase.

[0032] Specifically, when the access transistors of the selected row are placed in a conducting state, a current path may exist between the bit lines and the source plane (in the case of a programmed cell), and this implementation may avoid conflicts between unselected bit lines and source planes.

[0033] To summarize, in a specific example, the control gate voltages of unselected memory words, the word line voltages of unselected rows, the bit line voltages of unselected memory cells, and the source voltage of the source plane all take the same potential (ie, a first non-zero positive voltage).

[0034] For example, the first non-zero positive voltage is between 3 volts and 5 volts.

[0035] This allows a considerable simplification of the high voltage switching circuitry which is configured to route the various voltages involved during programming while providing optimal programming conditions and in particular while minimizing the risk of stray programming.

[0036] For example, voltage-divided programming of a selected memory cell includes applying a non-zero negative programming voltage to a control gate of a state transistor of the selected memory cell and applying a non-zero positive programming voltage to a drain region of the state transistor of the selected memory cell.

[0037] In general, the activation of the state transistor of a memory cell during programming is characterized primarily by the potential difference between its three control terminals: drain, source, control gate, with the potential of the substrate referenced to 0 V. However, if the voltages of the three terminals are offset by substantially the same value relative to the substrate potential, there are multiple operating points that satisfy these conditions. One of the differences between these operating points is the substrate effect of the state transistor (represented by the source-substrate voltage difference). All other conditions being equal, this voltage difference affects the electric field present in the channel of the state transistor during the programming phase, determines the leakage current in the channel and the generation of hot carriers under the floating gate, and therefore ages the state transistor during the programming phase. Therefore, a higher source voltage generally has a favorable effect on the aging of the state transistor.

[0038] According to another embodiment, an electrically erasable programmable read-only memory integrated circuit is proposed, comprising a memory plane organized into rows and columns of memory words, each memory word comprising a memory cell having a state transistor, the state transistor having a control gate and a floating gate. The memory comprises a writing device, the writing device being intended to perform a programming phase, the programming phase comprising a possible voltage division programming of selected memory cells in the selected memory word, and the writing device being configured to apply a first non-zero positive voltage to the control gates of the state transistors of the memory cells not belonging to the selected memory word during said programming phase.

[0039] Each memory cell may further comprise an access transistor connected in series with the state transistor and the corresponding bit line, the gates of the access transistors of the same row being coupled to the word line, and according to one embodiment, the writing device is configured to cause the bit lines other than the bit line of the selected memory cell and the word lines of the unselected rows to adopt a first non-zero positive voltage during the programming phase.

[0040] According to one embodiment, the writing device is configured to:

[0041] causing the non-zero positive programming voltage to reach a potential high enough to allow optimal programming of the selected memory cell (e.g., 11V);

[0042] Bringing the word line voltage of the selected row to a potential (e.g., 14V) that allows the select transistor to pass the non-zero positive programming voltage;

[0043] The first non-zero positive voltage on the bit lines of the unselected memory cells is brought to a potential high enough to avoid generating a gate-drain voltage that would degrade the access transistor (eg, 4V).

[0044] The memory plane may comprise a source plane or source line linked to the source region of the state transistor, and according to one embodiment the writing means are configured such that the potential of the source plane or source line during said programming phase is equal to a first non-zero positive voltage.

[0045] According to one embodiment, the first non-zero positive voltage is between 3 volts and 5 volts.

[0046] For example, the writing device is configured to apply a non-zero negative programming voltage to the control gate of the state transistor of the selected memory cell and to apply a non-zero positive programming voltage to the drain region of the state transistor of the selected memory cell during the programming phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Other advantages and features will become apparent by examining the detailed description of entirely non-limiting embodiments and implementations and the accompanying drawings, in which:

[0048] Figure 1 An exemplary embodiment is illustrated;

[0049] Figure 2 An exemplary embodiment is illustrated;

[0050] Figure 3 An exemplary implementation is illustrated; and

[0051] Figure 4 An exemplary implementation is illustrated. DETAILED DESCRIPTION

[0052] Figure 1 A non-volatile memory NVM integrated circuit CI is schematically shown.

[0053] The non-volatile memory NVM is an electrically erasable programmable read-only memory "EEPROM" and comprises a memory plane PM organized into rows and columns of memory words. Each memory word comprises a memory cell comprising a state transistor having a control gate and a floating gate (see below with reference to Figure 2 description).

[0054] The control gate decoder CGdec makes it possible to route the control gate voltages VCGsel, VCGunsel to the control gate switches associated with each memory word of the memory plane PM. Using the selection signals VCLsel, VCLunsel distributed by the row decoder WL / CLdec, the control gate switches are controlled to transmit one or the other of the control gate voltages VCGsel, VCGunsel to the state transistors of the memory word.

[0055] The bit line decoder BLdec enables the routing of the bit line voltages VBLsel, VBLunsel to the memory cells of the same column and selectively to the location of the memory cells within a memory word.

[0056] The source switch Ssw makes it possible to route the source voltage VSprog to a source plane linked to all sources of the state transistors in the memory plane.In another way, source lines extending along the columns may also be provided.

[0057] Furthermore, the memory NVM includes means for generating and distributing the voltages involved during voltage-divided programming (i.e., in particular, a charge pump CP for generating voltages (e.g., 5 V) from a power supply). A high-voltage sequencer HVseq makes it possible to coordinate the distribution of voltages in time, which are transmitted to a high-voltage switch HVsw, which distributes the voltages involved during programming in a manner controlled by the high-voltage sequencer HVseq.

[0058] The charge pump CP, the high voltage sequencer HVseq, the high voltage switch HVsw and the row decoder WL / CLdec, the control gate decoder CGdec, the bit line decoder BLdec and the source switch Ssw are incorporated into a write device MRPG which is particularly intended to perform a voltage division programming operation on a selected memory cell.

[0059] The memory cell being programmed is referred to as "selected", specifically, programming is selected by memory cell, whereas, for example, erasing is selected by memory word. A cell is selected on its row, column and bit line.

[0060] Thus, the term selected may specifically define these various elements and when referring, for example, to a selected bit line, a selected memory word, a selected row or a selected column, or a selected state transistor, reference will of course be made to the corresponding elements comprising or belonging to the selected memory cell.

[0061] Nevertheless, a distinction should be made between the selected memory words. A memory word containing the selected memory cells will necessarily be selected, but it may be the case that the selected memory word does not contain any selected memory cells. Specifically, if all bits to be written are 0 (no memory cells have been programmed after erasing the memory cells of the selected memory word), the selected memory word does not contain any selected memory cells within the meaning of the term given above.

[0062] In other words, the selected memory word belongs to the selected row and the selected column. The unselected memory word either does not belong to the selected row or the selected column, or does not belong to either the selected row or the selected column.

[0063] As the following reference Figure 4 As will become apparent in more detail, the writing means are configured to apply a first non-zero positive voltage Vlowglobalprog to the control gates of the state transistors of the unselected memory cells during said programming.

[0064] also, Figure 1 The example corresponds to a favorable embodiment in which the control gate voltage VCGunsel of the unselected memory word, the selection voltage VCLsel that controls the control gate switch of the selected memory word, the word line voltage VWLunsel of the unselected row, and the bit line voltage VBLunsel and the source voltage VSprog of the unselected memory cell all adopt the first non-zero positive voltage Vlowglobalprog.

[0065] This makes it possible to greatly simplify the circuit arrangements of the high-voltage switch HVsw, the high-voltage sequencer HVseq and the charge pump CP.

[0066] In particular, the source voltage V Sprog is selected such that the state transistor has a favorable source-substrate voltage.

[0067] Specifically, for a given operating point of source, drain, and control gate voltages that allow programming, the source-substrate voltage affects the electric field present in the channel of the state transistor during the programming phase, thereby determining the leakage current in the channel and the generation of hot carriers under the floating gate, as well as the aging of the state transistor during the programming phase.

[0068] In this advantageous exemplary embodiment, the source voltage VSprog therefore defines a first non-zero positive voltage Vlowglobalprog, the writing device MPRG then being configured such that the non-zero positive voltage Vlowglobalprog reaches the source voltage VSprog of the source plane.

[0069] Figure 2 The above reference is shown Figure 1 Details of a memory plane PM of a non-volatile memory NVM integrated circuit CI are described.

[0070] Figure 2 shows the columns COL of the memory plane PM i and two rows RG j RG j+1 Hereinafter, the index "i" in the reference numerals will indicate the intersection of the corresponding column COL i , and the index "j" in the reference numerals will indicate the row RG j .

[0071] Memory word WD i,j , WD i,j+1 WD i,j Located in column COL i With RG j RG j+1 The intersection of .

[0072] Each memory word WD i,j Including memory cell CEL i,j,k (e.g. 38 memory cells (4 bytes and 6 bits of error correction code)), each memory cell comprising a state transistor TE and an access transistor TA. In the following, the index "k" in the reference numerals will indicate a cell within a column, in particular belonging to column COL. i The corresponding bit line BL i,k location.

[0073] The state transistor TE has a floating gate and a control gate, a source region and a drain region, and the access transistor TA has a gate, a source region and a drain region. i,j,k The state transistor TE and the access transistor TA are connected in series, and the corresponding bit line BL to the drain of the access transistor TA i,k The source line S is connected to the source of the state transistor TE. For example, the source line can generally be a connection in a metallization layer such as a first metallization layer. In some specific cases, the source line S can be a source plane buried in the semiconductor substrate of the integrated circuit, and the transistors of the memory plane are installed below the source plane.

[0074] Belong to the same memory word WD i,j The control gate of the state transistor TE is linked to the control gate line CG i,j , thus from each memory word WD i,j The associated control gate switch CGSW i,j Routing control gate signals.

[0075] Switch CGSW i,j The inverters are controlled by the select signal, with respect to the voltages applied to the columns COL. i The p-type and n-type well potentials Bp and Bn of the p-type and n-type transistors of the inverter, the selection signal RG in each row j A selection line CL j Switch CGSW i,j The inverter can be used in memory word WD i,j The control gate line CG i,j The first voltage Dp from the drain of the p-type transistor is transmitted to the i or the second voltage Dn from the drain of the n-type transistor i .

[0076] The access transistor TA is controlled by a word line signal, which is coupled to the same row RG j The gate of the access transistor TA is the word line WL j Up transmission.

[0077] Now further reference Figure 3 and Figure 4 .

[0078] Figure 3 Shows Figure 2 The voltage values ​​in volts involved in the memory plane PM to achieve conventional voltage division programming, while Figure 4 The values ​​of the same voltages according to one advantageous mode of realization are shown.

[0079] Figure 3 and Figure 4 The table shows values ​​of various voltages for implementing a program operation according to whether the column COL is selected “COL(sel)” or unselected “COL(unsel)” and whether the row RG is selected “RG(sel)” or unselected “RG(unsel)”.

[0080] Figure 3 and Figure 4 Thus, the potentials Bn and Bp of the n-type and p-type wells, the drain voltage Dn and i 、Dp i and control gate switch CGSW i,j The selection line CL involved j The word line voltage WL is also shown. j , bit line voltage BL i,k , control gate voltage CG i,j and source voltage S.

[0081] Figure 3 The voltage values ​​used to implement programming using the basic voltage division principle are shown. A non-zero negative programming voltage of -6V is applied to the selected memory cell CEL i,j,k The control gate of the state transistor TE is connected to the control gate of the state transistor TE, and the non-zero positive programming voltage of 9V is connected to the corresponding bit line BL i,k Applied to the selected memory cell CEL i,j,k state of the drain region of the transistor TE.

[0082] This generates a voltage of -15 V between the control gate and drain region of the state transistor TE of the selected memory cell, sufficient to achieve the Fowler-Nordheim phenomenon of injecting charge onto the floating gate.

[0083] In order to control the gate CG of the state transistor i,j Apply a negative programming voltage of -6V to the select line CL of the selected row RG (sel) j The high level selection signal of 0V is communicated on the line Dn of the selected column COL (sel) i Up and inverter CGSW i,j The n-type well Bn communicates a negative programming voltage of -6 V. Therefore, the selected memory word WD i,j The inverter CGSW i,j The n-type transistor is in the on state and transmits the negative programming voltage of -6V from its drain to the control gate line CG of the selected memory word. i,j .

[0084] In order to apply a positive programming voltage of 9V to the selected memory cell CEL i,j,k The drain region of the state transistor TE of the selected column COL (sel) corresponds to the bit line BL i,k The positive programming voltage of 9 V is reached. The other bit lines of the selected column are at a lower positive voltage (2 V in this example). The word line voltage WL of the selected row RG(sel) j reaches 12V, so that given a voltage of 9V on the drain of one of the access transistors, the selected memory word WD i,j The access transistor TA of the bit line BL is in the on state. i,k The positive programming voltage of 9V is thus applied to the selected memory cell CEL i,j,k The access transistor TA is transmitted to the drain of the selected state transistor TE.

[0085] exist Figure 3 Among the voltages in the table, a positive voltage of at least 2 V is applied to the bit line BL of the unselected memory cell. i,k , in particular to prevent leakage current between a selected bit line and unselected bit lines (eg in the substrate between two drain regions of an access transistor).

[0086] Furthermore, the access transistors TA of the unselected memory cells in the selected row RG(sel) receive a voltage of 12 V on their gates, and applying a positive voltage of 2 V can also reduce the gate stress of these access transistors TA. Gate stress corresponds to a voltage greater than 12 V or even 10 V between the gate and the drain to benefit from a significant margin, Vg-Vd>10 V (Vg is the gate potential, Vd is the drain potential), and prematurely ageing the transistors.

[0087] Therefore, when the access transistor TA of the selected row is in the on state at 12V, current may flow between the unselected 2V bit line and the source plane (especially in the case of programmed cells). To avoid conduction from the bit line to the source in the memory cell during programming, the source voltage is equal to the unselected bit line voltage 2V.

[0088] In addition, the access transistors TA of the memory cells of the unselected row RG (unsel) on the selected bit line receive a positive programming voltage of 9V on their drains and an unselected word line voltage on their gates. In order to reduce drain stress and minimize the drain-channel leakage of these transistors, a positive voltage of at least 2V is applied to the unselected word lines. Specifically, drain stress typically causes leakage currents between the drain and channel of the transistor through a mechanism commonly referred to as GIDL, thereby reducing the gate-induced drain barrier. These leakage currents occur at voltages below the avalanche voltage of the drain / substrate diode of the transistor. An increase in the gate voltage offsets these leakage currents and is beneficial to the aging of the transistor.

[0089] Nevertheless, a sufficiently high unselected word line voltage can increase the source voltage of access transistor TA to the point of generating a spurious programming operation on the drain of state transistor TE (even though it is unselected, i.e., not receiving a negative programming voltage on the control gate). To avoid spurious programming operations, the unselected word line voltage should be less than 3V.

[0090] In summary, for unselected word lines WL j A compromise for applying a moderately positive voltage is between 2V and 3V.

[0091] It is now desirable to be able to achieve more efficient programming conditions, for example, where the voltage division level is increased overall ("more positive") (e.g., as Figure 3 The "(+2)" in the corresponding cell of the table shows -4 V and 11 V instead of -6 V and 9 V.)

[0092] Specifically, considering that the floating gate potential is coupled to the control gate potential to 70% and to the drain potential to 30%, and the positive programming charge is 1 V, the effective floating gate potential in the above initial case is -6*0.7+9*0.3+1=-0.5 V. With a negative effective potential in the floating gate, the state transistor is more prone to hot carrier injection into the floating gate oxide via the channel, which leads to premature aging of the memory cell.

[0093] Now, with the voltage level increased by 2V (+2), the effective floating gate potential is -4*0.7+11*0.3+1=1.5V. With a positive effective potential in the floating gate, the state transistor is less prone to hot carrier injection into the floating gate oxide via the channel, and the higher voltage tends to better prevent the state transistor from entering the on state via the substrate effect. This improves the reliability of the memory cell.

[0094] Therefore, for a given drain-source voltage (at Figure 3 The drain-source voltage is essentially the same between the initial voltage division condition and the condition of increasing the voltage level “(+2)”), the higher source voltage due to the positive shift in voltage tends to oppose the punching (stray drain-source conduction) of the state transistor, which is a source of hot carrier generation.

[0095] A higher effective floating gate potential (above 1.5V) will, by the cumulative effect of generating fewer hot carriers, avoid injecting these hot carriers (holes in this case) into the gate oxide of the state transistor; and not direct these hot carriers towards the gate oxide.

[0096] In order to meet the Fowler-Nordheim electric field constraint, bit line leakage constraint, gate stress and drain stress constraint of the access transistor TA, the bit line voltage BL j and word line voltage WL j 2V is added to each of them (as Bn, Dn, CL to which these voltages are applied) j voltage).

[0097] However, Figure 3 The most efficient programming condition (+2) involves a voltage on the drains of the state transistors of the unselected memory cells of at least 4V, which is above the tolerance for spurious programming and is unacceptable.

[0098] Reference now Figure 4 , Figure 4 The control gate CG of the state transistor of the unselected memory cell is shown by applying a first non-zero positive voltage Vlowglobalprog to the control gate CG of the state transistor of the unselected memory cell. i,j , an example of producing more efficient and optimal programming conditions.

[0099] The first non-zero positive voltage Vlowglobalprog may be between 3 V and 5 V, and 4 V will be arbitrarily chosen to describe this example. For simplicity, the first non-zero positive voltage Vlowglobalprog may be represented by "the voltage Vlowglobalprog".

[0100] exist Figure 4The values ​​framed by solid lines in the table of allow the voltage Vlowglobalprog to be applied to the control gates of unselected cells.

[0101] In order to apply a negative programming voltage of -4V and a voltage Vlowglobalprog of 4V to each control gate CG i,j , the select line CL of the selected row RG j A high level selection signal (sel) of 4V is applied to the select line CL of the unselected row RG (unsel) and a low level selection signal of -4V is applied to the select line CL of the unselected row RG (unsel). j .

[0102] Inverter CGSW i,j The n-type well Bn is negatively biased to -4V, and the inverter CGSW i,j The power supply line Dn of the n-type transistor reaches -4 V in the selected column COL (sel) and reaches 4 V in the unselected column COL (unsel).

[0103] Inverter CGSW i,j The p-type well Bp is positively biased at 4V, and the inverter CGSW i,j The drain line Dp of the p-type transistor reaches 4 V in the selected column COL (sel) and the unselected column COL (unsel).

[0104] Therefore, in the selected row RG(sel), the high level selection signal CL j The inverter CGSW i,j The n-type transistors are placed in a conductive state, transmitting the negative programming voltage -4 V to the selected column COL(sel) and transmitting the voltage Vlowglobalprog (transmitted at approximately 2 V due to the substrate effect in the n-type transistors) from the corresponding line Dn to the unselected columns COL(unsel).

[0105] In the unselected row RG (unsel), the low level selection signal CL j The inverter CGSW i,j The p-type transistor is placed in a conductive state, and the voltage Vlowglobalprog of 4 V is transmitted from the drain line Dp to the selected column COL (sel) and the unselected column COL (unsel).

[0106] In summary, a negative programming voltage is applied to the control gates of the selected state transistors, while a first non-zero positive voltage Vlowglobalprog is applied to the control gates of the state transistors of the memory cells that do not belong to the selected memory word.

[0107] Additionally, this makes it possible to increase the word line voltage WL of the unselected rows during the programming without introducing stray programming. j and the bit line voltage BL of the unselected memory cells i,k .

[0108] Therefore, the breakdown voltage limit of the selection transistor TA is increased by means of the gated diode effect, and the voltage applied to the selected bit line can be higher (11 V in this example), and / or the current leakage in these transistors can be lower.

[0109] The gate-drain voltage of the selected transistor is also lowered, making it possible to limit the degradation of the gate oxide of the access transistor.

[0110] Furthermore, these same advantages are beneficial for routing voltages to, for example, the bit line decoder BLdec ( Figure 1 ) and row decoder WL / CLdec( Figure 1 ) in a memory plane peripheral component.

[0111] Furthermore, the source plane S is biased equal to a first non-zero positive voltage Vlowglobalprog.

[0112] Therefore (ref. Figure 1 , and if Figure 4 ), the unselected bit line voltage VBLunsel, the unselected control gate voltage VCGunsel, the unselected word line voltage VWLunsel, the control signal voltage of the selected row VCLsel, and the source voltage VSprog are all at a low level of the overall programming potential (i.e., the first non-zero positive voltage Vlowglobalprog).

[0113] Besides producing optimal programming conditions with particular tolerance to stray programming, this can also greatly simplify the high voltage switch HVsw ( Figure 1 ) architecture and control to achieve voltage division programming.

Claims

1. A method for programming a non-volatile memory (NVM), the non-volatile memory (NVM) comprising a memory plane organized in rows and columns of memory words, each memory word comprising a memory cell, the method comprising: programming the selected memory word during a programming phase by applying a first non-zero positive voltage to control gates of state transistors of the memory cells not belonging to the selected memory word, wherein each memory cell comprises a state transistor having a control gate and a floating gate and an access transistor connected in series with the state transistor, the access transistor being connected to a respective bit line; and During the programming phase, the first non-zero positive voltage is applied to bit lines other than the bit line of the selected memory cell and word lines of unselected rows to which the gates of the access transistors of the same row are coupled.

2. The method according to claim 1, further comprising: selecting a word line voltage of the selected row so that the access transistor can pass a non-zero positive programming voltage; as well as programming the selected memory cell using the non-zero positive programming voltage, Wherein the first non-zero positive voltage on the bit line of an unselected memory cell is high enough so that a gate-drain voltage does not degrade the access transistor. 3 . The method of claim 2 , wherein the non-zero program voltage is 11V, wherein the word line voltage is 14V, and wherein the first non-zero positive voltage is 4V.

4. The method according to claim 1, further comprising: During the programming phase, a source voltage is applied to a source plane or source line, wherein the source voltage is equal to the first non-zero positive voltage, and wherein the memory plane includes: the source plane or the source line coupled to a source region of the state transistor. The method of claim 1 , wherein the first non-zero positive voltage is between 3 volts and 5 volts.

6. The method according to claim 1, wherein the programming is voltage division programming of the selected memory cell, wherein the voltage division programming comprises: A non-zero negative programming voltage is applied to a control gate of a state transistor of the selected memory cell, and a non-zero positive programming voltage is applied to a drain region of the state transistor of the selected memory cell.

7. A non-volatile memory (NVM) integrated circuit comprising: a memory plane organized into rows and columns of memory words, wherein each memory word includes memory cells, and each memory cell includes a state transistor having a control gate and a floating gate and an access transistor connected in series with the state transistor, the access transistor being connected to a corresponding bit line, wherein gates of access transistors in the same row are coupled to a word line; as well as A circuit device is written, configured to: programming the selected memory word by applying a first non-zero positive voltage to the control gates of the state transistors of the memory cells not belonging to the selected memory word during a programming phase; and; During the programming phase, the first non-zero positive voltage is applied to bit lines other than the bit line of the selected memory cell and word lines of unselected rows.

8. The integrated circuit of claim 7, wherein the write circuit is configured to: providing a non-zero positive programming voltage with a potential for programming the selected memory cell; providing a potential to a word line voltage of the selected row that allows the select transistor to pass the non-zero positive programming voltage; and The first non-zero positive voltage is provided to the bit lines of unselected memory cells so that gate-drain voltage does not degrade the access transistor.

9. The integrated circuit of claim 8, wherein the non-zero programming voltage is 11V, wherein the word line voltage is 14V, and wherein the first non-zero positive voltage is 4V.

10. An integrated circuit according to claim 7, wherein the memory plane includes a source plane or a source line linked to a source region of the state transistor, wherein the write circuit device is configured to: provide the first non-zero positive voltage to the source plane or the source line during the programming phase.

11. The integrated circuit of claim 7, wherein the first non-zero positive voltage is between 3 volts and 5 volts.

12. The integrated circuit of claim 7, wherein the write circuit device is configured to: applying a non-zero negative programming voltage to the control gate of the state transistor of the selected memory cell; and During the programming phase, a non-zero positive programming voltage is applied to the drain region of the state transistor of the selected memory cell.

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