Semiconductor device and forming method thereof

Abstract

Embodiments of the present invention provide a semiconductor device and a method for forming the same. This embodiment adds an oxide layer forming step during and after the floating gate formation process, and subsequently removes the oxide layer to smooth the top edge of the pillar-shaped active region beneath the floating gate. This creates a larger area than the surface of the subsequently formed control gate conductive structure extending into the tip region between the pillar-shaped floating gates, reducing the electric field between the two and preventing breakdown of the semiconductor device when leakage current passes through. This improves the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a forming method thereof. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the feature size of semiconductor devices is gradually shrinking. However, the reliability of semiconductor devices still needs to be improved. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, which can improve the reliability of the semiconductor device. The method includes:

[0004] Providing a semiconductor substrate, the semiconductor substrate comprising an active area base, a stop layer, a floating gate material layer and a hard mask layer stacked in sequence;

[0005] Etching the hard mask layer and the floating gate material layer in a predetermined area until the stop layer is exposed to form a discrete floating gate;

[0006] depositing a first oxide layer covering the floating gate and the stop layer;

[0007] Etching the first oxide layer, the stop layer, and the active area substrate between the floating gates to form a groove;

[0008] removing the first oxide layer;

[0009] oxidizing the surface of the floating gate to form a second oxide layer;

[0010] The second oxide layer is removed to smooth the top edge of the active area substrate below the floating gate.

[0011] Furthermore, the size of the floating gate is smaller than the size of the active region substrate between adjacent grooves.

[0012] Furthermore, depositing the first oxide layer covering the floating gate is specifically forming the first oxide layer by atomic layer deposition.

[0013] Furthermore, the thickness of the first oxide layer is 60-80 angstroms.

[0014] Furthermore, the removing of the first oxide layer is specifically removing the first oxide layer by using a wet etching process.

[0015] Furthermore, the method of oxidizing the surface of the floating gate includes: rapid thermal oxidation, trench planar antenna oxidation, plasma injection oxidation and ozone oxidation.

[0016] Furthermore, the floating gate material layer is polysilicon, and the second oxide layer is silicon dioxide.

[0017] Furthermore, the method for removing the second oxide layer is specifically to remove the second oxide layer by a wet etching process.

[0018] Furthermore, the etching of the first oxide layer, the stop layer and the active region substrate between the floating gates is specifically performed by etching the first oxide layer, the stop layer and the active region substrate between the floating gates using an anisotropic etching method.

[0019] Furthermore, the method for forming the semiconductor device further includes:

[0020] removing the hard mask layer;

[0021] forming an isolation layer covering a surface of the groove and a surface of the floating gate, wherein an upper surface of the isolation layer is higher than an upper surface of the floating gate;

[0022] Etching back the isolation layer to form a shallow trench isolation structure;

[0023] forming a gate dielectric layer covering the floating gate and the shallow trench isolation structure;

[0024] A control gate is formed on the gate dielectric layer and crosses the floating gate.

[0025] In another aspect, a semiconductor device is provided, comprising:

[0026] A semiconductor substrate comprising an active region base having a recess and a stop layer on top of the active region base;

[0027] a floating gate formed on the active region substrate;

[0028] Wherein, the top edge of the active area substrate below the floating gate is smooth.

[0029] Furthermore, the size of the floating gate is smaller than the size of the active region substrate between adjacent grooves.

[0030] In an embodiment of the present invention, an oxide layer is added during and after the floating gate is formed, and the oxide layer is subsequently removed to smooth the edge of the top of the pillar-shaped active region below the floating gate. This allows the edge to have a larger area than the surface of the subsequently formed control gate conductive structure that extends into the tip region between the pillar-shaped floating gates. This reduces the electric field between the two, preventing the semiconductor device from being broken down when leakage current passes through. This improves the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a circuit diagram of NAND memory.

[0033] Figure 2-Figure 6 is a schematic cross-sectional view of a structure formed in each step of a method for forming a semiconductor device of a comparative example;

[0034] Figure 7 is a photograph of a semiconductor device of a comparative example;

[0035] Figure 8 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0036] Figures 9-19 is a schematic cross-sectional view of a structure formed in each step of a method for forming a semiconductor device according to an embodiment of the present invention;

[0037] Figure 20 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described below based on the following embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, certain specific details are described in detail. Those skilled in the art can fully understand the present invention without these details. To avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0039] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0040] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include," "comprising," and similar expressions should be interpreted as inclusive rather than exclusive or exhaustive; that is, as meaning "including but not limited to." In the description of the present invention, unless otherwise specified, "multi-layer" means two or more layers.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For ease of description, spatial relationship terms such as "under," "below," "under," "above," and "on" may be used herein to describe the relationship between one element or feature and another element or feature(s) as shown in the accompanying drawings. It should be understood that the spatial relationship terms are intended to summarize different orientations of the device in use or operation other than the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "under" or "below" another element or feature would be "above" the other element or feature. Thus, the exemplary term "under" is capable of covering both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0042] The term "smooth edges" refers to the top edges of the active region substrate beneath the floating gate being obtuse or rounded in a cross-sectional view. For example, "the top edge of the active region substrate beneath the floating gate being smooth" means that, in a cross-sectional view perpendicular to the length of the floating gate, the width of the top surface of the active region substrate beneath the floating gate is substantially equal to the width of the floating gate, and the angles between the top surface and the sidewalls are obtuse or rounded.

[0043] Non-volatile memory (NVM) is a type of semiconductor memory that continues to store data even when the power supply is removed. NAND memory is a commonly used type of non-volatile memory. Its advantages include small memory cell area and large storage capacity, making it widely used in memory cards for portable electronic products such as MP3 players, digital cameras, digital camcorders, and mobile phones. However, NAND memory's voltage resistance needs to be improved, and its reliability is insufficient.

[0044] Figure 1 This is a circuit diagram of NAND memory, such as Figure 1As shown in the figure, in the NAND architecture, memory cells are organized in series with 64 memory transistors. The control gates of multiple memory transistors are connected to the word line (WL), which is equivalent to multiple memory cells sharing a single control gate. Within each string of memory cells (32 or 64), control transistors are connected to the source line (SL) and bit line (BL) at both ends of the memory cell. Each NAND memory cell string has a bit line to connect to other strings.

[0045] In a comparative example, a method for forming a semiconductor device includes the following steps:

[0046] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises an active region base and a floating gate material layer.

[0047] Step S2: patterning the semiconductor substrate to form a plurality of discrete floating gates.

[0048] Step S3: forming an isolation layer on the semiconductor substrate, wherein the isolation layer covers the active region base and the floating gate.

[0049] Step S4: forming a control gate on the isolation layer and crossing the floating gate.

[0050] Figure 2-Figure 6 The cross-sectional view of the structure formed by each step of the method for forming a semiconductor device of the comparative example is shown. The cross-sectional view is a cross-sectional view along the word line direction. Figure 2 As shown, in step S1, a semiconductor substrate is provided, wherein the semiconductor substrate comprises an active region base 1 and a floating gate material layer 2 stacked in sequence.

[0051] like Figure 3 As shown, in step S2, the semiconductor substrate is patterned to form a plurality of discrete floating gates 3.

[0052] Specifically, a photolithography process is used to form mutually spaced grooves on the semiconductor substrate. The depth of the grooves is greater than the thickness of the floating gate material layer, exposing the active area base 1. Thus, a plurality of discrete floating gates 3 are formed.

[0053] like Figure 4 and Figure 5 As shown, in step S3, an isolation layer 4 is formed on the semiconductor substrate. The isolation layer 4 covers the active region base 1 and the floating gate 3.

[0054] like Figure 4 As shown, an isolation material layer can be formed on the semiconductor substrate by coating or chemical vapor deposition. The upper surface of the isolation material layer is higher than the upper surface of the floating gate.

[0055] like Figure 5 As shown, the isolation material layer in a predetermined area is etched back to form a shallow trench isolation structure 41 covering a portion of the floating gate surface and the active area substrate surface. Specifically, a portion of the isolation layer 4 is etched back to expose a portion of the floating gate.

[0056] Optionally, after forming the shallow trench isolation structure 41 , a gate dielectric layer 42 is formed on the shallow trench isolation structure 41 .

[0057] like Figure 6 As shown, in step S4 , a control gate 5 is formed on the gate dielectric layer 42 to cross the floating gate 3 .

[0058] Figure 7 This is a photo of a semiconductor device of a comparative example. Figure 7 As shown, the semiconductor device includes an active region substrate 1, a floating gate 3 formed on the active region substrate 1, a shallow trench isolation structure 41 covering the active region substrate 1 and a portion of the floating gate 3, a control gate 5 spanning the floating gate 3, and a gate dielectric layer 42 between the floating gate 3 and the control gate 5. Due to process limitations, a sharp corner is formed at the bottom of the control gate 5 between two adjacent floating gates 3 (as shown in region 6), and a sharp corner is also formed at the top of the active region substrate 1 (as shown in region 7). During use, a high electric field is easily formed between region 6 of the control gate 5 and region 7 of the active region substrate 1 of the comparative semiconductor device. When leakage current passes through, the semiconductor device may be broken down, affecting the withstand voltage performance of the semiconductor device and resulting in poor reliability of the semiconductor device.

[0059] In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, which can improve the stability of the semiconductor device.

[0060] In the embodiment of the present invention, the formation of a NAND memory is taken as an example for description, but the formation method of the embodiment of the present invention is not limited to forming a NAND memory, and can also be used to form other semiconductor devices.

[0061] Figure 8 FIG. 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, the method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:

[0062] Step S100 , providing a semiconductor substrate, wherein the semiconductor substrate comprises an active region base, a stop layer, a floating gate material layer, and a hard mask layer stacked in sequence.

[0063] Step S200 , etching the hard mask layer and the floating gate material layer in a predetermined area until the stop layer is exposed, so as to form a discrete floating gate.

[0064] Step S300 , depositing a first oxide layer covering the floating gate and the stop layer.

[0065] Step S400: etching the first oxide layer, the stop layer, and the active area substrate between the floating gates to form a groove.

[0066] Step S500: removing the first oxide layer.

[0067] Step S600: oxidizing the surface of the floating gate to form a second oxide layer.

[0068] Step S700: removing the second oxide layer to smooth the top edge of the active area substrate below the floating gate.

[0069] Optionally, the method for forming a semiconductor device according to an embodiment of the present invention may further include the following steps:

[0070] Step S800: removing the hard mask layer.

[0071] Step S900 , forming an isolation layer covering the surface of the groove and the surface of the floating gate, wherein the upper surface of the isolation layer is higher than the upper surface of the floating gate.

[0072] Step S1000 , etching back the isolation layer to form a shallow trench isolation structure.

[0073] Step S1100 , forming a gate dielectric layer covering the floating gate and the shallow trench isolation structure.

[0074] Step S1200: forming a control gate on the isolation layer and crossing the floating gate.

[0075] Figures 9-19 1 is a schematic cross-sectional view of a structure formed in each step of a method for forming a semiconductor device according to an embodiment of the present invention along a word line direction. Figure 9 As shown, in step S100, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes an active region base 101, a stop layer 102, a floating gate material layer 103 and a hard mask layer 104 stacked in sequence.

[0076] The active area substrate 101 may be a silicon single crystal. Alternatively, the active area substrate 101 may also be a substrate of an epitaxial layer structure on silicon, such as silicon on insulator (SOI) or stacked silicon on insulator (SSOI), or a compound semiconductor. The compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Preferably, the active area substrate 101 is a silicon single crystal substrate. Several epitaxial interface layers or strained layers may also be formed on the surface of the active area substrate 101 to improve the electrical performance of the semiconductor device. The active area substrate 101 also includes a source region and a drain region. In order to better illustrate the solution of the present application, the source region and the drain region are not shown in the figure.

[0077] The material of the stop layer 102 may be silicon oxide, silicon nitride, silicon carbide, etc. The stop layer 102 may protect the active area substrate 101 and control the etching depth in subsequent processes.

[0078] The floating gate material layer 103 may be made of doped polysilicon.

[0079] The material of the hard mask layer 104 may be silicon nitride or silicon oxynitride, etc. The hard mask layer 104 is above the floating gate material layer 103 and plays a role in protecting the floating gate formed in the subsequent process.

[0080] like Figure 10 As shown, in step S200 , the hard mask layer 104 and the floating gate material layer 103 in a predetermined area are etched until the stop layer 102 is exposed, so as to form a discrete floating gate 105 .

[0081] Specifically, step S200 may include the following steps:

[0082] Step S201 : coating photoresist on the hard mask layer 104 .

[0083] Step S202 , performing exposure and development processing on the photoresist to solidify the photoresist in a partial area to form a predetermined photoresist pattern.

[0084] In step S203, the hard mask layer 104 is etched using the photoresist pattern as a mask until the photoresist pattern is transferred to the hard mask to form a patterned hard mask layer 104. Specifically, a dry etching process may be used, for example, a plasma etching process using a fluorine-containing gas as an etching gas.

[0085] Step S204: removing the photoresist pattern by using an ashing process or chemical reagents.

[0086] In step S205 , the floating gate material layer 103 is etched using the patterned hard mask layer 104 as a mask.

[0087] Furthermore, an etching process with a high selectivity ratio for the floating gate material layer 103 is selected so that during the etching process, the etching rate of the floating gate material layer 103 is higher than the etching rate of the stop layer 102. The etching is stopped after the stop layer 102 is exposed to ensure that the active area substrate 101 is not etched.

[0088] Furthermore, a dry etching process may be used to etch the floating gate material layer to form a separate floating gate 105 .

[0089] like Figure 11 As shown, in step S300 , a first oxide layer 106 is deposited to cover the floating gate 105 and the stop layer 102 .

[0090] Specifically, the first oxide layer 106 can be formed by atomic layer deposition (ALD). During the atomic layer deposition process, the chemical reaction of a new layer of atomic film is directly related to the previous layer. This method allows only one layer of atoms to be deposited per reaction. Therefore, the atomic layer deposition method can form a thin first oxide layer 106 with a precisely controllable thickness. Furthermore, the material of the first oxide layer 106 is silicon oxide. In an optional implementation, the thickness of the first oxide layer 106 is 60-80 angstroms.

[0091] The first oxide layer 106 at least covers the sidewalls of the floating gate 105 to protect the floating gate 105 in a subsequent etching process.

[0092] like Figure 12 As shown, in step S400 , the first oxide layer 106 , the stop layer 102 and the active region substrate 101 between the floating gates are etched to form a groove 107 .

[0093] Specifically, the etching of the first oxide layer 106, the stop layer 102, and the active region substrate 101 between the floating gates 105 is performed by using an anisotropic etching method to etch the first oxide layer 106, the stop layer 102, and the active region substrate 101 between the floating gates 105. Furthermore, a dry etching process can be used to etch the first oxide layer 106, the stop layer 102, and the active region substrate 101 between the floating gates 105.

[0094] In this embodiment, the floating gate material layer 103 and the active region substrate 101 are etched in two steps respectively, which can improve etching accuracy and avoid deviation in the shapes of the floating gate 105 and the active region substrate 101 .

[0095] like Figure 13 As shown, in step S500 , the first oxide layer 106 is removed.

[0096] Specifically, the removal of the first oxide layer 106 is specifically to remove the first oxide layer 106 by a wet etching process. Furthermore, an etching process with a high etching ratio for the first oxide layer 106 can be selected, so that the floating gate 105 will not be damaged while removing the first oxide layer. Furthermore, nitric acid, hydrofluoric acid or other solutions can be used to remove the first oxide layer 106. Since the thickness of the first oxide layer 106 is 60-80 angstroms and the thickness is relatively thin, the first oxide layer 106 can be quickly removed. Since wet etching is used, part of the stop layer 102 and part of the active area substrate 101 below the first oxide layer 106 will also be exposed to the etching solution. When the first oxide layer 106 is removed, part of the stop layer 102 and part of the active area substrate 101 will also be etched.

[0097] like Figure 14 As shown, in step S600 , the surface of the floating gate 105 is oxidized to form a second oxide layer 108 .

[0098] Methods for oxidizing the surface of the floating gate 105 include rapid thermal oxidation (RTO), slot planar antenna (SPA) oxidation, plasma implantation (PI) oxidation, and ozone oxidation.

[0099] The floating gate material layer 103 is polysilicon, and the second oxide layer 108 is silicon dioxide.

[0100] Since the polysilicon on the surface of the floating gate 105 is oxidized into silicon dioxide to form a second oxide layer 108, the size of the floating gate 105 is reduced accordingly compared to before oxidation. This makes the size of the floating gate 105 smaller than the size of the active area substrate between adjacent grooves. Figure 14 In the cross section shown in , the width of the floating gate 105 is smaller than the width of the active region substrate 101 thereunder.

[0101] In an optional implementation, when the material of the active region substrate 101 is single crystal silicon, during the process of oxidizing the floating gate 105 , part of the active region substrate 101 will also be oxidized (not shown in the figure).

[0102] like Figure 15 As shown, in step S700, the second oxide layer 108 is removed to make the top edge of the active area substrate 101 below the floating gate 105 smooth.

[0103] Specifically, the method for removing the second oxide layer 108 is to remove the second oxide layer 108 by a wet etching process.

[0104] Furthermore, nitric acid, hydrofluoric acid or a mixed solution thereof can be used to remove the first oxide layer 106. In an embodiment of the present invention, hydrofluoric acid is selected as the etching solution. Since hydrofluoric acid is used as the etching solution, the stop layer 102 and the active area substrate 101 will also be etched to a certain extent. Therefore, after the etching is completed, a portion of the area on the top surface of the stop layer 102 that is not covered by the floating gate will be etched, and a portion of the active area substrate 101 below the stop layer 102 will also be etched. Because wet etching is to immerse the area to be etched in the etching solution, and during the etching process, the top of the active area substrate 101 contacts the etching solution before the bottom of the active area substrate 101, the top of the active area substrate 101 is etched to a larger size. As in Figure 15 As shown in the cross section of FIG, the angle between the top surface and the sidewall of the active region substrate 101 is an obtuse angle.

[0105] In an embodiment of the present invention, wet etching is used to remove the second oxide layer, so that the top surface of the active area substrate 101 is partially etched, the size of the top surface of the active area substrate 101 is reduced, and the width of the active area substrate 101 gradually increases from the top surface downward. The angle between the sidewall of the active area substrate 101 and the top surface is an obtuse angle, or the sidewall of the area connected to the edge of the top of the active area substrate 101 is arc-shaped. Compared with the comparative example, the top size of the active area substrate 101 is reduced, and the top edge has no sharp corners. This makes the area of ​​the edge relative to the subsequently formed control gate conductive structure deep into the tip area between the columnar floating gates larger, reducing the electric field between the above two, and preventing the semiconductor device from being broken down when leakage current passes through. As a result, the reliability of the semiconductor device can be improved.

[0106] like Figure 16 As shown, in step S800 , the hard mask layer 104 is removed.

[0107] Specifically, wet etching may be used to remove the hard mask layer 104 .

[0108] like Figure 17 As shown, in step S900, an isolation layer 109 is formed to cover the surface of the groove 107 and the surface of the floating gate 105. The upper surface of the isolation layer 109 is higher than the upper surface of the floating gate. The isolation layer 109 is used to electrically isolate adjacent floating gates 105 and protect the active area substrate.

[0109] The isolation layer 109 may be made of silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (with a dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (with a dielectric constant less than 2.5). In an embodiment of the present invention, the isolation layer 109 is made of silicon oxide.

[0110] like Figure 18As shown, in step S1000 , the isolation layer 109 is etched back to form a shallow trench isolation (STI) structure 1091 .

[0111] The shallow trench isolation structure 1091 covers the surface of the active area substrate, and the upper surface of the shallow trench isolation structure 1091 is flush with or slightly higher than the upper surface of the active area substrate, so that adjacent floating gates 105 are electrically isolated from each other.

[0112] Specifically, the isolation layer 109 may be etched using a wet etching process to etch the portion of the isolation layer 109 between the floating gates 105. In the wet etching process, as the etching reaction proceeds, the concentration of the etching solution decreases accordingly, resulting in a gradual decrease in the etching rate. A trench with a cross-sectional width that gradually decreases from top to bottom is formed on the isolation layer 109 between the floating gates 105, and a sharp corner is formed at the bottom of the trench. Figure 18 The cross section of the groove shown in the figure is only an example. It should be understood that the cross section of the groove may vary depending on the actual etching process, and may also be a different shape such as an inverted trapezoid or an inverted triangle.

[0113] like Figure 18 As shown, in step S1100 , a gate dielectric layer 1092 is formed to cover the floating gate 105 and the shallow trench isolation structure 1091 .

[0114] Specifically, after forming the shallow trench isolation structure 1901, a gate dielectric layer 1092 is formed. The gate dielectric layer 1092 covers the floating gate 105 and the shallow trench isolation structure 1091. The gate dielectric layer 1092 may be an oxide-nitride-oxide (ONO) layer. The ONO layer has good corrosion resistance and density, and can protect the floating gate 105. It also electrically isolates the floating gate 105 from the subsequently formed control gate.

[0115] like Figure 19 As shown, in step S1200, a control gate 111 is formed on the gate dielectric layer 1092 and across the floating gate. The material of the control gate 111 can be polysilicon. In a semiconductor device, the control gate is used to connect to a power supply voltage.

[0116] Compared to the comparative example, the embodiment of the present invention reduces the size of the floating gate and increases the integration density of the semiconductor device by oxidizing the floating gate to form a second oxide layer covering the floating gate surface. The first and second oxide layers are removed using a wet etching process, and while removing the oxide layers, a portion of the active area substrate is also etched, reducing the size of the top of the active area and smoothing the top edge of the active area substrate. This avoids the phenomenon of excessively high electric fields between the control gate and the active area substrate, which can lead to semiconductor device failure, as in the comparative example, thereby improving the reliability of the semiconductor device.

[0117] In an embodiment of the present invention, an oxide layer is added during and after the floating gate is formed, and the oxide layer is subsequently removed to smooth the edge of the top of the pillar-shaped active region below the floating gate. This allows the edge to have a larger area than the surface of the subsequently formed control gate conductive structure that extends into the tip region between the pillar-shaped floating gates. This reduces the electric field between the two, preventing the semiconductor device from being broken down when leakage current passes through. This improves the reliability of the semiconductor device.

[0118] On the other hand, an embodiment of the present invention further provides a semiconductor device, comprising: a semiconductor substrate and a floating gate.

[0119] The semiconductor substrate includes an active region base having a groove and a stop layer on top of the active region base.

[0120] The floating gate is formed on the active region substrate.

[0121] Wherein, the top edge of the active area substrate below the floating gate is smooth.

[0122] Figure 20 FIG is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 20 As shown, in an optional implementation, the semiconductor device includes: a semiconductor substrate 10 ′, a floating gate 105 ′, a shallow trench isolation structure 1091 ′ and a control gate 111 ′.

[0123] The semiconductor substrate includes an active region base 101 ′ having a groove 107 ′ and a stop layer 102 ′ on top of the active region base 101 ′.

[0124] The active region substrate 101 ′ may be made of single crystal silicon.

[0125] The material of the stop layer 102' can be silicon oxide, silicon nitride or silicon carbide.

[0126] The floating gate 105' is formed on the active substrate 101'. The top edge of the active substrate 101' below the floating gate is smooth. The size of the floating gate 105' is smaller than the size of the active substrate 101' between adjacent grooves 107'.

[0127] The floating gate 105 ′ may be made of doped polysilicon.

[0128] The shallow trench isolation structure 1091' covers a portion of the sidewall of the floating gate 105' and the active region substrate 101'. The shallow trench isolation structure 1091' is used to isolate the floating gate 105' from the control gate 111'.

[0129] The shallow trench isolation structure 1091' covers the surface of the active area substrate. The upper surface of the shallow trench isolation structure 1091' is flush with or slightly higher than the upper surface of the active area substrate 101', thereby electrically isolating adjacent floating gates 105' from each other. The middle portion of the upper surface of the shallow trench isolation structure 1091' is recessed downward, forming a trench whose cross-sectional width gradually decreases from top to bottom.

[0130] The gate dielectric layer 1092' covers the floating gate 105' and the shallow trench isolation structure 1091'. The gate dielectric layer 1092' may be an oxide-nitride-oxide (ONO) layer. The ONO layer has good corrosion resistance and compactness and can protect the floating gate 105'.

[0131] The shallow trench isolation structure 1091' may be made of silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (with a dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (with a dielectric constant less than 2.5). In an embodiment of the present invention, the shallow trench isolation structure 1091' is made of silicon oxide.

[0132] The control gate 111 ′ is formed on the isolation layer 109 ′ and straddles the floating gate 105 ′.

[0133] The control gate 111 ′ may be made of doped polysilicon.

[0134] In an embodiment of the present invention, the top edge of the active area substrate beneath the floating gate is smooth, resulting in a larger area of ​​the edge relative to the control gate conductive structure extending into the tip region between the pillar-shaped floating gates. This reduces the electric field between the two and prevents breakdown of the semiconductor device when leakage current passes through. This improves the reliability of the semiconductor device. In an embodiment of the present invention, the top edge of the active area substrate beneath the floating gate is smooth, thereby improving the reliability of the semiconductor device.

[0135] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising an active area base, a stop layer, a floating gate material layer and a hard mask layer stacked in sequence; Etching the hard mask layer and the floating gate material layer in a predetermined area until the stop layer is exposed to form a discrete floating gate; depositing a first oxide layer covering the floating gate and the stop layer; Etching the first oxide layer, the stop layer, and the active area substrate between the floating gates to form a groove; removing the first oxide layer; oxidizing the surface of the floating gate to form a second oxide layer; removing the second oxide layer to smooth the top edge of the active area substrate below the floating gate; After removing the second oxide layer, removing the hard mask layer; forming an isolation layer covering a surface of the groove and a surface of the floating gate, wherein an upper surface of the isolation layer is higher than an upper surface of the floating gate; The isolation layer is etched back to form a shallow trench isolation structure.

2. The method according to claim 1, characterized in that The size of the floating gate is smaller than the size of the active region substrate between adjacent grooves.

3. The method according to claim 1, characterized in that Depositing the first oxide layer covering the floating gate specifically comprises forming the first oxide layer by atomic layer deposition.

4. The method according to claim 1, wherein The thickness of the first oxide layer is 60-80 angstroms.

5. The method according to claim 1, wherein The removing of the first oxide layer is specifically removing the first oxide layer by using a wet etching process.

6. The method according to claim 1, wherein The method of oxidizing the surface of the floating gate includes: rapid thermal oxidation, trench planar antenna oxidation, plasma injection oxidation and ozone oxidation.

7. The method according to claim 6, characterized in that The floating gate material layer is polysilicon, and the second oxide layer is silicon dioxide.

8. The method according to claim 1, characterized in that The method for removing the second oxide layer is specifically to remove the second oxide layer by using a wet etching process.

9. The method according to claim 1, characterized in that The etching of the first oxide layer, the stop layer and the active region substrate between the floating gates is specifically performed by etching the first oxide layer, the stop layer and the active region substrate between the floating gates using an anisotropic etching method.

10. The method according to claim 1, characterized in that The method for forming the semiconductor device further includes: forming a gate dielectric layer covering the floating gate and the shallow trench isolation structure; A control gate is formed on the gate dielectric layer and crosses the floating gate.

11. A semiconductor device, characterized in that: The semiconductor device is formed by the method for forming a semiconductor device according to any one of claims 1 to 10, and the semiconductor device comprises: A semiconductor substrate comprising an active region base having a groove and a stop layer on top of the active region base, wherein an angle between a top surface and a sidewall of the active region base is an obtuse angle; a floating gate formed on the active region substrate; A shallow trench isolation structure is provided, wherein a trench having a cross-sectional width gradually decreasing from top to bottom is formed between the floating gates, the bottom of the trench forming a sharp corner, or the cross-sectional shape of the trench being an inverted trapezoid or an inverted triangle; wherein the top edge of the active area substrate below the floating gate is smooth, and the size of the floating gate is smaller than the size of the active area substrate between adjacent grooves.

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