Semiconductor device and method of manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a gate structure located on the substrate, and a gate dielectric layer located between the substrate and the gate structure. The gate structure includes a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer is located on the first sidewall and the gate dielectric layer, and the first insulating layer includes a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacer walls are respectively located on the first insulating layer and the second sidewall.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device with an asymmetric gate structure and a manufacturing method thereof. Background Art

[0002] In power devices with high-voltage processing capabilities, double-diffused metal-oxide-semiconductor (DMOS) devices have been continuously attracting attention. Common DMOS devices include vertical double-diffused metal-oxide-semiconductor (VDMOS) devices and lateral double-diffused metal-oxide-semiconductor (LDMOS) devices. The main feature of the LDMOS device is that it includes a low-doping-concentration, large-area drift region to buffer the high voltage of the drain region, enabling the LDMOS device to withstand a higher operating voltage. In addition, due to the planar structure of the LDMOS device that is easy to integrate with other integrated circuit devices, it has now been widely used in high-voltage processing devices, such as central processing unit power supplies (CPU power supplies), power management systems, DC / AC converters, and high-power or high-frequency power amplifiers, etc.

[0003] In order to make the maximum voltage (or breakdown voltage) that the device can withstand meet the design requirements, the drift region of the LDMOS usually occupies a certain area, which is not conducive to the miniaturization of the device size. Therefore, how to maintain the breakdown voltage performance that meets the design requirements under the condition of device miniaturization is still an important topic that the field has been continuously researching. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof. By using a selective oxidation manufacturing process, an insulating layer is formed on the sidewall of the gate structure close to the drain region and the bottom corner of the gate structure is simultaneously rounded, which can improve the breakdown voltage of the semiconductor device.

[0005] According to a semiconductor device provided by an embodiment of the present invention, it includes a substrate, and a gate structure located on the substrate. The gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, a gate dielectric layer located between the substrate and the gate structure, and a first insulating layer located on the first sidewall and the gate dielectric layer. The first insulating layer includes a first bird's beak covering the rounded bottom corner of the gate structure, and a pair of spacer walls respectively located on the first insulating layer and the second sidewall.

[0006] A method for fabricating a semiconductor device according to another embodiment of the present invention includes first providing a substrate, then forming a gate structure on the substrate, wherein the gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, then forming a mask layer to completely cover the substrate and the gate structure, and patterning the mask layer to form an opening exposing the first sidewall of the gate structure. Subsequently, an oxidation process is performed to form a first insulating layer on the first sidewall, then the mask layer is removed, and then a pair of spacer walls are formed on the first insulating layer and the second sidewall respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 6 Schematic cross-sectional views of steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein:

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device at the beginning of the method;

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device after forming a mask layer;

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device after forming a patterned mask layer;

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after forming an insulating layer;

[0012] Figure 5 is a schematic cross-sectional view of a semiconductor device after forming a pair of spacer walls; and

[0013] Figure 6 is a schematic cross-sectional view of a semiconductor device after forming an interlayer dielectric layer and contact plugs;

[0014] Figures 7 to 10 Schematic cross-sectional views of steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention, wherein:

[0015] Figure 7 is a schematic cross-sectional view of a semiconductor device after forming a patterned mask layer;

[0016] Figure 8 is a schematic cross-sectional view of a semiconductor device after forming an insulating layer; and

[0017] Figure 9 is a schematic cross-sectional view of a semiconductor device after forming a pair of spacer walls; and

[0018] Figure 10 is a schematic cross-sectional view of a semiconductor device after forming an interlayer dielectric layer and contact plugs.

[0019] Description of Main Component Symbols

[0020] 10a Main Surface in the X Direction

[0021] 10b Rounded Top Angle in the Y Direction

[0022] 10 Substrate 18a First Part

[0023] 12 Well Region 18b Second Part

[0024] 14 Drift Region 22a First Top Angle

[0025] 16 Body Region 22b First Bottom Angle

[0026] 18 Gate Dielectric Layer 23a Rounded Top Angle

[0027] 20 Gate Structure 23b Rounded Bottom Angle

[0028] 22 First Sidewall 24a Second Top Angle

[0029] 23 First Sidewall 24b Second Bottom Angle

[0030] 24 Second Sidewall 40a Second Bird's Beak

[0031] 26 Top Surface 40b First Bird's Beak

[0032] 30 Mask Layer 42a Third Bird's Beak

[0033] 32 Opening 42b Bottom Surface

[0034] 34 Opening 42c Top Surface

[0035] 40 Insulating Layer 50a Spacer

[0036] 42 Insulating Layer 50b Spacer

[0037] 52 Drain Region D1 Width

[0038] 53 Part D2 Width

[0039] 54 Source Region P1 Oxidation Fabrication Process

[0040] 60 Interlayer Dielectric Layer T1 Thickness

[0041] 62 Contact Plug T2 Thickness

[0042] 140 Interface

[0043] 160 Interface Detailed Embodiments

[0044] To make the above objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are hereinafter specifically exemplified and described in detail in conjunction with the accompanying drawings. The accompanying drawings are all schematic diagrams, not drawn to scale, and the same or similar features are usually described with the same reference numerals. The embodiments described herein and the drawings are for reference and illustration only, and are not used to limit the present invention. The scope of the present invention is defined by the claims. Those having the same meaning as the claims of the present invention should also fall within the scope of the present invention. Hereinafter, taking the fabrication of a high-voltage metal-oxide semiconductor device as an example for illustration, it should be understood that the semiconductor devices and methods of the present invention can also be used for other semiconductor devices.

[0045] Figures 1 to 6 FIG. is a schematic cross-sectional view of the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention. The cross-section shown in the figure is a cross-section on a plane defined by the X direction and the Y direction. The X direction and the Y direction are perpendicular to each other. As Figure 1 shown, first, a substrate 10 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium semiconductor substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, etc., but not limited thereto. The substrate 10 has a main surface 10a perpendicular to the Y direction, and a well region 12 formed below the main surface 10a. The well region 12 can be a doped region formed by implanting dopants from the main surface 10a into the substrate 10 using an ion implantation process, or a doped epitaxial layer of the substrate 10. According to an embodiment of the present invention, the well region 12 can have a first conductivity type, such as N-type, and the substrate 10 can have a second conductivity type complementary to the first conductivity type, such as P-type. It should be particularly noted that the "first conductivity type" and "second conductivity type" mentioned herein are used to describe the complementary conductivity types of semiconductor materials. In this embodiment, the "first conductivity type" and "second conductivity type" respectively correspond to N-type and P-type, and it should be understood that in other embodiments, they can also respectively correspond to P-type and N-type.

[0046] As Figure 1As shown, a gate structure 20 is formed on the main surface 10a of a substrate 12, and is separated from the substrate 10 by a gate dielectric layer 18. The gate structure 20 has a first sidewall 22 and a second sidewall 24 on opposite sides along the X direction. The first sidewall 22 is between the first apex angle 22a and the first bottom angle 22b of the gate structure 20, and the second sidewall 24 is between the second apex angle 24a and the second bottom angle 24b. The gate structure 20 further includes a top surface 26 between the first sidewall 22 and the second sidewall 24. In some embodiments, the gate structure 20 may include a conductive material, such as polysilicon, but is not limited thereto. The gate dielectric layer 18 may include an insulating material, such as silicon oxide, silicon nitride, a high-k dielectric layer, etc., but is not limited thereto. A method of forming the gate structure 20 and the gate dielectric layer 18 is, for example, to form a gate dielectric material layer (such as silicon oxide) comprehensively on the substrate 10, then deposit a gate material layer (such as polysilicon) on the gate dielectric material layer, and then use a patterning process (such as a lithography and etching process) to etch and remove part of the gate material layer and the gate dielectric material layer to form the gate dielectric layer 18 and the gate structure 20 as shown in Figure 1 shown.

[0047] Please continue to refer to Figure 1 , a drift region 14 and a body region 16 are respectively formed in the substrate 10 adjacent to the first sidewall 22 and the second sidewall 24, and are separated by a well region 12 and do not contact directly. The drift region 14 has the same first conductivity type as the well region 12, such as N-type. The body region 16 has a second conductivity type, such as P-type. The first sidewall 22 of the gate structure 20 is located near directly above the interface 140 between the drift region 14 and the well region 12, and can be aligned with the interface 140 in the Y direction as shown in Figure 1 shown, or can be slightly displaced along the X direction and located directly above the drift region 14 or the well region 12. The gate structure 20 straddles directly above the interface 160 between the body region 16 and the well region 12, so that the gate structure 20 partially overlaps with the body region 16 in the Y direction.

[0048] Please refer to Figure 2 . Then, a mask layer 30 is deposited comprehensively on the substrate 10, conformally covering the main surface 10a of the substrate 10, the first sidewall 22, the second sidewall 24 and the top surface 26 of the gate structure 20. In some embodiments, the mask layer 30 is, for example, a silicon nitride layer formed by a plasma enhanced chemical vapor deposition (PECVD) or a sub-atmospheric chemical vapor deposition (SACVD) process, and its thickness T2 is preferably about 25% of the thickness T1 of the gate structure 20. For example, when the thickness T1 of the gate structure 20 is about 800 angstroms , the thickness T2 of the mask layer 30 is preferably about If the thickness of the mask layer 30 is too thick, it will cause difficulties in selectively removing part of the mask layer 30 for patterning the mask layer 30 later. If the thickness is insufficient, it will not be able to ensure that the area covered by it will not be oxidized during the subsequent oxidation process P1 (refer to Figure 4 ).

[0049] Please refer to Figure 3 . Then, a patterning process can be performed on the mask layer 30. For example, a lithography and etching process can be performed to remove part of the mask layer 30, and an opening 32 is formed in the mask layer 30 to expose the first sidewall 22, the first apex angle 22a, and part of the top surface 26 of the gate structure 20. It should be noted that after patterning the mask layer 30, the remaining parts of the gate structure 20 and the main surface 10a of the substrate 10 are still completely covered by the mask layer 30 and are not exposed.

[0050] Please refer to Figure 4 . Then, an oxidation process P1 is performed to oxidize the gate structure 20 from the opening 32, so as to oxidize part of the gate structure 20 into an insulating layer 40, covering the first sidewall 23 of the oxidized gate structure 20 and the gate dielectric layer 18. The oxidation process P1 can be a dry oxidation process using oxygen (O2) and nitrogen (N2), or a wet oxidation process using oxygen (O2), hydrogen (H2), and nitrogen (N2). In some embodiments, when the gate structure 20 includes polysilicon, the insulating layer 40 includes silicon oxide. In some embodiments, since the gas (such as oxygen) in the oxidation process P1 is more likely to penetrate along the junction of heterogeneous materials, for example, along the junction of the gate structure 20 and the gate dielectric layer 18, the gate structure 20 near the junction has a slightly higher oxidation rate. Therefore, a first beak portion 40b is formed in the part of the insulating layer 40 close to the gate dielectric layer 18, covering the rounded bottom corner 23b of the oxidized gate structure 20. Similarly, in some embodiments, the top surface 26 of the gate structure 20 also has a slightly higher oxidation rate, so that a second beak portion 40a is formed in the part of the insulating layer 40 close to the top surface 26, covering a rounded apex angle 23a of the gate structure 20. In some embodiments, the gas in the oxidation process P1, such as oxygen, hydrogen, or nitrogen, will diffuse to a first part 18a of the gate dielectric layer 18 directly below the insulating layer 40. Therefore, the composition of the first part 18a is different from that of the second part 18b of the gate dielectric layer 18 directly below the gate structure 20. For example, the first part 18a may have a higher oxygen, hydrogen, or nitrogen content compared to the second part 18b. As Figure 4 shown, the junction between the first part 18a and the second part 18b is generally aligned with the first beak portion 40b in the Y direction. In some embodiments, the width D1 of the opening 32 as shown in Figure 3 and the time of the oxidation process P1 can be controlled to control the thickness of the insulating layer 40 along the X direction.

[0051] Please refer to Figure 5 . After completing the oxidation process P1, the mask layer 30 is then removed to expose the top surface and the second sidewalls 22 of the gate structure 20 and the main surface 10a of the substrate, and then a pair of spacer walls 50a and 50b are formed on the insulating layer 40 and the second sidewalls 24 on both sides of the gate structure 20 respectively. The spacer walls 50a and 50b can be fabricated using existing self-aligned spacer wall fabrication processes. For example, a spacer wall material layer (not shown in the figure) is first deposited comprehensively on the substrate 10, and then an anisotropic etching process (such as a dry etching process) is performed to remove a portion of the spacer wall material layer, so that the remaining spacer wall material layer is self-aligned on the sidewalls of the gate structure 20, forming the spacer walls 50a and 50b on both sides of the gate structure 20 as shown in the cross-sectional view. Those skilled in the art should understand that single-layer or multi-layer spacer walls 50a and 50b can be fabricated by depositing a single layer or multiple layers of spacer wall material layers and combining single or multiple anisotropic etching processes. In some embodiments, one or more fabrication process steps may be further included during the period after removing the mask layer 30 and before forming the spacer walls 50a and 50b. For example, one or more lightly doped ion implantation processes may be included, using the gate structure 20 and the insulating layer 40 as masks to implant dopants into the substrate 10 on both sides of the gate structure 20 to form lightly doped regions (not shown in the figure). As Figure 6 shown, a portion of the gate structure 20 adjacent to the drain region 52 is selectively oxidized in the present invention. Therefore, the gate structure 20 located between the spacer walls 50a and 50b will have an asymmetric cross-sectional shape, and its top and bottom corners (i.e., the rounded top corner 23a and the rounded bottom corner 23b) adjacent to the drain region 52 have a more rounded cross-sectional shape compared to the top and bottom corners (i.e., the second top corner 24a and the second bottom corner 24b) adjacent to the source region 54.

[0052] Please refer to Figure 6。Next, an implantation process is carried out. Using the gate structure 20, the insulating layer 40, and the spacer walls 50a and 50b as masks, doping is implanted into the substrate 10 on both sides of the gate structure 20 to form a drain region 52 and a source region 54 that are self-aligned to the outside of the spacer walls 50a and 50b respectively. Then, an interlayer dielectric layer 60 is formed comprehensively to cover the substrate 10 and the gate structure 20. Next, contact plugs 62 that are electrically connected to the gate structure 20, the drain region 52, and the source region 54 are formed in the interlayer dielectric layer 60, obtaining the semiconductor device 100 of the present invention. In this embodiment, both the drain region 52 and the source region 54 have a first conductivity type, such as N-type. The drain region 52 is completely located in the drift region 14 and is separated from the rounded bottom corner 23b of the gate structure 20 by the spacer wall 50a, the first part 18a of the gate dielectric layer 18, and the insulating layer 40. The source region 54 is completely located in the body region 16 and is separated from the second bottom corner 24b of the gate structure 20 by the spacer wall 50b and the second part 18b of the gate dielectric layer 18. The channel region L of the semiconductor device 100 is located in the body region 16 directly below the gate structure 20 and close to the main surface 10a of the substrate 10, between the interface 160 between the body region 16 and the well region 12 and the source region 54. The channel length of the channel region L is affected by the width of the overlap between the gate structure 20 and the body region 16 and the distance between the source region 54 (or a lightly doped region, not shown in the figure) and the sidewall of the gate structure 20 during the manufacturing process. Through the voltage division of the drift region 14 and the well region 12 directly below the gate structure 20, the high voltage of the drain region 52 is reduced to a low enough level when reaching the channel region L, avoiding breakdown between the drain region 52 and the source region 54.

[0053] As Figure 6As shown, the present invention selectively oxidizes a portion of the gate structure 20 adjacent to the drain region 52 into the insulating layer 40 by means of the mask layer 30 in combination with the oxidation process P1, so that the conductive portion (such as the polysilicon portion) of the oxidized gate structure 20 is further away from the drain region 52. Thus, without unexpectedly affecting the electrical properties of the source region 54 and the channel region L of the semiconductor device 100 and other components integrated with the semiconductor device 100, the electrical insulation between the gate structure 20 and the drain region 52 is significantly improved. On the other hand, the present invention rounds the bottom corners of the gate structure 20 adjacent to the drain region 52 by means of the oxidation process P1 to form rounded bottom corners 23b, which can further reduce the electric field strength near the bottom corners of the gate structure 20 compared with the unrounded first bottom corners 22b. On the other hand, by allowing the gas of the oxidation process P1 to diffuse into the gate dielectric layer 18, the effect of repairing the defects generated in the gate dielectric layer 18 due to the manufacturing process (such as the etching process for patterning the gate structure 20 and the gate dielectric layer 18) can be achieved, that is, the first portion 18a of the gate dielectric layer 18 can have fewer defects and better dielectric quality. Combining the above features, the semiconductor device 100 of the present invention can effectively reduce the possibility of gate-drain breakdown and has a higher gate-drain breakdown voltage.

[0054] The following will describe different embodiments of the present invention. For the sake of simplicity, the following description mainly details the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in the various embodiments of the present invention are labeled with the same reference numerals for convenient comparison between the embodiments.

[0055] Figures 7 to 10 Schematic cross-sectional view of the steps of the manufacturing method of the semiconductor device according to the second embodiment of the present invention. The difference from the first embodiment described above is that, as Figure 7 shown, the opening 34 after patterning the mask layer 30 exposes the first sidewall 22, the first top corner 22a and a part of the top surface 26 of the gate structure 20, and also exposes the main surface 10a of a part of the substrate 10 adjacent to the first sidewall 22. Similarly, the remaining parts of the gate structure 20 and the remaining parts of the substrate 10 are still completely covered by the mask layer 30 and are not exposed.

[0056] Please refer to Figure 8。Next, an oxidation process P1 is performed. The portions of the gate structure 20 and the substrate 10 exposed from the opening 34 are oxidized to form an insulating layer 40 covering the first sidewall 23 of the oxidized gate structure 20 and an insulating layer 42 in the substrate 10 adjacent to the first sidewall 23. In some embodiments, when the substrate 10 comprises silicon, the insulating layer 42 comprises silicon oxide. The bottom surface 42b of the insulating layer 42 is lower than the main surface 10a of the substrate 10. In some embodiments, the thickness of the insulating layer 42 is approximately equal to the thickness of the insulating layer 40. In some embodiments, the insulating layer 42 may include a third bird's beak portion 42a near the main surface 10a of the substrate 10, and its end extends along the main surface 10a of the substrate 10, covering a rounded top corner 10b of the substrate 10. Similar to the first embodiment, the first portion 18a of the gate dielectric layer 18 adjacent to the first sidewall 22 will also be further oxidized into the first portion 18a during the oxidation process P1, and its oxygen content can be higher than that of the second portion 18b of the gate dielectric layer 18 directly below the gate structure 20. As Figure 8 shown, the insulating layer 40, the first portion 18a of the gate dielectric layer 18, and the insulating layer 42 together form an L-shaped insulating layer. Similarly, in some embodiments, the width D1 of the opening 34 and the time of the oxidation process P1 can be controlled to control the thickness of the insulating layer 40 along the X direction and the thickness of the insulating layer 42 along the Y direction.

[0057] Please refer to Figure 9 。Next, the mask layer 30 is removed, exposing the top surface of the gate structure 20, the second sidewall 22, and the main surface 10a of the substrate. Then, a pair of spacer walls 50a and 50b are formed on the L-shaped insulating layer and the second sidewall 24 on both sides of the gate structure 20. In some embodiments, the Figure 8 width D2 of the opening 34 shown can be controlled such that the length of the insulating layer 42 along the X direction is greater than the width of the spacer wall 50a, so that the bottom of the spacer wall 50a is completely located on the insulating layer 42, and a partial top surface 42c of the insulating layer 42 is exposed.

[0058] Please refer to Figure 10。Next, an implantation process is carried out. Using the gate structure 20, the insulating layer 40, and the spacer walls 50a and 50b as masks, doping is implanted into the substrate 10 on both sides of the gate structure 20 to form a drain region 52 and a source region 54 that are self-aligned to the outer sides of the spacer walls 50a and 50b respectively. Then, an interlayer dielectric layer 60 is formed comprehensively to cover the substrate 10 and the gate structure 20. Subsequently, contact plugs 62 that are electrically connected to the gate structure 20, the drain region 52, and the source region 54 are formed in the interlayer dielectric layer 60, obtaining the semiconductor device 100 of the present invention. It should be noted that in some embodiments, due to the partial blocking of the insulating layer 42, the portion 53 of the drain region 52 that is located below the insulating layer 42 and closer to the gate structure 20 has a lower doping concentration, which can reduce the electric field strength in this region and further improve the breakdown voltage resistance of the semiconductor device 100.

[0059] In summary, in one embodiment of the present invention, by selectively oxidizing the sidewall of the gate structure adjacent to the drain region, a first insulating layer is formed, making the conductive region of the oxidized gate structure farther away from the drain region, and at the same time rounding the bottom corners of the gate structure close to the drain region, thereby effectively increasing the breakdown voltage between the gate and the drain. In another embodiment of the present invention, a part of the substrate adjacent to the sidewall is also oxidized to form a second insulating layer. Through the partial blocking effect of the second insulating layer on the source / drain implantation process, the portion of the drain region close to the gate structure 20 has a lower doping concentration, which can further increase the breakdown voltage between the gate and the drain.

[0060] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a substrate; a gate structure located on a main surface of the substrate, the gate structure including a first sidewall and a second sidewall opposite to the first sidewall; a gate dielectric layer located between the substrate and the gate structure; a first insulating layer located on a side of the first sidewall and on a top surface of the gate dielectric layer, wherein the first insulating layer includes: a first bird's beak covering a rounded bottom corner of the gate structure; and a second bird's beak extending from the first sidewall toward the second sidewall and covering a side of a rounded top corner of the gate structure away from the gate dielectric layer; a first spacer located on a side of the first insulating layer; a second spacer located on a side of the second sidewall, wherein the second sidewall is in direct contact with the second spacer, and the first sidewall and the first spacer are completely separated by the first insulating layer; a second insulating layer located in the substrate below the first spacer and in direct contact with the first spacer; and a drain region located in the substrate adjacent to the second insulating layer, wherein a part of the drain region is below the second insulating layer.

2. The semiconductor device according to claim 1, wherein the gate dielectric layer includes a first part directly below the first insulating layer and a second part directly below the gate structure, and a junction between the first part and the second part is vertically aligned with the first bird's beak.

3. The semiconductor device according to claim 2, wherein the first part and the second part of the gate dielectric layer have different compositions.

4. The semiconductor device according to claim 1, wherein a bottom surface of the second insulating layer is lower than a top surface of the substrate.

5. The semiconductor device according to claim 4, wherein the second insulating layer includes a third bird's beak adjacent to the top surface of the substrate.

6. The semiconductor device according to claim 4, wherein a top surface of the second insulating layer is exposed from a bottom of the first spacer.

7. The semiconductor device according to claim 1, further including: a well region located in the substrate, the well region having a first conductivity type; a drift region located in the well region and adjacent to the first sidewall of the gate structure, the drift region having the first conductivity type; a body region located in the well region and adjacent to the second sidewall of the gate structure, the body region having a second conductivity type complementary to the first conductivity type, and the gate structure straddles a junction between the body region and the well region; the drain region located in the drift region outside the first spacer on the first insulating layer; and a source region located in the body region outside the second spacer on the second sidewall.

8. A method for manufacturing a semiconductor device, including: providing a substrate; forming a gate structure on a main surface of the substrate, the gate structure being separated from the substrate by a gate dielectric layer, the gate structure including a first sidewall and a second sidewall opposite to the first sidewall; forming a mask layer to completely cover the substrate and the gate structure; patterning the mask layer to form an opening exposing the first sidewall of the gate structure; Perform an oxidation process to form a first insulating layer on the side of the first sidewall and a second insulating layer on a part of the main surface of the substrate, where the first insulating layer includes: A first bird's beak portion covering the rounded bottom corner of the gate structure; A second bird's beak portion extending from the first sidewall toward the second sidewall and covering the side of the rounded top corner of the gate structure away from the gate dielectric layer; Remove the mask layer; And Form a first spacer and a second spacer, where the first spacer is located on the side of the first insulating layer and on the top surface of the second insulating layer, and the second spacer is located on the side of the second sidewall; Form a drain region in the substrate adjacent to the second insulating layer, where a part of the drain region is under the second insulating layer.

9. The manufacturing method according to claim 8, wherein the oxidation process includes oxidizing the gate structure to form the first insulating layer.

10. The manufacturing method according to claim 8, wherein the gate structure includes polysilicon and the first insulating layer includes silicon oxide.

11. The manufacturing method according to claim 8, wherein the mask layer includes silicon nitride.

12. The manufacturing method according to claim 8, wherein a part of the substrate adjacent to the first sidewall is exposed from the opening of the mask layer.

13. The manufacturing method according to claim 12, wherein the oxidation process includes: Oxidizing the first sidewall to form the first insulating layer; and Oxidizing the exposed part of the substrate to form the second insulating layer.

14. The manufacturing method according to claim 13, wherein the second insulating layer includes a bottom surface that is lower than the main surface of the substrate.

15. The manufacturing method according to claim 13, wherein the top surface of the second insulating layer is exposed from the bottom of the first spacer.

16. The manufacturing method according to claim 8, wherein before forming the gate structure, it further includes: Forming a well region in the substrate, having a first conductivity type; Forming a drift region and a body region in the well region, where the drift region and the body region are separated by the well region and do not directly contact each other. The drift region has the first conductivity type, the body region has a second conductivity type complementary to the first conductivity type, and the gate structure straddles a boundary between the body region and the well region.

17. The manufacturing method according to claim 16, wherein after forming the first spacer and the second spacer, it further includes: Performing an implantation process on the substrate using the first spacer and the second spacer as masks to form a drain region and a source region that are self-aligned with the first spacer and the second spacer respectively. The drain region is located in the drift region and includes the first conductivity type, and the source region is located in the body region and includes the first conductivity type.

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