Semiconductor structure and forming method thereof

Abstract

A method is provided that includes providing a substrate having an N-type region for n-type field effect transistors (nFETs) and a P-type region for p-type field effect transistors (pFETs); forming a gate dielectric layer in the N-type region and the P-type region to wrap the vertically stacked channels; performing dipole processing on the first part of the gate dielectric layer in the N-type region, and keeping the second part of the gate dielectric layer in the P-type region unprocessed; depositing a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region; and forming a filling metal layer on the P-type metal layer of the P-type region and the N-type region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor technology, and more particularly to semiconductor structures. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. As a result of this growth, the feature sizes of integrated circuits have decreased, and the densities of various components (e.g., transistors and other active devices) have increased. In the pursuit of smaller feature sizes and increased densities, traditionally-deposited materials have been replaced with epitaxially-grown materials having superior properties with respect to the traditionally-deposited materials. For example, as device sizes continue to shrink, device performance (e.g., device performance degradation associated with various defects) and manufacturing costs become more challenging. Although approaches to address this challenge have generally been adequate, they have not been entirely satisfactory in all respects. SUMMARY

[0003] The present disclosure provides a method of forming a semiconductor structure, comprising: providing a substrate, the substrate having an N-type region for an n-type field effect transistor and a P-type region for a p-type field effect transistor; forming a semiconductor fin protruding from the substrate, the semiconductor fin comprising a plurality of first semiconductor layers of a first semiconductor material and a plurality of second semiconductor layers of a second semiconductor material alternately stacked, the second semiconductor material having a different composition than the first semiconductor material; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source / drain (S / D) region adjacent to the first gate stack; performing an etching process to selectively remove the second semiconductor layers, thereby creating gaps between the first semiconductor layers; filling the gaps with a dielectric material to form a plurality of dummy spacers; epitaxially growing a source / drain component from the recess; removing the first gate stack, thereby forming a gate trench; performing an etching process to remove the dummy spacers through the gate trench; forming a gate dielectric layer to wrap around the first semiconductor layers; performing a dipole treatment on a first portion of the gate dielectric layer in the N-type region, while a second portion of the gate dielectric layer in the P-type region remains untreated; and depositing a P-type metal layer in the gate dielectric layer in the P-type region and the N-type region.

[0004] A method of forming a semiconductor structure is provided. The method includes providing a substrate having an N-type region for an n-type field-effect transistor and a P-type region for a p-type field-effect transistor (pFET), forming a gate dielectric layer in the N-type region and the P-type region to wrap a plurality of vertically stacked channels, performing a dipole treatment on a first portion of the gate dielectric layer in the N-type region while a second portion of the gate dielectric layer in the P-type region remains untreated, depositing a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region, and forming a fill metal layer in the P-type metal layer of the P-type region and the N-type region.

[0005] A semiconductor structure is provided. The semiconductor structure includes a substrate having an N-type region for an n-type field-effect transistor and a P-type region for a p-type field-effect transistor, a first channel region disposed on the N-type region of the substrate and a second channel region disposed on the P-type region of the substrate, wherein the first channel region includes a plurality of first channels vertically stacked with each other and the second channel region includes a plurality of second channels vertically stacked with each other, a first source / drain (S / D) region adjacent to the first channel region and a second S / D region adjacent to the second channel region, and a gate stack disposed on the first channel region and the second channel region, wherein the gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, the gate dielectric layer includes a first portion located in the P-type region and a second portion located in the N-type region, the first portion of the gate dielectric layer includes a first lanthanum concentration Cp and fits the first channel region and surrounds each of the first channels, the second portion of the gate dielectric layer includes a second lanthanum concentration Cn and fits the second channel region and surrounds each of the second channels, Cn is greater than Cp, the gate electrode includes a P-type metal layer disposed on the gate dielectric layer, and the P-type metal layer extends from the P-type region to the N-type region. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the illustrative embodiments can be best understood with reference to the following detailed description when read with the accompanying drawings in which:

[0007] Figure 1A A flow diagram of an example method for fabricating a semiconductor device according to some embodiments of the present disclosure is illustrated.

[0008] Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G and Figure 1H A flowchart illustrating an example method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided.

[0009] Figure 2A A three-dimensional perspective view of an example semiconductor device according to some embodiments of the present disclosure is illustrated.

[0010] Figure 2B A plan view of an example semiconductor device according to some embodiments of the present disclosure is shown.

[0011] Figure 3A Examples of some embodiments according to this disclosure are illustrated. Figure 1A The intermediate stage of the method embodiment in the semiconductor device Figure 2A and Figure 2B A cross-sectional view taken along line A-A'.

[0012] Figure 3B Examples of some embodiments according to this disclosure are illustrated. Figure 1A The intermediate stage of the method embodiment in the semiconductor device Figure 2A and Figure 2B A cross-sectional view taken along line B-B'.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Some embodiments according to this disclosure are illustrated. Figure 2A and Figure 2B Semiconductor devices in Figure 1A A cross-sectional view taken along line B-B' in the intermediate stage of an embodiment of the method.

[0014] Figure 4F and Figure 4G Some embodiments according to this disclosure are illustrated. Figure 2A and Figure 2B Semiconductor devices in Figure 1A A cross-sectional view taken along line C-C' in the intermediate stage of an embodiment of the method.

[0015] Figure 5A and Figure 5B Examples of structures constructed according to some embodiments of this disclosure are illustrated. Figure 2A and Figure 2B A partial cross-sectional view of a semiconductor device taken along line C-C'.

[0016] Figure 6A Examples of some embodiments according to this disclosure are illustrated. Figure 1A The intermediate stage of the method embodiment in the semiconductor device Figure 2A and Figure 2B A cross-sectional view taken along line A-A'.

[0017] Figure 6B Examples of some embodiments according to this disclosure are illustrated. Figure 1A The intermediate stage of the method embodiment is intercepted along line D-D'. Figure 2A and Figure 2B A cross-sectional view of a semiconductor device.

[0018] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G and Figure 7H Some embodiments according to this disclosure are illustrated. Figure 2A and Figure 2B Semiconductor devices in Figure 1B A partial cross-sectional view taken along line C-C' in the intermediate stage of an embodiment of the method.

[0019] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F Examples Figure 2A and Figure 2B Semiconductor devices according to Figure 1C A partial cross-sectional view taken along line C-C' in the intermediate stage of an embodiment of the method.

[0020] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F Examples Figure 2A and Figure 2B Semiconductor devices according to Figure 1D A partial cross-sectional view taken along line C-C' in the intermediate stage of an embodiment of the method.

[0021] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F Examples Figure 2A and Figure 2B Semiconductor devices according to Figure 1E A partial sectional view taken along line C-C' in the intermediate stage of an embodiment of the method.

[0022] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F semiconductor device of Figure 2A and Figure 2B is illustrated in a partial cross-sectional view taken along line C-C' at an intermediate stage of an embodiment of the method according to the present disclosure. Figure 1F

[0023] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F semiconductor device of Figure 2A and Figure 2B is illustrated in a partial cross-sectional view taken along line C-C' at an intermediate stage of an embodiment of the method according to the present disclosure. Figure 1G

[0024] wherein the reference signs are explained as follows:

[0025] 100: method

[0026] 102: operation

[0027] 104: step

[0028] 106: step

[0029] 108: operation

[0030] 109: operation

[0031] 110: operation

[0032] 112: operation

[0033] 114: operation

[0034] 116: operation

[0035] 118: operation

[0036] 120: operation

[0037] 122: operation

[0038] 124: operation

[0039] 126: operation

[0040] 128: operation

[0041] 130: operation

[0042] 132: operation

[0043] 136: operation

[0044] 138: operation ​​

[0045] 140: operation

[0046] 142: operation

[0047] 144: operation

[0048] 146: operation

[0049] 148: operation

[0050] 150: operation

[0051] 152: operation

[0052] 154: operation

[0053] 156: operation

[0054] 160: dipole treatment process

[0055] 162: block

[0056] 164: block

[0057] 166: block

[0058] 168: block

[0059] 200: semiconductor device

[0060] 202: substrate

[0061] 204: active region

[0062] 204A: first semiconductor material / first semiconductor material layer

[0063] 204B: second semiconductor material / second semiconductor material layer

[0064] 206: isolation structure

[0065] 206A: fill dielectric material

[0066] 206B: oxide liner

[0067] 208: dummy gate stack

[0068] 210: gate spacer

[0069] 212: dummy gate electrode

[0070] 214: dielectric layer

[0071] 216: hardmask layer

[0072] 218: hardmask layer

[0073] 220: first spacer layer

[0074] 222: second spacer layer

[0075] 228: source / drain trench (S / D recess)

[0076] 230: gap

[0077] 232: dielectric material

[0078] 234: inner spacer

[0079] 236: source / drain component

[0080] 236A: first semiconductor layer

[0081] 236B: second semiconductor layer

[0082] 238: interlevel dielectric (ILD) layer

[0083] 240: bottom contact etch stop layer

[0084] 242: gap

[0085] 244: via

[0086] 244A: circular shape

[0087] 244B: elliptical (or olivary) shape

[0088] 250: metal gate structure

[0089] 251: gate dielectric layer

[0090] 252: interfacial (IF) layer

[0091] 254: high-K dielectric material layer

[0092] 254-1: first high-K dielectric material layer

[0093] 254-2: second high-K dielectric material layer

[0094] 254-3: third high-K dielectric material layer

[0095] 256: gate electrode

[0096] 256-1: P-type metal layer

[0097] 256-2: bulk metal layer

[0098] 256B: bulk metal layer

[0099] 258: portion

[0100] 260: self-aligned gate cap (SAGC)

[0101] 262: source / drain (S / D) contact

[0102] 354: high-k dielectric layer

[0103] D: channel dimension

[0104] Hf: fin height

[0105] A-A': cross-sectional line

[0106] B-B': cross-sectional line

[0107] C-C': cross-sectional line

[0108] D-D': cross-sectional line

[0109] X: X direction

[0110] Y: Y direction

[0111] Z: Z direction DETAILED DESCRIPTION

[0112] The following disclosure provides numerous embodiments or examples for different components of the disclosure. Specific examples of elements and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, if a first element is described as being formed over a second element, this can include embodiments where the first and second elements are in direct contact, and can also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, the present embodiments can repeatedly refer to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent a relationship between the different embodiments and / or configurations being discussed.

[0113] Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily imply a common, shared, or related function between ilustrations that refer to a repeated reference numeral(s) and / or letter(s). Also, in the following description, it will be understood that, when a element is referred to as being formed "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it will be understood that when a element is referred to as being "connected" to or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can also be present. Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "top", "bottom", "side", "horizontal", "vertical", "up", "down", "front", "rear", and the like, can be used herein for ease of description to describe one element's or portion's relation to another element(s) or portion(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device described is turned over, elements described as "below" or "beneath" other elements or portions would then be oriented "above" the other elements or portions. Likewise, if devices are turned over, elements described as "above" other elements or portions would then be oriented "below" the other elements or portions. Therefore, the term "above" can encompass both an orientation of above and below. The device can be oriented in the other way, and the aforementioned orientation terms are used herein for the purpose of illustration and description only and is not a limitation on the scope of use. Also, descriptions of a device or portion thereof as "horizontal", "vertical", "up", "down", "top", "bottom", "front", "rear", etc., are used for convenience to describe the relative position of such element(s) or portion(s) as illustrated in the figures with regard to other element(s) or portion(s). The spatially relative terms are used herein for purposes of illustration and description only and can not necessarily be intended to further limit the scope of use.

[0114] The present disclosure relates generally to semiconductor devices and fabrication thereof, and more particularly to methods of fabricating field-effect transistors (FETs), such as fin-like FETs (FinFETs), gate-all-around FETs (GAAFETs), and / or other FETs. In the disclosed embodiments, dummy spacers are employed to reduce various defects in forming gate-all-around FETs (GAA FETs), and to perform dipole treatment on the gate structures, and to properly integrate with the process of the dummy spacers, to achieve enhanced performance of the corresponding FETs.

[0115] In the disclosed semiconductor fabrication, a wrap-around gate field effect transistor device with multiple channels stacked one by one is formed, first and second semiconductor layers are alternately deposited to form a semiconductor stack; the semiconductor stack is patterned to form active regions (e.g., fin active regions) surrounded by and separated from each other by isolation structures, such as shallow trench isolation (STI) structures; dummy gate structures are formed over the active regions, the dummy gate structures including dummy gate stacks and gate spacers; the semiconductor stack in source / drain (S / D) regions is recessed; the first semiconductor layer is removed via source / drain trenches, forming vertically stacked and spaced apart channels; dummy interposers, such as dummy oxide interposers (DOIs); are formed in the gaps; the dummy interposers are laterally recessed and form inner spacers in lateral recesses; source / drain components are formed in the source / drain trenches by epitaxial growth; the dummy gate stacks are removed; the dummy interposers are further removed to release the vertically stacked and spaced apart channels; high-K metal gate stacks are formed to surround the channels. In particular, the field effect transistors to be formed include n-type FETs (nFETs) in an nFET region and p-type FETs (pFETs) in a pFET region, and the high-K metal gate stacks include n-type gate stacks for the nFET region and p-type gate stacks for the pFET region, with different compositions designed and fabricated to optimize the nFETs and the pFETs, lower threshold voltage, and enhance performance.

[0116] A high-k dielectric metal gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a high-k dielectric material layer and may also include an interface (IF) layer located below the high-k dielectric material layer. The gate electrode includes a work function metal and a fill metal located above the work function metal. During the formation of the high-k dielectric metal gate stack, a dipole treatment is applied to the work function metal within one of the n-type and p-type field-effect transistor regions to adjust the work function, respectively. In the disclosed method, only one type of work function metal (e.g., p-type work function metal, simply referred to as P-type metal or p-metal) is deposited in the n-type and p-type field-effect transistor regions, and a dipole treatment is applied to the work function metal within one of the n-type and p-type field-effect transistor regions (e.g., the n-type field-effect transistor region) to adjust the work function in the n-type field-effect transistor region. Therefore, this method eliminates the need to deposit p-type and n-type work function metals (abbreviated as n-metal or N-type metal); and to etch one or both of the N-type and p-type metals. This avoids the loss of high-k dielectric material caused by work function metal etching; and significantly improves process efficiency and overall device performance.

[0117] Figure 1A A flowchart illustrating a method 100 for forming a semiconductor device 200 (hereinafter referred to as "device 200") according to some embodiments of the present disclosure is provided. Method 100 is merely illustrative and is not intended to limit the scope of the present disclosure beyond what is expressly stated in the claims. Additional operations may be performed before, during, and after method 100, and some described operations may be replaced, deleted, or moved for additional embodiments of this method. Method 100 is described below in conjunction with other figures illustrating various three-dimensional cross-sectional views of the semiconductor structure 200 during intermediate steps of method 100. Specifically, Figure 2A A three-dimensional view of device 200 is shown; Figure 2B A plan view of device 200 is shown; Figure 3A The device 200 is illustrated. Figure 2A and Figure 2B The cross-sectional view taken by line A-A' shown; Figure 3B The device 200 is illustrated. Figure 2A and Figure 2B The cross-sectional view taken by line B-B' shown; Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Showing Figure 2A and Figure 2B A cross-sectional view of the semiconductor device taken along line B-B'; Figure 4F and Figure 4G a cross-sectional view of the semiconductor device of Figure 2A and Figure 2B taken along line C-C’; Figure 5A and Figure 5B a partial cross-sectional view of the semiconductor device of Figure 2A and Figure 2B taken along line C-C’; Figure 6A a cross-sectional view of the semiconductor device of Figure 2A and Figure 2B taken along line A-A’; Figure 6B a cross-sectional view of the semiconductor device of Figure 2A and Figure 2B taken along line D-D’.

[0118] The device 200 can be an intermediate device fabricated during the fabrication of an integrated circuit (IC) or a portion thereof, which can include logic circuits, memory circuits such as static random-access memory (SRAM), and / or other suitable circuits having active elements (e.g., transistors, diodes, and image sensors) and passive elements (e.g., resistors, capacitors, and inductors). In various examples, the active elements include wrap-around gate field effect transistors, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), fin field effect transistors (FinFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other storage cells. The present disclosure is not limited to any particular number of devices or device regions, or any particular device configuration. For example, while the illustrated device 200 is a wrap-around gate field effect transistor structure, the present disclosure can also provide embodiments for fabricating other three-dimensional field effect transistor devices.

[0119] Referring to Figure 1A and Figure 2A-2BAt operation 102, the method 100 provides a device 200 including one or more active regions 204 protruding from a substrate 202 and separated by an isolation structure 206 and a dummy gate stack 208 disposed above the substrate 202. Operation 102 includes a step 104 of forming the semiconductor fins 204; and a step 106 of forming the isolation structure 206 around the active regions 204. In the disclosed embodiments, the active regions 204 protrude above the isolation structure 206 and are also referred to as semiconductor fins 204. The device 200 can include other elements, such as the dummy gate stack 208, gate spacers 210 disposed on sidewalls of the dummy gate stack 208, various hard mask layers disposed above the dummy gate stack 208, barrier layers, other suitable layers, or combinations thereof, which will be discussed in detail below.

[0120] The substrate 202 can include elemental (single element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 202 can be a single layer of material having a uniform composition. Alternatively, the substrate 202 can include multiple layers of material having similar or different compositions suitable for IC device fabrication. In one example, the substrate 202 can be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, the substrate 202 can include conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof.

[0121] In some embodiments, the substrate 202 includes various doped regions disposed in or on the substrate 202, such as doped wells and source / drain regions. The doped regions can be doped with p-type dopants, such as phosphorus or arsenic, and / or n-type dopants, such as boron or BF2, depending on design requirements. The doped regions can be formed directly on the substrate 202 (e.g., p-well structures, n-well structures, or dual-well structures) or using raised structures (e.g., epitaxial source / drain components). The doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, diffusion, and / or other suitable techniques.

[0122] Each semiconductor fin 204 can be adapted to provide an n-type field effect transistor or a p-type field effect transistor. In some embodiments, the semiconductor fins 204 as shown herein can be adapted to provide fins of the same type (i.e., both n-type or both p-type). Alternatively, they can be adapted to provide fins of opposite types (i.e., n-type and p-type). This configuration is for illustrative purposes only and is not intended to be limiting. The semiconductor fins 204 can be fabricated using suitable processes including photolithography and etching processes. The photolithography process can include forming a photoresist layer (or resist) overlying the substrate 202, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a mask element (not shown) including the resist. The mask element is then used to etch recesses in the substrate 202, leaving the semiconductor fins 204 on the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0123] Many other embodiments of methods for forming the semiconductor fins 204 can be suitable. For example, double-patterning or multi-patterning processes can be used to pattern the semiconductor fins 204. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller pitches than are obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0124] In the depicted embodiment, for example, with reference to Figure 3BThe semiconductor fin 204 may include alternating layers of semiconductor materials, such as a first semiconductor material 204A and a second semiconductor material 204B with a composition different from that of the first semiconductor material 204A. In the following description, the first semiconductor material layer 204A and the second semiconductor material layer 204B are also referred to as the first semiconductor material layer (or simply the first semiconductor layer) 204A and the second semiconductor material layer (or simply the second semiconductor layer) 204B. In some exemplary embodiments, the semiconductor fin 204 may include a total of three to ten alternating layers of semiconductor materials; however, this disclosure is not limited to this configuration. In this disclosure, the first semiconductor material 204A comprises silicon (Si), while the second semiconductor material 204B comprises silicon germanium (SiGe). Either (or both) of the semiconductor materials 204A and 204B may be doped with a suitable dopant, such as a p-type dopant or an n-type dopant, to form a desired field-effect transistor. Semiconductor materials 204A and 204B can both be formed by epitaxial processes, such as molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and / or other suitable epitaxial growth processes.

[0125] In many embodiments, alternating layers of semiconductor materials 204A and 204B are configured to provide nanowire or nanosheet devices such as fully wound gate field-effect transistors (GAA FETs), the formation of which is detailed below. The purpose of introducing fully wound gate field-effect transistors (GAA FETs) is to improve gate control, reduce off-state current, and reduce short-channel effects by increasing gate channel coupling. Multi-gate devices such as GAA FETs typically include a gate structure extending around their channel region (horizontally or vertically), providing access to all sides of the channel region. Fully wound gate field-effect transistors (GAA FETs) are generally compatible with complementary metal-oxide-semiconductor (CMOS) processes, thus allowing for significant size reduction while maintaining gate control and mitigating short-channel effects. Of course, this disclosure is not limited to forming only fully wound gate field-effect transistors (GAA FETs), but may also provide other three-dimensional field-effect transistors, such as fin-like FETs (FinFETs).

[0126] Isolation structures 206 surround and separate the active regions 204 from one another. The isolation structures 206 can include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. The isolation structures 206 can include shallow trench isolation (STI) features. In one embodiment, the isolation structures 206 are formed by etching trenches in the substrate 202 during formation of the semiconductor fins 204. The trenches can then be filled with one or more of the dielectric materials described above by a deposition process, followed by a chemical mechanical planarization (CMP) process. The isolation structures 206 can then be recessed, e.g., selectively etched, so that the top surface of the isolation structures 206 is lower than the top surface of the semiconductor fins 204, defining a fin height H of the semiconductor fins 204 f to optimize the coupling between the gate electrode and the channel. In some embodiments, the fin height of the semiconductor fins 204 is in a range between 40 nm and 80 nm.

[0127] Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the isolation structures 206. Alternatively, the isolation structures 206 can include a multi-layer structure, e.g., with one or more thermal oxide liners. The isolation structures 206 can be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), spin-on-glass (SOG), high density plasma chemical vapor deposition (HDPCVD), high aspect ratio process (HARP), other suitable methods, or combinations thereof.

[0128] Reference is made to Figure 1A and Figures 3A-3B, the method 100 proceeds to operation 108 to form one or more dummy gate stacks 208. In some embodiments, each dummy gate stack 208 serves as a placeholder for a subsequently formed high-k metal gate structure (HKMG; where "high-k" refers to a dielectric material having a dielectric constant greater than that of thermal silicon dioxide, which is approximately 3.9). The dummy gate stacks 208 can include a dummy gate electrode 212 and various other material layers, such as a dielectric layer below the dummy gate electrode 212. In some embodiments, the dummy gate electrode 212 includes polysilicon. In the depicted embodiment, the dummy gate electrode 212 is formed by a deposition and patterning process. The patterning process also includes a photolithography process and an etching process. In the depicted embodiment, a hard mask is also used in the patterning process to form the dummy gate stacks 208. In the depicted example, the hard mask includes a first hard mask layer 216 disposed above the dummy gate electrode 212 and a second hard mask layer 218 disposed above the first hard mask layer 216. As will be discussed in detail below, after other elements of the device 200 are fabricated (e.g., source / drain components 236), portions of the dummy gate stacks 208 are replaced with HKMG during a gate replacement process. The first and second hard mask layers 216, 218 can each include any suitable dielectric material, such as a semiconductor oxide and / or a semiconductor nitride. In one example, the first hard mask layer 216 includes silicon carbonitride and the second hard mask layer 218 includes silicon oxide. The various material layers of the dummy gate stacks 208 can be formed by any suitable process, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. In some embodiments, the dummy gate stacks 208 are formed by a suitable process, such as a process that includes deposition of various gate materials including the hard mask; and patterning of the gate materials by photolithography and etching. Figure 3B , the device 200 can include a dielectric layer 214 disposed between the semiconductor fin 204 and the dummy gate electrode 212 as an interface layer for the dummy gate stacks 208. In some embodiments, the dummy gate stacks 208 are formed by a deposition and patterning process. The patterning process also includes a photolithography process and an etching process. In the depicted embodiment, a hard mask is also used in the patterning process to form the dummy gate stacks 208. In the depicted example, the hard mask includes a first hard mask layer 216 disposed above the dummy gate electrode 212 and a second hard mask layer 218 disposed above the first hard mask layer 216. As will be discussed in detail below, after other elements of the device 200 are fabricated (e.g., source / drain components 236), portions of the dummy gate stacks 208 are replaced with HKMG during a gate replacement process. The first and second hard mask layers 216, 218 can each include any suitable dielectric material, such as a semiconductor oxide and / or a semiconductor nitride. In one example, the first hard mask layer 216 includes silicon carbonitride and the second hard mask layer 218 includes silicon oxide. The various material layers of the dummy gate stacks 208 can be formed by any suitable process, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. In some embodiments, the dummy gate stacks 208 are formed by a suitable process, such as a process that includes deposition of various gate materials including the hard mask; and patterning of the gate materials by photolithography and etching.

[0129] Still referring to Figure 1A and Figures 3A-3BThe method 100 proceeds to operation 109, where a gate spacer layer (or simply one or more spacer layers) 210 is formed on the sidewalls of the dummy gate stack 208. The spacer layer 210 is formed by deposition and anisotropic etching. The spacer layer 210 can include multiple films of different compositions. In some embodiments, the spacer layer 210 includes a first spacer layer 220 and a second spacer layer 222 disposed on the first spacer layer 220.

[0130] The first spacer layer 220 is deposited over the device 200. In some embodiments, the first spacer layer 220 is formed conformally over the device 200, including over the semiconductor fin 204 and the dummy gate stack 208. The first spacer layer 220 can include any suitable dielectric material, such as a nitrogen-containing dielectric material, and can be formed by any suitable method, such as ALD, CVD, PVD, other suitable methods, or combinations thereof. In the depicted embodiment, the first spacer layer 220 is formed by an ALD process. In some examples, the first spacer layer 220 can include silicon nitride, silicon carbonitride, silicon oxycarbonitride, other suitable dielectric materials, or combinations thereof. The second spacer layer 222 is formed on the first spacer layer 220. The second spacer layer 222 can be formed by deposition. Similar to the first spacer layer 220, the second spacer layer 222 can be formed conformally over the dummy gate stack 208 and the semiconductor fin 204. In some examples, the second spacer layer 222 includes a low-k dielectric material, silicon oxide, silicon oxycarbide, other suitable dielectric materials, or combinations thereof. The second spacer layer 222 can be formed by any suitable method, such as ALD, CVD, PVD, other suitable methods, or combinations thereof. In an example, each of the layers 220 and 222 is formed to have a thickness of less than about 10 nm. In the present embodiment, the first spacer layer 220 includes silicon nitride and the second spacer layer 222 includes silicon oxide. The second spacer layer 222 can be disposable. Operation 109 can also include anisotropic etching, such as plasma etching, to remove portions thereof disposed on top surfaces of the semiconductor fin 204 and the dummy gate stack 208.

[0131] Reference is now made to FIGS. 1 and Figure 4A-4G subsequent operations of the method 100 according to some embodiments. For brevity, some components are not illustrated in Figure 4A-4G FIGS. 1-108. For example, Figures 4A-4E the substrate 202 is not illustrated in Figure 4A-4G the hard masks 216 and 218 are not illustrated in

[0132] Referring to Figure 1A and Figure 4A At operation 110, the method 100 removes a portion of the semiconductor fin 204 within the source / drain (S / D) region to form a source / drain trench (or S / D recess) 228 therein. In some embodiments, the method 100 forms the source / drain trench 228 by a suitable etching process, such as a dry etching process, a wet etching process, a RIE process, or a combination thereof. In some embodiments, the method 100 selectively removes the semiconductor fin 204 without etching or substantially etching the portions of the spacer layers 220 and 222 formed on the sidewalls of the dummy gate stack 208. In some embodiments, the upper portions of the hard masks 216 and 218 above the dummy gate stack 208 can be removed during the etching process to form the source / drain trench 228. The etching process in operation 110 can use a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or a combination thereof. The extent of removal of the semiconductor fin 204 can be controlled by adjusting the duration of the etching process.

[0133] Referring to Figure 1A and Figure 4B At operation 112, the method 100 proceeds to completely remove the second semiconductor material layer 204B through the source / drain trench 228 by an etching process to form a gap 230 between the first semiconductor material layers 204A. As described above, the first semiconductor material 204A includes Si and the second semiconductor material 204B includes SiGe. During operation 110, the etching process substantially etches both the semiconductor materials 204A and 204B, while the etching process of operation 112 in the present embodiment selectively etches the second semiconductor layer 204B or SiGe. In the present embodiment, the etching process at operation 112 selectively etches the second semiconductor layer 204B or SiGe. In an example embodiment, the etching process at operation 112 includes a wet etching process using a hydrofluoride (HF) solution and / or an ammonium hydroxide (NH4OH) solution as an etchant, which selectively removes SiGe.

[0134] Referring to Figure 1A and Figure 4CAt operation 114, the method 100 forms a dielectric material 232 to completely fill the gaps 230. Thus, the dielectric material 232 replaces the second semiconductor layer 204B and functions as a dielectric interlayer (also denoted by the numeral 232) between the first semiconductor layers 204A. The dielectric interlayer 232 includes one or more suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric interlayer 232 is formed by suitable techniques, such as chemical vapor deposition (CVD), other suitable deposition methods, or combinations thereof. In some embodiments, the dielectric interlayer 232 includes silicon oxide deposited by low temperature techniques, such as flowable chemical vapor deposition (FCVD), other low temperature deposition methods, or combinations thereof. In some embodiments, the operation 114 can additionally include an anisotropic etch, such as a plasma etch, to remove excess portions of the dielectric interlayer 232.

[0135] Referring to Figure 1A and Figure 4D At operation 116, the method 100 forms inner spacers 234 under the gate spacers 210 on the sidewalls of the dummy gate stacks 208. The inner spacers 234 are formed vertically between adjacent first semiconductor layers 204A. The operation 116 can include a lateral etch; a deposition; and an anisotropic etch.

[0136] The lateral etch process selectively etches the dielectric interlayer 232 such that the dielectric interlayer 232 is laterally recessed to form undercuts under the gate spacers 210 on the sidewalls of the dummy gate stacks 208. For example, the lateral etch process can include a wet etch process with an etchant to selectively etch the dielectric interlayer 232. In some embodiments, the dielectric interlayer 232 includes silicon oxide and the etchant includes an HF solution to selectively etch the dielectric interlayer 232 of silicon oxide.

[0137] The deposition process of the operation 116 includes depositing one or more dielectric materials to fill the undercuts to form the inner spacers 234. The dielectric material of the inner spacers 234 includes one or more dielectric materials that are different from the dielectric material of the dielectric interlayer 232 in order to achieve etch selectivity during a later stage described channel release process. In some embodiments, the dielectric interlayer 232 includes silicon oxide and the inner spacers 234 include silicon nitride. The deposition of the dielectric material in the operation 116 includes CVD, atomic layer deposition (ALD), other suitable deposition, or combinations thereof.

[0138] The non-isotropic etch process of operation 116 is applied to trim the inner spacers 234 such that portions of the inner spacers 234 deposited on the sidewalls of the first semiconductor layer 204A are removed so that source / drain components can be properly formed in the source / drain trenches 228. In some embodiments, the isotropic etch process includes a plasma etch process using an etchant including a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or NF3).

[0139] Referring to Figure 1A and Figure 4E The method 100 proceeds to operation 118 of epitaxially growing source / drain components 236 from the source / drain trenches 228. The source / drain components 236 can include multiple epitaxial semiconductor layers, such as a first semiconductor layer 236A and a second semiconductor layer 236B on the first semiconductor layer. In some embodiments, the amount of dopant included in the first and second semiconductor layers is different. In some examples, the amount of dopant included in the first semiconductor layer 236A is less than the amount of dopant included in the second semiconductor layer 236B to minimize potential leakage current and reduce contact resistance. Dopant is introduced in situ during the selective epitaxial growth of the source / drain components 236. In some embodiments, the first semiconductor layer 236A and the second semiconductor layer 236B differ in composition to provide other advantages, such as a strain effect that enhances carrier mobility and transistor speed. For example, depending on the type of transistor, the layers 236A and 236B include silicon and silicon germanium, respectively, or vice versa.

[0140] The source / drain features 236 (i.e., the layers 236A and 236B contained therein) can be formed by any suitable method, such as molecular beam epitaxy (MBE) process, metalorganic chemical vapor deposition (MOCVD), other suitable epitaxial growth process, or combinations thereof. The source / drain features 236 can be suitable for p-type FinFET devices (e.g., p-type epitaxial material) or n-type FinFET devices (e.g., n-type epitaxial material). The p-type epitaxial material can include one or more layers of epi SiGe epitaxial layers, where the epi SiGe is doped with p-type dopants, such as boron, germanium, indium, and / or other p-type dopants. The n-type epitaxial material can include one or more layers of epi Si or epi SiC epitaxial layers, where the epi Si or epi SiC is doped with n-type dopants, such as arsenic, phosphorus, and / or other n-type dopants. Silicides can be additionally formed on the source / drain features 236 to reduce contact resistance by suitable processes, such as metal deposition, annealing to react the metal with silicon to form silicides.

[0141] Still referring to FIG. 1, the substrate 202 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable substrate. The substrate 202 can include a substrate surface 204, which can be a top surface of the substrate 202. The substrate surface 204 can be a planar surface, or can include one or more recesses, such as a recess 206. The recess 206 can be formed by any suitable method, such as anisotropic etching, or other suitable method. The recess 206 can be a trench, a hole, or other suitable recess. The recess 206 can be formed in the substrate surface 204 prior to forming the gate structure 208, or can be formed after forming the gate structure 208. The recess 206 can be formed in the substrate surface 204 prior to forming the source / drain features 236, or can be formed after forming the source / drain features 236. Figure 1A and Figure 4EThe method 100 proceeds to operation 120 to form an interlevel dielectric (ILD) layer 238 on the device 200 to provide an isolation function between various conductive components. The interlevel dielectric layer 238 can be formed by deposition and CMP. The interlevel dielectric layer 238 includes one or more dielectric materials, such as silicon oxide, tetraethyl orthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric materials, or other suitable dielectric materials. In various embodiments, the interlevel dielectric layer 238 is deposited by CVD, high density plasma chemical vapor deposition (HDPCVD), Sub-Atmospheric Chemical Vapor Deposition (SACVD), High Aspect Ratio Process (HARP), flowable chemical vapor deposition (FCVD), and / or spin-on processes. In some embodiments, forming the interlevel dielectric layer 238 also includes performing a CMP process to planarize a top surface of the device 200 such that a top surface of the dummy gate stack 208 is exposed. In some embodiments, a bottom contact etch-stop layer (BCESL) 240 is deposited between the interlevel dielectric layer 238 and the substrate 202, which has a different composition than the interlevel dielectric layer 238, such as silicon nitride, to achieve etch selectivity. The bottom contact etch-stop layer 240 is conformally deposited on the semiconductor fins 204 and the source / drain components 236.

[0142] Referring to Figure 1A and Figure 4FThe method 100 includes operation 122 to remove the dummy gate stacks 208 by etching to form gate trenches in the interlayer dielectric layer 238. Operation 122 can additionally include patterning with an optical lithography process. For example, the dummy gate stacks 208 for n-type field effect transistors are removed by a hard mask etch process to cover the regions for p-type field effect transistors; and the dummy gate stacks 208 for p-type field effect transistors are removed by another hard mask etch process to cover the regions for n-type field effect transistors, so as to be separately filled with different materials (e.g., different metals having respective work functions) to lower the threshold voltage. Forming the gate trenches can include one or more etch processes selective to the materials included in the dummy gate stacks 208 (e.g., polysilicon included in the dummy gate electrodes 212). The etch processes can include dry etching, wet etching, RIE, or other suitable etching methods, or combinations thereof. The isolation structures 206 are exposed in the gate trenches. In some embodiments, the isolation structures 206 are shallow trench isolation (STI) structures that include a plurality of dielectric materials, such as one or more thermal oxide liners and a fill dielectric material (e.g., a low-k dielectric material, silicon oxide deposited via CVD, other suitable dielectric materials, or combinations thereof).

[0143] Still referring to Figure 1A and Figure 4F The method 100 also includes operation 124 to perform an etch process to selectively remove the dielectric spacers 232 disposed in the gaps between adjacent first semiconductor layers 204A in the gate trenches to form gaps 242 between the first semiconductor layers 204A, such that portions of the first semiconductor layers 204A are suspended in the gaps 242 as channels 244 for the corresponding wraparound gate devices. This operation is also referred to as a channel release process.

[0144] As mentioned above, the first semiconductor material layers 204A include Si, and the dielectric spacers 232 include a dielectric material, such as silicon oxide. Thus, the etch process at operation 124 selectively removes the dielectric spacers 232 without removing or substantially removing the Si. In some embodiments, the etch process is an isotropic etch process (e.g., a dry etch process or a wet etch process), and the dielectric spacers 232, particularly portions of the dielectric spacers 232 in the corner regions adjacent to the inner spacers 234, can be completely removed without residue. In an example embodiment, the method 100 of selectively removing the dielectric spacers 232 by a wet etch process utilizes a hydrofluoric acid solution (HF) as the etchant.

[0145] By implementing the dielectric spacer 232 as a sacrificial part, various advantages can be realized. The channel 244 can be completely released without residue or with less residue. Even if there is any residue, it is a dielectric part without changing the profile of the channel 244 in the corner region. Overall, the wrap-around gate device formed therein is improved with enhanced performance.

[0146] In some embodiments, the method 100 can include an operation of converting the channel 244 to a different semiconductor material, such as for strain effect. In some examples, the first semiconductor material 204A is converted from silicon to silicon germanium. This can be realized by a suitable method, such as ion implantation to introduce germanium into the channel 24. In some examples, after the dielectric spacer 232 is removed by the operation 124, germanium is then grown on the channel 24. An anneal process is then applied to drive the germanium into the channel 244.

[0147] In some embodiments, the channel 244 can have different shapes in the cross-sectional view, such as a round shape 244A for a wrap-around gate field effect transistor (GAA FET) with a nanosheet structure, or an elliptical (or olive) shape 244B for a wrap-around gate field effect transistor (GAA FET) with a nanowire structure, as shown in Figure 5A In some examples, the channel 244 has a dimension D in the range of 4 nm to 8 nm, which is optimized with other dimensions to obtain better gate-channel coupling and enhanced device performance. The shape of the channel 244 can include a rectangle (e.g., as shown in Figure 4F ), an olive, or a round (e.g., as shown in Figure 5A ), or other suitable shapes, depending on the initial dimensions of the replacement semiconductor material and the etching characteristics (e.g., isotropic etching and anisotropic etching) of the etching process to selectively remove the second semiconductor material 204B in the operation 112 and the etching process to selectively remove the dielectric spacer 232 in the operation 124.

[0148] Reference is made to Figure 1A and Figure 4GAt operation 126, the method 100 proceeds to form a metal gate structure 250 in the gate trench. The metal gate structure 250 wraps around each of the vertically stacked plurality of channels 244. The metal gate structure 250 includes a gate dielectric layer 251 disposed on the channels 244 and a gate electrode 256 disposed on the gate dielectric layer 251. In some embodiments, the metal gate structure 250 is a high-K metal gate structure and includes a metal and a gate dielectric layer having a dielectric constant greater than silicon dioxide (about 3.9). The metal gate structure 250 is also referred to as a high-K dielectric and metal gate (HKMG) structure 250. The formation steps of the metal gate structure 250 include deposition of various gate materials (including gate dielectric materials and gate electrode materials), dipole treatment, and CMP.

[0149] During operation 126, various material layers of the metal gate structure 250 are deposited in the gap 242 formed between the channels 244 (first semiconductor material 204A). The metal gate structure 250 includes a gate dielectric layer 251 including a high-K dielectric material layer 254 and a gate electrode 256. The gate dielectric layer 251 can also include an interfacial (IF) layer 252 (e.g., silicon oxide) below the high-K dielectric material layer 254, as shown in FIG. 2B. Figure 5A and Figure 5BThe metal electrode can include multiple metal or metal alloy layers, such as a work function metal layer formed over a high-K dielectric material layer 254, a bulk conductive layer formed over the work function metal layer, a metal cap layer, other suitable layers, or combinations thereof, although not illustrated. The high-K dielectric material layer 254 can include one or more high-K dielectric materials (or one or more layers of high-K dielectric material), such as hafnium silicon oxide (HfSiO), hafnium oxide (Hf02), aluminum oxide (AI2O3), zirconium oxide (Zr02), lanthanum oxide (La203), titanium oxide (Ti02), yttrium oxide (Y203), strontium titanium oxide (SrTi03), or combinations thereof. The work function metal layer can include any suitable material, such as titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, the high-K dielectric material layer 254 includes multiple high-K dielectric films of different compositions; a first subset of the high-K dielectric films is dipole treated, and a second subset of the high-K dielectric films is not dipole treated.

[0150] The work function metal layer can include one or more material layers of the same or different types (i.e., both n-type work function metal or both p-type work function metal) in order to achieve a desired threshold voltage. The bulk conductive layer can include copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials, or combinations thereof. The metal gate structure 250 can include other material layers, such as a barrier layer, a glue layer, and / or a cap layer. The various layers of the metal gate structure 250 can be formed by any suitable method, such as CVD, ALD, PVD, plating, chemical oxidation, thermal oxidation, other suitable methods, or combinations thereof. Thereafter, the method 100 can perform one or more polishing processes (e.g., CMP) to remove any excess conductive material and planarize a top surface of the device 200.

[0151] However, the deposition and patterning of work function metals to form n-type and p-type work function layers (purely N-type and P-type metals) encounter various problems. For example, N-type metals containing Al suffer from Al scavenging, which attracts oxygen from high-k dielectric materials and causes HK dielectric reliability problems. In another example, the P-type metal patterning process including photolithography and etching before N-type metal deposition can cause damage to high-k dielectric layers in n-type field effect transistor regions, resulting in HK dielectric loss. In another example, N-type and P-type metals at the interface will inter-diffuse and change composition and increase threshold voltage Vt of both nFETs and pFETs. This effect is called MBE metal boundary effect.

[0152] In the disclosed embodiments, the formation of metal gate structures at operation 126 is designed to effectively eliminate the above problems and can enhance device performance without causing reliability problems and HK loss. The disclosed method of operation 126 includes depositing only one layer of work function metal layer (e.g., P-type metal) in both nFET and pFET regions (or simply N-type and P-type regions), and performing one or more dipole treatments to the gate dielectric layer 251 of only one of the N-type and P-type regions (e.g., the N-type region), thereby adjusting the work function of the gate dielectric layer 251 of that region (e.g., the N-type region). Overall, the threshold voltage of both nFETs and pFETs has been reduced and optimized.

[0153] Still referring to Figure 4G and Figure 5A , a gate material including an interface layer 252 and a high-k dielectric material layer 254 is deposited to wrap each channel 244. The gate dielectric layer 251 of the N-type region is subjected to one or more dipole treatments, while the gate dielectric layer 251 of the P-type region is covered and not treated. Thereafter, a gate electrode 256 including a P-type metal layer is deposited in both the N-type and P-type regions. A fill metal layer can also be deposited on the P-type metal layer, followed by a CMP process. In the disclosed embodiments, the P-type metal layer directly contacts the gate dielectric layer of both the N-type and P-type regions, and the fill metal layer directly contacts the P-type metal layer of both the N-type and P-type regions. In some embodiments, the gate electrode 256 also includes an adhesive layer interposed between the P-type metal layer and the fill metal layer. The adhesive layer is titanium nitride. At this point, the adhesive layer contacts the P-type metal layer of both the N-type and P-type regions. In some embodiments, the adhesive layer directly contacts the P-type metal layer in both the N-type and P-type regions.

[0154] In some embodiments, the glue layer is in the gate trench above the first channel and outside the space between the two first channels. In some embodiments, a portion of the P-type metal is between the high-k layer and the glue layer. In some embodiments, the fill metal is in the gate trench above the first channel and outside the space between the two first channels, where the fill metal includes tungsten.

[0155] The gate electrode 256 further extends vertically above the semiconductor fin 204. In some embodiments, a high-k dielectric material layer 254 is deposited on the interface layer 252, such that the high-k dielectric material layer 254 deposited on top of one channel 244 merges with the high-k dielectric material layer 254 deposited on the bottom of another channel 244, as shown. This merged structure can mitigate parasitic capacitance. Thus, the gate electrode 256 is eliminated from the region merged with the high-k dielectric material layer 254. The gate electrode 256 includes P-type metal, such as titanium nitride (TiN), on both the N-type region and the P-type region. In some embodiments, the gate electrode 256 also includes a bulk metal layer, such as the bulk metal described above. The work function can also be adjusted by different configurations of the various material layers of the gate dielectric layer 251. The formation of the metal gate structure 250, including deposition and dipole treatment, in operation 126 will be further described later with reference to Figure 5B Figures 1B to 1G and other figures.

[0156] Reference is made to Figure 1A and Figure 6A ​In some embodiments, the method 100 can include operation 128 to form a self-aligned gate cap (SAGC) 260 on top of the metal gate structure 250. The self-aligned gate cap 260 includes one or more dielectric materials that are different in composition from the ILD layer 238 to achieve etch selectivity. In some embodiments, the self-aligned gate cap 260 can be used to form a self-aligned via landing on the metal gate structure 250. The self-aligned gate cap 260 can be formed by a suitable process, such as one including a selective etch to recess the metal gate structure 250; and a selective deposition of a dielectric material to fill the recess. In some embodiments, the self-aligned gate cap 260 can be formed by a process including a selective etch to recess the metal gate structure 250; and a deposition of a dielectric material to fill the recess; and a CMP process to remove portions of the dielectric material above the ILD layer 238 and to planarize the self-aligned gate cap 260. Thus, when a via component is formed by etching and deposition on the gate electrode 256 to connect to the gate electrode 256, the etch process is designed to selectively etch the self-aligned gate cap 260, thus being confined to be self-aligned with the gate electrode 256. In some embodiments, a conductive cap 261 can be disposed on top of the metal gate structure 250. The conductive cap 261 can include a metal, a metal alloy, other conductive material, or a combination thereof. The conductive cap 261 is different in composition from the gate electrode 256 as an interface to prevent interdiffusion, to provide etch protection to the gate electrode 256, and to reduce contact resistance between the gate contact and the gate electrode 256. In some embodiments, the conductive cap 261 and the fill metal layer 256B include copper, tungsten, cobalt, other suitable metal, metal alloy, or a combination thereof. In some embodiments, the semiconductor device 200 can eliminate the self-aligned gate cap 260 such that the ILD layer 238 or other dielectric layer is disposed directly on the metal gate structure 250. In alternative embodiments, due to limited space (in X direction; if it is a short channel transistor), the glue layer is filled completely into the top gate (without metal fill). However, the glue layer amount in the top gate is greater than the glue layer amount between the two sheets. If it is a long channel, the fill metal can be filled into the top gate but not into the sheet-sheet region.

[0157] REFERENCE Figure 1A AND Figure 6BMethod 100 may include operation 130, in which source / drain (S / D) contacts 262 are deposited on source / drain components 236 to make electrical contact with the corresponding source / drain components 236. Each source / drain (S / D) contact 262 may include one or more conductive layers and may be formed by a process including patterning to form contact holes in an interlayer dielectric layer 238 and deposition to fill the contact holes with one or more conductive materials. Patterning processes include photolithography and etching processes. Deposition may be performed using any suitable method, such as ALD, CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, each source / drain (S / D) contact 262 includes a seed metal layer and a fill metal layer. In various embodiments, the seed metal layer includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or combinations thereof. The fill metal layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. Figure 6B As shown, the isolation structure 206 includes a variety of dielectric materials, such as a thermal oxide liner 206B and a filler dielectric material 206A (e.g., a low-k dielectric material, silicon oxide deposited by CVD, other suitable dielectric materials, or combinations thereof).

[0158] refer to Figure 1A Method 100 may perform additional processing steps at operation 132. For example, additional vertical interconnect components such as metal vias, horizontal interconnect components such as metal wires, and / or multilayer interconnect components such as metal layers and interlayer dielectrics may be formed above device 200. Various interconnect components can be implemented with various conductive materials, including copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), gold (Au), manganese (Mn), zirconium (Zr), ruthenium (Ru), their respective alloys, metal silicides, other suitable materials, or combinations thereof. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable metal silicides, or combinations thereof.

[0159] Return to reference Figure 1AThe operation 126 of forming the metal gate structure 250 in the method 100 of FIG. 1 includes depositing various gate materials and performing one or more dipole treatments on the gate dielectric layer 251, as described above. According to various embodiments, the operation 126 is described in further detail with reference to Figures 1B to 1G and other figures, such as Figures 7A to 7H . Figures 1B to 1G is a flowchart of the operation 126 according to various embodiments. Figures 7A to 7H are cross-sectional views of the semiconductor device 200 at various stages of fabrication according to some embodiments. Note that for brevity, only portions 258 of the semiconductor device 200 in Figures 7A to 7H are illustrated in Figure 4G .

[0160] With reference to Figure 1B and Figure 7A , the method 126 includes an operation 136 of forming an interface layer 252 on the channel 244 in both the N-type region (‘N’ in Figure 7A ) and the P-type region (‘P’ in Figure 7A ). In the disclosed embodiments, the interface layer 252 encircles each channel 244. The interface layer 252 can include silicon oxide, other suitable dielectric material, or a combination thereof. The interface layer 252 can be formed by applying a wet solution of a hydrochloric acid-hydrogen peroxide-water mixture to the channel 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or a combination thereof.

[0161] With reference to Figure 1B and Figure 7B , the method 126 includes an operation 138 of performing a dipole treatment on the interface layer 252 in the N-type region while not performing the treatment on the P-type region. The dipole treatment includes multiple steps, as illustrated by a dipole treatment process 160. Figure 1H The dipole treatment process 160 includes: at block 162, depositing a dipole material layer, such as lanthanum oxide (LaO or La2O3), by a suitable method, such as ALD; at block 164, patterning the dipole layer using optical lithography and etching to remove a portion of the dipole material layer such that the dipole material layer remains only in the N-type region; at block 166, performing a thermal anneal process such that the lanthanum diffuses to the interface layer 252 in the N-type region; and at block 168, performing an etch process to remove the dipole layer.

[0162] In some embodiments, the etching process at block 168 includes a wet etching process using an etchant to remove LaO. In disclosed examples, the etchant includes a hydrochloric acid peroxide mixture (HPM). In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C. The anneal duration is between 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes a plurality of steps: depositing a dipole material layer, such as LaO2, by a suitable method, such as ALD; forming a mask layer using a photolithography process and etching such that the dipole layer of the P-type region is covered while the dipole layer of the N-type region is exposed; performing a thermal anneal process to diffuse lanthanum to the interface layer 252 of the N-type region; removing the mask layer (e.g., when the patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by stripping or plasma ashing); and etching to remove the dipole layer. As a result, the interface layer 252 in the N-type region is treated and has a different composition than the interface layer 252 in the P-type region. Specifically, the interface layer 252 in the N-type region contains more lanthanum than the interface layer 252 in the P-type region. In some embodiments, the lanthanum concentration C n0 of the interface layer 252 in the N-type region is greater than the lanthanum concentration C p0 of the interface layer 252 in the P-type region. In some embodiments, the ratio C n0 / C p0 is defined as greater than 6. In some embodiments, the ratio C n1 / C p1 is between 6 to 16.

[0163] Referring to Figure 1B and Figure 7C , the method 126 proceeds to operation 140 to form a first high-k dielectric layer 254-1 over the interface layer 252 in the N-type region and the P-type region after the dipole treatment at operation 138. In some embodiments, the first high-k dielectric layer 254-1 includes hafnium oxide (HfO) or zirconium oxide (ZrO). The first high-k dielectric layer 254-1 is deposited by ALD, other suitable methods, or a combination thereof.

[0164] Referring to Figure 1B and Figure 7D, method 126 proceeds to operation 142 to perform dipole treatment on the first high-k dielectric layer 254-1 in the N-type region while not performing treatment on the P-type region. The dipole treatment in operation 142 is similar to the dipole treatment in operation 138. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as lanthanum oxide, by a suitable method, such as ALD; patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process such that lanthanum diffuses into the first high-k dielectric layer 254-1 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process includes a thermal anneal temperature in a range from 550 °C to 1050 °C; an anneal duration in a range from 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as LaO, by a suitable method, such as ALD; forming a mask layer using photolithography and etching such that the dipole layer in the P-type region is covered while the dipole layer in the N-type region is exposed; performing a thermal anneal process such that lanthanum diffuses into the first high-k dielectric layer 254-1 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by lift-off or plasma ashing); and etching to remove the dipole layer. As a result, the first high-k dielectric layer 254-1 in the N-type region is treated and its composition is different from the first high-k dielectric layer 254-1 in the P-type region. Specifically, the first high-k dielectric layer 254-1 in the N-type region contains more lanthanum than the first high-k dielectric layer 254-1 in the P-type region. The lanthanum concentration of the first high-k dielectric layer 254-1 in the N-type region is denoted as C n1 , and the lanthanum concentration of the first high-k dielectric layer 254-1 in the P-type region is denoted as C p1 . In some embodiments, the ratio C n1 / C p1 is greater than 6. In some embodiments, the ratio C n1 / C p1 is between 6 and 16.

[0165] In some embodiments, the dipole treatment at operation 142 can drive the dipole material (e.g., lanthanum) to diffuse into the interface between the interface layer 252 and the high-k dielectric layer 254 (e.g., the first high-k dielectric layer 254-1) to form an interface layer with a high-k dielectric material (e.g., hafnium oxide or zirconium oxide), lanthanum, and silicon oxide in its composition therebetween.

[0166] Referring to Figure 1B and Figure 7EMethod 126 proceeds to operation 144, where, following the dipole processing of operation 142, a second high-dielectric-constant (HK) dielectric layer 254-2 is formed over the first high-dielectric-constant (HK) dielectric layer 254-1 in the N-type and P-type regions. The second high-dielectric-constant (HK) dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In some embodiments, the second high-dielectric-constant dielectric layer 254-2 comprises a high-dielectric-constant (HK) dielectric material different from that of the first high-dielectric-constant dielectric layer 254-1. For example, the first high-dielectric-constant dielectric layer 254-1 comprises HfO and the second high-dielectric-constant dielectric layer 254-2 comprises ZrO. In another example, the first high-dielectric-constant dielectric layer 254-1 comprises ZrO and the second high-dielectric-constant dielectric layer 254-2 comprises HfO. In some alternative embodiments, the first high dielectric constant dielectric layer 254-1 and the second high dielectric constant dielectric layer 254-2 comprise the same composition, such as HfO (or ZrO).

[0167] refer to Figure 1B and Figure 7F Method 126 proceeds to operation 146, where a dipole treatment is performed on the second high-dielectric-constant (HK) dielectric layer 254-2 in the N-type region, while no treatment is performed on the P-type region. The dipole treatment in operation 146 is similar to the dipole treatment in operation 142. In some embodiments, the dipole treatment includes several steps: depositing a dipole material layer, such as lanthanum oxide, by a suitable method (e.g., ALD); patterning the dipole layer using optical lithography and etching such that the dipole layer remains only in the N-type region; performing a thermal annealing process to diffuse lanthanum into the second high-dielectric-constant (HK) dielectric layer 254-2 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal annealing process has a thermal annealing temperature ranging from 550°C to 1050°C; an annealing duration between 5 seconds and 5 minutes; and an annealing gas. The annealing gas may include an inert gas, such as argon, nitrogen, other inert gases, or combinations thereof. In some embodiments, the dipole treatment includes several steps: depositing a dipole material layer by a suitable method (e.g., ALD); forming a mask layer using optical lithography and etching, such that the dipole layer in the P-type region is covered while the dipole layer in the N-type region is exposed; performing a thermal annealing process to diffuse lanthanum into the second high-dielectric-constant dielectric layer 254-2 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by stripping or plasma ashing); and etching to remove the dipole layer. Therefore, the second high-dielectric-constant dielectric layer 254-2 in the N-type region is treated and includes lanthanum. The lanthanum concentration of the second high-dielectric-constant dielectric layer 254-2 in the N-type region is referred to as C. n2 Furthermore, the lanthanum concentration of the second highest dielectric constant dielectric layer 254-2 in the P-type region is called C. p2 In some embodiments, the ratio Cn2 / C p2 greater than 6. In some embodiments, the ratio C n2 / C p2 between 6 and 16.

[0168] Method 126 can include operation 148 to repeat operations 144 and 146 a plurality of times to form one or more additional high-k dielectric layers on which the dipole treatment is performed. For example, a third high-k dielectric layer 254-3 (not illustrated) is formed and dipole treatment is performed on the third high-k dielectric layer 254-3. The number of times operations 144 and 146 are repeated depends on the application so that the final structure is optimized.

[0169] Referring to Figure 1B and Figure 7G , method 126 proceeds to operation 150 to form a metal layer of P-type metal (or simply P-metal layer) 256-1 on the gate dielectric layer 251 (which includes the interface layer 252 and one or more layers of high-k dielectric material 254) in the P-type region and the N-type region. The P-type metal layer 256-1 includes an aluminum-free metal material. In some embodiments, the P-type metal layer 256-1 includes a metal, a metal compound having a work function equal to or greater than 4.7 eV. In the present embodiment, the P-type metal layer 256-1 is a layer of titanium nitride (TiN). In various embodiments, the P-type metal layer 256-1 includes titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The P-type metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or a combination thereof.

[0170] Referring to Figure 1B and Figure 7H , method 126 can include operation 152 to form a fill metal (or bulk metal) layer 256-2 on the P-type metal layer 256-1. In various embodiments, the fill metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or a combination thereof. The fill metal layer can include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or a combination thereof. The fill metal layer 256-2 can be formed by PVD, electroplating, ALD, other suitable methods, or a combination thereof. In some embodiments, the fill metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed on the seed layer by electroplating.

[0171] In some embodiments, the glue layer can be formed prior to forming the fill metal layer. In one embodiment, the glue layer is a titanium nitride (TiN) layer. In some embodiments, the glue layer completely fills the spaces between the trenches. In further embodiments, the fill metal layer 256-2 is only disposed in the gate trenches above the trenches 244, and the fill metal layer does not fill the spaces between the trenches. In this case, reference number 256-2 collectively refers to the glue layer and the fill metal layer disposed on the glue layer. In some embodiments, the glue layer completely fills the spaces between the trenches and the gate trenches, such that the fill metal layer is eliminated and replaced by the glue layer. In this case, the number 256-2 represents the glue layer. In various embodiments where the glue layer is present, the glue layer contacts the P-type metal layer 256-1 in the P-type region and the N-type region.

[0172] In some embodiments, the glue layer is in the gate trench above the first trench and outside the space between two first trenches. In some embodiments, a portion of the P-type metal is between the high-k layer and the glue layer. In some embodiments, the fill metal is in the gate trench above the first trench and outside the space between two first trenches, where the fill metal comprises tungsten.

[0173] Method 126 proceeds to operation 154, performing a chemical mechanical polishing (CMP) process to remove excess gate material and planarize the top surface, as shown in Figure 4G .

[0174] Figure 1C is a flowchart of method 126 constructed in accordance with some embodiments. Figures 8A to 8F is a cross-sectional view of semiconductor device 200 at various stages of fabrication in accordance with some embodiments. Note that for brevity, only portions 258 of semiconductor device 200 in Figures 8A to 8F are illustrated. Figure 4G

[0175] Referring to Figure 1C and Figure 8A , method 126 includes operation 136 of forming an interface layer 252 on the trenches 244 in both the N-type region and the P-type region. In the disclosed embodiments, the interface layer 252 surrounds each trench 244. The interface layer 252 can include silicon oxide, other suitable dielectric material, or a combination thereof. The interface layer 252 can be formed by applying a wet solution of a hydrochloric acid-hydrogen peroxide-water mixture (SC-2) to the trenches 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or a combination thereof.

[0176] Referring to Figure 1C and Figure 8B ​, method 126 includes operation 138, which performs dipole treatment on the interface layer 252 in the N-type region while not performing treatment on the P-type region. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as lanthanum oxide (LaO or La2O3), by a suitable method (e.g., ALD); patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process to diffuse lanthanum to the interface layer 252 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C; an anneal duration ranging from 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as LaO2, by a suitable method (e.g., ALD); forming a mask layer using photolithography and etching such that the dipole layer in the P-type region is covered while the dipole layer in the N-type region is exposed; performing a thermal anneal process to diffuse lanthanum to the interface layer 252 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by peeling or plasma ashing); and etching to remove the dipole layer. Thus, the interface layer 252 in the N-type region is treated and has a different composition than the interface layer 252 in the P-type region. Specifically, the interface layer 252 in the N-type region contains more lanthanum than the interface layer 252 in the P-type region. In some embodiments, the lanthanum concentration C n0 of the interface layer 252 in the N-type region is greater than the lanthanum concentration C p0 of the interface layer 252 in the P-type region. In some embodiments, the ratio C n0 / C p0 is defined as a value greater than 6. In some embodiments, the ratio C n0 / C p0 is between 6 and 16.

[0177] Referring to Figure 1C and 8C , method 126 proceeds to operation 140, which forms a first high-k dielectric layer 254-1 over the interface layer 252 in both the N-type region and the P-type region after the dipole treatment of operation 138. In some embodiments, the first high-k dielectric layer 254-1 includes hafnium oxide (HfO) or zirconium oxide (ZrO). The first high-k dielectric layer 254-1 is deposited by ALD, other suitable methods, or a combination thereof.

[0178] Referring to Figure 1C and Figure 8D, method 126 proceeds to operation 144 to form a second high-k dielectric layer 254-2 over the first high-k dielectric layer 254-1 in the N-type region and the P-type region after the dipole treatment. The second high-k dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In some embodiments, the second high-k dielectric layer 254-2 includes a high-k dielectric material that is different from the first high-k dielectric layer 254-1. For example, the first high-k dielectric layer 254-1 includes HfO and the second high-k dielectric layer 254-2 includes ZrO. In another example, the first high-k dielectric layer 254-1 includes ZrO and the second high-k dielectric layer 254-2 includes HfO. In some alternative embodiments, the first high-k dielectric layer 254-1 and the second high-k dielectric layer 254-2 include the same composition, e.g., HfO (or ZrO).

[0179] Referring to Figure 1C and Figure 8E , method 126 proceeds to operation 150 to form a P-metal metal layer (or simply P-metal layer) 256-1 on the gate dielectric layer 251 (which includes the interface layer 252 and one or more layers of high-k dielectric material layers 254) of the P-type region and the N-type region. The P-metal layer 256-1 includes an aluminum-free metal material. In some embodiments, the P-metal layer 256-1 includes a metal, a metal compound having a work function equal to or greater than 4.7 eV. In the present embodiment, the P-metal layer 256-1 is a titanium nitride (TiN) layer. In various embodiments, the P-metal layer 256-1 includes titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The P-metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or a combination thereof.

[0180] Referring to Figure 1C and Figure 8F , method 126 can include operation 152 to form a fill metal (or bulk metal) layer 256-2 on the P-metal layer 256-1. In various embodiments, the fill metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or a combination thereof. The fill metal layer can include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or a combination thereof. The fill metal layer 256-2 can be formed by PVD, electroplating, ALD, other suitable methods, or a combination thereof. In some embodiments, the fill metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed on the seed layer by electroplating.

[0181] In some embodiments, a glue layer can be formed prior to forming the fill layer. In one embodiment, the glue layer is a titanium nitride (TiN) layer. In some embodiments, the glue layer completely fills into the gap between the channels 244. In some embodiments, the glue layer does not fill into the space between the channels 244 and is located in a region outside the sheet- sheet space, nor does it fill into the gate trench above the channels 244. In some embodiments, the fill metal layer 256-2 is only disposed in the gate trench above the channels 244, and the fill metal layer does not have the space between the channels. In some embodiments, the reference numeral 256-2 collectively refers to the glue layer and the fill metal layer disposed on the glue layer. In some embodiments, the glue layer completely fills the space between the channels and the gate trench, such that the fill metal layer is eliminated and replaced by the glue layer. In this case, the numeral 256-2 represents the glue layer. In various embodiments where the glue layer is present, the glue layer contacts the P-type metal layer 256-1 in the P-type region and the N-type region.

[0182] In some embodiments, the glue layer is located in the gate trench above the first channel and outside the space between the two first channels. In some embodiments, a portion of the P-type metal is located between the high-k layer and the glue layer. In some embodiments, the fill metal is located in the gate trench above the first channel and outside the space between the two first channels, where the fill metal comprises tungsten.

[0183] The method 126 proceeds to operation 154, where excess gate material is removed and the top surface is planarized by performing a CMP process, as shown in Figure 4G .

[0184] Figure 1D is a flowchart of the method 126 according to various embodiments. Figures 9A to 9F are cross-sectional views of a semiconductor device 200 at various stages of fabrication according to some embodiments. Note that for simplicity, only a portion 258 of the semiconductor device 200 in Figures 9A to 9F is illustrated. Figure 4G

[0185] Referring to Figure 1D and Figure 9A , the method 126 includes an operation 136 of forming an interface layer 252 on the channels 244 in both the N-type region and the P-type region. In the disclosed embodiments, the interface layer 252 encircles each channel 244. The interface layer 252 can include silicon oxide, other suitable dielectric material, or a combination thereof. The interface layer 252 can be formed by applying a wet solution of a hydrochloric acid-hydrogen peroxide-water mixture (SC-2) to the channels 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or a combination thereof.​

[0186] Referring to Figure 1D and Figure 9B , the method 126 proceeds to operation 140 to form a first high-k dielectric layer 254-1 over the interface layer 252 in the N-type region and the P-type region. In some embodiments, the first high-k dielectric layer 254-1 includes hafnium oxide (HfO) or zirconium oxide (ZrO). The first high-k dielectric layer 254-1 is deposited by ALD, other suitable methods, or a combination thereof.

[0187] Referring to Figure 1D and Figure 9C , the method 126 proceeds to operation 142 to perform a dipole treatment on the first high-k dielectric layer 254-1 in the N-type region while not performing the treatment on the P-type region. The dipole treatment in operation 142 is similar to the dipole treatment in operation 138. In some embodiments, the dipole treatment includes a plurality of steps: depositing a dipole material layer, such as lanthanum oxide, by a suitable method, such as ALD; patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process such that lanthanum diffuses into the first high-k dielectric layer 254-1 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C; an anneal duration ranging from 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes a plurality of steps: depositing a dipole material layer, such as LaO, by a suitable method, such as ALD; and forming a mask layer using photolithography and etching such that the dipole layer in the P-type region is covered while the dipole layer in the N-type region is exposed; performing a thermal anneal process such that lanthanum diffuses into the first high-k dielectric layer 254-1 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by stripping or plasma ashing); and etching to remove the dipole layer. As a result, the first high-k dielectric layer 254-1 in the N-type region is treated and has a different composition than the first high-k dielectric layer 254-1 in the P-type region. Specifically, the first high-k dielectric layer 254-1 in the N-type region contains more lanthanum than the first high-k dielectric layer 254-1 in the P-type region. The lanthanum concentration of the first high-k dielectric layer 254-1 in the N-type region is denoted as C n1 , and the lanthanum concentration of the first high-k dielectric layer 254-1 in the P-type region is denoted as C p1 . In some embodiments, the ratio C n1 / C p1 is greater than 6. In some embodiments, the ratio C n1 / C p1between 6 and 16.

[0188] Referring to Figure 1D and Figure 9D After the dipole treatment of operation 142, the method 126 proceeds to operation 144, forming a second high-k dielectric layer 254-2 over the first high-k dielectric layer 254-1 in the N-type region and the P-type region. The second high-k dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In the disclosed embodiments, the first high-k dielectric layer 254-1 (before the dipole treatment at operation 142) and the second high-k dielectric layer 254-2 include the same composition, e.g., both include HfO (or ZrO). After the dipole treatment of operation 142, the first high-k dielectric layer 254-1 contains more lanthanum than the second high-k dielectric layer 254-2.

[0189] Referring to Figure 1D and Figure 9E The method 126 proceeds to operation 156, forming a third high-k dielectric layer 254-3 over the second high-k dielectric layer 254-2 in the N-type region and the P-type region. The third high-k dielectric layer 254-3 is deposited by ALD, other suitable methods, or a combination thereof. In the disclosed embodiments, the third high-k dielectric layer 254-3 includes a high-k dielectric material that is different from the second high-k dielectric layer 254-2. For example, the second high-k dielectric layer 254-2 includes HfO and the third high-k dielectric layer 254-3 includes ZrO. In another example, the second high-k dielectric layer 254-2 includes ZrO and the third high-k dielectric layer 254-3 includes HfO.

[0190] Referring to Figure 1D and Figure 9F The method 126 proceeds to operation 150, forming a P-metal metal layer (or simply P-metal layer) 256-1 over the gate dielectric layer 251 (which includes the interface layer 252 and the three high-k dielectric layers 254-1, 254-2, and 254-3) in the P-type region and the N-type region. The P-metal layer 256-1 includes an aluminum-free metal material. In the present embodiment, the P-metal layer 256-1 is a titanium nitride (TiN) layer. In various embodiments, the P-metal layer 256-1 includes titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The P-metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or a combination thereof.

[0191] Still referring to Figure 1D and Figure 9FIn some embodiments, method 126 includes operation 152 of forming a fill metal (or bulk metal) layer 256-2 over P-type metal layer 256-1. In various embodiments, fill metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or combinations thereof. Fill metal layer can include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. Fill metal layer 256-2 can be formed by PVD, electroplating, ALD, other suitable methods, or combinations thereof. In some embodiments, fill metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed over the seed layer via electroplating.

[0192] Method 126 proceeds to operation 154 of performing a chemical mechanical polishing (CMP) process to remove excess gate material and planarize the top surface, as shown in Figure 4G .

[0193] Figure 1E is a flowchart of method 126 constructed in accordance with some embodiments. Figures 10A to 10F is a cross-sectional view of semiconductor device 200 at various stages of fabrication in accordance with some embodiments. Note that for brevity, only portions 258 of semiconductor device 200 in Figures 10A to 10F are illustrated in Figure 4G . Reference is made to Figure 1E and Figures 10A to 10F for further details of method 126.

[0194] Reference is made to Figure 1E and Figure 10A , method 126 includes operation 136 of forming an interface layer 252 over channel 244 in both the N-type region and the P-type region. In disclosed embodiments, interface layer 252 encircles each channel 244. Interface layer 252 can include silicon oxide, other suitable dielectric materials, or combinations thereof. Interface layer 252 can be formed by applying a wet solution of a hydrochloric acid-hydrogen peroxide-water mixture to channel 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or combinations thereof.

[0195] Reference is made to Figure 1E and Figure 10B , method 126 proceeds to operation 140 of forming a first high-k dielectric layer 254-1 over interface layer 252 in both the N-type region and the P-type region. In some embodiments, first high-k dielectric layer 254-1 includes hafnium oxide (HfO) or zirconium oxide (ZrO). First high-k dielectric layer 254-1 is deposited by ALD, other suitable methods, or combinations thereof.

[0196] Reference is made to Figure 1E and Figure 10C At operation 142, the method 126 performs dipole treatment on the first high-k dielectric layer 254-1 in the N-type region while not performing treatment on the P-type region. The dipole treatment at operation 142 is similar to the dipole treatment at operation 138. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as lanthanum oxide, by a suitable method, such as ALD; patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process such that lanthanum diffuses into the first high-k dielectric layer 254-1 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C; an anneal duration between 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as LaO, by a suitable method, such as ALD; forming a mask layer using photolithography and etching such that the dipole layer of the P-type region is covered while the dipole layer of the N-type region is exposed; performing a thermal anneal process such that lanthanum diffuses into the first high-k (HK) dielectric layer 254-1 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by lift-off or plasma ashing); and etching to remove the dipole layer. As a result, the first high-k dielectric layer 254-1 in the N-type region is treated and has a different composition than the first high-k dielectric layer 254-1 in the P-type region. Specifically, the first high-k dielectric layer 254-1 in the N-type region contains more lanthanum than the first high-k dielectric layer 254-1 in the P-type region. In some embodiments, the lanthanum concentration C n0 and the lanthanum concentration C p0 of the interface layer 252 in the P-type region is defined as a ratio C n0 / C p0 greater than 6. In some embodiments, the ratio C n0 / C p0 is between 6 and 16.

[0197] Referring to Figure 1E and Figure 10D, method 126 proceeds to operation 144, after the dipole treatment, a second high-k dielectric layer 254-2 is formed over the first high-k dielectric layer 254-1 in the N-type region and the P-type region. The second high-k dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In disclosed embodiments, the second high-k dielectric layer 254-2 includes a high-k dielectric material that is different from the high-k dielectric material of the first high-k dielectric layer 254-1 at the time of deposition and prior to the dipole treatment in operation 142. For example, the first high-k dielectric layer 254-1 includes HfO and the second high-k dielectric layer 254-2 includes ZrO. In another example, the first high-k dielectric layer 254-1 includes ZrO and the second high-k dielectric layer 254-2 includes HfO.

[0198] Referring to Figure 1E and Figure 10E , method 126 proceeds to operation 150, a P-metal metal layer (or simply P-metal layer) 256-1 is formed on the gate dielectric layer 251 (which includes the interface layer 252 and the two high-k dielectric layers 254-1 and 254-2) in the P-type region and the N-type region. The P-metal layer 256-1 includes an aluminum-free metal material. In the present embodiment, the P-metal layer 256-1 is a titanium nitride (TiN) layer. In various embodiments, the P-metal layer 256-1 includes titanium nitride (TiN), titanium silicon nitride (TiSiN), molybdenum nitride (MoN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The P-metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or a combination thereof.

[0199] Referring to Figure 1E and Figure 10F , method 126 can include operation 152 of forming a fill metal (or bulk metal) layer 256-2 on the P-metal layer 256-1. In various embodiments, the fill metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or a combination thereof. The fill metal layer can include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or a combination thereof. The fill metal layer 256-2 can be formed by PVD, electroplating, ALD, other suitable methods, or a combination thereof. In some embodiments, the fill metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed on the seed layer by electroplating.

[0200] Method 126 proceeds to operation 154 to perform a chemical mechanical polishing (CMP) process to remove excess gate material and planarize the top surface, as shown in Figure 4G .

[0201] Figure 1F is a flowchart of method 126 constructed in accordance with some embodiments. Figures 11A to 11F are cross-sectional views of semiconductor device 200 at various stages of fabrication in accordance with some embodiments. Note that for simplicity, only portions 258 of semiconductor device 200 in Figures 11A to 11F are illustrated in Figure 4G . Reference is made to Figure 1F and Figures 11A to 11F for further details of method 126.

[0202] Reference is made to Figure 1F and Figure 11A , method 126 includes operation 136 to form an interface layer 252 over the channel 244 in both the N-type region and the P-type region. In disclosed embodiments, interface layer 252 surrounds each channel 244. Interface layer 252 can include silicon oxide, other suitable dielectric material, or combinations thereof. Interface layer 252 can be formed by applying a wet solution of hydrochloric acid-hydrogen peroxide-water mixture (SC-2) to the channel 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or combinations thereof.

[0203] Reference is made to Figure 1F and Figure 11B , method 126 proceeds to operation 140 to form a first high-k dielectric layer 254-1 over interface layer 252 in the N-type region and the P-type region. In some embodiments, first high-k dielectric layer 254-1 includes hafnium oxide (HfO) or zirconium oxide (ZrO). First high-k dielectric layer 254-1 is deposited by ALD, other suitable methods, or combinations thereof.

[0204] Reference is made to Figure 1F and Figure 11C, method 126 proceeds to operation 144, after the dipole treatment, a second high-k dielectric layer 254-2 is formed over the first high-k dielectric layer 254-1 in the N-type region and the P-type region. The second high-k dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In disclosed embodiments, the second high-k dielectric layer 254-2 includes a high-k dielectric material that is different from the high-k dielectric material of the first high-k dielectric layer 254-1 at the time of deposition and before the dipole treatment in operation 142. For example, the first high-k dielectric layer 254-1 includes HfO and the second high-k dielectric layer 254-2 includes ZrO. In another example, the first high-k dielectric layer 254-1 includes ZrO and the second high-k dielectric layer 254-2 includes HfO.

[0205] Reference is made to Figure 1F and Figure 11D , method 126 proceeds to operation 146, a dipole treatment is performed on the second high-k dielectric layer 254-2 in the N-type region while no treatment is performed on the P-type region. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, e.g., lanthanum oxide, by a suitable method, e.g., ALD; patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process such that lanthanum diffuses into the second high-k dielectric layer 254-2 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C; an anneal duration between 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, e.g., argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, e.g., LaO, by a suitable method, e.g., ALD; and forming a mask layer using photolithography and etching such that the dipole layer of the P-type region is covered while the dipole layer of the N-type region is exposed; performing a thermal anneal process such that lanthanum diffuses into the second high-k dielectric layer 254-2 in the N-type region; removing the mask layer, e.g., when a photoresist layer is patterned as the mask layer, the patterned photoresist layer can be removed by stripping or plasma ashing; and etching to remove the dipole layer. As a result, the first high-k dielectric layer 254-1 in the N-type region is treated and its composition is different from the second high-k dielectric layer 254-2 in the P-type region. Specifically, the second high-k dielectric layer 254-2 in the N-type region contains more lanthanum than the second high-k dielectric layer 254-2 in the P-type region. The lanthanum concentration of the second high-k dielectric layer 254-2 in the N-type region is denoted as C n2Furthermore, the lanthanum concentration of the second highest dielectric constant dielectric layer 254-2 in the P-type region is called C. p2 In some embodiments, the ratio C n2 / C p2 Greater than 6. In some embodiments, the ratio C n2 / C p2 Between 6 and 16.

[0206] refer to Figure 1F and Figure 11E Method 126 proceeds to operation 150, where a P-metal layer (or simply P-metal layer) 256-1 is formed on the gate dielectric layer 251 (which includes an interface layer 252 and two high dielectric constant (HK) dielectric layers 254-1 and 254-2) in the P-type and N-type regions. The P-type metal layer 256-1 comprises an aluminum-free metallic material. In this embodiment, the P-type metal layer 256-1 is a titanium nitride (TiN) layer. In various embodiments, the P-type metal layer 256-1 comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), molybdenum nitride (MoN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof. The P-type metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or combinations thereof.

[0207] refer to Figure 1F and Figure 11F Method 126 may include operation 152 of forming a filler metal (or bulk metal) layer 256-2 on the P-type metal layer 256-1. In various embodiments, the filler metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or combinations thereof. The filler metal layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. The filler metal layer 256-2 may be formed by PVD, electroplating, ALD, other suitable methods, or combinations thereof. In some embodiments, the filler metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed on the seed layer by electroplating.

[0208] Method 126 proceeds to operation 154, performing a chemical mechanical polishing (CMP) process to remove excess gate material and planarize the top surface, such as... Figure 4G As shown.

[0209] Figure 1G This is a flowchart of method 126 constructed according to some embodiments. Figures 12A to 12F This is a cross-sectional view of a semiconductor device 200 at various manufacturing stages according to some embodiments. Note that, for the sake of brevity, ... Figures 12A to 12F Only examples are shown in the text. Figure 4GPart 258 of the semiconductor device 200. (See reference) Figure 1G and Figures 12A to 12F Method 126 is described in further detail.

[0210] refer to Figure 1G and Figure 12A Method 126 includes using the N-type region ( Figure 7A The “N” in the middle) and the P-type region ( Figure 7A The operation 136 involves forming an interface layer 252 on channel 244 in both (P in the diagram). In the disclosed embodiments, the interface layer 252 surrounds each channel 244. The interface layer 252 may include silicon oxide, other suitable dielectric materials, or combinations thereof. The interface layer 252 may be formed by applying a wet solution of a hydrochloric acid-hydrogen peroxide-water mixture to the channel 244, thermal oxidation, atomic layer deposition (ALD), other suitable techniques, or combinations thereof.

[0211] refer to FIG. 1G and FIG. 12B Method 126 proceeds to operation 140, where, following the dipole treatment in operation 138, a first high-dielectric-constant (HK) dielectric layer 254-1 is formed over the interface layer 252 in the N-type and P-type regions. In an embodiment, the first high-dielectric-constant dielectric layer 254-1 comprises hafnium oxide (HfO) or zirconium oxide (ZrO). The first high-dielectric-constant dielectric layer 254-1 is deposited by ALD, other suitable methods, or a combination thereof.

[0212] refer to FIG. 1G and FIG. 12C Method 126 proceeds to operation 144, where a second high-dielectric-constant (HK) dielectric layer 254-2 is formed over a first high-dielectric-constant (HK) dielectric layer 254-1 in the N-type and P-type regions. The second high-dielectric-constant dielectric layer 254-2 is deposited by ALD, other suitable methods, or a combination thereof. In the disclosed embodiments, the second high-dielectric-constant dielectric layer 254-2 comprises a high-dielectric-constant (HK) dielectric material different from that of the first high-dielectric-constant dielectric layer 254-1. For example, the first high-dielectric-constant dielectric layer 254-1 comprises HfO and the second high-dielectric-constant dielectric layer 254-2 comprises ZrO. In another example, the first high-dielectric-constant dielectric layer 254-1 comprises ZrO and the second high-dielectric-constant dielectric layer 254-2 comprises HfO.

[0213] refer to FIG. 1G and FIG. 12D, method 126 proceeds to operation 146 to perform dipole treatment on the second high-k dielectric layer 254-2 in the N-type region while not performing treatment on the P-type region. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer, such as lanthanum oxide, by a suitable method (e.g., ALD); patterning the dipole layer using photolithography and etching such that the dipole layer is only retained in the N-type region; performing a thermal anneal process such that lanthanum diffuses into the second high-k dielectric layer 254-2 in the N-type region; and etching to remove the dipole layer. In some embodiments, the thermal anneal process has a thermal anneal temperature ranging from 550 °C to 1050 °C; an anneal duration ranging from 5 seconds to 5 minutes; and an anneal gas. The anneal gas can include an inert gas, such as argon, nitrogen, other inert gas, or a combination thereof. In some embodiments, the dipole treatment includes multiple steps: depositing a dipole material layer by a suitable method (e.g., ALD); forming a mask layer using photolithography and etching such that the dipole layer in the P-type region is covered while the dipole layer in the N-type region is exposed; performing a thermal anneal process such that lanthanum diffuses into the second high-k dielectric layer 254-2 in the N-type region; removing the mask layer (e.g., when a patterned photoresist layer is used as the mask layer, the patterned photoresist layer can be removed by stripping or plasma ashing); and etching to remove the dipole layer. As a result, the second high-k dielectric layer 254-2 in the N-type region is treated and includes lanthanum. The lanthanum concentration of the second high-k dielectric layer 254-2 in the N-type region is denoted as C n2 , and the lanthanum concentration of the second high-k dielectric layer 254-2 in the P-type region is denoted as C p2 . In some embodiments, the ratio C n2 / C p2 is greater than 6. In some embodiments, the ratio C n2 / C p2 is between 6 and 16.

[0214] Referring to FIG. 1G and FIG. 12EThe method 126 proceeds to operation 156 to form a third high-k dielectric layer 254-3 over the second high-k dielectric layer 254-2 in the N-type region and the P-type region. The third high-k dielectric layer 254-3 is deposited by ALD, other suitable methods, or combinations thereof. In the disclosed embodiments, the third high-k dielectric layer 254-3 includes a high-k dielectric material that is different from the high-k dielectric material of the first high-k dielectric layer 254-1 but the same as the high-k dielectric material of the second high-k dielectric layer 254-2 before the dipole treatment in operation 146. For example, the first high-k dielectric layer 254-1 includes HfO, while the second high-k dielectric layer 254-2 and the third high-k dielectric layer 354-3 include ZrO. In another example, the first high-k dielectric layer 254-1 includes ZrO, while the second high-k dielectric layer 254-2 and the third high-k dielectric layer 254-3 include HfO. Note that after the dipole treatment in operation 146, the second high-k dielectric layer 254-2 and the third high-k dielectric layer 254-3 are different from each other because the second high-k dielectric layer 254-2 has more lanthanum than the third high-k dielectric layer 25-3. For example, the second high-k dielectric layer 254-2 and the third high-k dielectric layer 354-3 both include ZrO, but the third high-k dielectric layer 354-3 includes more lanthanum than the second high-k dielectric layer 254-2. In another example, the second high-k dielectric layer 254-2 and the third high-k dielectric layer 354-3 both include HfO, but the third high-k dielectric layer 354-3 includes more lanthanum than the second high-k dielectric layer 254-2.

[0215] Reference FIG. 1G and FIG. 12F, method 126 proceeds to operation 150 to form a metal layer of P-metal (or simply P-metal layer) 256-1 on the gate dielectric layer 251 (which includes the interface layer 252 and the three high-k dielectric layers 254-1, 254-2, and 254-3) in the P-type region and the N-type region. The P-metal layer 256-1 includes an aluminum-free metal material. In some embodiments, the P-metal layer 256-1 includes a metal, a metal compound having a work function equal to or greater than 4.7 eV. In the present embodiment, the P-metal layer 256-1 is a titanium nitride (TiN) layer. In various embodiments, the P-metal layer 256-1 includes titanium nitride (TiN), titanium silicon nitride (TiSiN), molybdenum nitride (MoN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The P-metal layer 256-1 is deposited by physical vapor deposition (PVD), ALD, other suitable methods, or a combination thereof.

[0216] Still referring to FIG. 1G and FIG. 12F , method 126 can include operation 152 to form a fill metal (or bulk metal) layer 256-2 on the P-metal layer 256-1. In various embodiments, the fill metal layer 256-2 includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or a combination thereof. The fill metal layer can include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or a combination thereof. The fill metal layer 256-2 can be formed by PVD, electroplating, ALD, other suitable methods, or a combination thereof. In some embodiments, the fill metal layer 256-2 includes a seed layer formed by PVD and a bulk metal layer formed on the seed layer by electroplating.

[0217] Method 126 proceeds to operation 154 to perform a chemical mechanical polishing (CMP) process to remove excess gate material and planarize the top surface, as shown in FIG. 4G .

[0218] In summary, the present disclosure provides a method of forming a semiconductor device having a GAA structure using dummy spacer approach and gate structure formation using dipole treatment and single work function metal on P-type and N-type regions. Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits for semiconductor devices and their formation. The present disclosure provides a method of forming a fully wrapped gate device having an engineered metal gate structure. The formation of the metal gate structure is intended to effectively eliminate various issues such as HK dielectric reliability issues, HK dielectric loss, and metal boundary effects. The disclosed method includes depositing only one work function metal layer in both regions of nFETs and pFETs and performing one or more dipole treatments to the gate dielectric layer in only one of the N-type and P-type regions to adjust the work function of the gate dielectric layer in that region. Overall, the threshold voltages of both nFETs and pFETs have been reduced and optimized.

[0219] In one example aspect, the present disclosure provides a method including providing a substrate having N-type regions for n-type field effect transistors (nFETs) and P-type regions for p-type field effect transistors (pFETs); forming a semiconductor fin protruding from the substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material in an alternating stack, a composition of the second semiconductor material being different from the first semiconductor material; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source / drain (S / D) region adjacent to the first gate stack; performing an etch process to selectively remove the second semiconductor layers to create gaps between the first semiconductor layers; filling the gaps with a dielectric material to form dummy spacers; epitaxially growing source / drain features from the recess; removing the first gate stack to form a gate trench; performing an etch process to remove the dummy spacers through the gate trench; forming a gate dielectric layer to wrap around the first semiconductor layers; dipole treating the gate dielectric layer at a first portion of the N-type regions and leaving the gate dielectric layer untreated at a second portion of the P-type regions; and depositing a P-type metal layer in the gate dielectric layer of the P-type regions and the N-type regions.

[0220] In another example aspect, the present disclosure provides a method including providing a substrate having N-type regions for n-type field effect transistors (nFETs) and P-type regions for p-type field effect transistors (pFETs); forming a gate dielectric layer to wrap around vertically stacked channels in the N-type regions and the P-type regions; dipole treating the gate dielectric layer at a first portion of the N-type regions and leaving the gate dielectric layer untreated at a second portion of the P-type regions; depositing a P-type metal layer in the gate dielectric layer of the P-type regions and the N-type regions; and forming a fill metal layer on the P-type metal layer of the P-type regions and the N-type regions.

[0221] In another example embodiment, this disclosure provides a semiconductor structure including a substrate having an N-type region for n-type field-effect transistors (nFETs) and a P-type region for p-type field-effect transistors (pFETs); a first channel region disposed on the N-type region of the substrate and a second channel region disposed on the P-type region of the substrate, wherein the first channel region includes a plurality of first channels stacked perpendicularly to each other, and the second channel region includes a plurality of second channels stacked perpendicularly to each other; a first source / drain (S / D) region adjacent to the first channel region and a second source / drain (S / D) region adjacent to the second channel region; and a gate stack disposed on the first channel region and the second channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first portion located in a P-type region and a second portion located in an N-type region. The first portion of the gate dielectric layer includes a first lanthanum concentration Cp and engages with a first channel region and surrounds each first channel. The second portion of the gate dielectric layer includes a second lanthanum concentration Cn and engages with a second channel region and surrounds each second channel. Cn is greater than Cp. The gate electrode includes a P-type metal layer disposed on the gate dielectric layer and the P-type metal layer extends from the P-type region to the N-type region.

[0222] The foregoing outlines components of several embodiments to facilitate a better understanding of the views expressed in the embodiments of this disclosure by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate having an N-type region and a P-type region, the N-type region being used for an n-type field-effect transistor and the P-type region being used for a p-type field-effect transistor; A semiconductor fin is formed protruding from the substrate. The semiconductor fin includes multiple first semiconductor layers of a first semiconductor material and multiple second semiconductor layers of a second semiconductor material stacked alternately. The composition of the second semiconductor material is different from that of the first semiconductor material. A first gate is formed on the semiconductor fin; A groove is formed in the semiconductor fin within a source / drain region adjacent to the first gate stack; An etching process is performed to selectively remove the plurality of second semiconductor layers, thereby creating gaps between the plurality of first semiconductor layers; The gaps are filled with a dielectric material to form a plurality of dummy intermediaries; A source / drain component is epitaxially grown from the groove; Remove the first gate stack to form a gate trench; An etching process is performed to remove the plurality of dummy intermediates via the gate trench; A gate dielectric layer is formed to surround the plurality of first semiconductor layers; A dipole treatment is performed on a first portion of the gate dielectric layer in the N-type region, while a second portion of the gate dielectric layer in the P-type region remains untreated; and A P-type metal layer is deposited in the gate dielectric layer of the P-type region and the N-type region.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of performing the dipole treatment on the first portion of the gate dielectric layer in the N-type region includes: A dipole material layer is deposited in the gate dielectric layer of the N-type region and the P-type region; The dipole material layer is patterned such that a portion of the dipole material layer located in the P-type region is removed; A thermal annealing process is performed to allow the dipole material layer to diffuse into the gate dielectric layer of the N-type region; as well as The dipole material layer is removed by etching.

3. The method for forming a semiconductor structure as described in claim 2, wherein the dipole processing is performed on the first portion of the gate dielectric layer located in the N-type region, while the second portion of the gate dielectric layer located in the P-type region remains unprocessed, wherein... The first portion of the gate dielectric layer located in the N-type region includes a first lanthanum concentration Cn; The second portion of the gate dielectric layer located in the P-type region includes a second lanthanum concentration Cp; and The ratio of Cn / Cp is greater than 6.

4. The method for forming a semiconductor structure as claimed in claim 2, wherein the step of forming the gate dielectric layer to surround the plurality of first semiconductor layers further comprises: Deposit an interface layer; A first high dielectric constant dielectric layer is deposited on the interface layer; as well as A second high dielectric constant dielectric layer is deposited on the first high dielectric constant dielectric layer, wherein the composition of the second high dielectric constant dielectric layer is different from that of the first high dielectric constant dielectric layer, wherein the first high dielectric constant dielectric layer includes hafnium oxide; and the second high dielectric constant dielectric layer includes zirconium oxide.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of depositing the P-type metal layer in the gate dielectric layer of the P-type region and the N-type region comprises: Titanium nitride layers are deposited on the gate dielectric layer in the P-type region and the N-type region.

6. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate having an N-type region and a P-type region, the N-type region being used for an n-type field-effect transistor and the P-type region being used for a p-type field-effect transistor; A gate dielectric layer is formed in the N-type region and the P-type region to surround the vertically stacked channels; A dipole treatment is performed on a first portion of the gate dielectric layer in the N-type region, while a second portion of the gate dielectric layer in the P-type region remains untreated. Deposit a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region; and A filler metal layer is formed in the P-type metal layer of the P-type region and the N-type region.

7. The method for forming a semiconductor structure as described in claim 6, further comprising: A semiconductor fin is formed protruding from the substrate. The semiconductor fin includes multiple silicon first semiconductor layers and multiple silicon germanium second semiconductor layers stacked alternately. The step of forming the gate dielectric layer on the N-type region and the P-type region to surround the vertically stacked multiple channels includes forming the gate dielectric layer on the semiconductor fin on the N-type region and the P-type region. A dummy gate is formed on the semiconductor fin; A groove is formed in the semiconductor fins adjacent to the source / drain region of the dummy gate stack; An etching process is performed to selectively remove the second semiconductor layers, thereby creating gaps between the plurality of first semiconductor layers; The gaps are filled with a dielectric material to form a plurality of dummy intermediaries; The dummy interposer is etched laterally to create multiple undercuts between the plurality of first semiconductor layers; Multiple inner spacers are formed in the multiple undercuts; A source / drain component is epitaxially grown from the groove; Remove the dummy gate stack to form a gate trench; An etching process is performed to remove the plurality of dummy intermediates via the gate trench; as well as A titanium nitride adhesive layer is formed and inserted between the P-type metal layer and the filler metal layer.

8. The method for forming a semiconductor structure as claimed in claim 6, wherein the step of performing the dipole treatment on the first portion of the gate dielectric layer in the N-type region comprises: A lanthanum oxide layer is deposited on the gate dielectric layer in the N-type region and the P-type region; The lanthanum oxide layer is patterned such that a portion of the lanthanum oxide in the P-type region is removed; A thermal annealing process is performed to allow lanthanum in the lanthanum oxide layer to diffuse into the gate dielectric layer of the N-type region; as well as The lanthanum oxide layer is removed by etching.

9. The method of forming a semiconductor structure as claimed in claim 6, wherein the step of forming the gate dielectric layer in the N-type region and the P-type region to surround the vertically stacked plurality of channels includes: Deposit an interface layer; A first high dielectric constant dielectric layer is deposited on the interface layer; as well as A second high dielectric constant dielectric layer is deposited on the first high dielectric constant dielectric layer, wherein a first of the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer comprises hafnium oxide, and a second of the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer comprises zirconium oxide.

10. A semiconductor structure comprising: A substrate having an N-type region and a P-type region, wherein the N-type region is used for an n-type field-effect transistor and the P-type region is used for a p-type field-effect transistor; A first channel region and a second channel region, the first channel region being disposed on the N-type region of the substrate, and the second channel region being disposed on the P-type region of the substrate, wherein the first channel region includes a plurality of first channels stacked perpendicularly to each other, and the second channel region includes a plurality of second channels stacked perpendicularly to each other. A first source / drain region and a second source / drain region, the first source / drain region being adjacent to the first channel region, and the second source / drain region being adjacent to the second channel region; and A gate stack is disposed on the first channel region and the second channel region, wherein The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first portion located in the P-type region and a second portion located in the N-type region. The first portion of the gate dielectric layer includes a first lanthanum concentration Cp and fits the first channel region and surrounds each first channel. The second portion of the gate dielectric layer includes a second lanthanum concentration Cn and fits the second channel region and surrounds each second channel, where Cn is greater than Cp. The gate electrode includes a P-type metal layer disposed on the gate dielectric layer, and The P-type metal layer extends from the P-type region to the N-type region.

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