Fractional Valley Switching Controller

Abstract

A power converter controller includes a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a main switch, the target number of valleys corresponding to a desired turn-off time of the main switch, the fractional valley controller modulating the turn-off time of the main switch between two or more modulated turn-off times. The target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch. Each of the modulated turn-off times of the main switch corresponds to an integer number of valleys, and the two or more modulated turn-off times of the main switch have an average value corresponding to the desired turn-off time.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. non-provisional patent application No. 16 / 269,931, filed on February 7, 2019, and entitled “Fractional Valley Switching Controller,” which claims the benefit of U.S. Provisional Patent Application No. 62 / 630,639, filed on February 14, 2018, and entitled “Fractional Valley Switching Controller,” and is related to U.S. Patent Application No. 16 / 020,496, filed on June 27, 2018, and entitled “Switch-Mode Power Supply Controller”; all of which are hereby incorporated by reference in their entirety for all purposes. Technical Field

[0003] Embodiments of the present disclosure relate to a fractional valley switching controller. Background Art

[0004] Switched mode power supplies (SMPS) ("power converters") are widely used in consumer, industrial, and medical applications to provide well-regulated power while maintaining high power handling efficiency, tight output voltage regulation, and reduced conducted and radiated electromagnetic interference (EMI).

[0005] To meet these conflicting goals, state-of-the-art power converters (flyback converters, forward converters, boost converters, buck converters, etc.) typically employ quasi-resonant control methods. Quasi-resonant control methods induce a resonant waveform with sinusoidal voltage oscillations at the drain of one or more semiconductor switches of the power converter. Through timely control actions, the semiconductor switches are turned on at the moment when the drain voltage is minimum (i.e., valley switching), thereby minimizing semiconductor switching losses and drain-source dv / dt slopes, thereby improving power handling efficiency and reducing electromagnetic interference (EMI).

[0006] In order to maintain these benefits over the entire operating range of the power converter, it is generally necessary to "jump" between valleys of the resonant waveform in a manner that minimizes the sum of conduction losses and switching losses (which are generally inversely proportional to each other). Typically, this problem is partially addressed by introducing large valley jump hysteresis constraints. In addition, if there are frequent and / or repeated low-frequency mode transitions, the magnetic and / or capacitive elements of the power converter may generate audible noise.

[0007] Typically, this problem is partially addressed by introducing large valley jump hysteresis constraints. However, such approaches can negatively impact power handling efficiency and eliminate any potential spread spectrum benefits from more frequent valley jumps. Additionally, large output voltage perturbations are still introduced due to such valley mode transitions. Summary of the invention

[0008] Some embodiments described herein provide a power converter controller including a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a main switch, the target number of valleys corresponding to a desired off-time of the main switch, the fractional valley controller modulating the off-time of the main switch between two or more modulated off-times. The target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch. Each of the modulated off-times of the main switch corresponds to an integer number of valleys.

[0009] The two or more modulated turn-off times of the main switch have an average value corresponding to the desired turn-off time.

[0010] Some embodiments described herein provide a power converter including a transformer having a primary winding configured to receive an input voltage and a secondary winding configured to provide an output voltage to a load. A main switch is coupled to the primary winding and configured to control a current through the primary winding to generate the output voltage. A resonant waveform at a drain node of the main switch includes one or more valleys during a disconnection time of the main switch. The power converter includes a primary side controller configured to control the main switch. The primary side controller includes a fractional valley controller configured to control the disconnection time of the main switch. The fractional valley controller is configured to determine a target number of valleys corresponding to a desired disconnection time of the main switch, the target number of valleys corresponding to a non-integer number of valleys. The fractional valley controller is configured to modulate the disconnection time of the main switch between two or more modulated disconnection times, each of the modulated disconnection times of the main switch corresponding to a corresponding integer number of valleys of the resonant waveform, and the two or more modulated disconnection times of the main switch have an average value corresponding to the desired disconnection time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a simplified schematic diagram of a power converter implementing fractional valley switching in accordance with some embodiments.

[0012] Figure 2 According to some embodiments Figure 1A simplified schematic of a power converter configured as a flyback converter.

[0013] Figure 3 According to some embodiments Figure 2 A simplified graph of signals associated with a power converter is shown.

[0014] Figure 4 According to some embodiments Figure 2 A simplified schematic diagram of the primary side controller of the power converter is shown.

[0015] Figure 5 According to some embodiments Figure 4 A simplified schematic diagram of a fractional valley controller of the primary side controller is shown.

[0016] Figure 6 to Figure 7 According to some embodiments Figure 5 A simplified schematic diagram of a valley integer modulator of a fractional valley controller is shown.

[0017] Figure 8 According to some embodiments Figure 2 A simplified graph of signals associated with a power converter is shown.

[0018] Figures 9 and 10 According to some embodiments Figure 2 The power converter shown is similar to a screenshot of the experimental results of a tested power converter. DETAILED DESCRIPTION

[0019] Some embodiments described herein provide a fractional valley switching controller of a switch mode power supply ("power converter") that implements fractional valley switching during a quasi-resonant operating mode of the power converter. In some embodiments, the fractional valley switching controller ("fractional valley controller") is part of a primary side controller of the power converter. In general, the power converter converts an input voltage on the primary side of a transformer to an output voltage on the secondary side of the transformer by controlling the current through the primary winding of the transformer using a primary side switch ("main switch"). During the disconnection of the main switch, a resonant waveform is formed at the drain node of the main switch. Based on the disconnection time of the main switch, the resonant waveform includes one or more peaks (local maxima) and one or more valleys (local minima). The primary side controller of the power converter is configured to control the disconnection time of the main switch so that the main switch is generally switched only when the drain-source voltage of the main switch is at a local minimum (i.e., at the valley of the resonant waveform). Unfortunately, in some cases, the total power delivered by the power converter may correspond to a non-integer number of valleys. Since the non-integer number of valleys does not correspond to the local minimum of the resonant waveform, switching the main switch at the non-integer number of valleys will result in switching losses greater than the switching losses in the case of switching the main switch when the drain-source voltage is at a local minimum (i.e., corresponding to an integer number of valleys). The fractional valley switching controller disclosed herein advantageously controls the disconnection time of the main switch by fractional valley switching, so that the main switch is usually switched only at integer valleys, but the power converter is still able to deliver the total power corresponding to the non-integer number of valleys. As disclosed herein, this fractional valley switching is achieved by the fractional valley controller by modulating a series of disconnection times of the main switch, each modulated disconnection time corresponding to a corresponding integer number of valleys. The average value of the modulated disconnection time converges to the disconnection time corresponding to the non-integer (i.e., fractional) valley. Therefore, advantageously, an accurate amount of power is delivered by the power converter, and the switching losses are still minimized. In addition, the fractional valley controller disclosed herein advantageously enables or disables fractional valley switching based on the switching cycle frequency of the main switch to prevent undesirable audible tones. Furthermore, the fractional valley controller disclosed herein provides a fractional resolution for a non-integer number of valleys, which is greater than the fractional resolution provided by typical valley dithering techniques.

[0020] Figure 1 is a simplified circuit diagram of a power converter 100 according to some embodiments. To simplify the description of the power converter 100, Figure 1Some elements of the power converter 100 are omitted in the figure, but should be understood to be present. In general, the power converter 100 includes an input voltage filter block 102, a rectifier block 104 (in the case of AC input), a quasi-resonant converter circuit 106, a fractional valley controller 108 of a primary side controller 110 ("power converter controller"), an output buffer circuit 111, a compensator / isolator ("feedback network") 112, a signal difference block 114, an auxiliary winding 116 of a transformer 118 of the quasi-resonant converter circuit 106, an input voltage buffer capacitor C1', and a main switch M1', coupled as shown. Also shown is the drain-source voltage V of the main switch M1' at the signal node 120. dsM1’ 、Input voltage V 输入 ', the regulated input voltage V at the signal node 122 输入 , auxiliary voltage V 辅助 , output voltage V 输出 , output current i 负载 , feedback signal t 接通 , error signal e 输出 and reference voltage V 参考 .

[0021] The power converter 100 is configured to receive an input voltage V 输入 ' and based on the on-time and off-time of the main switch M1', the output voltage V 输出 and the output current i 负载 Provided to load R L' The on-time and off-time of the main switch M1' are controlled by the primary side controller 110. The primary side controller 110 is configured to receive an input voltage V 输入 , auxiliary voltage V 辅助 and feedback signals (e.g., magnetizing inductance charging time t 接通 or other feedback signals), and generates the main switch control signal PWM M1 To control the on-time and off-time of the main switch M1 ′. In some embodiments, the quasi-resonant converter circuit 106 is implemented as a flyback, forward, boost or buck power converter.

[0022] Figure 2 is a simplified circuit diagram of a power converter 200 according to some embodiments. When the quasi-resonant converter circuit 106 is implemented as a flyback converter, the power converter 200 is an example embodiment of the power converter 100. To simplify the description of the power converter 200, Figure 2Some elements of the power converter 200 are omitted from the figure, but should be understood to be present. In general, the power converter 200 includes an input voltage filter block 202 coupled as shown, a rectifier block 204 (in the case of AC input), a fractional valley controller 208 of a primary side controller 210 ("power converter controller"), an output buffer circuit 211, a compensator / isolator ("feedback network") 212, a signal difference block 214, an auxiliary winding 216 of a transformer 218, a clamp circuit 232, a primary winding 234 of the transformer 218 located on the input side of the power converter 200, a secondary winding 236 of the transformer 218 located on the output side of the power converter 200, a synchronous switch controller 238, an input voltage buffer capacitor C1, a main switch M1, and a synchronous switch M2. Also shown is the drain-source voltage V of the main switch M1 at the signal node 220. dsM1 、Input voltage V 输入 ', the regulated input voltage V at the signal node 222 输入 , optional active clamp control signal AC 控制 , auxiliary voltage V 辅助 , output voltage V 输出 , output current i 负载 , feedback signal (for example, magnetizing inductance charging time t 接通 or other feedback signals), error signal e 输出 and reference voltage V 参考 .

[0023] The power converter 200 is configured to receive an input voltage V 输入 'And based on the on time and off time of the main switch M1, the output voltage V 输出 and the output current i 负载 Provided to load R L The on-time and off-time of the main switch M1 are controlled by the primary side controller 210. The primary side controller 210 is configured to receive an input voltage V 输入 , auxiliary voltage V 辅助 and magnetizing inductance charging time t 接通 (or other feedback signal), and generates the main switch control signal PWM M1 To control the on time and off time of the main switch M1.

[0024] The main switch M1 is coupled to the primary winding 234 and is configured to control the current through the primary winding 234 to use the input voltage V during the first part of the switching cycle of the power converter 200 (ie, when the main switch M1 is turned on). 输入The magnetizing inductance of transformer 218 is charged. Synchronous rectifier switch M2 controls the current through secondary winding 236 to discharge transformer 218 to output buffer circuit 211 and load R during the subsequent portion of the switching cycle (i.e., when main switch M1 is turned off). L The clamp circuit 232 generates a drain-source voltage V at the drain node of the main switch M1. dsM1 The clamp circuit 232 is limited to a voltage less than the maximum safe operating voltage of the main switch M1. In some embodiments, the clamp circuit 232 is a self-driven active clamp circuit (e.g., the clamp circuit 232 does not require a control signal provided by the primary side controller 210). In other embodiments, the clamp circuit 232 is an active clamp circuit that is driven by the primary side controller 210 using an optional active clamp control signal AC 控制 In yet other embodiments, the clamp circuit 232 is a resistor-capacitor-diode (RCD) snubber circuit.

[0025] Feedback network 212 generates an internal error signal that represents the output voltage V at the output terminal of power converter 200. 输出 With reference voltage V 参考 In some embodiments, the feedback network 212 processes the difference through an internal proportional integral (PI) or proportional integral derivative (PID) compensator. In some embodiments, an isolator is used to mirror the output from the feedback network 212 from the output side of the power converter 200 to the input side of the power converter 200. The feedback network 212 provides a feedback signal to the primary side controller 210, which adjusts the main switch control signal PWM based on the feedback signal. M1 For example, in some embodiments, the feedback signal corresponds to a desired on-time t for the main switch M1 to charge the magnetizing inductance of the transformer 218 . 接通 .

[0026] The primary side controller 210 is configured to receive a feedback signal from a feedback network 212, an input voltage V 输入 and auxiliary voltage V 辅助 , and generates a main switch control signal PWM based on these received signals M1 . Main switch control signal PWM M1 The main switch M1 is set according to the on time and off time t of the main switch M1. 断开 During quasi-resonant operation of the power converter 200, when the main switch M1 is turned off, a resonant waveform is formed at the drain node of the main switch M1. The resonant waveform includes a series of voltage peaks (local maxima) and valleys (local minima). The primary side controller 210 advantageously uses the main switch control signal PWM M1To control the main switch M1, so that when the voltage V dsM1 When the main switch M1 is at a local minimum (i.e., at a valley of the resonant waveform), the main switch M1 is turned on. During a series of switching cycles of the main switch M1, the fractional valley controller 208 modulates the valleys at which the main switch M1 is turned on, so that the average value of the modulated valley sequence converges to a non-integer number of valleys. For example, the non-integer (i.e., fractional) average value of the integer valley sequence of an integer number of valleys: {2, 2, 2, 1} is 1.75.

[0027] exist Figure 3 The drain-source voltage V at the drain node of the main switch M1 is shown in dsM1 A simplified graph 300 of a resonant waveform having integer valleys 304a-c during a first switching period 306 and integer valleys 308a-b during a second switching period 310 is shown. By adjusting the off time of the main switch M1, the primary side controller 210 adjusts the power delivered to the load R L The total power (i 负载 ,V 输出 For example, by adjusting the off time of the main switch M1 to start at the third valley 304c of the first switching cycle 306 compared to the second switching cycle 310 during which the main switch M1 starts at the second valley 308b, the primary side controller 210 will cause less power to be delivered to the load R. L .

[0028] Unfortunately, in some cases, delivering to the load R L The total power will correspond to a non-integer number of valleys (eg, point 312). As previously discussed, when the drain-source voltage V dsM1 Switching the main switch M1 when it is not at its minimum value causes greater switching losses than when the drain-source voltage V dsM1 The switching loss when the main switch M1 is switched at the minimum value (i.e., corresponding to an integer number of valleys). Therefore, if the main switch M1 is frequently switched at a non-integer number of valleys (e.g., point 312), the switching loss of the power converter 200 will be greater than the switching loss when the main switch M1 is switched at any integer number of valleys (e.g., 304a-c).

[0029] The fractional valley controller 208 as disclosed herein advantageously controls the off time of the main switch M1 by fractional valley switching, so that the main switch M1 is switched only at an integer number of valleys (i.e., in the middle of a valley), but the power converter 200 is still able to deliver a total power corresponding to a non-integer number of valleys to the load R. L. In addition, fractional valley switching as disclosed herein enables a range of such non-integer valley numbers to be greater than a typical fractional range. For example, a typical valley dithering method that jitters or jumps between two adjacent valleys can deliver a total power corresponding to an average value between the two adjacent valleys. That is, jumping or jittering between valley 1 (304a) and valley 2 (304b) will converge to an average value corresponding to valley 1.5. However, such a typical valley dithering method cannot deliver a total power corresponding to a greater resolution of fractional values ​​between integer valleys (e.g., corresponding to valley 1.25, valley 1.3, valley 1.4, valley 1.45, valley 1.55, etc.).

[0030] exist Figure 4 Detailed description of the primary side controller 210 according to some embodiments is shown in FIG. Figure 4 Some elements and signals of the primary side controller 210 are omitted, but should be understood to exist. In general, the primary side controller 210 includes a PWM ramp generator ("PWM Ramp Gen.") 402, an analog-to-digital converter (ADC) module 404, a power optimization controller 406, a fractional valley controller 408, a zero crossing detector (ZCD) 410, and other modules 412 coupled as shown. In some embodiments, the other modules 412 include other digital and / or analog modules of the primary side controller 210, such as additional control circuit systems, one or more processors (e.g., microcontrollers, microprocessors, DSPs, ASICs, FPGAs), volatile data storage devices, non-volatile data storage devices, communication modules, or other other components. In some embodiments, one or more components of the other modules 412 can communicate signals with one or more of the described components of the primary side controller 210 and / or with other components of the power converter 200.

[0031] The ADC module 404 is configured to generate a signal based on the feedback signal t 接通 (the expected on-time of the main switch M1) to generate the digital feedback signal t 接通 (n). The ADC module 404 is also configured to generate a voltage signal based on the regulated input voltage V 输入 To generate the digital input voltage V 输入 (n). In some embodiments, as described in related application US Patent Application No. 16 / 020,496, the power optimization controller 406 generates a desired off time t of the main switch M1. 断开 * (n). ZCD 410 generates a valley detection signal valley for each detected valley (eg, valley 304a-c). 检测In some embodiments, the ZCD 410 uses an auxiliary voltage V generated by the auxiliary winding 216. 辅助 To detect each valley of the resonant waveform at the drain node of the main switch M1. In other embodiments, the ZCD 410 detects each valley of the resonant waveform at the drain node of the main switch M1 using a voltage received from the drain node of the main switch M1 or based on a voltage at the drain node of the main switch M1. The fractional valley controller 408 is configured to receive a valley detection signal valley from the power optimization controller 406. 检测 , the measured disconnection time t of the main switch M1 断开 (n), switching period frequency signal t 切换 (n) (representing the value of the switching period or switching frequency of the main switch M1) and the expected off time t of the main switch M1 断开 * (n). Expected disconnection time t 断开 * (n) is the calculated off time of the main switch M1, which corresponds to the power to be delivered to the load R L As mentioned above, in some cases, the expected off time t of the main switch M1 is 断开 * (n) corresponds to a non-integer number of valleys. The fractional valley controller 408 is configured to modulate the off time t of the main switch M1 between a series of modulated off times. 断开 (n). The modulated disconnection time is a disconnection time of the main switch M1 that is different in time from one or more other disconnection times in a series of modulated disconnection times. That is, in the series of modulated disconnection times, the first modulated disconnection time may have a duration of t, the second modulated disconnection time may have a duration of t+τ, the third modulated disconnection time may also have a duration of t+τ, the fourth modulated disconnection time may have a duration of t..., and so on, where τ is the delay.

[0032] Each modulated off-time corresponds to an integer number of valleys of the resonant waveform at the drain node of the main switch M1. However, the average value of the modulated off-time of the main switch M1 converges to an average off-time of the main switch M1 corresponding to a non-integer number of valleys. Therefore, the fractional valley controller 408 advantageously increases the drain-source voltage V dsM1 The main switch M1 is switched at the point of minimization, but the current delivered to the load R L When the number of valleys detected using ZCD 410 exceeds the target number of valleys determined by fractional valley controller 408, fractional valley controller 408 resets the reset signal PWM 重置The PWM ramp generator 402 causes the main switch M1 to switch according to the modulated off time of the main switch M1.

[0033] exist Figure 5 A simplified schematic diagram of the fractional valley controller 408 according to some embodiments is shown in FIG. Figure 5 Some elements of the fractional valley controller 408 are omitted in the figure, but should be understood to be present. Generally speaking, the fractional valley controller 408 includes an OR gate 502, a valley counter 504, an audible noise filter 506, a first signal comparison block 508, a second signal comparison block 510, a valley integer modulator 512, and a target valley generator 514. The audible noise filter 506 generally includes a third signal comparison block 516.

[0034] The first signal comparison block 508 is configured to receive the measured off time t of the main switch M1. 断开 (n) and the expected disconnection time t of the main switch M1 断开 * (n), and generates a disconnection time adjustment signal ("increment / decrement"). The first signal comparison block 508 compares the measured disconnection time t 断开 (n) and expected disconnection time t 断开 * (n) is compared. If the measured disconnection time t 断开 (n) is greater than the expected disconnection time t 断开 * (n), the first signal comparison block 508 generates a decremental disconnection time adjustment signal indicating that the main switch M1 should be switched to a time point corresponding to a valley value earlier than the valley value of the current switching main switch M1. 断开 (n) not greater than the expected disconnection time t 断开 * (n), the first signal comparison block 508 generates an incremental off-time adjustment signal indicating that the main switch M1 should be switched to a time point corresponding to a valley value later than the valley value of the current switching main switch M1.

[0035] The target valley generator 514 receives the off time adjustment signal ("increment / decrement") from the first signal comparison block 508 and generates a target valley value having an integer portion (ie, n 整数 ) and the fractional part (i.e., n 小数 )'s target valley number valley * (n 整数 ,n 小数). For example, if the target number of valleys is 2.65, the integer part corresponds to the integer value 2, and the decimal part corresponds to the decimal value 0.65. However, the target number of valleys is not limited to corresponding to only a non-integer number of valleys. For example, for some desired disconnection time t of the main switch M1 断开 * (n), the target valley number may have a fractional part equal to zero.

[0036] The valley integer modulator 512 is configured to receive a target valley number valley * (n 整数 ,n 小数 ), and generates a series of modulated integer valley values * (n). The modulated integer valley number is a valley number that is different in number from one or more other valley numbers in a series of modulated integer valley numbers. That is, in a series of modulated integer valley numbers, the first modulated integer valley number may be 1, the second modulated integer valley number may be 2, the third modulated integer valley number may also be 2, the fourth modulated integer valley number may be 1..., and so on. Advantageously, in some embodiments, the valley integer modulator 512 is configured to generate a non-alternating sequence of modulated integer valley numbers. An example of an alternating sequence of integer valley numbers is {1,2,1,2,1,2,...}. An example of a non-alternating sequence of integer valleys is {1,2,2,2,1,2,2,2,...}. That is, the fractional valley controller 208 is configured to generate a first sequence of one or more serially connected first integer valley numbers, followed by a second sequence of one or more serially connected second integer valley numbers, wherein the length of the first sequence is different from the length of the second sequence, and the one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

[0037] The number of integer valleys after each modulation * (n) corresponds to the modulated off time of the main switch M1. Therefore, a series of modulated integer valley values ​​are * (n) converges to an average number of valleys that is equal to or close to (ie, "approximately") a target number of valleys, which is a non-integer number of valleys.

[0038] Valley counter 504 receives valley from ZCD 410 检测 signal, and increments the internal counter to generate the detected valley count valley(n). The second signal comparison block 510 compares the most recently detected valley count valley(n) with the most recently modulated integer valley number valley *(n) is compared. After determining that the most recently detected valley count valley(n) is greater than the integer valley count valley after the most recent modulation * (n), the second signal comparison block 510 converts PWM 重置 The signal is transmitted to the OR gate 502 and the PWM ramp generator 402. Upon receiving the PWM 重置 signal, the PWM ramp generator 402 transmits the main switch control signal PWM at a level that enables the main switch M1. M1 Therefore, even if the output power of the power converter 200 converges to a power corresponding to a non-integer number of valleys, the main switch M1 is advantageously switched at a time point corresponding to an integer number of valleys.

[0039] OR gate 502 receives PWM 重置 The OR gate 502 transmits a reset signal to the valley counter 504 when receiving the blanking signal. Upon receiving the reset signal, the valley counter 504 resets the internal valley count value to an initial value (e.g., 0). In addition, the OR gate 502 transmits a reset signal to the valley counter 504 when receiving the blanking signal (e.g., during the time when the main switch M1 is not disabled).

[0040] The valley integer modulator 512 is advantageously configured to perform fractional valley switching only when the switching frequency of the main switch M1 is above a minimum frequency threshold, so that the modulated off-time of the main switch M1 will not generate a frequency within the audible noise range (e.g., equal to or less than 30 kHz). The audible noise filter 506 receives the measured switching cycle frequency signal t from the PWM ramp generator 402. 切换 (n), and receiving (eg, from a processor or other component of other module 412, or from another source, such as a configuration component of power converter 200) a minimum switching cycle frequency threshold t 最小 (n). After determining the measured switching cycle frequency signal t 切换 (n) is less than the minimum switching cycle frequency threshold t 最小 (n), the third signal comparison block 516 will deassert the fractional en The signal is sent to the valley integer modulator 512 to disable fractional valley switching. 切换 (n) not less than the minimum switching cycle frequency threshold t 最小 (n), the third signal comparison block 516 will assert the fractional en A signal is sent to the valley integer modulator 512 to enable fractional valley switching. Thus, fractional valley switching is advantageously disabled if it would result in an undesirable audible tone.

[0041] Figure 6is a simplified schematic diagram of an exemplary valley integer modulator 612 that implements the valley integer modulator 512 according to some embodiments. The valley integer modulator 612 is suitable for switching cycle frequencies t greater than 60 kHz due to the generated tones. 切换 (n), the tone in some cases is a switching cycle frequency t 切换 To simplify the description of valley integer modulator 612, Figure 6 Some elements of the valley integer modulator 612 are omitted from the figure, but should be understood to be present. The valley integer modulator 612 generally includes a multiplexer 602 (i.e., a component that receives two or more input signals and selectively passes one of the two or more input signals to the output of the multiplexer), a first modulator 604, a second modulator 606, and a signal adder block 608. The multiplexer 602 receives the fractional en If the fractional en signal is de-asserted, the multiplexer 602 passes the output from the first modulator 604 to the signal adder block 608. If the fractional en signal is asserted, the multiplexer 602 passes the output from the second modulator 606 to the signal adder block 608. In some embodiments, the first modulator 604 generates an output with hysteresis such that for a given initial output of 0, if the fractional valley * (n 小数 ) is greater than or equal to 0.75, the output inc of the multiplexer 602 transitions to 1. In such embodiments, the first modulator 604 typically generates an output with hysteresis such that for a given initial output of 1, if the fractional part valley * (n 小数 ) is less than or equal to 0.25, the output inc of the multiplexer 602 transitions to 0. When fractional valley switching is disabled, the output ripple of the power converter 200 may increase compared to the output ripple when fractional valley switching is enabled.

[0042] In some embodiments, the second modulator 606 generates an output using a different hysteresis than the first modulator 604. In such embodiments, the second modulator 606 generates an output based on the target valley number valley * (n 整数 ,n 小数 ) decimal part valley * (n 小数) generates an output modulated between 1 and 0. That is, for a small value range corresponding to the dead zone of the first modulator 604 by comparison, the second modulator 606 generates a stream of values ​​modulated between 0 and 1.

[0043] The output inc of the multiplexer 602 is added to the target valley number valley through the signal adder block 608. * (n 整数 ,n 小数 ) * (n 整数 ) are added to generate the modulated output valley value flow valley * (n).

[0044] Figure 7 is a simplified schematic diagram of another exemplary valley integer modulator 712 implementing the valley integer modulator 512 according to some embodiments. The valley integer modulator 712 is suitable for switching cycle frequencies t greater than 250 kHz due to low frequency tones. 切换 (n), the low frequency tone is in some cases generated by a k-th order sigma-delta modulator implemented by the second modulator 706. To simplify the description of the valley integer modulator 712, Figure 7 Some elements of the valley integer modulator 712 are omitted in the figure, but should be understood to be present. The valley integer modulator 712 generally includes a multiplexer 702, a first modulator 704, a second modulator 706, and a signal adder block 708. The multiplexer 702 receives the fractional en If the fractional en The signal is de-asserted, and the multiplexer 702 generates an output inc using the output from the first modulator 704. The signal adder block 708 receives the output inc of the multiplexer 702. If the fractional en The signal is asserted, then the multiplexer 702 uses the output from the second modulator 706 to generate the output inc. In some embodiments, the first modulator 704 is as shown in FIG. Figure 6 The first modulator 604 generates an output as described.

[0045] The k-th order sigma-delta modulator implemented by the second modulator 706 is configured to receive a target valley number valley * (n 整数 ,n 小数 ) decimal part valley * (n 小数 ), and based on the fractional part valley * (n 小数) to generate an output stream of "high" and "low" (i.e., 1 and 0). The sigma-delta modulator of the second modulator 706 generates an output stream of values ​​such that the number of 1s in the output stream of values ​​increases with the fractional part valley * (n 小数 ) increases with the increase of the value of ). Similarly, the sigma-delta modulator of the second modulator 706 generates an output stream of values ​​such that the number of 0s in the output stream of values ​​increases with the increase of the fractional part valley * (n 小数 ) decreases and increases. The order of the sigma-delta modulator of the second modulator 706 specifies the number of integrators used, i.e., the number of feedback loops. The higher the order, the higher the fractional valley resolution that can be achieved. The sigma-delta modulator of the second modulator 706 advantageously generates the output stream as a noise shaped signal to achieve a higher resolution of fractional valley switching with a predicted frequency content compared to hysteresis-based methods. For example, an exemplary modulated integer valley number valley generated by the valley integer modulator 712 * The sequence of (n) may include a sequence of non-integer numbers of valleys that converge to 2.25, such as {4, 2, 1, 2, ...}.

[0046] Figure 8 FIG. 8 is a simplified graph 800 of signals related to the power converter 200 indicating its operation according to some embodiments. The simplified graph 800 includes a drain-source voltage V dsM1 The curve graph 802 (ie, the resonant waveform), the target valley value number valley * (n 整数 ,n 小数 ) * (n 整数 ), a graph 804 of the output inc of the multiplexer 602 or 702, and a graph 806 of the modulated valley number valley * In the example shown in the simplified graph 800, the average number of valleys of the resonant waveform at the drain node of the main switch M1 converges to a non-integer number of valleys of 2.5.

[0047] Fig. 9 Screen shots 902, 904 show experimental results of testing a power converter similar to power converter 200 according to some embodiments. Each of the screen shots 902, 904 shows the drain-source voltage V of the main switch of the test power converter over a period of time. dsM1Screen shot 902 shows fractional valley switching between the 1st valley and the 2nd valley to achieve a 1.5A output to the load of the test power converter. Screen shot 904 shows fractional valley switching between the 4th valley and the 5th valley to achieve a 0.75A output to the load of the test power converter.

[0048] Fig.10 Screen shots 1002, 1004 show experimental results of testing a power converter similar to power converter 200 according to some embodiments. Each of the screen shots 1002, 1004 shows the drain-source voltage V of the main switch of the tested power converter. dsM1 Screen shot 1002 shows the time domain (1002a / 1004a) and frequency domain (1002b / 1004b) measurements of the power converter under test at 90Vac / 5.1Vdc 1.5A operation when fractional valley switching (i.e., en =1) when V dsM1 The time domain and frequency domain measurements of FIG. 1004 are shown in FIG. 1005 , and the screenshot 1004 shows the time domain and frequency domain measurements of FIG. 1005 when the fractional valley switching is disabled (ie, fractional en =0) when V dsM1 As shown in the figure, when fractional valley switching is enabled, the output voltage ripple of the test power converter is advantageously reduced from 340mV to 260mV. When fractional valley switching is enabled, the test power converter generates a frequency component of 60kHz, however, the frequency component of 60kHz is beyond the audible noise range.

[0049] With detailed reference to the disclosed embodiments of the present invention, one or more examples of the present invention have been shown in the accompanying drawings. Each example has been provided by way of explaining the present technology rather than limiting the present technology. In fact, although this specification has been described in detail with respect to specific embodiments of the present invention, it will be appreciated that those skilled in the art can easily conceive of alternative forms, variant forms, and equivalents of these embodiments after obtaining an understanding of the foregoing. For example, a feature shown or described as part of one embodiment can be used together with another embodiment to produce yet another embodiment. Therefore, the present subject matter is intended to encompass all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations of the present invention may be practiced by those of ordinary skill in the art without departing from the scope of the present invention specifically set forth in the appended claims. In addition, those of ordinary skill in the art will appreciate that the foregoing description is merely an example and is not intended to limit the present invention.

Claims

1. A power converter controller, comprising: a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a primary switch, the target number of valleys corresponding to a desired off time of the primary switch, the fractional valley controller modulating an off time of the primary switch between a plurality of modulated off times; in: The target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch; Each of the modulated off-times of the main switch corresponds to an integer number of valleys; and The plurality of modulated turn-off times of the main switch have an average value corresponding to the desired turn-off time.

2. The power converter controller of claim 1, wherein: Each modulated off time of the plurality of modulated off times corresponds to a corresponding modulated integer number of valleys of a plurality of modulated integer numbers of valleys; The plurality of modulated integer valley numbers comprises a first sequence of one or more concatenated first integer valley numbers followed by a second sequence of one or more concatenated second integer valley numbers; The length of the first sequence is different from the length of the second sequence; and The one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

3. The power converter controller of claim 1 , further comprising: The target valley generator of the fractional valley controller is configured to generate the target valley number based on a difference between the expected turn-off time of the main switch and a measured turn-off time of the main switch.

4. The power converter controller of claim 1 , further comprising: a PWM ramp generator configured to control the main switch; Power optimization controller; an off-time comparison module of the fractional valley controller, the off-time comparison module being configured to: i) receive a measurement of the off-time of the main switch from the PWM ramp generator, and ii) receive the desired off-time of the main switch from the power optimization controller, and issue an off-time adjustment signal based on a difference between the measurement of the off-time and the desired off-time; as well as The target valley determination module of the fractional valley controller is configured to receive the disconnection time adjustment signal and generate the target valley number based on the disconnection time adjustment signal.

5. The power converter controller of claim 1 , further comprising: an audible noise filter of the fractional valley controller, the audible noise filter being configured to: i) generate a fractional mode enable signal if the switching frequency of the main switch is greater than a threshold switching frequency, and ii) generate a fractional mode disable signal if the switching frequency of the main switch is not greater than the threshold switching frequency.

6. The power converter controller of claim 5, further comprising: A valley integer modulator of the fractional valley controller is configured to generate a plurality of modulated integer valley quantities based on the target valley quantity, the valley integer modulator being configured to receive the fractional mode enable signal and the fractional mode disable signal.

7. The power converter controller of claim 6, wherein: The valley integer modulator is configured to generate the plurality of modulated integer valley quantities using a first modulator upon receiving the fractional mode disable signal; and The valley integer modulator is configured to generate the plurality of modulated integer valley quantities using a second modulator upon receiving the fractional mode enable signal.

8. The power converter controller of claim 7, wherein: The first modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having two fixed levels.

9. The power converter controller of claim 7, wherein: The second modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having a varying first level and a fixed second level.

10. The power converter controller of claim 7, wherein: The second modulator generates the plurality of modulated integer number of valleys using a sigma-delta modulator.

11. A power converter comprising: a transformer having a primary winding configured to receive an input voltage and a secondary winding configured to provide an output voltage to a load; a main switch coupled to the primary winding and configured to control current through the primary winding to generate the output voltage, a resonant waveform at a drain node of the main switch including one or more valleys during an off-time of the main switch; as well as a primary side controller configured to control the main switch, the primary side controller comprising a fractional valley controller configured to control the off time of the main switch; in: The fractional valley controller is configured to determine a target number of valleys corresponding to a desired off time of the primary switch, the target number of valleys corresponding to a non-integer number of valleys; the fractional valley controller being configured to modulate the off-time of the main switch between a plurality of modulated off-times, each of the modulated off-times of the main switch corresponding to a respective integer number of valleys of the resonant waveform; and The plurality of modulated turn-off times of the main switch have an average value corresponding to the desired turn-off time.

12. The power converter of claim 11, wherein: Each modulated off time of the plurality of modulated off times corresponds to a corresponding modulated integer number of valleys of a plurality of modulated integer numbers of valleys; The plurality of modulated integer valley numbers comprises a first sequence of one or more concatenated first integer valley numbers followed by a second sequence of one or more concatenated second integer valley numbers; The length of the first sequence is different from the length of the second sequence; and The one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

13. The power converter of claim 11, further comprising: a valley detection circuit of the primary side controller, the valley detection circuit being configured to generate a valley detection signal for each of the one or more valleys; as well as an auxiliary winding of the transformer, the auxiliary winding being coupled to the valley detection circuit and being configured to provide an auxiliary voltage corresponding to the one or more valleys of the resonant waveform during the off time of the main switch, the valley detection signal being generated based on the auxiliary voltage.

14. The power converter of claim 11, further comprising: a disconnection time comparison module of the fractional valley controller, the disconnection time comparison module being configured to: i) receive a measurement of the disconnection time of the main switch, and ii) receive the desired disconnection time of the main switch, and issue a disconnection time adjustment signal based on a difference between the measurement of the disconnection time and the desired disconnection time; as well as The target valley determination module of the fractional valley controller is configured to receive the disconnection time adjustment signal and generate the target valley number based on the disconnection time adjustment signal.

15. The power converter of claim 11, further comprising: and a valley integer modulator of the fractional valley controller, the valley integer modulator being configured to receive the target valley number and generate a plurality of modulated integer valley numbers based on the target valley number, each of the modulated integer valley numbers corresponding to a respective modulated off time of the plurality of modulated off times.

16. The power converter of claim 15, further comprising: a valley detection circuit of the primary side controller, the valley detection circuit being configured to generate a valley detection signal for each of the one or more valleys; a valley counter of the fractional valley controller, the valley counter configured to receive each of the valley detection signals and increment the valley count upon receipt of each of the valley detection signals; as well as a valley count comparison block of the fractional valley controller, the valley count comparison block being configured to compare a most recent valley count with a most recent modulated valley number among the plurality of modulated integer valley numbers, and to issue a PWM reset signal upon determining that the most recent valley count exceeds the most recent modulated valley number, the PWM reset signal controlling the off time of the main switch.

17. The power converter of claim 15, further comprising: an audible noise filter of the fractional valley controller, the audible noise filter being configured to: i) generate a fractional mode enable signal if the switching frequency of the main switch is greater than a threshold switching frequency, and ii) generate a fractional mode disable signal if the switching frequency of the main switch is not greater than the threshold switching frequency.

18. The power converter of claim 17, further comprising: a first modulator of the valley integer modulator; as well as a second modulator of the valley integer modulator; in: The valley integer modulator is configured to generate the plurality of modulated integer valley quantities using the first modulator upon receiving the fractional mode disable signal; and The valley integer modulator is configured to generate the plurality of modulated integer valley quantities using the second modulator upon receiving the fractional mode enable signal.

19. The power converter of claim 18, wherein: The first modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having two fixed levels.

20. The power converter of claim 18, wherein: The second modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having a varying first level and a fixed second level.

21. The power converter of claim 18, wherein: The second modulator generates the plurality of modulated integer number of valleys using a sigma-delta modulator.

22. A method for power conversion, comprising: determining a target number of valleys of a resonant waveform at a drain node of a main switch of a power converter, the target number of valleys corresponding to a desired off time of the main switch and corresponding to a non-integer number of valleys; and An off time of the main switch is modulated between a plurality of modulated off times, each of the modulated off times of the main switch corresponding to an integer number of valleys, the plurality of modulated off times of the main switch having an average value corresponding to the desired off time.

23. The method of claim 22, wherein: Each modulated off time of the plurality of modulated off times corresponds to a corresponding modulated integer number of valleys of a plurality of modulated integer numbers of valleys; The plurality of modulated integer valley numbers comprises a first sequence of one or more concatenated first integer valley numbers followed by a second sequence of one or more concatenated second integer valley numbers; The length of the first sequence is different from the length of the second sequence; and The one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

24. The method of claim 22, further comprising: Measure the disconnection time of the main switch; determining a difference between the expected turn-off time of the main switch and a measured turn-off time of the main switch; and The target number of valleys is generated based on the determined difference.

25. The method of claim 22, further comprising: Measure the disconnection time of the main switch; determining a difference between the measured turn-off time of the main switch and the expected turn-off time of the main switch; determining a difference between the determined measured turn-off time of the main switch and the expected turn-off time of the main switch, generating a turn-off time adjustment signal; and The target valley number is generated based on the off time adjustment signal.

26. The method of claim 22, further comprising: In case the switching frequency of the main switch is greater than a threshold switching frequency, generating a fractional mode enable signal, and In case the switching frequency of the main switch is not greater than the threshold switching frequency, a fractional mode disable signal is generated.

27. The method of claim 26, further comprising: A plurality of modulated integer valley numbers are generated based on the target valley number.

28. The method of claim 27, further comprising: upon receiving the fractional mode disable signal, generating the plurality of modulated integer valley numbers using a first modulator; and Upon receiving the fractional mode enable signal, the plurality of modulated integer number of valleys are generated using a second modulator.

29. The method of claim 28, wherein: The first modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having two fixed levels.

30. The method of claim 28, wherein: The second modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having a varying first level and a fixed second level.

31. The method of claim 28, wherein: The second modulator generates the plurality of modulated integer number of valleys using a sigma-delta modulator.

32. A method for power conversion, comprising: receiving an input voltage at a transformer having a primary winding; The output voltage is provided to the load through the secondary winding of the transformer; controlling a current through the primary winding to provide an output voltage via a main switch coupled to the primary winding, a resonant waveform at a drain node of the main switch including one or more valleys during an off time of the main switch; determining a target number of valleys corresponding to a desired off time of the main switch, the target number of valleys corresponding to a non-integer number of valleys; and The off time of the main switch is modulated between a plurality of modulated off times, each of the modulated off times of the main switch corresponding to a respective integer number of valleys of the resonant waveform, the plurality of modulated off times of the main switch having an average value corresponding to the desired off time.

33. The method of claim 32, wherein: Each modulated off time of the plurality of modulated off times corresponds to a corresponding modulated integer number of valleys of a plurality of modulated integer numbers of valleys; The plurality of modulated integer valley numbers comprises a first sequence of one or more concatenated first integer valley numbers followed by a second sequence of one or more concatenated second integer valley numbers; The length of the first sequence is different from the length of the second sequence; and The one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

34. The method of claim 32, further comprising: measuring the disconnection time of the main switch; determining a difference between the measured disconnection time of the primary switch and the expected disconnection time; generating an off time adjustment signal based on the determined difference; as well as The target valley number is generated based on the off time adjustment signal.

35. The method of claim 32, further comprising: A plurality of modulated integer valley numbers are generated based on the target valley number, each of the modulated integer valley numbers corresponding to a respective modulated off time of the plurality of modulated off times.

36. The method of claim 35, further comprising: generating a valley detection signal for each of the one or more valleys; incrementing the valley count upon receipt of each of the valley detection signals; comparing the most recent valley count to a most recent modulated integer valley number in the plurality of modulated integer valley numbers, and A pulse width modulation reset signal is issued upon determining that the most recent valley count exceeds the most recently modulated integer valley number, the pulse width modulation reset signal controlling the off time of the main switch.

37. The method of claim 36, further comprising: generating an auxiliary voltage corresponding to the one or more valleys of the resonant waveform during the off-time of the main switch using an auxiliary winding of the transformer; and A valley detection signal is generated for each of the one or more valleys based on the auxiliary voltage.

38. The method of claim 35, further comprising: generating a fractional mode enable signal when a switching frequency of the main switch is greater than a threshold switching frequency; and In case the switching frequency of the main switch is not greater than the threshold switching frequency, a fractional mode disable signal is generated.

39. The method of claim 38, further comprising: upon receiving the fractional mode disable signal, generating the plurality of modulated integer valley numbers using a first modulator; and Upon receiving the fractional mode enable signal, the plurality of modulated integer number of valleys are generated using a second modulator.

40. The method of claim 39, wherein: The first modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having two fixed levels.

41. The method of claim 39, wherein: The second modulator generates the plurality of modulated integer valley numbers using a hysteresis controller having a varying first level and a fixed second level.

42. The method of claim 39, wherein: The second modulator generates the plurality of modulated integer number of valleys using a sigma-delta modulator.

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