Starting circuit and oscillation circuit

Abstract

The present application provides a startup circuit and an oscillation circuit, the startup circuit comprising: a control circuit for generating a first control signal; a generation circuit connected to the control circuit for generating a changing reference signal according to the first control signal; a comparison circuit, the inverting input end of the comparison circuit is connected to the generation circuit, the positive input end is connected to the comparison signal, the comparison circuit is used to compare the reference signal with the comparison signal, and then output a clock signal that changes according to a preset frequency. The present application realizes providing a clock signal that changes according to the crystal resonant frequency through a startup circuit, so as to accelerate the startup of a crystal oscillator circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a starting circuit and an oscillation circuit. Background Art

[0002] Crystal oscillator circuits have good stability and little variation with external influences such as temperature and voltage. They are widely used in various circuit systems and are usually used as precise clock sources. They can provide a calibration source for the RC (Resistor Capacitance) clock circuit inside the integrated circuit system. They can also be used as a reference source for the RF system. They are essential timing modules in Bluetooth, 5G and other systems.

[0003] The crystal oscillator circuit requires an off-chip crystal device, and its oscillation frequency is determined by the resonant frequency of the crystal. In a traditional crystal oscillator circuit, the crystal is driven by a larger inverter. When the circuit is working, the voltage amplitude across the crystal changes slowly and gradually increases. When the amplitude exceeds a certain range, the crystal oscillator circuit starts to oscillate and a clock is output. When the voltage amplitude across the crystal increases further, the frequency of the crystal oscillator circuit gradually stabilizes. The larger the amplitude on the crystal, the more conducive it is to reducing the phase noise of the output clock.

[0004] A common problem with crystal oscillator circuits is that the circuit starts oscillating too slowly. Taking a 32M crystal oscillator circuit as an example, it usually takes hundreds of us or even milliseconds for a traditional crystal oscillator circuit to start up and output a clock, which will undoubtedly increase the overall power consumption of the integrated circuit system. There are also some fast-starting crystal oscillator circuits, which usually accelerate the startup by increasing the drive of the crystal oscillator circuit output MOS tube, but this will greatly increase the overall power consumption. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a starting circuit and an oscillation circuit, so as to provide a clock signal that changes according to a preset frequency through the starting circuit, so as to accelerate the starting of the oscillation circuit.

[0006] A first aspect of an embodiment of the present application provides a startup circuit, comprising: a control circuit, for generating a first control signal; a generation circuit, connected to the control circuit, for generating a changing reference signal according to the first control signal; a comparison circuit, wherein the inverting input terminal of the comparison circuit is connected to the generation circuit, and the non-inverting input terminal is connected to the comparison signal, and the comparison circuit is used to compare the reference signal with the comparison signal and output a clock signal that changes according to a preset frequency.

[0007] In one embodiment, the generating circuit includes: a first resistor, connected in series with a first switch, the first switch is used to control the power-on state of the first resistor; a tuning capacitor, connected to the first resistor, the tuning capacitor is connected in parallel with a second switch, and the second switch is used to control the power-on state of the tuning capacitor.

[0008] In one embodiment, the control circuit is connected to the first switch, and the first control signal is used to control the opening or closing of the first switch.

[0009] In one embodiment, it further includes: a second inverter, the input end of the second inverter is connected to the control circuit, the output end of the second inverter is connected to the second switch, and the second control signal output by the second inverter is used to control the opening or closing of the second switch.

[0010] In one embodiment, when the first switch is closed and the second switch is open, the generating circuit composed of the first resistor and the tuning capacitor generates the changing reference signal.

[0011] In one embodiment, the first resistor is an adjustable first resistor; and the tuning capacitor is an adjustable capacitor.

[0012] In one embodiment, the device further includes: a third inverter, wherein an input end of the third inverter is connected to the generating circuit, and an output end of the third inverter is connected to the control circuit.

[0013] In one embodiment, the comparison circuit includes: a first comparator, the output end of the generating circuit is connected to the inverting input end of the first comparator, and the positive input end of the first comparator is connected to a first comparison signal; a second comparator, the output end of the generating circuit is connected to the inverting input end of the second comparator, and the positive input end of the second comparator is connected to a second comparison signal; when the first comparator and the second comparator work alternately, a clock signal that changes according to the preset frequency is generated.

[0014] In one embodiment, the comparison circuit further includes: a first signal source connected to the positive input terminal of the first comparator and configured to generate the first comparison signal.

[0015] In one embodiment, the comparison circuit further includes: a second signal source connected to the positive input terminal of the second comparator and configured to generate the second comparison signal.

[0016] In one embodiment, the comparison circuit also includes: a trigger, wherein the input end of the trigger is respectively connected to the output end of the first comparator and the output end of the second comparator; the output end of the trigger is connected to the first signal source, and the first clock signal output by the trigger is used to control the opening or closing of the first signal source.

[0017] In one embodiment, the first signal source includes: a first current source connected to the output end of the trigger; and a first capacitor, one end of which is connected to the first current source and the other end is grounded.

[0018] In one embodiment, the comparison circuit also includes: a first inverter, the input end of the first inverter is connected to the output end of the trigger, the output end of the first inverter is connected to the second signal source, and the second clock signal output by the first inverter is used to control the opening or closing of the second signal source.

[0019] In one embodiment, the second signal source includes: a second current source connected to the output terminal of the trigger; and a second capacitor, one end of which is connected to the second current source and the other end is grounded.

[0020] The second aspect of the embodiments of the present application provides an oscillation circuit, comprising: the starting circuit described in the first aspect of the embodiments of the present application and any one of the embodiments thereof; a crystal oscillator circuit, connected to the output end of the comparison circuit of the starting circuit, for receiving a clock signal that changes according to the preset frequency, wherein the preset frequency is the resonant frequency of the crystal oscillator circuit.

[0021] In one embodiment, the method further comprises: a third switch and a fourth switch, connected to the control circuit and the crystal oscillator circuit respectively, and the first control signal output by the control circuit is also used to control the opening or closing of the third switch and the fourth switch. The method is used to perform the method of the first aspect of the embodiment of the present application and any embodiment thereof to identify the flow direction information of the document information.

[0022] The starting circuit and oscillation circuit provided in the present application generate a first control signal through a control circuit, and the generating circuit generates a changing reference signal according to the first control signal. Subsequently, the comparing circuit compares the reference signal with the connected comparison signal and outputs a result. The output result of the comparing circuit changes according to a preset frequency to form a clock signal. The clock signal is input into the oscillation circuit, which can enable the oscillation circuit to start quickly and reduce the starting power consumption of the oscillation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of an oscillator circuit according to an embodiment of the present application;

[0025] Figure 2 This is a schematic diagram of the structure of a startup circuit according to an embodiment of the present application;

[0026] Figure 3 This is a schematic diagram of the structure of a startup circuit according to an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the timing changes of a reference signal and a first clock signal according to an embodiment of the present application;

[0028] Figure 5 A schematic diagram of frequency variation of a clock signal output by a startup circuit according to an embodiment of the present application;

[0029] Figure 6 A schematic diagram of signal waveforms of key nodes of an embodiment of the present application.

[0030] Reference numerals:

[0031] 1-oscillation circuit, 10-startup circuit, 11-startup module, 111-generation circuit, 112-comparison circuit, 12-control circuit, 20-crystal oscillator circuit, T0-inverter, R0-resistance, J0 crystal, S1-third switch, S2-fourth switch, R1-first resistor, K1-first switch, C-tuning capacitor, K2-second switch, Q1-first comparator, Q2-second comparator, 31-first signal source, A1-first current source, C1-first capacitor, 32-second signal source, A2-second current source, C2-second capacitor, Q3-trigger, T1-first inverter, T2-second inverter, T3-third inverter, first control signal startup_en, second control signal startup_enb, first clock signal clk0, second clock signal clk0_b, reference signal Vref, feedback signal flag, f0-resonance frequency of the crystal. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the present application, the terms "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0033] like Figure 1 As shown, this embodiment provides an oscillation circuit 1, including: a start-up circuit 10, a crystal oscillator circuit 20, a third switch S1 and a fourth switch S2, wherein:

[0034] The startup circuit 10 includes a startup module 11 and a control circuit 12. The control circuit 12 controls the startup module 11 to generate a first clock signal clk0 and a second clock signal clk0_b through a first control signal startup_en and a second control signal startup_enb. The startup module 11 generates a feedback signal flag which is input to the digital control circuit 12. The feedback signal flag can be used to turn the digital control circuit 12 on and off.

[0035] The crystal oscillator circuit 20 includes: a crystal J0, a resistor R0 and an inverter T0 connected in parallel, wherein the input ends of the crystal J0, the resistor R0 and the inverter T0 are connected to a node XI, and the output ends of the crystal J0, the resistor R0 and the inverter T0 are connected to a node XO. The crystal oscillator circuit 20 is connected to the startup circuit 10 through a third switch S1 and a fourth switch S2. In the fast startup phase of the crystal oscillator circuit 20, the third switch S1 and the fourth fast switch S2 are turned on, and the first clock signal clk0 and the second clock signal clk0_b of the startup module 11 are applied to both ends of the crystal J0, and the current amplitude in the crystal J0 is quickly increased, thereby accelerating the startup process of the crystal oscillator circuit 20.

[0036] In one embodiment, the crystal oscillator circuit 20 is connected to the output end of the comparison circuit 112 of the start-up circuit 10 and is used to receive a clock signal that changes according to a preset frequency. The preset frequency is the resonant frequency f0 of the crystal J0 in the crystal oscillator circuit 20 .

[0037] In one embodiment, the third switch S1 and the fourth switch S2 are respectively connected to the control circuit 12 , and the first control signal startup_en output by the control circuit 12 can also be used to control the opening or closing of the third switch S1 and the fourth switch S2 .

[0038] like Figure 2 As shown, this embodiment provides a startup circuit 10, which can be used as follows Figure 1 In the oscillating circuit 1 shown, the crystal oscillator circuit 20 in the oscillating circuit 1 is started up quickly. The starting circuit 10 comprises: a control circuit 12 and a starting module 11 , wherein the starting module 11 may comprise a generating circuit 111 and a comparing circuit 112 .

[0039] The control circuit 12 can be implemented by a digital controller and is used to generate a first control signal startup_en. The generation circuit 111 is connected to the control circuit 12 and is used to generate a changing reference signal vref according to the first control signal startup_en. The inverting input terminal of the comparison circuit 112 is connected to the generation circuit 111, and the non-inverting input terminal is connected to the comparison signal. The comparison circuit 112 is used to compare the reference signal vref with the comparison signal and output a clock signal that changes according to a preset frequency.

[0040] In one embodiment, the startup module 11 may be a common clock circuit, a ring oscillator clock circuit composed of an inverter chain, or a commonly used RC (resistance-capacitance) charging and discharging clock circuit. These clock circuits can work quickly to output clock signals.

[0041] In one embodiment, if Figure 3 As shown, this embodiment provides a startup circuit 10, which can be used as follows Figure 1 In the oscillation circuit 1 shown, the crystal oscillator circuit 20 in the oscillation circuit 1 is accelerated to start. Here, the RC clock circuit is used as an example to explain in detail the starting module 11. The generating circuit 111 includes: a first resistor R1, a first switch K1, a tuning capacitor C, and a second switch K2, wherein the first resistor R1 is connected in series with the first switch K1, and the first switch K1 is used to control the power-on state of the first resistor R1. The tuning capacitor C is connected to the first resistor R1, one end of the second switch K2 is connected to the connection point between the first resistor R1 and the tuning capacitor C, and the other end of the second switch K2 is grounded, and the second switch K2 is used to control the power-on state of the tuning capacitor C.

[0042] In one embodiment, the control circuit 12 is connected to the first switch K1 , and the first control signal startup_en generated by the control circuit 12 can be used to control the opening or closing of the first switch K1 . For example, when the first control signal startup_en is at a high level, the first switch K1 is controlled to be closed.

[0043] In one embodiment, it also includes: a second inverter T2, the input end of the second inverter T2 is connected to the control circuit 12, the output end of the second inverter T2 is connected to the second switch K2, after the first control signal startup_en is input to the second inverter T2, the second inverter T2 can output the second control signal startup_enb, and the second control signal startup_enb can be used to control the opening or closing of the second switch K2.

[0044] In one embodiment, when the first control signal startup_en is at a high level, the first switch K1 is controlled to be closed, and at this time, the second control signal startup_enb is at a low level, and the second switch K2 can be controlled to be opened, so that the generating circuit 111 starts to work and generates a reference signal vref at the connection point between the first resistor R1 and the tuning capacitor C. It can be seen that the reference signal vref is a variable reference level.

[0045] In one embodiment, the comparison circuit 112 includes: two comparators, wherein the output end of the generation circuit 111 is connected to the inverting input end of the first comparator Q1, and the positive input end of the first comparator Q1 is connected to the first comparison signal. The output end of the generation circuit 111 is connected to the inverting input end of the second comparator Q2, and the positive input end of the second comparator Q2 is connected to the second comparison signal. When the first comparator Q1 and the second comparator Q2 work alternately, a clock signal that changes according to a preset frequency is generated.

[0046] In one embodiment, the comparison circuit 112 further includes: a first signal source 31 connected to the positive input terminal of the first comparator Q1 and configured to generate a first comparison signal.

[0047] In one embodiment, the first signal source 31 may be composed of a first current source A1 and a first capacitor C1, wherein the first current source A1 is connected to the positive input terminal of the first comparator Q1, one end of the first capacitor C1 is connected to the connection point between the first current source A1 and the first comparator Q1, and the other end is grounded. The first current source A1 may generate a first comparison signal.

[0048] In one embodiment, the comparison circuit 112 further includes: a second signal source 32 connected to the positive input terminal of the second comparator Q2 for generating a second comparison signal.

[0049] In one embodiment, the second signal source 32 is composed of a second current source A2 and a second capacitor C2, wherein the second current source A2 is connected to the positive input terminal of the second comparator Q2, one end of the second capacitor C2 is connected to the second current source A2, and the other end is grounded. The second current source A2 can generate a second comparison signal.

[0050] In one embodiment, the comparison circuit 112 further includes: a trigger Q3, wherein the input end of the trigger Q3 is respectively connected to the output end of the first comparator Q1 and the output end of the second comparator Q2. The trigger Q3 may be an SRQ trigger Q3, wherein the output end of the first comparator Q1 may be connected to the input end S of the trigger Q3, and the output end of the second comparator Q2 may be connected to the input end R of the trigger Q3.

[0051] In one embodiment, the output terminal Q of the trigger Q3 is connected to the first signal source 31, and the first clock signal clk0 output by the trigger Q3 can be used to control the opening or closing of the first signal source 31. For example, when the first clock signal clk0 is at a high level, the first current source A1 is controlled to be closed, so that the first signal source 31 generates a first comparison signal.

[0052] In one embodiment, the comparison circuit 112 further includes: a first inverter T1, the input end of the first inverter T1 is connected to the output end Q of the trigger Q3, the first inverter T1 outputs the second clock signal clk0_b after the first clock signal clk0 output by the trigger Q3 passes through the first inverter T1, the output end of the first inverter T1 is connected to the second signal source 32, and the second clock signal clk0_b is used to control the opening or closing of the second signal source 32. For example, when the second clock signal clk0_b is at a high level, the second signal source 32 is controlled to be closed, so that the second signal source 32 generates the second reference signal vref. In this way, the first comparator Q1 and the second comparator Q2 can work alternately.

[0053] In one embodiment, if Figure 4 As shown, it is a timing diagram of the reference signal vref and the first clock signal clk0. When the first switch K1 is closed and the second switch K2 is opened, the generating circuit 111 generates the reference signal vref. When the level of the reference signal vref is low, the frequency of the output first clock signal clk0 is higher. When the reference signal vref gradually rises, the frequency of the output first clock signal clk0 gradually becomes lower.

[0054] In one embodiment, in the fast startup phase of the crystal oscillator circuit 20, the first clock signal clk0 is connected to the XI terminal of the crystal J0, and the second clock signal clk0_b is connected to the XO terminal of the crystal J0, that is, there is a clock frequency with a frequency change at both ends of the crystal J0. When the changed clock frequency becomes the resonant frequency f0 of the crystal J0, the amplitude of the current ixo on the crystal J0 changes suddenly, which will greatly improve the start-up time of the crystal oscillator. In order to ensure that the clock frequency of the startup circuit 10 chip can sweep the resonant frequency f0 of the crystal J0 under various conditions, it is necessary to reasonably select the maximum value fmax and the minimum value fmin of the clock frequency output by the startup circuit 10. The maximum value fmax can be twice the resonant frequency f0 of the crystal J0, and the minimum value fmin can be 0.1*f0.

[0055] In one embodiment, the first resistor R1 is an adjustable first resistor R1. The tuning capacitor C is an adjustable capacitor. Figure 5As shown, by adjusting the values ​​of the first resistor R1 and the tuning capacitor C, the slope of the frequency change of the first clock signal clk0 in the fast startup phase can be changed. The smaller the slope, the greater the amplitude of the jump of the current ixo at the resonant frequency f0. Under the conditions of a fixed maximum value fmax and a minimum value fmin, the smaller the slope of the frequency change of the first clock signal clk0, the slower the entire scanning process. In practical applications, it can be selected according to the actual situation of the circuit.

[0056] In one embodiment, it further includes: a third inverter T3, the input end of the third inverter T3 is connected to the connection point between the first resistor R1 and the tuning capacitor C in the generating circuit 111, and the output end of the third inverter T3 is connected to the control circuit 12. After the reference signal vref generated by the generating circuit 111 passes through the third inverter T3, the third inverter T3 outputs a feedback signal flag, and the feedback signal flag can make the first control signal startup_en output by the control circuit 12 become a low level. The third inverter T3 is a hysteresis inverter.

[0057] In one embodiment, if Figure 6 As shown, it provides Figure 3 The first control signal startup_en, the reference signal vref, the feedback signal flag, the frequency of the first clock signal clk0 at the node XO and the signal waveform change timing diagram of the node XI. After the first control signal startup_en becomes high, the reference signal vref node of the generating circuit 111 starts to charge, and its level gradually increases, and the frequency of the output first clock signal clk0 changes from high to low with the change of the reference signal vref. In the stage where the first control signal startup_en is at a high level, the first clock signal clk0 and the second clock signal clk0_b are directly connected to both ends of the crystal J0, so the level of the crystal J0 at the XI end is the first clock signal clk0 when the first control signal startup_en=1.

[0058] In one embodiment, during the operation of the startup circuit 10, the reference signal vref can be sent to the third inverter T3 to obtain a feedback signal flag, and the flip-up threshold of the third inverter T3 is lower than the flip-down threshold. In the initial stage of the rapid startup, the reference signal is at a high level. When the reference signal vref gradually increases and exceeds the flip-down threshold of the third inverter T3, the feedback signal flag becomes a low level. Subsequently, the feedback signal flag is sent to the control circuit 12, and after the reference signal vref becomes a low level, the control circuit 12 changes the first control signal startup_en to a low level after a delay period of time, indicating that the rapid startup process has been completed. Subsequently, the crystal J0 is driven by the crystal oscillator circuit 20 to work, and the signal on the node XI oscillates near the DC operating point and gradually increases the amplitude. Since the current ixo on the crystal J0 has a sudden change in the rapid startup stage, after the rapid startup is completed, the voltage amplitude on the crystal J0 will be larger than when the ordinary crystal oscillator circuit 20 is started. Taking the 32M circuit as an example, after adopting the startup circuit 10 of this embodiment, the start-up time of the crystal oscillator circuit 20 can be shortened from 1 ms to 200 us.

[0059] In one embodiment, after the startup is completed, the startup circuit 10 can be turned off, and the startup circuit 10 will no longer generate power consumption. Usually, the power consumption of the startup circuit 10 is tens of uA, which is negligible compared with the hundreds of uA of the crystal oscillator circuit 20. However, the startup circuit 10 of this embodiment can shorten the crystal oscillator stabilization time, reduce the overall power consumption, and improve the circuit response speed.

[0060] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A starting circuit, characterized in that: include: A control circuit, configured to generate a first control signal; a generating circuit connected to the control circuit and used to generate a changing reference signal according to the first control signal, the generating circuit comprising: a first resistor connected in series with a first switch, the first switch being used to control the power-on state of the first resistor; a tuning capacitor connected to the first resistor, the tuning capacitor being connected in parallel with a second switch, the second switch being used to control the power-on state of the tuning capacitor; the control circuit being connected to the first switch, the first control signal being used to control the opening or closing of the first switch; a second inverter, the input end of the second inverter being connected to the control circuit, the output end of the second inverter being connected to the second switch, the second control signal output by the second inverter being used to control the opening or closing of the second switch; when the first switch is closed and the second switch is open, the generating circuit composed of the first resistor and the tuning capacitor generates the changing reference signal; A comparison circuit, wherein the inverting input terminal of the comparison circuit is connected to the generating circuit, and the non-inverting input terminal is connected to the comparison signal. The comparison circuit is used to compare the reference signal with the comparison signal, and then output a clock signal that changes according to a preset frequency. The clock signal is input into an oscillation circuit to quickly start the oscillation circuit.

2. The circuit according to claim 1, characterized in that Also includes: A third inverter, wherein an input end of the third inverter is connected to the generating circuit, and an output end of the third inverter is connected to the control circuit.

3. The circuit according to claim 1, characterized in that The comparison circuit comprises: A first comparator, wherein the output end of the generating circuit is connected to the inverting input end of the first comparator, and the positive input end of the first comparator is connected to the first comparison signal; A second comparator, wherein the output end of the generating circuit is connected to the inverting input end of the second comparator, and the positive input end of the second comparator is connected to the second comparison signal; When the first comparator and the second comparator work alternately, a clock signal that changes according to the preset frequency is generated.

4. The circuit according to claim 3, characterized in that The comparison circuit further comprises: A trigger, wherein the input end of the trigger is respectively connected to the output end of the first comparator and the output end of the second comparator.

5. The circuit according to claim 4, characterized in that The comparison circuit further comprises: a first signal source connected to the positive input terminal of the first comparator and used to generate the first comparison signal; an output terminal of the trigger is connected to the first signal source, and a first clock signal output by the trigger is used to control the opening or closing of the first signal source; The first signal source comprises: A first current source connected to the output terminal of the trigger; A first capacitor, one end of which is connected to the first current source, and the other end of which is grounded; A second signal source, connected to the positive input terminal of the second comparator, for generating the second comparison signal; The second signal source comprises: A second current source connected to the output terminal of the trigger; The second capacitor has one end connected to the second current source and the other end grounded.

6. The circuit according to claim 5, characterized in that The comparison circuit further comprises: A first inverter, wherein an input end of the first inverter is connected to an output end of the trigger, an output end of the first inverter is connected to the second signal source, and a second clock signal output by the first inverter is used to control the opening or closing of the second signal source.

7. An oscillator circuit, characterized in that: include: The starting circuit according to any one of claims 1 to 6; A crystal oscillator circuit is connected to the output end of the comparison circuit of the startup circuit and is used to receive a clock signal that changes according to the preset frequency, where the preset frequency is the resonant frequency of the crystal oscillator circuit.

8. The circuit according to claim 7, characterized in that Also includes: The third switch and the fourth switch are connected to the control circuit and the crystal oscillator circuit respectively, and the first control signal output by the control circuit is also used to control the opening or closing of the third switch and the fourth switch.

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