Integrated scheme of chamferless through hole

Abstract

Methods and apparatuses for processing semiconductor substrates to form unchipped vias in an integrated scheme are provided. Methods include diverging etching a dielectric by depositing a conformal removable sealant layer having a property of selective removal relative to the dielectric material without damaging the dielectric material. Some methods include forming a conformal sealant layer that is ashable. Methods also include forming a hard mask comprising a group IV metal and removing the conformal removable sealant layer and the hard mask using the same etching chemistry in one operation.

Description

[0001] Incorporated by Reference

[0002] The application table, along with the specification, is hereby incorporated by reference as part of this application. Each of the applications that this application claims benefit of or priority from, as identified in the concurrently filed application table, is hereby incorporated by reference in its entirety and for all purposes. BACKGROUND

[0003] Fabrication of semiconductor devices involves patterning schemes for forming various structures of integrated circuits. As devices shrink, challenges are presented for forming reliable structures.

[0004] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently designated inventor(s), to the extent the work is described in this background section, as well as aspects of the description that can not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the application. SUMMARY

[0005] Provided herein are methods and apparatuses for processing semiconductor substrates.

[0006] Any suitable combination of one or more layers of any Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide or combination thereof used as a conformal removable sealant layer can be used in combination with any one or more layers of any Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide or combination thereof as a hard mask.

[0007] One example includes an integration scheme in which etch bifurcation of an ultra- low-k (ULK) dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between a trench level and a via level of the ULK dielectric material.

[0008] One example includes an integration scheme in which etch bifurcation of an ultra- low-k (ULK) dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between a trench level and a via level of the ULK dielectric material.

[0009] One example includes an integration scheme in which etch bifurcation of an ultra- low-k (ULK) dielectric material is enabled by depositing a conformal removable tin nitride sealant layer (deposited under anaerobic conditions) between a trench level and a via level of the ULK dielectric material.

[0010] One example includes an integration scheme in which etch bifurcation of an ultra- low-k (ULK) dielectric material is enabled by depositing a conformal removable sealant layer comprising tin nitride and underlying tin oxide between a trench level and a via level of the ULK dielectric material.

[0011] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0012] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0013] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0014] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0015] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0016] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0017] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0018] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0019] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0020] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0021] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0022] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0023] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0024] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0025] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0026] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin nitride-containing and underlying tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0027] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between a trench extent and a via extent of the ULK dielectric material.

[0028] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between a trench extent and a via extent of the ULK dielectric material.

[0029] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0030] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0031] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0032] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0033] One example includes an integration scheme for a substrate having a patterned tin oxide hardmask, wherein etch divergence of a ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer (deposited under anaerobic conditions) between a trench extent and a via extent of the ULK dielectric material.

[0034] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer (deposited under anaerobic conditions) between the trench and via extent of the ULK dielectric material.

[0035] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0036] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer (deposited under anaerobic conditions) between the trench and via extent of the ULK dielectric material.

[0037] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0038] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0039] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer (deposited under anaerobic conditions) between the trench and via extent of the ULK dielectric material.

[0040] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0041] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin nitride sealant layer (deposited under anaerobic conditions) between the trench and via extent of the ULK dielectric material.

[0042] One example includes an integration scheme for substrates with patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0043] One example includes an integration scheme for substrates with patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0044] One example includes an integration scheme for substrates with patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0045] One example includes an integration scheme for substrates with patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0046] One example includes an integration scheme for substrates with patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable tin oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0047] One example includes an integration scheme, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0048] One example includes an integration scheme, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0049] One example includes an integration scheme, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable sealant layer comprising tin nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0050] One example includes an integration scheme, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable sealant layer comprising lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0051] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0052] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0053] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0054] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0055] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0056] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0057] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0058] One example includes an integration scheme for substrates having patterned Group IV metal-containing oxide or Group IV metal-containing nitride or sulfide hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0059] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing tin nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0060] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0061] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0062] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0063] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0064] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0065] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0066] One example includes an integration scheme for substrates having patterned tin-containing oxide or tin-containing nitride hardmasks, where etch divergence of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying tin oxide between the trench and via extent of the ULK dielectric material.

[0067] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0068] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0069] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0070] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0071] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0072] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0073] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0074] One example includes an integration scheme for substrates with patterned tin nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead oxide sealant layer between the trench and via extent of the ULK dielectric material.

[0075] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0076] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0077] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0078] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0079] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0080] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0081] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0082] One example includes an integration scheme for substrates with patterned lead-containing oxide or lead-containing nitride hardmasks, where etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable encapsulant layer containing lead nitride and underlying lead oxide between the trench and via extent of the ULK dielectric material.

[0083] One example includes an integration scheme for substrates having patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0084] One example includes an integration scheme for substrates having patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0085] One example includes an integration scheme for substrates having patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0086] One example includes an integration scheme for substrates having patterned lead nitride hardmasks, wherein etch bifurcation of ULK dielectric material is enabled by depositing a conformal removable lead nitride sealant layer between the trench and via extent of the ULK dielectric material.

[0087] These and other aspects are further described below with reference to the figures. BRIEF DESCRIPTION OF DRAWINGS

[0088] Figure 1A is a schematic diagram of an exemplary substrate having material layers.

[0089] Figure 1B is a schematic diagram of an exemplary substrate having material layers after via etch.

[0090] Figure 2 , 3 and 4 are process flow diagrams of operations performed in accordance with certain disclosed embodiments.

[0091] Figures 5A-5G is a schematic diagram of an exemplary substrate in various stages of processing in accordance with certain disclosed embodiments.

[0092] Figures 6A-6G is a schematic diagram of an exemplary substrate in various stages of processing in accordance with certain disclosed embodiments.

[0093] Figure 7 is a schematic diagram of an exemplary processing station for performing disclosed embodiments.

[0094] Figure 8 is a schematic diagram of an exemplary processing tool for performing disclosed embodiments. DETAILED DESCRIPTION

[0095] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented implementations. The disclosed implementations can be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the disclosed implementations. While the disclosed implementations will be described in conjunction with the specific implementations, it will be understood that it is not intended to limit the disclosed implementations.

[0096] Manufacturing of semiconductor devices involves patterning schemes to achieve desired structures. For example, in complementary metal-oxide semiconductor (CMOS) manufacturing for constructing integrated circuits, one technique includes performing trench first metal hard mask patterning to form self-aligned vias for 20 nm to 22 nm nodes. Some processes can result in the formation of a chamfer in the via-to-trench bottom junction. This chamfer can impact the scaling of dimensions on reliability and chain yield. For example, a chamfer formed by etching can reduce the minimum insulator between two adjacent vias, which can result in the device being more likely to short, resulting in leakage, reduced reliability, and causing suppression of via chain yield.

[0097] Provided herein are methods of processing semiconductor substrates to form vias that are substantially free of chamfers, with zero to minimal chamfers. Embodiments include various integration schemes for depositing removable material on ultra-low-k dielectric material during formation of via and trench structures, enabling removal of the deposited material without damaging the ultra-low-k dielectric material. Examples include forming a liner layer after partially etching the ultra-low-k dielectric material, to form the trench first and then the via.

[0098] For example, one integration scheme can start with a stack having an ultra-low-k (“ULK”) dielectric material, with a trench extent and underlying via extent, a liner layer (e.g., a layer deposited from tetraethyl orthosilicate (“TEOS”)) over and adjacent to the ULK to protect the ULK from the surrounding environment, and a metal hard mask (e.g., titanium nitride) on top of the liner layer. The ULK dielectric material is defined as a dielectric material with a k value less than 2.5. The metal hard mask can be etched to form a pattern. The ULK dielectric material can be etched to form a trench, and then a via can be formed in the trench. Figure 1A An example stack is provided in a cross-sectional side view, showing a dielectric material 102 with a metal line 106, a first liner layer 104, a ULK layer 108, a second liner layer 110 (e.g., TEOS), and a patterned metal hard mask 112. Subsequently, spin-on carbon can be formed on the substrate, then patterned to form a mask for forming a via. The via is etched partially into the ULK using the spin-on carbon mask, to form a partial via, and the spin-on carbon mask is removed after partially etching the via. After the spin-on carbon mask is removed, the trench is then etched. The via is then formed in the trench. Figure 1BAn exemplary cross-sectional side view of a substrate after etching a trench is provided in FIG. 1C, showing an etched hard mask 112', an etched liner layer 110', an etched ULK 108', and an open liner layer 104'. The etching operation can result in via-trench interface corrosion and / or sagging, as shown at corner 114, resulting in a sloped sidewall 116. After etching the via and trench, metallization is performed, filling the via and trench. As devices shrink and metal lines are formed closer and closer together, the chamfer formed at corner 114 can cause reliability problems, as the distance between the metal in metal line 106b and the metal in via 118 can be less than the distance between metal lines 106b and 106a at the same level. Device tolerances can assume the latter distance to be the minimum distance, causing reliability problems when it is not.

[0099] Provided herein are methods of forming vias with vertical sidewalls. In some embodiments, the method includes forming a sacrificial layer during a bifurcation method to form vias and trenches in a patterning scheme. In various embodiments, after depositing a sacrificial layer on a ULK dielectric material, a patterned mask can be formed on the sacrificial layer. The patterned mask is then used to etch the ULK dielectric material. The sacrificial layer can then act as a protective sealant to prevent damage to the underlying ULK dielectric material during etching of the ULK dielectric material. For example, if the patterned mask is formed directly on the ULK dielectric material and a sacrificial layer is not used, the etching process of the ULK dielectric material can erode the corners of the ULK dielectric material, resulting in a chamfer. The sacrificial layer protects the corners of the ULK dielectric material to maintain the profile of the pattern. In some embodiments, the sacrificial layer acts as a protective sealant to prevent the mask material from seeping into the underlying ULK dielectric material. In some embodiments, the sacrificial layer has properties that can be removed during removal of the mask material. In some embodiments, a single removal operation can be performed to remove the mask material and the sacrificial layer. The disclosed embodiments also include using a sacrificial layer material as a hard mask prior to etching a first amount of ULK dielectric material. This can facilitate maintaining the aspect ratio of the etched features in an integration scheme. In some embodiments, the hard mask and the sacrificial layer are the same material, enabling both to be etched in operations after etching the ULK dielectric material.

[0100] In some embodiments, a single chemical process can be used to remove the sacrificial layer and the mask, which can be performed in a single operation. In some embodiments, two different chemical processes performed in two separate operations can be used to remove the sacrificial layer and the mask. In some embodiments, since the sacrificial layer can protect the ULK dielectric material, the substrate can be exposed to a more aggressive chemical process that can damage the ULK dielectric to remove the mask material, followed by a milder etching operation that selectively etches the sacrificial layer relative to the ULK dielectric layer without damaging the ULK dielectric layer. In some embodiments, the method further includes forming the via by using a metal hard mask having the same removability as the sacrificial layer to reduce the number of processing steps. Examples of the sacrificial layer material include metal oxides having metals of Group IV of the Periodic Table and metal nitrides having metals of Group IV of the Periodic Table. For example, the sacrificial layer material can be tin oxide (e.g., tin oxide or tin (II) oxide (SnO), and tin dioxide or tin (IV) oxide (Sn02)), tin nitride (e.g., tin nitride or tin (II) nitride (Sn3N2) and tritin nitride or tin (IV) nitride (Sn3N4)), lead oxide (e.g., lead (II) oxide (PbO) and lead (IV) oxide (Pb20)) or lead nitride (e.g., lead (II) nitride (Pb3N2) and lead (IV) nitride (Pb2N)). Additionally, in some embodiments, the sacrificial layer can include two or more layers, each layer can have a different composition or the same composition.

[0101] Figure 2 A process flow diagram of operations performed in accordance with certain disclosed embodiments is provided. In operation 202, a substrate having a first dielectric material layer and a trench is provided. In some embodiments, the substrate is provided to a processing chamber. The processing chamber includes a pedestal or substrate support on which the substrate is placed. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more layers of material (e.g., a dielectric material, a conductive material, or a semiconductive material) deposited thereon. The substrate can have multiple layers, such as a barrier layer or an adhesion layer. Non-limiting examples of layers include dielectric layers and conductive layers, such as a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a metal oxide layer, a metal nitride layer, a metal carbide layer, and a metal layer.

[0102] The substrate includes a first dielectric material layer and a trench. In various embodiments, the first dielectric material layer can be formed by a gap fill deposition process, chemical vapor deposition ("CVD"), plasma enhanced CVD ("PECVD"), atomic layer deposition ("ALD"), plasma enhanced ALD ("PEALD"), or any other suitable deposition technique. The first dielectric material layer has a thickness between 50 nm and 100 nm. The patterned hardmask has a thickness between 10 nm and 50 nm. The patterned hardmask can be defined by a photolithography technique. In some embodiments, the patterned hardmask is formed by deposition via physical vapor deposition ("PVD").

[0103] The trench is characterized by one or more of a narrow portion and / or a re-entrant opening, a constriction within the feature. The trench is formed in the first dielectric material layer, but can not penetrate the entire thickness of the first dielectric material layer. The trench can be formed in the first dielectric material layer such that the trench depth, measured from the trench opening to the trench bottom, is at least about 25% of the first layer thickness. The trench can be formed by etching between about 50% to about 75% of the thickness of the first dielectric material layer. The trench can have an aspect ratio of at least about 1 : 1, at least about 2: 1, at least about 4: 1, at least about 6: 1, at least about 10: 1, or higher. The trench has a dimension, e.g., an opening diameter or line width, near the opening between about 10 nm and 500 nm, e.g., between about 25 nm and about 300 nm. The trench can also be referred to as a feature. The terms "trench" and "feature" can be used interchangeably in this disclosure and will be understood to include any hole, via, or recessed area of the substrate.

[0104] In operation 206, a removable sealant layer is conformally deposited on the dielectric material. The removable sealant layer can be conformal to the trench topography. The removable sealant layer can be deposited using a technique that minimizes damage to the underlying dielectric, and can be deposited to within about 5% of the trench critical dimension. In some embodiments, the removable sealant layer prevents lithographic material used to pattern the via from entering the trench dielectric. In various embodiments, the removable sealant layer provides sufficient etch selectivity, e.g., greater than about 10: 1 relative to other materials on the surface, to favor the lithographic material above it during patterning, such that the lithographic material can be over-etched when it lands on the removable sealant layer. In various embodiments, the removable sealant layer can be removed using a reducing chemistry, which can be any one or more of the following: a mixture of nitrogen and hydrogen gas, a mixture of helium and hydrogen gas, methane gas, ethylene gas, or an organic acid.

[0105] In some embodiments, the removable sealant layer can be ashable. Ashable is defined as removable by dry plasma isotropic removal. In various embodiments, the removable sealant layer is deposited directly on the exposed trench surface, which can be a ULK dielectric material. The removable sealant layer can be conformally deposited. Conformality of the film can be gauged by step coverage. Step coverage can be calculated by comparing the average thickness of the film deposited on the bottom, sidewall, or top of the trench to the average thickness of the film deposited on the bottom, sidewall, or top of the trench.

[0106] One example of step coverage can be calculated by dividing the average thickness of the film deposited on the sidewall by the average thickness of the film deposited at the top of the feature and multiplying by 100 to obtain a percentage. In certain disclosed embodiments, the step coverage of the removable sealant layer deposited on the first dielectric material layer can be between about 90% and about 100%, or at least about 90%, or between about 95% and about 100%.

[0107] The removable sealant layer has various properties. One property is that it can act as a barrier layer, thereby "freezing" the profile of the structure underneath, preventing damage to the underlying structure. In various embodiments, the removable sealant layer is a hyphenation film, defined as a layer used as a barrier to prevent photolithography materials and reagents used in the application, patterning, and removal of the material from entering into the trench dielectric, thereby protecting the trench dielectric. The removable sealant layer prevents the penetration of the masking material (e.g., spin-on carbon) into the underlying ULK film before another masking layer material (e.g., spin-on carbon) is formed on the ULK dielectric material and thus in the vicinity of the ULK dielectric material, and can be essentially a "sealant" defined as having the property of preventing or eliminating diffusion from the material on one side of the layer to the other. Another property is that it is a removable film. The removable sealant layer has the property that it can be removed using chemicals that will not damage the underlying ULK material. It also allows for the use of different etching chemicals to remove the overlying masking material, thereby preventing damage to the underlying ULK in the process of removing, for example, the spin-on carbon masking material, as the removal of the removable sealant layer can be performed using a separate chemical process after the spin-on carbon is removed. In some embodiments, the removable sealant layer is considered a sacrificial film.

[0108] The removable sealant layer is an oxide or nitride film containing Group IV. For example, in some embodiments, the removable sealant layer is a tin oxide containing film. In some embodiments, the removable sealant layer is a tin nitride containing film. In some embodiments, the removable sealant layer is a lead oxide containing film. In some embodiments, the removable sealant layer is a lead nitride containing film. For example, the removable sealant layer can be tin oxide or tin(II) oxide (SnO), tin dioxide or tin(IV) oxide (Sn02), tin nitride or tin(II) nitride (Sn3N2), trititanium nitride or tin(IV) nitride (Sn3N4), lead(II) oxide (PbO), lead(IV) oxide (Pb20), lead(II) nitride (Pb3N2), or lead(IV) nitride (Pb2N). It should be understood that in some embodiments, the film is not necessarily a stoichiometric film. For example, in some cases, the film is sub-stoichiometric. For example, the tin oxide containing film can be tin oxide or tin dioxide, which can include an atomic ratio of tin to oxygen of about 0.45 to about 1.05. In some embodiments, the removable film is tin(II) oxide having the chemical structure SnO. In some embodiments, the removable film is tin(IV) oxide having the chemical structure Sn02.

[0109] In various embodiments, the removable tin nitride sealant layer is deposited under anaerobic conditions. Anaerobic is defined as oxygen free. In various embodiments, the removable tin nitride or tin sulfide sealant layer is deposited in an oxygen free environment. In various embodiments, the removable tin nitride sealant layer is deposited in an oxygen free environment. For example, in some embodiments, the tin nitride is deposited by PECVD.

[0110] In some embodiments, where the removable sealant layer is deposited on an environmentally sensitive layer (e.g., a ULK dielectric layer), the removable sealant layer can include an oxide underlayer having a Group IV metal and a nitride or sulfide containing Group IV metal deposited on the oxide underlayer containing Group IV metal.

[0111] The removable sealant layer can be deposited by CVD, PECVD, ALD, PEALD, or any other suitable deposition technique. The removable sealant layer can be deposited to a thickness of between about 2.5 nm and about 5 nm. In various embodiments, the removable sealant layer has a thickness of about 5 nm. In some embodiments, the removable sealant layer is deposited to a thickness of less than about 5 nm. The removable sealant layer can be deposited at a substrate temperature of between about 50 °C and about 400 °C. In some embodiments, the substrate is processed in a process chamber.

[0112] In some embodiments, the removable sealant layer is a tin oxide film, such as tin oxide. The removable tin oxide sealant layer is deposited by any suitable method, such as by CVD (including PECVD), ALD (including PEALD), sputtering, or the like. In some embodiments, the removable tin oxide sealant layer is conformally deposited to a thickness of between about 5 nm and about 30 nm, such as between about 10 nm and about 20 nm. One of the suitable deposition methods for a conformal tin oxide film is ALD. Either thermal ALD or PEALD can be used. In a thermal ALD method, the substrate is provided to an ALD processing chamber and is sequentially exposed to a tin-containing precursor and an oxygen-containing reactant, where the tin-containing precursor and the oxygen-containing reactant are reacted on the surface of the substrate to form tin oxide. After exposing the substrate to the tin-containing precursor, and before allowing the oxygen-containing reactant to enter the processing chamber, the ALD processing chamber can be purged with an inert gas to prevent reaction in the bulk portion of the processing chamber. Further, after treating the substrate with the oxygen-containing reactant, the ALD processing chamber can be purged with an inert gas. The sequential exposure is repeated for several cycles, each cycle having a tin-containing precursor exposure and an oxidizer exposure, for example, between about 10 and 100 cycles can be performed until a tin oxide layer having a desired thickness is deposited. Examples of suitable tin-containing precursors include halogenated tin-containing precursors, such as tin (II) chloride (SnCl4) and tin (II) bromide (SnBr4), as well as non-halogenated tin-containing precursors, such as organotin compounds, including alkyl-substituted stannyl amides, and the like. Specific examples of alkyl-substituted stannyl amides suitable for use in ALD include tetrakis(dimethylamino)tin, tetrakis(ethylmethylamino)tin, N 2 ,N 3- di-t-butyl butane-2,3-diamino-tin(II) and (1,3-bis(1,1-dimethylethyl)-4,5-dimethyl- (4R,5R)-1,3,2-diazastannolidin-2-ylidine). Oxygen-containing reactants include, but are not limited to, oxygen (O2), ozone (O3), water (H2O), hydrogen peroxide (H2O2), and nitric oxide (NO). Mixtures of oxygen-containing reactants can also be used, and the deposition conditions will vary depending on the choice of ALD reactants, with more reactive precursors generally reacting at lower temperatures than less reactive precursors. The process can be carried out at temperatures between about 20 °C and about 500 °C and at pressures lower than atmospheric pressure. The temperature and pressure can be chosen such that the reactants remain in gaseous form in the processing chamber to avoid condensation. Each reactant is provided to the processing chamber in gaseous form, mixed with a carrier gas such as argon, helium, or nitrogen (N2), individually. The flow rates of these mixtures will depend on the size of the processing chamber and, in some embodiments, are between about 10 seem and about 10,000 seem.

[0113] A specific example of thermal ALD process conditions suitable for depositing the conformal, removable, tin oxide sealant layers provided herein is described in Li et al., "Tin Oxide with Controlled Morphology and Crystallinity by Atomic Layer Deposition onto Graphene Nanosheets for Enhanced Lithium Storage," Advanced Functional Materials, 2012, 22, 8, 1647-1654, the entire contents of which are incorporated herein by reference. The process includes exposing the substrate to SnCl4 (tin-containing precursor) and deionized water (oxygen-containing reactant) at temperatures of 200 °C - 400 °C in an ALD vacuum chamber, sequentially and alternately. In a specific example of an ALD cycle, a mixture of SnCl4 vapor and N2 carrier gas is introduced into the ALD processing chamber for 0.5 seconds, followed by exposure to the substrate for 3 seconds. Next, the ALD processing chamber is purged with N2 for 10 seconds to remove SnCl4 from the bulk of the processing chamber, and a mixture of H2O vapor and N2 carrier gas is flowed into the processing chamber for 1 second and exposed to the substrate for 3 seconds. Next, the ALD processing chamber is purged with N2 and the cycle is repeated. The ALD process is carried out at sub-atmospheric pressure (e.g., 0.4 Torr) and temperatures of 200 °C to 400 °C.

[0114] Another example of thermal ALD process conditions suitable for depositing a removable tin oxide sealant layer in certain methods provided herein is given in an article by Du et al. entitled "In situ Examination of Tin Oxide Atomic Layer Deposition using Quartz Crystal Microbalance and Fourier Transform Infrared Techniques" (J. Vac. Sci. Technol. A 23, 581 (2005)), the entire contents of which are incorporated herein by reference. In this process, the substrate is sequentially exposed to SnCl4and H2O2in an ALD process chamber at a temperature between about 150 °C and about 430 °C.

[0115] While the use of a tin halide precursor in ALD is suitable in many embodiments, in some embodiments, a non-halogenated organotin precursor can be used to avoid corrosion issues that occur due to the use of halogenated precursors such as SnCl4. An example of a suitable non-halogenated organotin precursor includes an alkylamino tin (alkylated tin amide) precursor such as tetrakis(dimethylamino)tin. An example of a suitable thermal ALD deposition method using this precursor is provided in an article by Elam et al. entitled "Atomic Layer Deposition of Tin Oxide Films using Tetrakis(dimethylamino)tin" (J. Vac. Sci. Technol. A 26, 244 (2008)), the entire contents of which are incorporated herein by reference. In this method, the substrate is sequentially exposed to tetrakis(dimethylamino)tin and H2O2in an ALD chamber at a temperature between about 50 °C and about 300 °C. The use of this precursor allows for the deposition of tin oxide films at low temperatures of 100 °C or less. For example, tin oxide films can be deposited at 50 °C without the use of plasma to increase the reaction rate. Another example of thermal ALD of tin oxide using tetrakis(dimethylamino)tin and H2O2is provided in an article by Elam et al. entitled "Atomic Layer Deposition of Indium Tin Oxide Thin Films Using Nonhalogenated Precursors" (J. Phys. Chem. C 2008, 112, 1938-1945), which is incorporated herein by reference.

[0116] Heo et al., "Low temperature Atomic Layer Deposition of Tin Oxide," Chem. Mater., 2010, 42(7) 4964-4973, which is incorporated by reference herein in its entirety, provides another example of a low temperature thermal ALD process using a reactive organotin precursor. In this deposition process, which can be adapted to deposit the tin oxide films provided herein, a substrate is sequentially exposed to N 2 3 di-tert-butyltin butane-2,3-diamino-(II) and 50% H2O2. These reactants are vaporized and provided to the process chamber mixed with N2carrier gas, respectively. After each exposure of the substrate to the reactants, the chamber is purged with N2. Deposition can be carried out at temperatures between about 50 °C and about 150 °C.

[0117] While H2O2can be effective as an oxygen-containing reactant to form tin oxide in an ALD process, due to decomposition of H2O2, at times it can not be possible to adequately control growth of the tin oxide film. In some embodiments, a more stable oxygen-containing precursor is used, such as NO. Heo et al., "Atomic Layer Deposition of Tin Oxide with Nitric Oxide as an Oxidant Gas," J. Mater. Chem., 2012, 22, 4599, which is incorporated by reference herein, provides one example of suitable process conditions using NO as an oxygen-containing reactant. Deposition includes sequentially exposing a substrate to cyclic Sn(II) amide (1,3-bis(1,1-dimethylethyl)-4,5-dimethyl-(4R,5R)-1,3,2-diazastannatane-2-ylidene and NO at temperatures of about 130 °C - 250 °C.

[0118] ​In some embodiments, a tin oxide film is deposited by PEALD. The same types of tin-containing precursors and oxygen-containing reactants used for thermal ALD described above can be used. In PEALD, the ALD apparatus is equipped with a system for generating plasma in the process chamber and for treating the substrate with the plasma. In a PEALD processing sequence, the substrate is provided to the PEALD process chamber and exposed to a tin-containing precursor, causing the tin-containing precursor to adsorb on the substrate surface. The process chamber is purged with an inert gas (e.g., argon or helium) to remove precursor molecules that are not adsorbed to the substrate surface from the process chamber, and the substrate is exposed to an oxygen-containing reactant introduced into the process chamber. Simultaneously with or after a delay from the introduction of the oxygen-containing reactant, a plasma is formed in the process chamber. The plasma facilitates a reaction between the oxygen-containing reactant and the tin-containing precursor on the substrate surface, resulting in the formation of tin oxide. The process chamber is purged with an inert gas, and in some embodiments, a cycle including exposure to a tin-containing precursor, purging, exposure to an oxygen-containing reactant, generating a plasma, and a second purging is repeated as many times as needed to form a tin oxide film of the desired thickness, layer-by-layer. In some embodiments, the cycle forms a monolayer or less than a monolayer of tin oxide on the surface of the substrate.

[0119] An article by Seop et al., entitled "The Fabrication of Tin Oxide Films by Atomic Layer Deposition using Tetrakis(ethylmethylamino)tin Precursor" (Transactions on Electrical and Electronic Materials, 2009, 10, 5, 173-176), which is incorporated by reference herein, provides an example of process conditions suitable for PEALD formation of a tin oxide film. A substrate is provided into a PEALD process chamber and exposed to tetrakis(ethylmethylamino)tin without plasma for 4 seconds. Next, the tin-containing precursor is purged from the process chamber by flowing argon through the process chamber for 20 seconds. Then, O2 is injected for 2 seconds, followed by another 2 seconds at 100 W of radio frequency (RF) power. An argon purge follows, completing one PEALD cycle. In this example, the process is performed at a temperature range of 50 °C to 200 °C and a pressure of 0.8 Torr.

[0120] While ALD (thermal-enhanced and plasma-enhanced) is one method of depositing a tin oxide film, it is understood that other tin oxide deposition methods, such as CVD, PECVD, and sputtering, can also be used.

[0121] Figure 3A process flow diagram of operations performed according to some disclosed embodiments is shown. In operation 302, a substrate having a removable sealant layer is provided between a dielectric material and a patterned hard mask above the removable sealant layer. The dielectric material also comprises a metal. Figure 5D An example is provided in the following example, relative to Figure 4 and Figure 5D This is described in more detail. In some embodiments, the substrate is pretreated; for example, in some embodiments, this can be performed... Figure 2 Operation 206 is used to form the substrate provided in operation 302.

[0122] In operation 310, a conformal removable sealant layer is orientedly etched and the dielectric material is exposed. Removal can be performed by exposure to a hydrogen-containing gas, which may be one or more of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof. In some embodiments, oriented etching can be performed by exposing the conformal removable sealant layer to one or more of the following dry etching conditions: (1) chlorine (Cl2) and boron trichloride (BCl3); (2) hydrogen bromide (HBr); (3) methane (CH4); (4) ammonia (NH3); (5) hydrogen (H2) diluted with argon, helium, or nitrogen; (6) a combination thereof, either alone or together. In some embodiments, the operation involves oriented etching using an etching chemistry suitable for removing the conformal removable sealant layer. Oriented etching can be achieved by applying a bias during etching. In some embodiments, the bias is applied to a pedestal holding the substrate being processed. In various implementations, a removable sealant layer is etched in an anaerobic environment while maintaining its shape.

[0123] In operation 312, a patterned hard mask is used as a mask to etch the dielectric material to expose the surface of the metal. In various embodiments, etching the dielectric material includes exposing the substrate to oxygen-containing chemicals, such as oxygen, oxygen plasma, etc.

[0124] Figure 4 An example of a process flow diagram is shown, illustrating one example of the operations that can be performed according to certain disclosed embodiments. In operation 402, a substrate is provided having a first dielectric material layer on a surface having exposed metal and a dielectric surface, and a patterned hard mask on the first dielectric material layer.

[0125] exist Figure 5A It describes what can be done Figure 4 An example of a substrate provided in operation 402. Figure 5AA substrate layer 502 is shown with metal lines 506a and a liner or barrier layer 504, which can be, for example, a TEOS deposited liner layer. In some embodiments, the liner layer 504 can be a diffusion barrier layer. In some embodiments, there is no liner layer 504. On the liner layer 504 is a first dielectric material layer 508, which has a liner layer 510' and a patterned hardmask 512'. In some embodiments, the liner layer 510' can be a diffusion barrier layer. In some embodiments, there is no liner layer 510'.

[0126] In various embodiments, the substrate layer 502 is a silicon oxide material. In various embodiments, the substrate 502 is a ULK dielectric material, such as a ULK silicon oxide. In some embodiments, the substrate layer 502 and the first dielectric layer 508 have the same composition. In some embodiments, the substrate layer 502 and the first dielectric layer 508 have different compositions. In some embodiments, the first dielectric layer 508 is a ULK dielectric material. The metal lines 506a can be any suitable metal. Examples include, but are not limited to, copper, tungsten, and cobalt. Although Figure 5A The examples depicted in FIG. 6A show different widths of the metal lines 506a, but the thickness of the lines and the distance between the metal lines can be any suitable amount, depending on the structure to be fabricated by the integration scheme. In some embodiments, the hardmask 512' can be a metal hardmask. In some embodiments, the hardmask 512' is a metal-containing hardmask. One exemplary hardmask material is titanium oxide. In some embodiments, the hardmask 512' is a tin-containing hardmask or a lead-containing hardmask, described in more detail below with reference to FIG. 6B. Figures 6A-6G Embodiments thereof are described in more detail below with reference to the examples provided in FIG. 6B. For purposes of illustration and example only, Figures 5A-5G An example is shown in which the hardmask 512' has a different material than the removable encapsulant 550, which is described in more detail below. For example, Figures 5A-5G The hardmask 512' in FIG. 6B can be titanium oxide.

[0127] Returning to FIG. 6A, Figure 4In operation 404, the first dielectric material layer is partially etched to leave a thinner second dielectric material layer on the substrate. During operation 404, the patterned hard mask serves as a mask that enables etching of the trench structure. Only a partial thickness of the dielectric material is etched, bifurcating the etching process into two separate operations, with operation 404 being the first operation that defines the extent of the trench. The thinner second dielectric material layer is thinner compared to the first dielectric material layer prior to the partial etching of the first dielectric material layer. In various embodiments, at least 50% of the thickness of the first dielectric material layer, or between about 50% to about 75% of the thickness of the first dielectric material layer, is etched during operation 404. In various embodiments, the thinner second dielectric material layer is at least about 25% of the thickness of the first dielectric material layer. In various embodiments, operation 404 is performed to form a trench having a horizontal bottom surface.

[0128] In Figure 5B An example is provided. Figure 5B The substrate is shown with the first dielectric layer 508 etched to leave a thinner second dielectric layer 508' to form a trench 518 on the substrate.

[0129] Returning to Figure 4 In operation 406, a conformal removable encapsulant layer is deposited on the trench structure. Figure 5C An example of a conformal removable encapsulant layer 550 deposited on the structure is provided.

[0130] Returning to Figure 4 In operation 408, a second patterned hard mask can be formed over the conformal removable encapsulant layer to define a via such that the pattern leaves an exposed area of the conformal removable encapsulant layer. For example, in some embodiments, the second patterned hard mask is formed by depositing a hard mask material, such as spin-on carbon, and patterning using photolithography techniques. In some embodiments, the depositing can be performed by a spin-on technique. The patterning can be performed by exposing the substrate to a dry etch chemistry containing fluorocarbon gas to create the via.

[0131] Figure 5D An example is provided showing a second patterned hard mask 524 patterned on the conformal removable encapsulant layer 550, leaving an exposed surface in the via 516.

[0132] Returning to Figure 4In operation 410, the conformal removable encapsulant layer is etched using the second patterned hardmask as a mask to expose the underlying thinner second dielectric material layer underneath the conformal removable encapsulant layer. In some embodiments, this operation involves a directional etch using an etch chemistry appropriate for removing the conformal removable encapsulant layer. The directional etch can be achieved by applying a bias during the etch. In some embodiments, the bias is applied to a pedestal that holds the substrate being processed. In various embodiments, the conformal removable encapsulant layer is etched in an anaerobic environment. Operation 410 can be performed using any of the process conditions and etch chemistries described above with respect to operation 310.

[0133] In Figure 5E An example is provided in FIG. 5G, which shows the exposed metal surface at the bottom of the via 526, leaving a conformal removable encapsulant layer 550' on vertical surfaces and under the second patterned hardmask 524.

[0134] Returning to Figure 4 In operation 412, the thinner second dielectric material layer is etched using the second patterned hardmask as a mask to expose the underlying metal surface located underneath the thinner second dielectric material layer. In various embodiments, etching the thinner second dielectric material layer involves exposing the substrate to an oxygen-containing chemical, such as oxygen gas, oxygen plasma, etc.

[0135] In Figure 5F An example is provided in FIG. 5G, which shows the exposed metal surface at the bottom of the via 526, leaving a conformal removable encapsulant layer 550' on vertical surfaces and under the second patterned hardmask 524.

[0136] Returning to Figure 4 In operation 414a, the second patterned hardmask is removed. In operation 414b, the conformal removable encapsulant layer is removed. In various embodiments, the conformal removable encapsulant layer is etched in an anaerobic environment. If the conformal removable encapsulant layer includes more than one layer, where the layers include more than one type of metal-containing film, such as lead oxide and tin oxide on top of it, or lead oxide and tin nitride on top of it, or lead nitride and tin oxide on top of it, or lead nitride and tin nitride on top of it, tin oxide and lead oxide on top of it, or tin nitride and lead oxide on top of it, or tin oxide and lead nitride on top of it, or tin nitride and lead nitride on top of it, then two or more etch chemistries can be used to remove the conformal removable encapsulant layer. For example, if the upper layer is tin nitride or tin oxide, then a hydrogen-containing chemical can be used to remove the upper layer, while if the upper layer is lead oxide or lead nitride, then a weak organic acid can be used to remove the upper layer.

[0137] In some embodiments, operations 414a and 414b are combined into a single operation to remove both the second patterned hardmask and the conformal removable sealant layer in one exposure of the substrate to an etching chemistry. In some embodiments, operations 414a and 414b are performed in two separate operations with two different chemistries. These two embodiments are described in detail below.

[0138] Where operations 414a and 414b are performed in a single operation, the substrate is exposed to a chemistry that is capable of etching both the second patterned hardmask material and the conformal removable sealant layer. For example, if the second patterned hardmask material is a carbon-containing material, and the conformal removable sealant layer is one or more tin-oxide (e.g., tin oxide) layers or tin-nitride (e.g., tin nitride) layers, or both, the etching to remove both the second patterned hardmask and the conformal removable sealant layer can be performed by exposing the substrate to hydrogen gas in an ashing operation. The tin-oxide and / or tin-nitride layers form volatile metal hydrides, whereby the hydrogen gas used to etch the second patterned hardmask and / or the conformal removable sealant layer does not etch or damage underlying dielectric materials. Removing both in a single operation can reduce the steps in the process flow, thereby improving efficiency.

[0139] When operations 414a and 414b are performed in two separate operations, one etch chemistry can be used to remove the second patterned hardmask, while a different etch chemistry is used to remove the conformal removable encapsulant layer. Since the conformal removable encapsulant layer protects the underlying dielectric layer from damage or etching when the second patterned hardmask is removed, this allows a more aggressive etch chemistry to be used to tune the etch, for example, to increase the etch rate of the second patterned hardmask. For example, operation 414a can use an aerobic condition for etching, while operation 414b uses an anaerobic condition for etching. As an example, the second patterned hardmask can be etched using an oxygen-containing plasma, which can be formed by generating a plasma in an oxygen-containing environment. The oxygen-containing environment can be formed by flowing one or more oxygen-containing gases (e.g., O3, including H2O2 peroxide, O2, H2O), alcohols (e.g., methanol, ethanol, and isopropyl alcohol), NO, nitrous dioxide (NO2), nitrous oxide (N2O), carbon monoxide (CO), and carbon dioxide (CO2)). By "plasma" is meant a plasma ignited within or remotely and brought into a reaction chamber. The plasma can include reactants as described herein, and can include other reagents, such as a carrier gas, or reactive species, such as hydrogen. The reactants and other reagents can be present in the reaction chamber when the plasma is excited, or a remote plasma can be flowed into a chamber where the reactants are present, and / or the reactants and / or carrier gas can be ignited into a plasma remotely and brought into the reaction chamber. By "plasma" is meant to include any plasma known to be technologically feasible, including inductively coupled plasmas and microwave surface wave plasmas. In various embodiments, the plasma is an in-situ plasma, such that the plasma is formed directly over the surface of the substrate in the chamber. The plasma can be formed at a power of about 0.2122 W / cm 2 and about 2.122 W / cm 2between about 600 W and about 6000 W. The plasma process can be generated by applying a radio frequency (RF) field to the gas using two capacitively coupled plates. The plasma is ignited by ionizing the gas between the plates by the RF field, creating free electrons in the plasma discharge region. These electrons are accelerated by the RF field and can collide with gas phase reactant molecules. These collisions of electrons with reactant molecules can form radical species that participate in the deposition process. It will be appreciated that the RF field can be coupled via any suitable electrode. Non-limiting examples of electrodes include a process gas distribution showerhead and a substrate support pedestal. It will be appreciated that the plasma process can be formed by one or more suitable methods in addition to the capacitive coupling of the RF field to the gas. In some embodiments, the plasma is a remote plasma such that the second reactant is ignited in a remote plasma generator upstream of the station and then delivered to the station housing the substrate.

[0140] The conformal removable sealant layer can be subsequently removed in operation 414b. When the conformal removable sealant layer is one or more tin-containing oxide layers and / or one or more tin-containing nitride layers, the conformal removable sealant layer is removed using a hydrogen-containing chemical, such as hydrogen gas. When the conformal removable sealant layer is one or more lead-containing oxide layers and / or one or more lead-containing nitride layers, the conformal removable sealant layer is removed using a weak acid, such as an acid having a pKa value between about -2 and about 12. The weak acid can be an organic acid. Examples of weak acids include acetic acid and citric acid. Such etching chemistries are mild enough to prevent etching and / or damage to underlying dielectric materials.

[0141] Figure 5G An example of a substrate with a bevel-less via 546 is shown, where the second patterned hardmask and the conformal removable sealant layer are removed, resulting in the bevel-less via 546. Note that the bevel is removed at 564.

[0142] Returning to Figure 4 In operation 414c, the first patterned hardmask is removed. In the case where the first patterned hardmask is a titanium nitride layer deposited, for example, by physical vapor deposition, a TK-10 plasma cleaner available from Entegris can be used. TMThe mask is removed. In some embodiments, operations 414a, 414b, and 414c are performed simultaneously in one operation. This can be performed in some embodiments where the first patterned hardmask material has the same composition as the conformal removable encapsulant layer. In some embodiments, the first patterned hardmask material can be a Group IV metal-containing oxide, a Group IV metal-containing nitride, a Group IV metal-containing sulfide, a tin-containing oxide, a tin-containing nitride, a tin-containing sulfide, a lead-containing oxide, a lead-containing nitride, a lead-containing sulfide, or any combination thereof. In some embodiments, the first patterned hardmask material has a different composition than the conformal removable encapsulant layer, but both the first patterned hardmask material and the conformal removable encapsulant layer are, for example, a Group IV metal-containing oxide, a Group IV metal-containing nitride, a Group IV metal-containing sulfide, a tin-containing oxide, a tin-containing nitride, a lead-containing oxide, a lead-containing nitride, or any combination thereof. See below for more detailed descriptions of examples where the first patterned hardmask material is the same as the conformal removable encapsulant layer material. Figures 6A-6G More detailed descriptions of examples where the first patterned hardmask material is the same as the conformal removable encapsulant layer material.

[0143] Figure 6A A substrate 602 is shown having metal lines 606a and an etch stop layer 604 under a first dielectric layer 608, a liner layer 610, and a patterned hardmask 612', where the patterned hardmask 612' is a Group IV metal-containing oxide, a Group IV metal-containing nitride, a Group IV metal-containing sulfide, a tin-containing oxide, a tin-containing nitride, a tin-containing sulfide, a lead-containing oxide, a lead-containing nitride, a lead-containing sulfide, or any combination thereof. In some embodiments, this can correspond to operation 402 of Figure 4 A substrate is provided in operation 402.

[0144] In operation 404, the first dielectric layer 608 is etched to form a thinner second dielectric layer 608' to form a "trench degree" by exposing the substrate 602 to an etching chemistry such as a partially oxygen-containing etching chemistry. In some embodiments, this can correspond to operation 404 of Figure 6B Figure 4 A conformal removable encapsulant layer 650 is deposited on the substrate in operation 406. In some embodiments, this can correspond to operation 406 of

[0145] In operation 408, a second patterned hardmask 624 is formed by depositing and patterning a hardmask material, which can be, for example, spin-on carbon. The patterned hardmask is patterned to expose the conformal removable encapsulant layer 650 at the bottom of the via 616. In some embodiments, this can correspond to operation 408 of Figure 6C Figure 4 In operation 410, the conformal removable encapsulant layer 650 is removed by exposing the substrate to an etching chemistry such as a partially oxygen-containing etching chemistry. In some embodiments, this can correspond to operation 410 of

[0146] In operation 412, the second patterned hardmask 624 is removed. In some embodiments, this can correspond to operation 412 of Figure 6D Figure 4 ​​​Operation 408.

[0147] exist Figure 6E In this process, a conformal removable sealant layer 650 is oriented etched to form an etched conformal removable sealant layer 650' and to open the surface beneath this conformal removable sealant layer to expose the dielectric 608' at the bottom of the via 626. Note that in some embodiments, some etching may occur at the top 670 of the hard mask, but without removing the entire thickness of the hard mask. In some embodiments, this may correspond to Figure 4 Operation 410.

[0148] exist Figure 6F In this process, a second patterned hard mask 624 is used as a mask to etch the substrate, and the etch stop layer 604 is etched to form an etched etch stop layer 604', thereby exposing the exposed surfaces of the metal line 606a and the dielectric 602. In some embodiments, this may correspond to Figure 4 Operation 412.

[0149] exist Figure 6G In this process, the second patterned hard mask 624, the conformal removable sealant layer 650', and the first patterned hard mask 660' are all removed. If all three materials can be removed using hydrogen-containing etching chemicals, this can be performed in a single operation, such as using hydrogen gas. For example, one embodiment in which all three can be etched simultaneously is where the second patterned hard mask 624 is spin-coated carbon, the conformal removable sealant layer 650' is one or more tin oxide layers, one or more tin nitride layers, or both, and the first patterned hard mask 660' is one or more tin oxide layers, one or more tin nitride layers, or both. In this case, the substrate can be exposed to hydrogen gas in a single operation to remove the second patterned hard mask 624, the conformal removable sealant layer 650', and the first patterned hard mask 660'. In some embodiments, this may correspond to... Figure 4 Operations 414a, 414b, and 414c.

[0150] In another example, the second patterned hardmask 624 can be removed using a first etch chemistry, the conformal removable encapsulant layer 650' etched using a second etch chemistry, and the first patterned hardmask 660' etched using a third etch chemistry. For example, the second patterned hardmask 624 can be spin-on carbon etched by an oxygen-containing plasma, and the conformal removable encapsulant layer 650' can be tin-containing oxide, tin-containing nitride, or a combination thereof etched using a hydrogen-containing chemistry, and the first patterned hardmask 660' can be lead-containing oxide, lead-containing nitride, or a combination thereof etched using a weak organic acid chemistry. In another example, the second patterned hardmask 624 can be spin-on carbon etched by an oxygen-containing plasma, and the conformal removable encapsulant layer 650' can be lead-containing oxide, lead-containing nitride, or a combination thereof etched using a weak organic acid chemistry, and the first patterned hardmask 660' can be tin-containing oxide, tin-containing nitride, or a combination thereof etched using a hydrogen-containing chemistry.

[0151] In another example, the second patterned hardmask 624 can be removed using a first etch chemistry, the conformal removable encapsulant layer 650' etched using a second etch chemistry, and the first patterned hardmask 660' etched using a third etch chemistry. For example, the second patterned hardmask 624 can be spin-on carbon etched by an oxygen-containing plasma, and the conformal removable encapsulant layer 650' can be tin-containing oxide, tin-containing nitride, or a combination thereof etched using a hydrogen-containing chemistry, and the first patterned hardmask 660' can be lead-containing oxide, lead-containing nitride, or a combination thereof etched using a weak organic acid chemistry. In another example, the second patterned hardmask 624 can be spin-on carbon etched by an oxygen-containing plasma, and the conformal removable encapsulant layer 650' can be lead-containing oxide, lead-containing nitride, or a combination thereof etched using a weak organic acid chemistry, and the first patterned hardmask 660' can be tin-containing oxide, tin-containing nitride, or a combination thereof etched using a hydrogen-containing chemistry.

[0152] Apparatus

[0153] Figure 7 A schematic diagram depicting an embodiment of a deposition processing station 700 having a process chamber body 702 for maintaining a low pressure environment. Multiple processing stations 700 can be included in a common low pressure processing tool environment. For example, Figure 8 An embodiment of a multi-station processing tool 800 is depicted. In some embodiments, one or more hardware parameters of the processing stations 700, including those discussed in detail below, can be adjusted programmatically by one or more computer controllers 750.

[0154] The processing station 700 is in fluid communication with a reactant delivery system 701 for delivering process gas to the distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 for mixing and / or conditioning process gas for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of process gas to the mixing vessel 704.

[0155] As an example, Figure 7 Embodiments include a vaporization point 703 for vaporizing liquid reactants to be supplied to the mixing vessel 704. In some embodiments, the vaporization point 703 can be a heated vaporizer. Saturated reactant vapor produced by such a vaporizer can condense in downstream delivery piping. Exposure of incompatible gases to condensed reactants can produce small particles. These small particles can clog piping, interfere with valve operation, contaminate substrates, and the like. Some methods to address these problems involve purging and / or evacuating the delivery piping to remove residual reactants. However, purging the delivery piping can increase processing station cycle time, reducing the throughput of the processing station. Accordingly, in some embodiments, the delivery piping downstream of the vaporization point 703 can be heat traced. In some examples, the mixing vessel 704 can also be heat traced. In one non-limiting example, the piping downstream of the vaporization point 703 has an increasing temperature profile from about 100°C to about 150°C at the mixing vessel 704.

[0156] In some embodiments, liquid precursors or liquid reactants can be vaporized at a liquid injector. For example, a liquid injector can inject pulses of liquid reactant into a carrier gas stream upstream of the mixing vessel. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets, which are subsequently vaporized in a heated delivery tube. Smaller liquid droplets vaporize more quickly than larger liquid droplets, reducing the delay between liquid injection and complete vaporization. Faster vaporization can reduce the length of piping downstream of the vaporization point 703. In one case, the liquid injector can be mounted directly to the mixing vessel 704. In another case, the liquid injector can be mounted directly to the showerhead 706.

[0157] In some embodiments, a liquid flow controller (LFC) upstream of vaporization point 703 can be provided for controlling the mass flow of liquid for vaporization and delivery to processing station 700. For example, the LFC can include a thermal mass flow meter (MFM) downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it can take a second or more to stabilize the liquid flow using feedback control. This can extend the dosing time of the liquid reactants. Accordingly, in some embodiments, the LFC can dynamically switch between a feedback control mode and a direct control mode. In some embodiments, this can be performed by disabling the sense tube of the LFC and the PID controller.

[0158] Showerhead 706 distributes process gases to substrate 712. In the illustrated embodiment, substrate 712 is positioned below showerhead 706 and is shown resting on pedestal 708. Showerhead 706 can have any suitable shape and can have any suitable number and arrangement of ports for distributing process gases to substrate 712. Exemplary process gases include soak gases, removable sealant layer precursor gases, oxygen or nitrogen containing reactant gases, and carrier or purge gases. Figure 7

[0159] In some embodiments, micro-volume space 707 is positioned below showerhead 706. Implementing the disclosed embodiments in a micro-volume space of a processing station rather than the entire volume of the processing station can reduce exposure and purge times of reactants, can reduce the time for changing processing conditions (e.g., pressure, temperature, etc.), can limit exposure of a processing station robot to process gases, etc. Exemplary micro-volume space dimensions include, but are not limited to, a volume between 0.1 liters and 2 liters. This can also affect throughput. In some embodiments, the disclosed embodiments are not performed in a micro-volume space.

[0160] In some embodiments, pedestal 708 can be raised or lowered to expose substrate 712 to micro-volume space 707 and / or to change the volume of micro-volume 707. For example, during substrate transfer phases, pedestal 708 can be raised to position substrate 712 in micro-volume space 707. In some embodiments, micro-volume 707 can completely enclose substrate 712 as well as a portion of pedestal 708 to create a region of high flow impedance.

[0161] ​Optionally, the pedestal 708 can be lowered and / or raised during portions of the process within the micro-volume space 707 to adjust the process pressure, reactant concentrations, etc. In one case where the process chamber body 702 is maintained at a substantially constant pressure during processing, lowering the pedestal 708 can enable the micro-volume space 707 to be evacuated. Exemplary ratios of micro-volume to process chamber volume include, but are not limited to, volume ratios between 1 :500 and 1 : 10. It should be appreciated that in some embodiments, the pedestal height can be adjusted programmatically by a suitable computer controller 750.

[0162] In another case, adjusting the height of the pedestal 708 can allow for varying the plasma density during a plasma activation and / or processing cycle included in the process. At the end of the processing phase, the pedestal 708 can be lowered during another substrate transfer phase to allow for removal of the substrate 712 from the pedestal 708.

[0163] While the exemplary micro-volume space variations described herein refer to an adjustable height pedestal, it should be appreciated that in some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to vary the volume of the micro-volume space 707. Further, it should be appreciated that the vertical position of the pedestal 708 and / or the showerhead 706 can be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 can include a rotational axis for rotating the orientation of the substrate 712. It should be appreciated that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more suitable computer controllers 750.

[0164] In some embodiments in which plasma can be used as described above, the showerhead 706 and the pedestal 708 are electrically connected to a radio frequency (RF) power source 714 and a matching network 716 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and the matching network 716 can operate at any suitable power to form a plasma with a desired composition of radical species. Examples of suitable powers are included above. Similarly, the RF power source 714 can provide RF power at any suitable frequency. In some embodiments, the RF power source 714 can be configured to control high frequency and low frequency RF power sources independently of one another. Example low frequency RF frequencies can include, but are not limited to, frequencies between 50 kHz and 500 kHz. Examples of high frequency RF frequencies can include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, such as 2 MHz, 13.56 MHz, or 27 MHz. It will be appreciated that any suitable parameter can be modulated discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power can be pulsed intermittently with respect to a continuously powered plasma to reduce ion bombardment of the substrate surface.

[0165] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage sensors, current sensors (e.g., VI probes). In another case, the plasma density and / or process gas concentration can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be adjusted programmatically based on measurements from such in situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide programmed control of the plasma power. It will be appreciated that other monitors can be used to monitor the plasma and other process characteristics in some embodiments. Such monitors can include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

[0166] In some embodiments, instructions for controller 750 can be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting conditions of a process phase can be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases can be sequentially arranged such that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters can be included in a recipe phase. For example, a first recipe phase can include instructions for setting flow rates of an inert gas and / or a reactant gas (e.g., a Group IV metal-containing precursor), instructions for setting a flow rate of a carrier gas, instructions for setting a susceptor temperature, and a time delay instruction for the first recipe phase. A subsequent second recipe phase can include instructions for adjusting or stopping the flow rate of the inert gas and / or the reactant gas, and instructions for adjusting the flow rate of the carrier gas or a purge gas, and a time delay instruction for the second recipe phase. A third recipe phase can include instructions for setting flow rates of an inert and / or reactant gas (e.g., an oxygen or nitrogen containing reactant), instructions for adjusting the flow rate of the carrier gas, and a time delay instruction for the third recipe phase. A fourth recipe phase can include instructions for adjusting or stopping the flow rate of the inert gas and / or the reactant gas, instructions for adjusting the flow rate of the carrier gas or a purge gas, and a time delay instruction for the fourth recipe phase. It should be understood that these recipe phases can be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0167] In some embodiments, temperature control of susceptor 708 can be provided by heater 710. The susceptor can be set to a deposition temperature. For example, to deposit nitrides or carbides, the susceptor can be set at a temperature between about 200 °C and about 300 °C. Further, in some embodiments, pressure control for processing station 700 can be provided by butterfly valve 718. As shown in embodiments of the present disclosure, butterfly valve 718 throttles a vacuum provided by a downstream vacuum pump (not shown). In some embodiments, butterfly valve 718 is used as an outlet for coupling to a vacuum. However, in some embodiments, pressure control of processing station 700 can also be adjusted by varying the flow rate of one or more gases introduced to processing station 700. Figure 7

[0168] As described above, one or more processing stations can be included in a multi-station processing tool. Figure 8 ​A schematic diagram of an embodiment of a multi-station processing tool 800 with an inbound loading lock 802 and an outbound loading lock 804 is shown, either or both of which may include a remote plasma source. A manipulator 806, operating at atmospheric pressure, is configured to move a substrate or wafer from a pod loaded via a pod 808 to the inbound loading lock 802 via an atmospheric port 810. In the inbound loading lock 802, the manipulator 806 places the substrate on a base 812, the atmospheric port 810 is closed, and the loading lock is evacuated. If the inbound loading lock 802 includes a remote plasma source, the substrate can be exposed to remote plasma processing within the loading lock before being introduced into the processing chamber 814. Furthermore, the substrate can also be heated in the inbound loading lock 802, for example, to remove moisture and adsorbed gases. Next, a chamber delivery port 816 leading to the processing chamber 814 is opened, and another manipulator (not shown) places the substrate into the reactor on the base of the first station shown in the reactor for processing. Although Figure 8 The embodiments described include loading locks; however, it should be understood that in some embodiments, the substrate may be allowed to enter the processing station directly. In various embodiments, immersion gas is introduced into the station when the substrate is placed on the base 812 by a robotic arm 806.

[0169] The depicted processing room 814 includes four processing stations, in Figure 8 The embodiments shown are numbered 1 to 4. Each station has a heated base (shown as 818 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may be used for different or multiple purposes. For example, in some embodiments, the processing station may be switchable between ALD and PEALD processing modes. Additionally or alternatively, in some embodiments, processing chamber 814 may include one or more matched pairs of ALD and plasma-enhanced ALD processing stations. Although the depicted processing chamber 814 includes four stations, it should be understood that a processing chamber according to the invention may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0170] Figure 8 An embodiment of a wafer handling system 890 for transferring substrates within a processing chamber 814 is depicted. In some embodiments, the wafer handling system 890 can transfer substrates between individual processing stations and / or between a processing station and a loading lock. It should be understood that any suitable wafer processing system can be employed. Non-limiting examples include wafer conveyors and wafer handling robots. Figure 8Embodiments of a system controller 850 for controlling process conditions and hardware states of the process tool 800 are also depicted. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processors 852 can include CPUs or computers, analog and / or digital input / output connections, stepper motor controller boards, etc. In some embodiments, the system controller 850 includes machine-readable instructions for performing operations such as those described above with reference to FIGS. 1-4. Figure 2 , 3 and 4.

[0171] In some embodiments, the system controller 850 controls the activities of the process tool 800. The system controller 850 executes system control software 858 stored in mass storage device 854, loaded into memory device 856 and executed on processor 852. Alternatively, control logic can be hard coded in the controller 850. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays or FPGAs), and the like can be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic can be used in its place. The system control software 858 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, substrate temperatures, target power levels, RF power levels, substrate pedestal, chuck, and / or susceptor positions, and other parameters of the particular process being performed by the process tool 800. The system control software 858 can be configured in any suitable manner. For example, various process tool component subroutines or control objects can be written to control the operation of the process tool components used to perform various process tool processes. The system control software 858 can be coded in any suitable computer readable programming language.

[0172] In some embodiments, the system control software 858 can include input / output control (IOC) sequencing instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on mass storage devices 854 and / or memory devices 856 associated with the system controller 850 can be employed. Examples of programs or program segments for these purposes include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0173] The substrate positioning programs can include program code for the process tool components for loading a substrate onto the pedestal 818 and controlling the spacing between the substrate and other portions of the process tool 800.

[0174] A process gas control program can include code for controlling gas composition (e.g., first precursor gas, soak gas, second reactant gas, and purge gas as described herein) and flow rates, and optionally for flowing gas into one or more processing stations prior to deposition to stabilize pressure in the processing stations. A pressure control program can include code for controlling pressure in a processing station by adjusting, for example, a throttle valve in an exhaust system of the processing station, gas flow into the processing station, etc.

[0175] A heater control program can include code for controlling current to a heating unit used to heat a substrate. Alternatively, a heater control program can control delivery of a heat transfer gas (e.g., a soak gas) to a substrate.

[0176] According to embodiments herein, a plasma control program can include code for setting RF power levels applied to a processing electrode in one or more processing stations.

[0177] According to embodiments herein, a pressure control program can include code for maintaining pressure in a reaction chamber.

[0178] In some embodiments, there can be a user interface associated with the system controller. The user interface can include a display screen, graphical software displays of devices and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0179] In some embodiments, parameters adjusted by the system controller 850 can relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (e.g., RF bias power levels), pressure, temperature, etc. These parameters can be provided to the user in the form of a recipe, which can be entered using the user interface.

[0180] Signals for monitoring processing can be provided by analog and / or digital input connections of the system controller 850 from various process tool sensors. Signals for controlling processing can be output on analog and / or digital output connections of the process tool 800. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

[0181] The system controller 850 can provide program instructions for implementing the deposition processes described above, for example, a process employing soak prior to initiating ALD on a substrate inserted into a reaction chamber, where the soak is performed under any of the soak conditions described herein. The program instructions can control various process parameters such as direct current (DC) power levels, RF bias power levels, pressure, temperature, etc. According to various embodiments described herein, the instructions can control the parameters to operate in-situ deposition of a film stack.

[0182] The system controller will typically include one or more memory devices and one or more processors configured to execute instructions so that the device will perform a method according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments can be coupled to the system controller.

[0183] In some embodiments, the system controller 850 is part of a system, which can be part of the above-described embodiments. Such systems can include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling the operations of the systems before, during, and after processing of a semiconductor wafer or substrate. The electronics can be referred to as the “controller,” which can control various components of a system or systems. Depending on the

[0184] Broadly speaking, the system controller 850 can be defined as the electronic hardware that is programmed to implement processes and operations (e.g., software) for controlling the system. The system controller 850 can be implemented with various general-purpose

[0185] In some embodiments, the system controller 850 can be part of, or coupled to, a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 850 can be in the "cloud" or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. Computer can enable remote access to the system to monitor current process operations, inspect the history of past process operations, inspect trends or performance metrics from a plurality of process operations, to change parameters of current process operations, to set process operations to follow a current process, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which can include a local network or the Internet. The remote computer can include a user interface that allows a user to input or edit parameters and / or settings, which are then transmitted over the network to the system. In some examples, the system controller 850 receives instructions in the form of data, which specify parameters for each of the processing steps during one or more operations. It should be understood that the parameters can be specific to a type of process to be performed, and a type of tool that the system controller 850 is configured to interface with or control. Thus as described above, the system controller 850 can be distributed such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for these purposes can be one or more chambers integrated with one or more remote integrated circuits (e.g., at a platform level or as part of a remote computer) that combine to control processes on the chambers.

[0186] Example systems can include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that can be associated or used in the preparation and / or manufacturing of semiconductor wafers.

[0187] As described above, depending on the process step or steps to be performed by the tool, the system controller 850 can communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0188] Appropriate apparatus for performing the methods disclosed herein are further discussed and described in U.S. Patent Application No. 13 / 084,399, filed April 11, 2011, entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION," and U.S. Patent Application No. 13 / 084,305, filed April 11, 2011, entitled "SILICON NITRIDE FILMS AND METHODS," each of which is incorporated herein in its entirety.

[0189] The apparatus / process described herein can be used in conjunction with lithographic patterning tools or processes, e.g., for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools / processes will be used together in a common manufacturing facility. A lithographic patterning film typically includes some or all of the following operations, each of which can be implemented with multiple possible tools: (1) applying photoresist on a workpiece (i.e., substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or furnace or ultraviolet (UV) curing tool; (3) exposing the photoresist to visible or UV or X-ray light with a tool such as a wafer stepper; (4) developing the resist to selectively remove resist, thereby patterning it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma- assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0190] CONCLUSION

[0191] While the forgoing implementations have been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications can be made within the scope of the appended claims. It should be noted that there are many alternative ways of implementing both the processes, systems, and apparatuses. Accordingly, the present implementations are to be considered as illustrative and not restrictive, and the implementations are not to be limited to the details given herein.

Claims

1. A method of processing a semiconductor substrate, comprising: providing a substrate having a trench formed in a dielectric material; conformally depositing a removable sealant layer in the trench, wherein the removable sealant layer comprises a Group IV metal; forming a patterned hardmask on the removable sealant layer; etching the dielectric material using the patterned hardmask; and removing the patterned hardmask and the removable sealant layer to produce a non-chamfered via.

2. The method of claim 1, wherein, the Group IV metal is selected from the group consisting of tin and lead.

3. The method of claim 1, wherein the removable sealant layer is selected from the group consisting of tin oxide, tin nitride, tin sulfide, lead oxide, lead nitride, lead sulfide, and combinations thereof.

4. The method of claim 1, further comprising selectively removing the removable sealant layer relative to the dielectric material using hydrogen gas or an organic acid.

5. The method of claim 1, wherein, the trench includes an opening and a bottom, and a distance from the opening to the bottom is at least 25% of a total thickness of the dielectric material.

6. The method of claim 1, wherein, the removable sealant layer includes more than one layer.

7. The method of any one of claims 1-6, wherein, the substrate further comprises a metal hardmask over the dielectric material.

8. The method of any of claims 1-6, wherein the patterned hardmask is removable using a hydrogen-containing gas.

9. The method of any one of claims 1-6, wherein, the dielectric material is ultra-low-k silicon oxide.

10. The method of claim 4, wherein the organic acid is selected from the group consisting of acetic acid and citric acid.

11. The method of claim 7, wherein, the metal hardmask comprises a Group IV metal.

12. The method of claim 7, wherein, the Group IV metal is selected from the group consisting of tin and lead.

13. The method of claim 7, further comprising selectively removing the metal hardmask relative to the dielectric material using a hydrogen-containing gas.

14. The method of claim 13, wherein, the hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

15. The method of claim 6, wherein the removable sealant layer includes two layers.

16. The method of claim 15, wherein, the two layers have different compositions.

17. The method of claim 8, wherein, the hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

18. The method of claim 8, wherein the patterned hardmask comprises spin-on carbon.

19. A method of processing a semiconductor substrate, the method comprising: providing a semiconductor substrate comprising a material layer, a removable sealant layer on the material layer, and a patterned hardmask on the removable sealant layer, the material layer comprising a dielectric material and a metal under the dielectric material; selectively etching the removable sealant layer relative to the dielectric material using the patterned hardmask to expose the dielectric material; etching the dielectric material using the patterned hardmask to expose a surface of the metal, and removing the patterned hardmask and the removable sealant layer to form a via exposing the surface of the metal.

20. The method of claim 19, wherein, the removable sealant layer is selected from the group consisting of tin oxide, tin nitride, lead oxide, lead nitride, and combinations thereof. the method further comprises selectively removing the metal hardmask relative to the dielectric material using a hydrogen-containing gas.

21. The method of claim 19, wherein etching the dielectric material comprises exposing the dielectric material to an oxygen-containing reactant.

22. The method of claim 19, wherein selectively etching the removable sealant layer comprises applying a bias.

23. A method of processing a semiconductor substrate, comprising: providing a semiconductor substrate having a dielectric material comprising a trench and a first patterned hardmask; conformally depositing a removable sealant layer on the dielectric material, wherein the removable sealant layer comprises a Group IV metal; forming a second patterned mask on a portion of the removable sealant layer; etching the dielectric material using the second patterned mask; selectively removing the second patterned mask relative to the removable sealant layer and dielectric material; and selectively removing the removable sealant layer relative to the dielectric material.

24. The method of claim 23, wherein, The selectively removing the second patterned mask and the selectively removing the removable sealant layer are performed using the same etch chemistry.

25. The method of claim 24, wherein the etch chemistry comprises a hydrogen-containing gas.

26. The method of claim 25, wherein, The hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

27. The method of any of claims 23-25, further comprising selectively removing the first patterned hardmask relative to other exposed surfaces on the semiconductor substrate.

28. The method of claim 27, wherein, The selectively removing the removable sealant layer is performed using the same etch chemistry as selectively removing the second patterned mask and / or selectively removing the first patterned hardmask.

29. The method of claim 28, wherein the etch chemistry comprises a hydrogen-containing gas.

30. The method of claim 29, wherein, The hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

31. The method of claim 27, further comprising performing the selectively removing the second patterned mask using a first etch chemistry, performing the selectively removing the removable sealant layer using the first etch chemistry, and performing the selectively removing the first patterned hardmask using the first etch chemistry.

32. The method of claim 31, wherein the etch chemistry comprises a hydrogen-containing gas.

33. The method of claim 32, wherein, The hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

34. The method of claim 27, further comprising performing the selectively removing the removable sealant layer using a first etch chemistry, and performing the selectively removing the first patterned hardmask using the first etch chemistry.

35. The method of claim 34, wherein the etch chemistry comprises hydrogen gas.

36. A method of processing a semiconductor substrate, comprising: A substrate having a dielectric disposed on a metal surface is provided; The dielectric is etched to form a via to the metal surface; and The etching of the dielectric is bifurcated by: etching a first amount of the dielectric to form a trench, wherein the first amount of the dielectric etched is between 50% and 75% of the total thickness of the dielectric; etching a second amount of the dielectric to expose the metal surface, and between the time of etching the first amount of the dielectric and the time of etching the second amount of the dielectric, depositing a removable sealant layer on the dielectric, patterning a hard mask on the removable sealant layer.

37. The method of claim 36, wherein, The removable sealant layer includes tin nitride deposited using anaerobic conditions.

38. The method of claim 36, wherein, The removable sealant layer includes tin oxide.

39. The method of claim 36, wherein, The removable sealant layer includes more than one layer.

40. The method of claim 36, wherein, The removable sealant layer includes a tin nitride bottom layer and a tin oxide top layer.

41. A method of processing a semiconductor substrate, comprising: providing a substrate having a dielectric material comprising a trench formed by a first patterned hard mask; conformally depositing a removable sealant layer on the dielectric material, wherein the removable sealant layer comprises a Group IV metal; forming a second patterned mask on the removable sealant layer; selectively etching the removable sealant layer by exposing the removable sealant layer to a hydrogen-containing gas and applying a bias; etching the dielectric material using the second patterned mask as a mask; and selectively removing the second patterned mask and the removable sealant layer relative to the dielectric material using hydrogen gas.

42. The method of claim 41, wherein, The hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof. The hydrogen-containing gas is selected from the group consisting of hydrogen (H2), methane (CH4), ethylene (C2H4), ammonia (NH3), or mixtures thereof.

Images