Method of arranging VFET cells and cell architecture

Abstract

The present invention provides a cell architecture and a method for arranging a plurality of cells to form a cell architecture. The cell architecture at least includes a first cell and a second cell arranged adjacent to each other in a cell width direction, wherein the first cell includes a fin connector formed around one of a plurality of fins of the first cell and connecting a vertical field effect transistor (VFET) of the first cell to a power rail of the first cell, and the second cell includes a connector connected to a power rail of the second cell, wherein a fin of the first cell and the connector of the second cell are arranged adjacent to each other in the cell width direction in the cell architecture, and wherein a fin connector of the first cell and the connector of the second cell are merged.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 846,157, filed on May 10, 2019, entitled "VFET CELL PLACEMENT WITHOUT SINGLE FIN", and to U.S. Application No. 16 / 741,209, filed on January 13, 2020, entitled "VFET CELL PLACEMENT AND CELL ARCHITECTURE", the entire contents of which are incorporated herein by reference. Technical Field

[0003] Devices and methods consistent with embodiments of the inventive concept relate to semiconductor cell architectures for vertical field - effect transistors (VFETs). Background Art

[0004] One of the advantages of VFETs over planar or horizontal fin - type FETs is that VFETs can easily form a fin - type semiconductor cell, thereby obtaining a high - density semiconductor cell with at least a smaller cell width.

[0005] A fin - type semiconductor cell refers to a semiconductor cell in which a connector or connection structure (hereinafter referred to as "connector") is formed around one fin or fin structure (hereinafter referred to as "fin") rather than at least two fins or fin structures, and connects the VFET to the power rails of a fin - type semiconductor cell to supply a power voltage (Vdd) or a ground voltage (Vss) to the VFET. The connector formed around one fin (referred to as a fin connector) can be implemented by a bottom source / drain (S / D) region (referred to as a fin bottom S / D region) formed around the one fin of the VFET. Hereinafter, for simplicity, the VFET semiconductor cell is referred to as a cell, and the fin - type semiconductor cell, the semiconductor cell of at least one fin, and the semiconductor cell of at least two fins are referred to as a fin cell, at least one fin cell, and at least two fin cells, respectively.

[0006] Since a fin connector such as a fin bottom S / D region is formed around one fin in the cell, its width in the cell width direction is smaller than that of a connector of at least two fins, such as at least two bottom S / D regions of at least two fins formed around at least two fins in the cell. Therefore, when designing and manufacturing a cell architecture including multiple cells, compared with at least two fin cells including at least two fin connectors, fin cells including a fin connector have an advantage in reducing the cell width. Herein, the bottom S / D region formed around the fin may refer to a bottom S / D region configured to contact or surround the lower part of the fin.

[0007] Although having the advantage of a smaller cell width, it is difficult to implement a fin unit due to the complexity of patterning a fin connection structure (such as a fin bottom S / D region) connected to the power rail of a fin unit. In addition, since the cell design rules control the dimensions of back-end-of-line (BEOL) components (such as metal contact lines) and middle-of-line (MOL) components (such as power contact structures), the design and manufacture of a cell architecture including fin units are very complex and restricted.

[0008] Therefore, when designing and arranging cells in a cell layout to form a cell architecture, it is necessary to avoid setting or arranging a fin connection structure, such as a fin bottom S / D region connected to the power rail of a corresponding cell. SUMMARY OF THE INVENTION

[0009] Various embodiments of the inventive concept are directed to a cell layout, a cell architecture, and a method for arranging a plurality of cells in a cell layout to form a cell architecture including a plurality of VFETs.

[0010] These embodiments may provide an improved cell architecture having a reduced cell width, and a method for implementing the improved cell architecture.

[0011] According to an embodiment, there is provided a cell architecture including at least a first cell and a second cell arranged adjacent to each other in a cell width direction, wherein the first cell may include a fin connector that is formed around one of a plurality of fins of the first cell and connects a VFET of the first cell to a power rail of the first cell, and the second cell may include a connector connected to a power rail of the second cell. Here, a fin of the first cell and at least one fin of the second cell may be arranged adjacent to each other in the cell width direction in the cell architecture, and one fin connector of the first cell and at least one fin connector of the second cell are merged.

[0012] According to an embodiment, the connector of the second cell may include at least one fin connector that is formed around at least one fin of the second cell and connects at least one VFET of the second cell to a power rail of the second cell.

[0013] According to an embodiment, one fin connector of the first cell may include a fin bottom S / D region of a VFET of the first cell, and at least one fin connector of the second cell may include at least one fin bottom S / D region of at least one VFET of the second cell.

[0014] According to an embodiment, a fin connector of a first unit may include a fin top source / drain (S / D) contact structure formed on a top S / D region of a VFET of the first unit, and at least one fin connector of a second unit includes at least one fin top S / D contact structure formed on at least one top S / D region of at least one VFET of the second unit.

[0015] According to an embodiment, a cell architecture is provided that includes a first unit and a second unit arranged adjacent to each other in a cell width direction. The first unit may include at least two fin connectors that are formed around at least two fins of the first unit and connect at least one VFET of the first unit to a power rail of the first unit, and the second unit may include at least one fin connector that is formed around at least one fin of the second unit and connects at least one VFET of the second unit for internal signal routing without connecting to a power rail of the second unit. Here, at least two fins of the first unit and at least one fin of the second unit are arranged adjacent to each other in the cell width direction in the cell architecture.

[0016] According to an embodiment, a method for arranging cells in a cell layout to form a cell architecture including a plurality of vertical field effect transistors (VFETs) is provided. The method may include: arranging a first unit including a fin connector in the cell layout, the fin connector connecting a VFET to a power rail of the first unit and formed around one fin of the first unit; determining characteristics of a second unit to be arranged next to the first unit for at least one fin connector, the at least one fin connector connecting at least one VFET to a power rail of the second unit and formed around at least one fin of the second unit; based on the determined result, performing: a first operation of arranging the second unit next to the first unit in the cell layout and merging a fin connector of the first unit with at least one fin connector of the second unit; a second operation of replacing the first unit with a third unit that is configured to perform the same logical function or operation as the first unit and includes at least two fin connectors that connect at least one VFET of the third unit to a power rail of the third unit and are formed around at least two fins of the third unit; or a third operation of arranging a fill unit next to the first unit and merging a connector connected to a power rail of the fill unit with a fin connector of the first unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings.

[0018] Figure 1A Symbols and schematic diagrams of a NAND3 circuit are shown;

[0019] Figures 1B to 1D Shows a top view of a cell layout according to an embodiment, the cell layout including a two-fin cell, an equivalent two-fin cell, and an equivalent one-fin cell for implementing a NAND3 circuit, respectively;

[0020] Figure 2 Shows a flowchart describing a method for arranging a plurality of cells in a cell layout to form a cell architecture according to an embodiment;

[0021] Figure 3 Shows a flowchart describing a detailed method for arranging a plurality of cells in a cell layout to form a cell architecture according to an embodiment;

[0022] Figure 4 Shows a top view of a cell layout according to an embodiment, in which one-fin NAND3 cells are arranged adjacent to each other to form a cell architecture;

[0023] Figure 5 Shows a top view of a cell layout according to an embodiment, in which one-fin NAND3 cells and two-fin inverter cells are arranged adjacent to each other to form a cell architecture;

[0024] Figure 6 Shows a top view of a cell layout according to an embodiment, in which one-fin NAND3 cells and fill cells are arranged adjacent to each other to form a cell architecture;

[0025] Figure 7 Shows a flowchart describing another method for arranging a plurality of cells in a cell layout to form a cell architecture according to an embodiment;

[0026] Figure 8 Shows a top view of a cell layout according to an embodiment, in which one-fin NAND3 cells and two-fin NAND3 cells are arranged adjacent to each other in the cell layout to form a cell architecture;

[0027] Figure 9 Shows a top view of a cell layout according to an embodiment, in which one-fin NAND3 cells, fill cells 500, and another one-fin NAND3 cell are arranged in a row in the cell layout to form a cell architecture;

[0028] Figure 10 Shows a method for arranging a plurality of VFET cells in a cell layout to form a cell architecture by considering the positions of the bottom S / D regions connected to the power rails in each cell according to an embodiment;

[0029] Figure 11A and Figure 11B Show top views of a two-fin NAND2 cell and a one-fin NAND2 cell for implementing a NAND2 circuit according to an embodiment, respectively;

[0030] Figure 11C Shows a schematic diagram of a NAND2 circuit;

[0031] Figure 12 Shows a cell layout according to an embodiment, in which two one-fin NAND2 cells are arranged adjacent to each other to form a cell architecture; and

[0032] Figure 13 Shows a computer system configured to implement one or more embodiments of the inventive concept according to an embodiment. Detailed Description

[0033] Hereinafter, various embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. These embodiments are all exemplary and may be embodied in many different forms and should not be construed as limiting the inventive concept. On the contrary, these embodiments are provided only so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of the various layers and regions may have been exaggerated, and thus, the drawings are not necessarily drawn to scale and some features may be exaggerated to show details of a particular component or element. Accordingly, the specific structural and functional details disclosed herein should not be construed as restrictive, but merely as a representative basis for teaching those skilled in the art various ways of using the embodiments.

[0034] The embodiments provided herein do not exclude being associated with one or more features of another example or another embodiment consistent with the inventive concept provided or not provided herein. For example, even if what is described in a particular embodiment is not described in different embodiments, unless explicitly stated in its description, such content can be understood as being related to or combined with different embodiments.

[0035] For the purposes of the following description, the terms "upper", "lower", "top", "bottom", "left", and "right" and their derivatives based on context may be related to the disclosed structure as their orientation in the drawings. The same reference numerals in different drawings may refer to the same structural components or elements.

[0036] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on the other element or layer, directly connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0037] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one of..." follows a list of elements, it modifies the entire list of elements and not individual elements in the list. Thus, for example, "at least one of A, B or C" and "A, B and / or C" both mean A or B or C or any combination thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in this document.

[0039] Figure 1A The symbol and schematic diagram of a NAND3 circuit having three gate input terminals A, B, and C and an output terminal Y are shown. The NAND3 circuit can be implemented by Figures 1B to 1D the cells shown in Figures 1B to 1D The top views of a two-fin cell, an equivalent two-fin cell, and an equivalent one-fin cell for implementing the same NAND3 circuit according to an embodiment are shown. Each of the cells shown below will Figures 1B to 1D be referred to as a NAND3 cell.

[0040] Refer to Figure 1B, the NAND3 cell 100 as a two-fin unit includes six P-channel metal-oxide semiconductor (PMOS) VFETs (hereinafter referred to as "PMOS") P1 to P6 and six N-channel metal-oxide semiconductor (NMOS) VFETs (hereinafter referred to as "NMOS") N1 to N6 formed respectively around six fins F1 to F6. Each of the fins F1 and F6 is included in two solid fin regions RFA1 and RFA2 formed on a substrate SUB. Thus, in fact, PMOS P1 to P6 are respectively formed around the fins F1 to F6 included in the solid fin region RFA1, and NMOS N1 to N6 are respectively formed around the fins F1 to F6 included in the solid fin region RFA2. PMOS P1 to P6 are connected to a power rail M1 that supplies a positive voltage Vdd to the NAND3 cell 100 through a multi-fin bottom S / D region RX1 formed around the fins F1 to F6 in the solid fin region RFA1. NMOS N1 and N2 among NMOS N1 to N6 are connected to a power rail M2 that supplies a ground voltage Vss to the NAND3 cell 100 through a multi-fin bottom S / D region RX2 formed around the fins F1 and F2 in the solid fin region RFA2. Here, it should be noted that bottom S / D regions such as the multi-fin bottom S / D regions RX1 and RX2 or a single-fin bottom S / D region can be connected to the power rail through a power contact structure formed under the power rail.

[0041] The power rail M1 and the power rail M2 can be formed of metal, metal compound, or their equivalents. The NAND3 cell 100 further includes three gate connection patterns PB, each of which connects two gate structures of two adjacent PMOSs (e.g., PMOS P1 and P2), and two gate structures of two adjacent NMOSs N1 and N2. On each gate connection pattern PB, a gate contact structure CB is formed to connect four gates to a metal pattern M3 through a via V formed thereon. Each metal pattern M3 is arranged to receive a gate input signal A, B, or C of the NAND3 circuit, as Figure 1A shown. Above the fin F6, a metal pattern M4 is formed to output an output signal Y of the NAND3 circuit, as Figure 1A shown.

[0042] Each of PMOS P1 to P6 and NMOS N1 to N6 includes a top S / D region (not shown) and a bottom S / D region (not shown) to form a VFET having a gate structure. The bottom S / D regions of NMOS N3 to N6 are connected to form a four-fin bottom S / D region RX3, which connects the four NMOS N3 to N6 to each other for internal signal routing without being connected to the power rail M2.

[0043] The NAND3 cell 100 further includes a six-fin top S / D region CA1 formed by connecting the top S / D regions of PMOS P1 to P6, a four-fin top S / D region CA2 formed by connecting the top S / D regions of NMOS N1 to N4, and a two-fin top S / D region CA3 formed by connecting the top S / D regions of NMOS N5 and N6.

[0044] To fabricate the NAND3 cell 100, the bottom S / D regions of each of PMOS P1 to P6 and NMOS N1 to N2 do not need to be formed independently and separately for power or ground connection, but instead, multi-fin bottom S / D regions RX1 and RX2 with sufficient width can be designed to facilitate patterning during the fabrication of the NAND3 cell 100.

[0045] Reference Figure 1C , the NAND3 cell 200 includes five PMOS VFETs (hereinafter referred to as "PMOS") P1 to P5 and five NMOS VFETs (hereinafter referred to as "NMOS") N1 to N5 respectively formed around five fins F1 to F5. Since the VFETs forming the NAND3 cell 200 have the same or substantially the same structure as the VFETs forming the Figure 1B NAND3 cell 100 in Figure 1B , the redundant description is omitted here. Thus, similar to the two-fin bottom S / D region RX2 of the NAND3 cell 100 in Figure 1C , the NAND3 cell 200 also has a two-fin bottom S / D region RX2 for power rail connection, with sufficient width to facilitate patterning during the fabrication of the NAND3 cell 200. The difference between the NAND3 cell 200 and the NAND3 cell 100 is that the NAND3 cell 200 is configured to receive the gate input signal B input only to one PMOS P3 and one NMOS N3, while the NAND3 cell 100 is configured to receive the same gate input signal B input to two PMOS P3 and P4 and two NMOS N3 and N4.

[0046] Reference Figure 1D , the NAND3 cell 300, as a one-fin cell, includes four PMOS P1 to P4 and four NMOS N1 to N4 respectively formed around four fins F1 to F4. Since the VFETs forming the NAND3 cell 300 have the same structure as the VFETs forming Figure 1BThe structures of the VFETs in the NAND3 cell 100 are the same or substantially the same, so redundant descriptions are omitted here. The difference between the NAND3 cell 300 and the NAND3 cell 100 is that: the NAND3 cell 300 is configured to receive the gate input signal A input only to one PMOS P1 and one NMOS N1, and the gate input signal B input only to one PMOS P2 and one NMOS N2, while the NAND3 cell 100 is configured to receive the same gate input signal A input to two PMOS P1 and P2 and two NMOS N1 and N2, and receive the same gate input signal B input to two PMOS P3 and P4 and two NMOS N3 and N4. In addition, the NAND3 cell 300 is different from the NAND3 cells 100 and 200 in that: the NAND3 cell has a fin bottom S / D region RX2 for power rail connection formed around the fin F1 (on which the NMOS N1 is formed), and thus, the width of the fin bottom S / D region RX2 is narrower than the width of the two-fin bottom S / D region RX2 of the NAND3 cells 100 and 200. As described above, although having the advantages of the above-mentioned one-fin cell, it is difficult to pattern the fin bottom S / D region RX2 of the one-fin cell during the design and manufacturing processes.

[0047] Therefore, when forming a cell architecture including a one-fin cell, it is necessary to avoid connecting the fin bottom S / D region of the VFET to the power rail corresponding to the one-fin cell.

[0048] Figure 2 A flowchart showing a method or algorithm (collectively referred to as "method" herein) for arranging a plurality of cells in a cell layout to form or constitute a cell architecture according to an embodiment is shown. Reference is provided Figure 2 The described method is used for cell arrangement in a cell layout to form a cell architecture including at least one NAND3 cell corresponding to the schematic diagram shown in Figure 1A However, the inventive concept is not limited to this embodiment, but can be applied to cell architectures including different cells having different logic circuits configured to perform different logic functions or operations.

[0049] By executing the computer instruction code for implementing the method according to the embodiment, the unit layout and unit architecture mentioned in the embodiments described herein can be provided on a computer screen in the form of a graphical display. The unit architecture can be designed and manufactured to perform one or more predetermined logic functions using a plurality of units included in the unit architecture. Hereinafter, when an element or component (such as a fin of a unit) is described as being arranged beside another element or component (such as another fin of the unit or another unit) to form a unit architecture, it means that the two elements or components are arranged adjacent to each other and are adjacent to each other in the unit width direction, thereby forming the unit architecture.

[0050] Reference Figure 2 , the first unit (which is a one-fin NAND3 unit including four PMOSs and four NMOSs) is set and arranged in the unit layout for forming a desired unit architecture (S10). Here, the first unit of the present embodiment may have the same structure as the Figure 1D shown NAND3 unit 300. Thus, similar to the one-fin bottom S / D region RX2 of the NAND3 unit 300, the first unit includes a one-fin bottom S / D region as a one-fin connector that connects the corresponding NMOS (i.e., Figure 1D the NMOS N1 in) to the power rail in the first unit, and the width of the one-fin bottom S / D region is narrow. In addition, the one-fin bottom S / D region of the NMOS in the first unit is formed around one fin among the plurality of fins included in the first unit. Other components or elements forming the first unit may also have the same structure as the components or elements forming the NAND3 unit 300, and thus, redundant descriptions thereof will be omitted hereinafter.

[0051] Next, at least considering and determining the characteristics of the second unit to be arranged beside the first unit in the unit layout to form or constitute the unit architecture with respect to the connector connected to the power rail in the second unit (S20). When the second unit is a VFET unit, the connector may be the bottom S / D region of at least one VFET included in the second unit, as described hereinafter. The characteristics of the second unit may include the position of at least one fin surrounded by the connector of the second unit.

[0052] According to the result determined in operation S20, the second unit is arranged beside the first unit in the unit layout to form the unit architecture, and the connector of the second unit is merged with the one-fin bottom S / D region of the first unit, or the first unit is replaced with a third unit, which is configured to perform the same logic function or operation as the first unit and includes at least a two-fin bottom S / D region as at least a two-fin connector that connects the corresponding at least one NMOS to the power rail of the third unit and is formed around at least two fins of the third unit (S30).

[0053] Figure 3 A flowchart is shown that describes a detailed method for arranging a plurality of cells in a cell layout to form a desired cell architecture according to an embodiment. The method begins with the same operation as the previous embodiment, that is, arranging a first cell including a fin bottom S / D region in the cell layout, the fin bottom S / D region connecting the corresponding NMOS surrounded by the fin bottom S / D region to the power rail of the first cell, and forming around one of the plurality of fins included in the first cell (S110).

[0054] Next, when a second cell to be arranged next to the first cell is arranged next to the first cell, it is determined whether at least one fin surrounded by a connector connected to the power rail of the second cell is arranged next to the one fin of the first cell, so that a fin bottom S / D region of the first cell can be merged with the connector of the second cell (S120).

[0055] Based on the result determined at operation S120 being "yes", the second cell is arranged next to the first cell to form a cell architecture (S130), and further, a fin bottom S / D region unit of the first cell is merged with the connector of the second cell (S140), so that the merged bottom S / D region (that is, the fin bottom S / D region of the first cell merged with the connector of the second cell) can be easily patterned during the manufacturing process of the cell architecture.

[0056] However, based on the result determined at operation S120 being "no", the first cell is replaced with a third cell, which is configured to perform the same logical function or operation as the first cell and includes at least two fin bottom S / D regions, the at least two fin bottom S / D regions connecting the corresponding at least one NMOS to the power rail of the third cell and forming around at least two fins of the third cell (S150). At this time, since the at least two fin bottom S / D regions of the third cell have a sufficient width to be easily patterned during the manufacturing process of the cell architecture, the at least two fin bottom S / D regions in the third cell are not merged with the connector of the second cell (S160). Here, the at least two fin bottom S / D regions of the third cell can be formed by connecting or merging at least two bottom S / D regions of at least one NMOS formed around at least two fins in the third cell. According to an embodiment, the third cell (S150) replacing the first cell can also be a NAND3 cell configured to perform the same logical function or operation as the first cell.

[0057] According to an embodiment, the second unit may include a VFET unit having at least one fin, wherein at least one fin bottom S / D region is formed around the at least one fin to connect at least one NMOS formed on the at least one fin to the power rail of the VFET unit, or the second unit may include a fill unit that includes only one fin, wherein a connector is formed around the one fin to connect to the power rail of the fill unit. According to an embodiment, the only one fin of the fill unit may be referred to as a pseudo fin, which is the only fin in the fill unit.

[0058] When the second unit includes the VFET unit as described above, based on the determination result made in operation S120 being "no", a replacement operation (S150) and subsequent non-merging operation (S160) are performed. That is, when the VFET unit is arranged next to the first unit, it is determined that at least one fin surrounded by at least one fin bottom S / D region of the VFET unit connecting at least one NMOS to the power rail of the VFET unit is not arranged next to one fin of the first unit to form a cell architecture.

[0059] Meanwhile, when the second unit is the VFET unit as described above, based on the determination result made in operation S120 being "yes", an arrangement operation (S130) and a merging operation (S140) are performed. Here, when the VFET unit is arranged next to the first unit, it is determined that at least one fin of the VFET unit surrounded by at least one fin bottom S / D region connecting at least one NMOS to the power rail of the VFET unit is arranged next to one fin of the first unit to form a cell architecture, as shown in the following Figure 4 shown.

[0060] Figure 4 A top view of a cell layout according to an embodiment is shown, in which one-fin NAND3 units are arranged adjacent to each other to form a cell architecture.

[0061] Refer to Figure 4 , in the cell layout, NAND3 unit 300A and NAND3 unit 300B, both of which are one-fin NAND3 units, are arranged adjacent to each other. NAND3 unit 300B may have the same structure as the Figure 1D shown NAND3 unit 300, and thus, repeated descriptions are omitted hereinafter. However, as described below, NAND3 unit 300A is different from NAND3 unit 300B in the position of the one-fin bottom S / D region connected to the power rail.

[0062] In Figure 4In the cell layout shown, a fin bottom S / D region RX2A formed around the rightmost fin F4A and connected to a power rail M2A in the NAND3 cell 300A is merged with a bottom S / D region RX2B formed around the leftmost fin F1B and connected to a power rail M2B in the NAND3 cell 300B. Thus, as Figure 4 shown, during the fabrication of the cell architecture, the merged fin bottom S / D regions RX2A and RX2B can be easily patterned. Here, as Figure 4 shown, the power rail M2B can also be connected to the power rail M2A. However, according to an embodiment, the two power rails M2A and M2B may not be connected to each other.

[0063] As Figure 4 shown, the NAND3 cells 300A and 300B are identical logic cells configured to perform the same logic function or operation. However, at the position of the NAND3 cell 300A, different logic cells configured to perform different logic functions or operations can be arranged in the cell layout such that the bottom S / D regions connected to the power rail M2A or M2B can be wider. For example, as described below Figure 5 shown, a two-fin inverter cell can be arranged next to the NAND3 cell 300B, and the two-fin inverter cell includes a two-fin bottom S / D region connected to a power rail of the two-fin inverter cell.

[0064] Figure 5 A top view of a cell layout according to an embodiment is shown, in which a one-fin NAND3 cell and a two-fin inverter cell are arranged adjacent to each other to form a cell architecture.

[0065] Referring to Figure 5 , according to an embodiment, in the cell layout, the NAND3 cell 300B and the two-fin inverter cell 400 are arranged adjacent to each other. Figure 5 The NAND3 cell 300B shown in Figure 1D and Figure 4 can be a one-fin NAND3 cell having the same structure as the NAND3 cells 300 and 300B, respectively, and thus, repeated descriptions are omitted hereinafter.

[0066] In Figure 5 the cell layout shown, a fin bottom S / D region RX2B formed around the leftmost fin F1B and connected to a power rail M2B in the NAND3 cell 300B is merged with a two-fin bottom S / D region RX2I formed around two fins F1A and F2A and connected to a power rail M2I in the two-fin inverter cell 400. Thus, as Figure 5As shown, during the manufacturing of the cell architecture, the merged single-fin bottom S / D region RX2B and double-fin bottom S / D region RX2I can be easily patterned. Here, as Figure 5 shown, the power rail M2B can also be connected to the power rail M2I. However, according to an embodiment, the two power rails M2B and M2I may not be connected to each other.

[0067] Meanwhile, when the second cell is a fill cell as described above in Figure 3 the embodiment, the arrangement operation (S130) and the merging operation (S140) can be performed based on determining that the fill cell includes a connector formed by a power rail connected to the fill cell and surrounding a unique fin (possibly a pseudo-fin) of the fill cell, and the fill cell can be arranged next to a fin of the first cell in the cell layout as shown in Figure 6 to form the cell architecture.

[0068] Figure 6 A top view of a cell layout according to an embodiment is shown, in which a single-fin NAND3 cell and a fill cell are arranged adjacent to each other to form a cell architecture.

[0069] Referring to Figure 6 , the NAND3 cell 300B and the fill cell 500 are arranged adjacent to each other in the cell layout. The NAND3 cell 300B may be a single-fin NAND3 cell having the same structure as the NAND3 cells 100 and 300B shown in Figure 1D , Figure 4 and Figure 5 respectively, and thus, repeated descriptions are omitted hereinafter.

[0070] In Figure 6 the shown cell layout, the single-fin bottom S / D region RX2B formed around the leftmost fin F1B in the NAND3 cell 300B and connected to the power rail M2B is merged with the connector C formed around a single pseudo-fin DF in the fill cell 500 and connected to the power rail M2F. Thus, as shown in Figure 6 , during the manufacturing of the cell architecture, the merged single-fin bottom S / D region RX2B and the connector C can be easily patterned. According to an embodiment, the connector C of the fill cell 500 may be the bottom S / D region of a pseudo-NMOS formed on the pseudo-fin DF. Here, as shown in Figure 6 , the power rail M2B can also be connected to the power rail M2F. However, according to an embodiment, the two power rails M2B and M2F may not be connected to each other.

[0071] Returning to reference Figure 3, based on the result determined at operation S120 being “No”, that is, when the second cell to be arranged next to the first cell is arranged next to the first cell, if it is determined that at least one fin surrounded by the connector connected to the power rail of the second cell is not arranged next to one fin of the first cell, the first cell is replaced with a third cell that is configured to perform the same logical function or operation as the first cell and includes at least two fin bottom S / D regions connected to the power rail of the third cell and formed around at least two fins (S150). However, according to reference Figure 7 In some embodiments, operation S150 may be replaced by a different operation.

[0072] Figure 7 A flow chart describing another method for arranging a plurality of cells in a cell layout to form a desired cell architecture according to an embodiment is shown.

[0073] In the method according to this embodiment, repeating Figure 3 Operations S110, S120, S130 and S140 are shown, and therefore, for the sake of brevity, their description is omitted herein. However, operations S150 and S160 are replaced by different operations, and the different operations include filling the unit (e.g. Figure 6 The filler cell 500 in the embodiment of the present invention is arranged next to the first cell to merge the connector of the filler cell with the bottom S / D region of a fin of the first cell (S170), and then the second cell is arranged next to the filler cell, wherein when the second cell is arranged to the first cell, at least one fin surrounded by the connector connected to the power rail of the second cell is not arranged next to the bottom S / D region of a fin of the first cell, but is arranged next to the filler cell, so that the second cell, the filler cell and the first cell are arranged in a row in the cell layout to form a cell architecture (S180), as will be described later Figure 9 shown.

[0074] Figure 8 A top view of a cell layout according to an embodiment is shown, wherein a one-fin NAND3 cell and a two-fin NAND3 cell are arranged adjacent to each other in the cell layout to form a cell architecture.

[0075] refer to Figure 8 In the cell layout, the one-fin NAND3 cell 300B and the two-fin NAND3 cell 300C are arranged adjacent to each other. The cell layout is generated according to the above operations S30 and S150. Figures 4 - 6The NAND3 cell 300B shown in [the figure] is arranged in the cell layout (S10 and S110). Then, when another NAND3 cell 300B is arranged beside the first NAND3 cell 300B on the left side of the first NAND3 cell 300B, it is determined that the two one-fin bottom S / D regions RX2B of the two NAND3 cells 300B cannot be merged (S20 and S120). Therefore, the first NAND3 cell 300B is replaced with a NAND3 cell 300C of a two-fin cell (S30 and S150). The NAND3 cell 300C that replaces the first NAND3 cell 300B includes a two-fin bottom S / D region RX2C formed around two fins and connected to the power rail M2C. The two-fin bottom S / D region RX2C does not merge with the one-fin bottom S / D region RX2B (S160).

[0076] Figure 9 A top view of a cell layout according to an embodiment is shown, in which a one-fin NAND3 cell, a fill cell 500, and another one-fin NAND3 cell are arranged in a row in the cell layout to form a cell architecture.

[0077] Reference Figure 9 , the NAND3 cell 300A, the fill cell 500, and the NAND3 cell 300B are arranged in a row in the cell layout. Figure 9 The NAND3 cells 300A and 300B shown can be one-fin NAND3 cells having the same structure as the Figure 1D and Figures 4 - 6 shown NAND3 cells 300 and 300B, and Figure 9 the fill cell 500 shown can have the same structure as the Figure 6 shown fill cell. Therefore, repeated descriptions are omitted hereinafter.

[0078] In Figure 9 the shown cell layout, the fill cell 500 is arranged beside the NAND3 cell 300B to merge the connector C of the fill cell 500 with the one-fin bottom S / D region RX2B formed around the leftmost fin F1B in the NAND3 cell 300B and connected to the power rail M2B. The cell layout also shows that the NAND3 cell 300A is arranged beside the fill cell 500 without merging the bottom S / D region RX2A formed around the leftmost fin F1A and connected to the power rail M2A with the connector C of the fill cell 500 or the one-fin bottom S / D region RX2B of the NAND3 cell 300B. By using the fill cell 500, Figure 9 the cell layout shown in [the figure] can maintain the NAND3 cell 300B to form a cell architecture without replacing the NAND3 cell 300B with another cell (such as Figure 8The NAND3 cell 300C shown in

[0079] According to the above embodiments, in the cell layout for designing a desired cell architecture including a fin unit, a fin bottom S / D region that is difficult to pattern can be avoided.

[0080] Return to reference Figure 4 , which shows a cell layout in which two NAND3 cells 300A and 300B are arranged adjacent to each other to form a cell architecture by merging the bottom S / D regions RX2A and RX2B. Note that the bottom S / D region RX2A of the NAND3 cell 300A should be formed around the rightmost fin F4A of the NAND3 cell 300A, and the bottom S / D region RX2B of the NAND3 cell 300B should be formed around the leftmost fin F1B of the NAND3 cell 300B. In addition, Figure 4 The cell layout of shows that the bottom S / D region RX2A of the NAND3 cell 300A is connected to the power rail M2A as a ground rail and is formed at the lower part of the rightmost fin included in the real fin region RFA2, and the bottom S / D region RX2B of the NAND3 cell 300B is connected to the power rail M2B as a ground rail and is formed at the lower part of the leftmost fin F1B included in the real fin region RFA2. Therefore, according to the embodiment, the cell arrangement method may include an operation or step of determining the positions of connectors (such as the bottom S / D regions connected to the cell power rails) connected to the cell power rails at the four corners of the cell (corresponding to the regions of the leftmost fin in the real fin region RFA1, the leftmost fin in the real fin region RFA2, the rightmost fin in the real fin region RFA1, and the rightmost fin in the real fin region RFA2). The foregoing considerations can also be applied to designing a cell architecture including more than two logic units.

[0081] Figure 10 Shows a method of arranging a plurality of VFET cells in a cell layout to form a cell architecture in consideration of the positions of the bottom S / D regions connected to the power rails in each cell.

[0082] Reference Figure 10 , arrange cells 1, 3, and 5 having bottom S / D regions connected to the power rails of the corresponding cells and formed around the rightmost fin at odd positions, i.e., the 1st, 3rd, and 5th positions in the cell width direction in the cell layout, and arrange cells 2 and 4 having bottom S / D regions connected to the power rails of the corresponding cells and formed around the leftmost fin at even positions, i.e., the 2nd and 4th positions in the cell width direction in the cell layout. Subsequently, merge the bottom S / D regions of cells 1 and 2, and merge the bottom S / D regions of cells 3 and 4.

[0083] Figure 10Further shown is that the bottom S / D region of unit 6 to be arranged beside unit 5 is connected to the power rail of unit 6 only on the rightmost fin of unit 6. In this case, a fill unit can be arranged between unit 5 and unit 6, and the fill unit has a connector connected to the power rail of the fill unit, such that the connector of the fill unit can be merged with the bottom S / D region of unit 5. Here, the fill unit can have the same structure as discussed in Figure 6 and Figure 9 discussed.

[0084] In the embodiment described in reference Figure 10 each bottom S / D region of units 1 to 6 is a fin bottom S / D region. However, the inventive concept is not limited thereto, rather, one of the two merged bottom S / D regions can be at least a two-fin bottom S / D region formed around two or more fins of the corresponding unit and connected to the power rail of the corresponding unit.

[0085] The foregoing embodiments provide various methods for arranging units in a unit layout to form a unit architecture, in which the arrangement of a fin bottom S / D region as a connector connected to the power rail of a unit is avoided. However, the inventive concept is not limited to the bottom S / D region connected to the power rail as a connector, but can be extended to at least a top S / D contact structure formed on the top S / D region of a VFET, because the top S / D contact structure rather than the bottom S / D region can be connected to the power rail of a unit as a connector. In this case, the top S / D contact structure can be connected to the power rail through a power contact structure formed under the power rail.

[0086] Figure 11A and Figure 11B respectively show top views of a two-fin NAND2 unit and a one-fin NAND2 unit implementing a NAND2 circuit according to an embodiment. Figure 11C A schematic diagram showing a NAND2 circuit is shown.

[0087] Reference Figure 11A and Figure 11B show a NAND2 unit 600 as a two-fin unit and a NAND2 unit 700 as a one-fin unit implementing Figure 11C of a NAND2 circuit. The NAND2 unit 600 includes four PMOS P1 to P4 and four NMOS N1 to N4 formed around four fins F1 to F4, and the NAND2 unit 700 includes three PMOS P1 to P3 and three NMOS N1 to N3 formed around three fins F1 to F3. Since most components constituting the NAND2 unit 600 and the NAND2 unit 700 are the same as Figure 1DThose components described for the NAND3 cell 300 are similar, except for the number and location of the components, so the redundant description is omitted herein.

[0088] However, compared with Figure 1D the NAND3 cell 300 in , the NAND2 cell 600 is characterized in that, instead of the S / D region RX2 at the bottom of one fin, the two-fin top S / D contact structure CA formed around the two fins F1 and F2 is connected to the power rail M2 that supplies the ground voltage to the NMOS N1 and N2. Therefore, since it has a sufficient width during the manufacturing process of the NAND2 cell 600, the two-fin top S / D contact structure CA can be easily patterned.

[0089] On the contrary, since the NAND2 cell 700 is a one-fin cell, the NAND2 cell 700 has a narrow one-fin top S / D contact structure CA that is formed around the fin F1 and connected to the power rail M2 that supplies the ground voltage to the NMOS N1. Therefore, when designing and manufacturing a cell architecture including the NAND2 cell 700, it will be difficult to pattern the top S / D contact structure CA.

[0090] Therefore, just as Figure 4 shown in , the S / D region RX2A at the bottom of one fin of the NAND3 cell 300A is merged with the S / D region RX2B at the bottom of one fin of the NAND3 cell 300B, it can be considered that when two NAND2 cells need to be arranged adjacent to each other to form a desired cell architecture, the two one-fin top S / D contact structures of these two NAND2 cells can be merged to provide a wider top S / D contact structure, as described below.

[0091] Figure 12 Fig. shows a cell layout according to an embodiment, in which two one-fin NAND2 cells are arranged adjacent to each other to form a cell architecture.

[0092] Referring to Figure 12 , the NAND2 cell 700A and the NAND2 cell 700B are arranged adjacent to each other in the cell layout. The NAND2 cell 700A has a one-fin top S / D contact structure CA1 formed around the rightmost fin F3A and connected to the power rail M2A, and the NAND2 cell 700B has another one-fin top S / D contact structure CA2 formed around the leftmost fin F1B and connected to the power rail M2B. In addition, these two one-fin top S / D contact structures CA1 and CA2 are merged so that the merged one-fin top S / D contact structures CA1 and CA2 can be easily patterned during the manufacturing of the cell architecture. Here, as Figure 12As shown, power rail M2B can also be connected to power rail M2A. However, according to an embodiment, the two power rails M2A and M2B may not be connected to each other.

[0093] According to the above embodiment, it is possible to more easily design and manufacture a higher density cell architecture, in which a fin cell including at least one fin connector connected to a power rail is arranged next to another cell including at least one fin connector connected to the power rail of the other cell, such that the two connectors are combined to provide a wider connector, thereby facilitating patterning. As described above, the connectors mentioned herein may include a bottom S / D region, a top S / D contact structure, or a fill cell.

[0094] In the above embodiment, the connectors combined with other connectors are all connected to a power rail providing a ground voltage. However, the inventive concept is not limited thereto, and the inventive concept may also be applicable when the same connectors are connected to a power rail providing a power voltage opposite to the ground voltage.

[0095] The method described in the above embodiment is provided for the cell arrangement of NAND3 cells and NAND2 cells. However, the inventive concept may also be applicable to the cell arrangement of different logic cells, such as but not limited to this or an inverter 211 (OAI211) cell and an AND-OR-inverter 21 (AOI21) cell, to form a desired cell architecture.

[0096] The operations or steps of the above method may be embodied as computer-readable code on a computer-readable recording medium or transmitted through a transmission medium. A computer-readable recording medium is any data storage device that can store data that can be read by a computer system later. Examples of computer-readable recording media include read-only memory (ROM), random access memory (RAM), compact disc (CD)-ROM, digital versatile disc (DVD), magnetic tape, floppy disk, and optical data storage devices, but are not limited thereto. The transmission medium may include a carrier wave transmitted through the Internet or various types of communication channels. The computer-readable recording medium may also be distributed on network-coupled computer systems so as to store and execute the computer-readable code in a distributed manner.

[0097] Figure 13 A computer system configured to implement one or more embodiments of the inventive concept according to an embodiment is shown.

[0098] Reference Figure 13, which shows a computer system for implementing one or more of the above embodiments. The computer 1000 may include at least one processor 1010 and at least one memory 1020. The processor 1010 may include at least one central processing unit (CPU) implemented by at least one microprocessor, or may be embodied as various numbers of hardware, software, and / or firmware structures that execute the methods described above in one or more of the above embodiments. The memory 1020 may include RAM, non-volatile memory such as ROM, flash memory, or a combination thereof. In addition, the computer 1000 may include a storage device 1030 that is fixed therein or removable therefrom, including but not limited to magnetic storage devices, optical storage devices, etc. The storage device 1030 may store computer-readable code that embodies the above methods and is loaded onto the memory 1020 for execution by the processor 1010. The storage device 1030 may include a unit library that includes a plurality of units including the units described in the above embodiments. The computer 1000 may further include an input interface 1040, such as a keyboard, mouse, touch sensor, camera, microphone, etc., and an output interface 1050, such as one or more displays, speakers, printers, etc. The input interface 1040 is configured to receive user input to control the computer 1000 to execute one or more of the above methods in a wired or wireless manner. The output interface 1050 may provide the user with a plurality of units, unit layouts, and / or unit architectures described in the above embodiments in a displayed form on a computer screen. The computer 1000 may also include a communication interface 1060 that is combined with or separated from the input interface 1040 and / or the output interface 1050 to receive user input. When the above computer-readable code and / or unit library are stored in an external memory, they may be received at the computer 1000 in a wired or wireless manner through the communication interface 1060.

[0099] The foregoing is an illustration of embodiments and should not be construed as a limitation thereof. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the above embodiments without substantially departing from the inventive concept.

Claims

1. A cell architecture includes at least a first cell and a second cell arranged adjacent to each other in a cell width direction. Wherein the first cell includes a fin connector formed around one fin among a plurality of fins of the first cell and connecting a vertical field effect transistor (VFET) of the first cell to a power rail of the first cell. Wherein the second cell includes a connector connected to a power rail of the second cell. Wherein the one fin of the first cell and the connector of the second cell are arranged adjacent to each other in the cell width direction in the cell architecture, and Wherein the fin connector of the first cell and the connector of the second cell are merged.

2. The cell architecture according to claim 1, wherein the connector of the second cell includes at least one fin connector formed around at least one fin of the second cell and connecting at least one VFET of the second cell to a power rail of the second cell.

3. The cell architecture according to claim 2, wherein the fin connector of the first cell includes a fin bottom source / drain (S / D) region of the VFET of the first cell, and the at least one fin connector of the second cell includes at least one fin bottom S / D region of the at least one VFET of the second cell.

4. The cell architecture according to claim 2, wherein the fin connector of the first cell includes a fin top S / D contact structure formed on a top source / drain (S / D) region of the VFET of the first cell, and the at least one fin connector of the second cell includes at least one fin top S / D contact structure formed on at least one top S / D region of the at least one VFET of the second cell.

5. The cell architecture according to claim 2, wherein the first cell and the second cell respectively constitute a first logic circuit and a second logic circuit, and the first logic circuit and the second logic circuit are configured to perform the same logic function or operation.

6. The cell architecture according to claim 2, wherein the first cell and the second cell respectively constitute a first logic circuit and a second logic circuit, and the first logic circuit and the second logic circuit are configured to perform different logic functions or operations.

7. The cell architecture according to claim 2, wherein the at least one VFET of the second cell is at least one pseudo-VFET configured not to receive a gate input signal.

8. The unit architecture according to claim 1, wherein the connector of the second unit is formed around one fin that is the only fin of the second unit.

9. The unit architecture according to claim 1, further comprising a third unit, the third unit including at least one fin connector formed around at least one fin of the third unit for internal signal routing without being connected to the power rail of the third unit, and wherein the third unit is arranged beside the second unit such that at least one fin of the third unit is arranged beside at least one fin of the second unit in the unit width direction in the unit architecture.

10. The unit architecture according to claim 9, wherein at least one fin of the third unit and at least one fin of the second unit do not merge.

11. The unit architecture according to claim 9, wherein the third unit further includes another at least one fin connector formed around another at least one fin of the third unit to connect at least one VFET included in the third unit to the power rail of the third unit, and wherein at least one fin of the third unit is arranged between another at least one fin of the third unit and at least one fin of the second unit in the unit width direction in the unit architecture.

12. A unit architecture, including a first unit and a second unit arranged adjacent to each other in the unit width direction, wherein the first unit includes at least two fin connectors formed around at least two fins of the first unit and connecting at least one vertical field effect transistor (VFET) of the first unit to the power rail of the first unit, wherein the second unit includes at least one fin connector formed around at least one fin of the second unit to connect at least one VFET of the second unit for internal signal routing without being connected to the power rail of the second unit; and wherein at least two fins of the first unit and at least one fin of the second unit are arranged adjacent to each other in the unit width direction in the unit architecture.

13. The unit architecture according to claim 12, wherein at least two fin connectors of the first unit are at least two fin bottom source / drain (S / D) regions of at least one VFET of the first unit, and at least one fin connector of the second unit is at least one fin bottom S / D region of at least one VFET of the second unit.

14. The cell architecture according to claim 12, wherein the at least two fin connectors of the first cell are at least two fin top S / D contact structures formed on at least two top S / D regions of at least one VFET of the first cell, and the at least one fin connector of the second cell is at least one fin top S / D contact structure formed on at least one top S / D region of at least one VFET of the second cell.

15. A method for arranging cells in a cell layout to form a cell architecture including a plurality of vertical field effect transistors (VFETs), the method comprising: Arrange a first unit in the unit layout, the first unit including a fin connector that connects a VFET to a power rail of the first unit and is formed around one fin of the first unit; Determine whether at least one fin surrounded by a connector that will be connected to a power rail of a second unit is arranged beside the one fin of the first unit for at least one fin connector, wherein the second unit is to be arranged beside the first unit, and wherein the at least one fin connector connects at least one VFET to the power rail of the second unit and is formed around at least one fin of the second unit; And Based on the result of the determination, perform: A first operation of arranging the second unit beside the first unit in the unit layout and merging the one fin connector of the first unit with the at least one fin connector of the second unit, A second operation of replacing the first unit with a third unit, wherein the third unit is configured to perform the same logical function or operation as the first unit and includes at least two fin connectors that connect at least one VFET of the third unit to a power rail of the third unit and are formed around at least two fins of the third unit, or A third operation of arranging a fill unit beside the first unit and merging a connector connected to a power rail of the fill unit with the one fin connector of the first unit, wherein the first operation is performed based on the result of the determination being "yes", and one of the second operation and the third operation is performed based on the result of the determination being "no".

16. The method according to claim 15, wherein in the fill cell, the connector is formed around the only fin of the fill cell.

17. The method according to claim 16, wherein the connector of the fill cell includes bottom S / D regions of pseudo VFETs configured not to receive gate input signals.

18. The method according to claim 15, wherein in the second cell, the at least one fin connector includes one of the following: at least one fin bottom S / D region of the at least one VFET; and at least one fin top S / D contact structure formed on at least one top S / D region of the at least one VFET and connected to a power rail of the second cell, wherein based on the result of the determination being "no", the third operation is performed, and wherein the method further includes: Arrange the second unit beside the fill unit so that the second unit, the fill unit, and the first unit are arranged in a row in the unit width direction in the unit layout, thereby forming the unit architecture.

19. The method according to claim 15, wherein the cell architecture includes a plurality of cells, the plurality of cells including the first cell and the second cell, and wherein the method further includes: In each of the plurality of units, determine the position of at least one fin surrounded by at least one fin connector connected to a power rail; Arrange a plurality of first units including the first unit at even positions in the unit width direction of the unit layout, wherein each first unit includes a fin connector that is connected to a power rail of each first unit and is formed around the leftmost single fin provided for at least one VFET; Arrange a plurality of second units including the second unit at odd positions in the unit width direction of the unit layout such that each second unit is arranged between two adjacent first units among the plurality of first units, and wherein each second unit includes at least one fin connector that is connected to a power rail of each second unit and is formed around at least one fin on the rightmost side provided for at least one VFET; And Merge the one fin connector of each first unit with the at least one fin connector of each second unit arranged beside each first unit.

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