Methods and apparatus related to forming barrier materials on electrodes

Abstract

The present application relates to methods and apparatuses related to forming barrier materials on electrodes. Methods, apparatuses and systems related to forming barrier materials on electrodes are described. An example method includes: forming a top electrode of a storage node on a dielectric material in a semiconductor manufacturing sequence; and forming the barrier material on the top electrode in situ in a semiconductor manufacturing device to reduce damage to the dielectric material when it is in an ex-situ position in the semiconductor manufacturing device.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods, and more particularly to forming a barrier material on an electrode to reduce oxidation of the electrode. Background Art

[0002] Memory devices are usually provided in a computer or other electronic device in the form of an internal semiconductor integrated circuit. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM) and flash memory, etc. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used in various electronic applications requiring high memory density, high reliability and low power consumption. Compared to non-volatile memory cells (e.g., flash memory cells) that do not require power to retain the stored state, volatile memory cells (e.g., DRAM cells) require power to retain their stored data state (e.g., through a refresh process). However, the speed of operating (e.g., programming, reading, erasing, etc.) various volatile memory cells such as DRAM cells may be faster than the speed of operating various non-volatile memory cells such as flash memory cells. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method comprising: forming a top electrode of a storage node on a dielectric material in a semiconductor manufacturing sequence; and forming a barrier material in situ on the top electrode in a semiconductor manufacturing device to reduce damage to the dielectric material that occurs when the dielectric material is in an off-site position in the semiconductor manufacturing device.

[0004] Some embodiments of the present disclosure provide a device comprising: a top electrode; a barrier material formed on a first surface of the top electrode; and a dielectric material, wherein a second surface of the top electrode is in direct contact with the dielectric material.

[0005] Some embodiments of the present disclosure provide a device comprising: a top electrode; a barrier material formed within the top electrode; and a dielectric material, wherein a surface of the top electrode is in direct contact with the dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A-1C Example cross-sectional top views of storage nodes including a barrier material formed on an electrode of the storage node according to various embodiments of the present disclosure are shown.

[0007] Figure 2 Shown Figure 1A An example cross-sectional side view of the storage node shown in FIG. 1 is taken along cut line 2 - 2 .

[0008] Figure 3 Cross-sectional views of a working surface of a semiconductor structure at a point in time in a semiconductor fabrication sequence are shown according to various embodiments of the present disclosure.

[0009] Figure 4 Cross-sectional views of a working surface of a semiconductor structure including a barrier material at a point in time in a semiconductor fabrication sequence according to various embodiments of the present disclosure are shown.

[0010] Figures 5A-5C Cross-sectional views of a working surface of a semiconductor structure including a barrier material at a point in time in a semiconductor fabrication sequence according to various embodiments of the present disclosure are shown.

[0011] Figure 6 is a functional block diagram of an apparatus for implementing an example semiconductor fabrication sequence according to various embodiments of the present disclosure.

[0012] Figure 7 is a flow chart of an example method for forming a barrier material according to various embodiments of the present disclosure.

[0013] Figure 8 A functional block diagram of a computing system including at least one memory array having an architecture formed according to various embodiments of the present disclosure is presented. DETAILED DESCRIPTION

[0014] Various types of memory devices including arrays of volatile and / or nonvolatile memory cells (e.g., memory arrays) may include thin electrodes, such as top electrodes of capacitor structures. For example, the thickness of the top electrode may be about twenty angstroms. Thin electrodes may be particularly susceptible to oxidation between semiconductor fabrication sequences where the electrode may leave the controlled gas environment (i.e., "ex situ") of the semiconductor fabrication equipment (e.g., located outside a vacuum chamber and exposed to air). In order to reduce the adverse effects of subsequent steps of the fabrication process on the material below the electrode and / or to reduce oxidation of the electrode, at least one embodiment of the present disclosure includes forming a barrier material on the electrode. Forming a barrier material on a top electrode is used herein as an illustrative example. However, embodiments of the present disclosure are not limited thereto. For example, at least one embodiment may include forming a barrier material on a bottom electrode.

[0015] In at least one embodiment, the resistivity of the barrier material can be higher than the resistivity of the electrode (the conductivity of the barrier can be lower than the conductivity of the electrode), so that electrical conduction through the electrode can be less than electrical conduction through the electrode material alone. However, electrical conduction through the barrier material may be less than electrical conduction through oxide material formed on the electrode due to oxidation of the electrode, resulting in a net increase in conductivity relative to oxidation.

[0016] The fabrication of semiconductor structures, such as storage nodes of memory devices, may involve moving semiconductor wafers in which the semiconductor structures are formed in a vacuum environment (i.e., "in situ") and outside of a vacuum environment (i.e., "ex situ") according to a particular semiconductor fabrication sequence. This may include using multiple semiconductor chambers to perform various semiconductor fabrication sequences. The semiconductor wafer and the semiconductor structures formed thereon may be transported between different semiconductor fabrication equipment during the semiconductor fabrication sequence. During transport between semiconductor fabrication equipment, the semiconductor structures may be exposed to the surrounding environment (e.g., oxygen, moisture, and other elements in the air), which may cause the exposed surface of the metal material (e.g., the top electrode) to oxidize.

[0017] Oxidation of the exposed surface may result in the formation of an oxide material (e.g., a metal oxide material) on the exposed surface. The resistivity of the oxide material may be higher than the resistivity of the unoxidized metal material (the conductivity of the oxide material may be lower than the conductivity of the unoxidized metal material), such that electrical conduction through the metal material is inhibited by the oxide formed on the metal material. Therefore, oxidation of the metal material may adversely affect the performance and / or operation of the resulting semiconductor device. The timing of the semiconductor structure ex situ transport may become important, but to a small extent. Therefore, a tight processing sequence window may be used to avoid oxidation.

[0018] A memory device may include a thin layer of a metal material that serves as a component of a storage node (e.g., a top electrode of a capacitor structure). For example, in some architectures, a capacitor cell of a DRAM device may include a top electrode that includes a metal material having a thickness of twenty angstroms or less. For example, a layer of an oxide material having a thickness of two to three angstroms formed on a layer of a metal material having a thickness of twenty angstroms may significantly inhibit electrical conduction through the metal material.

[0019] At least one embodiment of the present disclosure includes: forming a top electrode of a storage node on a dielectric material in a semiconductor manufacturing sequence; and forming a barrier material in situ on the top electrode in a semiconductor processing device to reduce oxidation of the top electrode that occurs when the top electrode is in an ectopic position of the semiconductor manufacturing device. Forming the barrier material in situ in the semiconductor manufacturing device can reduce or eliminate the risk of oxidation of the top electrode. The top electrode may not be exposed to oxygen while in the semiconductor manufacturing device. For example, the top electrode may be maintained in a gas-controlled chamber that is isolated from the surrounding environment (in situ), and oxygen may not be present or may not be used to form the top electrode or the barrier material. The barrier material provides a barrier to oxygen, moisture, and / or other elements that may be in an ectopic position of the semiconductor processing device, thereby reducing the risk of damaging materials below the top electrode and / or oxide materials formed on the top electrode due to oxidation of the top electrode.

[0020] It is worth noting that although the present disclosure discusses (e.g., illustrates) processes for top electrodes of storage nodes in the form of capacitor cells in the context of DRAM memory arrays, embodiments are not limited to such example structures, circuit systems, or device formations in the form of semiconductor fabrication sequences. Embodiments may encompass forming barrier materials on other semiconductor components (such as access lines (e.g., word lines), sense lines (e.g., digit lines, bit lines, etc.), or otherwise conductive surfaces) and resulting devices formed according to the techniques described herein.

[0021] Additionally or alternatively, as design rules shrink, chemicals used in semiconductor manufacturing sequences for forming other semiconductor structures to form semiconductor devices, for example, after forming the top electrode, may damage dielectric materials below the top electrode. The top metal material of the top electrode may include grains on a specific surface of the top electrode. The gaps between the grain boundaries of the metal material may provide diffusion paths for gases and liquids used in subsequent semiconductor manufacturing sequences to pass through the metal material to reach the dielectric material below. For example, chlorine species may corrode the dielectric material. Forming a barrier material in situ on the top electrode as described herein can reduce or even eliminate the damage caused to the dielectric material below by the chemicals used in the subsequent semiconductor manufacturing sequence. In at least one embodiment, the barrier material may at least partially fill the gaps between the grain boundaries of the metal material of the top electrode. In at least one embodiment, the barrier material may amorphize the surface of the top electrode where the barrier material is formed. In this way, the diffusion paths through which gases and liquids used in subsequent semiconductor manufacturing sequences may be able to reach the dielectric material below are blocked, thereby protecting the dielectric material below.

[0022] The present disclosure includes methods, devices and systems related to forming a barrier material on a top electrode to reduce oxidation of the top electrode when it is in an ex-situ position of a semiconductor manufacturing device. Examples of the methods described herein include: forming a top electrode of a storage node on a dielectric material in a semiconductor manufacturing sequence; and forming a barrier material in situ on the top electrode in a semiconductor manufacturing device to reduce oxidation of the top electrode when it is in an ex-situ position of the semiconductor manufacturing device.

[0023] In the following detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of the detailed description and in which one or more embodiments of the present disclosure are illustrated by way of diagrams. The description of these embodiments is detailed enough to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it should be understood that other embodiments may be utilized and that process changes, electrical changes, and / or structural changes may be made without departing from the scope of the present disclosure. As used herein, "multiple" things may refer to one or more such things. For example, multiple capacitors may refer to at least one capacitor.

[0024] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by using similar numerals. For example, reference numeral 104 may refer to Figure 1A Component "04" in the figure, and similar components can be found in Figure 2 204. Multiple similar elements in one figure may be referenced by a reference numeral followed by a hyphen and another number or letter. For example, 115-1 may be referenced by Figure 1C 15-1 in FIG. 15-2 may refer to element 15-2 which may be similar to element 115-1. Such similar elements may generally be referenced without hyphens and additional numbers or letters. For example, elements 115-1 and 115-2 or other similar elements may be referenced as 115 in general.

[0025] Figures 1A-1C Example cross-sectional views of storage nodes 130 , 132 , and 134 including barrier material 115 formed on electrodes 102 thereof are shown according to various embodiments of the present disclosure. Figures 1A-1C The storage nodes 130, 132, and 134 are illustrated as capacitors 130, 132, and 134 including the barrier material 115. However, embodiments of the present disclosure are not limited to capacitors as storage nodes.

[0026] Figure 1AA single-sided capacitor 130 is shown, in which a bottom electrode 118 in contact with a filling material 119 can be formed. Non-limiting examples of the filling material 119 include polysilicon, silicon nitride, titanium nitride, tungsten, and doped forms thereof. A dielectric material 104 in contact with the bottom electrode 118 can be formed. A non-limiting example of the dielectric material 104 is a zirconium oxide material. A top electrode 102 can be formed in contact with the dielectric material 104. Non-limiting examples of the top electrode 102 can include platinum (Pt) materials, ruthenium (Ru) materials, titanium nitride (TiN) materials, tungsten (W) materials, molybdenum (Mo) materials, tantalum nitride (TaN) materials, aluminum (Al) materials, rhodium (Rh) materials, tungsten nitride (WN) materials, and ruthenium oxide (RuO) materials.

[0027] The barrier material 115 is formed in contact with the top electrode 102. Figure 4-5C The formation of the barrier material 115 is further described. Non-limiting examples of the barrier material 115 may include a silicide material, a nitride material, a boride material, an aluminide material, a carbide material, a tungsten material, a combination thereof, and / or an alloy thereof. In at least one embodiment, the barrier material 115 may include a binary nitride material, such as a silicon nitride (SiN) material, a boron nitride (BN) material, a zirconium nitride (ZrN) material, a hafnium nitride (HfN) material, a germanium nitride (GeN) material, a tungsten nitride (WN) material, an aluminum nitride (AlN) material, a tantalum nitride (TaN) material, and a gallium nitride (GaN) material. In at least one embodiment, the barrier material 115 may include a ternary nitride material, such as a tungsten silicon nitride (WSiN) material, a titanium silicon nitride (TiSiN) material, a tungsten carbon nitride material (WCN), and a tungsten boron nitride (WBN) material.

[0028] In at least one embodiment, the barrier material 115 may include a binary carbide material such as titanium carbide (TiC), tungsten carbide (WC), and aluminum carbide (AlC). In at least one embodiment, the barrier material 115 may include titanium aluminum carbon nitride (TiAlCN).

[0029] Figure 1B A single sided capacitor 132 is shown in which a bottom electrode 118 can be formed in contact with a dielectric material 104. A top electrode 102 can be formed in contact with the dielectric material 104. A barrier material 115 can be formed in contact with the top electrode 102. A fill material 119 can be formed in contact with the barrier material 115.

[0030] Figure 1CA double-sided capacitor 134 is shown in which an inner barrier material 115-2 can be formed in contact with a fill material 119. The inner barrier material 115-2 can be formed in contact with an inner top electrode 102-2. An inner dielectric material 104-2 can be formed in contact with the inner top electrode 102-2 and the bottom electrode 118. An outer dielectric material 104-1 can be formed in contact with the bottom electrode 118 and the outer top electrode 102-1. An outer barrier material 115-2 can be formed in contact with the outer top electrode 102-1.

[0031] Figures 1A-1C Capacitors 130, 132, and 134 are shown as having circular cross-sections; however, embodiments of the present disclosure are not limited thereto. For example, capacitors 130, 132, and 134 may have square, rectangular, or other polygonal cross-sections. Any of capacitors 130, 132, and 134 may be a storage node of a memory cell. For example, a memory device may include a memory cell array that includes an array of capacitors 130, 132, and / or 134. Dielectric material 104 may be a storage node material of a storage node.

[0032] Figure 2 Shown Figure 1A An example cross-sectional side view of the storage node 130 taken along the cut line 2 - 2 is shown in FIG. 2 . The capacitor 230 and its components may be similar to the capacitor 130 and its components shown in FIG. 1 . Figure 2 The capacitor 130 is shown along Figure 1A The cross-sectional view is shown taken along the cutting line 2-2. Figure 1A The capacitor 230 is shown along Figure 2 A cross-sectional view taken along cutting line 1A-1A is shown.

[0033] like Figure 2 As shown, capacitor 230 may include bottom electrode 218 and may be formed in contact with substrate material 201. Filling material 219 may be formed in the cavity formed by bottom electrode 218. Dielectric material 204 may be formed in contact with bottom electrode 218 and filling material 219. Top electrode 202 may be formed in contact with dielectric material 204. Barrier material 215 may be formed in contact with top electrode 202. Figure 3-5C The formation of barrier material 215 is further described.

[0034] Figure 3A cross-sectional view of a working surface of a semiconductor structure 300 at a point in time in a semiconductor fabrication sequence according to various embodiments of the present disclosure is shown. The semiconductor structure 300 includes a top electrode 302 formed on a dielectric material 304. The top electrode 302 includes grains 306-1, 306-2, 306-3, 306-4, 306-5, 306-6, and 306-7 (collectively referred to as grains 306). Between two grains in the grains 306 is a gap between the grain boundaries of the two grains. Figure 3 A gap 308-1 between the grain boundaries of grains 306-1 and 306-2, a gap 308-2 between the grain boundaries of grains 306-2 and 306-3, a gap 308-3 between the grain boundaries of grains 306-3 and 306-4, a gap 308-4 between the grain boundaries of grains 306-4 and 306-5, a gap 308-5 between the grain boundaries of grains 306-5 and 306-6, and a gap 308-6 between the grain boundaries of grains 306-6 and 306-7 (collectively referred to as gaps 308) are shown.

[0035] One or more semiconductor fabrication sequences after forming the top electrode 302 on the dielectric material 304 may be performed in a semiconductor fabrication facility different from the semiconductor fabrication facility in which the top electrode 302 is formed on the dielectric material 304. Therefore, the top electrode 302 may be exposed to oxygen ex situ during transportation between the two semiconductor fabrication facilities. Since it is not protected, the top electrode may be oxidized during transportation between the two semiconductor fabrication facilities.

[0036] Oxidation may result in the formation of oxide material on the top electrode ( Figure 3 The oxide material may have a higher resistivity than the top electrode (not shown). The oxide material may have a higher resistivity than the top electrode (the oxide material may have a lower conductivity than the top electrode), such that the oxide material inhibits electrical conduction through the top electrode. The increased resistance of the oxide material may affect the operation and / or performance of the semiconductor structure 300. For example, timing problems may occur because the time it takes for an electrical signal to conduct through the top electrode 302 and the oxide material may be longer than expected. Figure 1A-2 As described, dielectric material 304 and top electrode 302 may be components of a memory cell, such as a capacitor. The increased resistance of the oxide material may adversely affect the capacitance of the capacitor of the memory cell including top electrode 302 and dielectric material 304.

[0037] To reduce the risk of oxidation of the top electrode 302, some previous methods include reducing the queue time between forming the top electrode 302 on the dielectric material 304 in the first semiconductor fabrication equipment and the subsequent processing steps performed in the second semiconductor fabrication equipment. However, strict time constraints may complicate the fabrication of semiconductor devices. Non-limiting examples of queue times may be in the range of 2-12 hours. For example, a delay in the second semiconductor fabrication equipment ready to receive the semiconductor structure may increase the risk of oxidation of the top electrode 302 after removal from the first semiconductor fabrication equipment and / or may cause a delay in removing the semiconductor structure from the first semiconductor fabrication equipment.

[0038] The gap 308 may provide a diffusion path for chemicals used in the semiconductor fabrication sequence to fabricate the semiconductor structure 300 after forming the top electrode 302 on the dielectric material 304 to reach the dielectric material 304. For example, chlorine species may damage the dielectric material 304, thereby causing a decrease in capacitance and / or an increase in current leakage in a memory cell including the top electrode 302 and the dielectric material 304.

[0039] Figure 4 A cross-sectional view of a working surface of a semiconductor structure 410 including a barrier material 412 at a certain point in time in a semiconductor fabrication sequence is shown according to various embodiments of the present disclosure. Figure 4 The time points shown in Figure 3 After the time point shown in FIG. 4 , the top electrode 402, the grain 406, the gap 408, and the dielectric material 404 may be combined with Figure 3 The top electrode 302, grains 306, gaps 308, and dielectric material 304 are similar to those described above. The barrier material 412 may be similar to the bonding Figure 1A-2 Barrier materials 115 and 215 are described.

[0040] In at least one embodiment, the top electrode 402 may be formed by atomic layer deposition (ALD). The barrier material 412 may be formed in situ on the top electrode 402 in the same semiconductor chamber where the top electrode 402 is formed on the dielectric material 404. However, the embodiments of the present disclosure are not limited thereto. Figure 4 As shown, barrier material 412 is formed on a top surface 414 of top electrode 402 .

[0041] In at least one embodiment, the barrier material 412 may be a silicon barrier material 412 formed by performing a silane soak on the top electrode 402. As used herein, "silane soak" refers to exposing a semiconductor structure to a silane-based gas. Examples of silane-based gases include, but are not limited to, monosilane, disilane, dichlorosilane (DCS), trichlorosilane (TCS), tris(dimethylamino)silane (3DMAS), tetra(dimethylamino)silane (4DMAS), and tetraethylsilanediamine. In at least one embodiment, after the silane soak of the top electrode 402, the top electrode may be exposed to a nitride precursor. Non-limiting examples of nitride precursors include ammonia, hydrazine, and amino derivatives. In at least one embodiment, forming the silicon nitride barrier material 412 may include at least one cycle of: exposing the top electrode 402 to a silicon precursor (e.g., a silane-based gas) in a semiconductor processing device; purging the silicon precursor from the semiconductor processing device; exposing the top electrode 402 to a nitride precursor; and purging the nitride precursor from the semiconductor processing device. In at least one embodiment where the top electrode 402 includes a nitride material (e.g., titanium nitride), each of the multiple cycles of exposing the top electrode 402 to the silane-based gas may form a sub-monolayer of the silicon nitride barrier material.

[0042] The silane soaking of the top electrode 402 can form a sub-monolayer of silicon nitride barrier material on the top surface 414 of the top electrode 402. Multiple silane soakings can be used to form a monolayer of silicon nitride barrier material. Each silane soaking can be used to form multiple sub-monolayers of silicon nitride barrier material stacked on each other. For example, multiple silane soakings can be used to form a monolayer of silicon nitride material having a thickness of about 0.1 angstroms to 5 angstroms on the top surface 414 of the top electrode 402.

[0043] In at least one embodiment, the formation of the silicon barrier material 412 by silane soaking can be a self-limiting process. In a non-self-limiting process, for example, a silicon precursor such as a silane-based gas may continue to decompose and form the silicon barrier material on the substrate material even if the silicon barrier material has been formed on all active sites. In contrast, the formation of the silicon barrier material 412 by one or more cycles of silane soaking as described herein can be a self-limiting process because there is a thermal window (e.g., in the range of 150° C. to 700° C., depending on the silicon precursor) where the silane-based gas will decompose, and the silicon barrier material 412 will only be formed on the active sites. Therefore, the formation of the silicon barrier material 412 will not disappear. In this way, a thin and controllable amorphous barrier material 412 can be formed on the top electrode 402.

[0044] Compared to some previous methods involving reducing the queue time between forming the top electrode 402 on the dielectric material 404 in the first semiconductor fabrication tool and the subsequent processing steps performed in the second semiconductor fabrication tool, the barrier material 412 can act as a barrier to prevent oxidation of the top electrode 402. Therefore, since the barrier material 412 can protect the underlying top electrode 402 from oxygen, the restriction on the queue time can be relaxed or even eliminated.

[0045] like Figure 4 As shown, the barrier material 412 may at least partially fill the gaps 408 between the grain boundaries of the grains 406 of the top electrode 402 and / or amorphize the top surface 414 of the top electrode 402. In contrast to the structured granular nature of the material comprising the top electrode 402, the barrier material 412 may be an amorphous material, thereby preventing access to the gaps 408 between the grain boundaries of the grains 406 of the material comprising the top electrode 402. Thus, in contrast to some previous approaches, in at least one embodiment, the barrier material 412 blocks diffusion paths such as the gaps 408 that may be available for chemicals used in a subsequent semiconductor fabrication sequence to pass through the top electrode 402 to reach the dielectric material 404. Thus, the barrier material 412 may protect the dielectric material 404 from oxygen scavenging by chemicals used in a subsequent semiconductor fabrication sequence. Scavenging oxygen from the dielectric material may cause cell leakage in a storage node of a memory cell containing the dielectric material. For example, the dielectric material 404 may be damaged by chlorine species used in a subsequent semiconductor fabrication sequence, resulting in reduced cell capacitance and / or cell leakage. Barrier material 412 can protect dielectric material 404 from chlorine corrosion due to reactive gases used in subsequent semiconductor fabrication sequences. Barrier material 412 can protect dielectric material 404 from boron diffusion from subsequent semiconductor fabrication sequences that diffuses through gap 408 into dielectric material 404 (which may cause cell leakage). Thus, barrier material 412 can minimize or prevent cell capacitance reduction and / or reduce cell leakage relative to previous approaches.

[0046] Although not in Figure 4 4, but a portion of the silicon barrier material 412 may be oxidized and form a silicon oxide material at an ex-situ location of the semiconductor fabrication equipment. The silicon oxide material formed on the silicon barrier material 412 may act as another barrier material to prevent oxidation of the top electrode 402. Oxygen may be trapped in the silicon barrier material 412, thereby preventing oxygen from reaching and oxidizing the top electrode 402.

[0047] The top surface 414 of the top electrode 402 can have irregularities. These irregularities can cause large variations in the resistivity of the electrode including the top electrode 402. The surface of the barrier material 412 can be more uniform than the surface 414. The more uniform surface of the barrier material 412 can cause less variation (e.g., reduced variability) in the resistivity of the electrode including the top electrode 402 having the barrier material 412 formed thereon.

[0048] Figures 5A-5C FIG. 5 shows a cross-sectional view of a working surface of semiconductor structures 520, 521, and 523 including barrier material 522 at a certain point in a semiconductor fabrication sequence according to various embodiments of the present disclosure. The top electrode 502, the grain 506, the gap 508, and the dielectric material 504 may be similar to the combination of Figure 4 The top electrode 402, grain 406, gap 408 and dielectric material 404 are depicted. The barrier material 522 may be similar to the bonding Figure 1A-2 Barrier materials 115 and 215 are described.

[0049] Combined with Figure 4 In contrast to the exemplary embodiments described, in conjunction with Figures 5A-5C In the exemplary embodiment described, the barrier material 522 is formed by doping the top electrode 502 with a precursor during the formation of the top electrode 502. The precursor may include, but is not limited to, a silicon (Si) precursor, a boron (B) precursor, a zirconium (Zr) precursor, a hafnium (Hf) precursor, a germanium (Ge) precursor, an aluminum (Al) precursor, a gallium (Ga) precursor, a carbon (C) precursor, a tungsten (W) precursor, a tungsten silicide (WSi) precursor, a titanium silicide (TiSi) precursor, a tungsten carbide (WC) precursor, and a tungsten boride (WB) precursor. Non-limiting examples of boron precursors may include borane (BH3), diborane (B2H6), boron trifluoride (BF3), and boron tribromide (BBr3). Non-limiting examples of aluminum precursors may include trimethylaluminum (TMA) and aluminum chloride (AlCl3). Non-limiting examples of carbon precursors may include methane (CH4), ethane (C2H6), propane (C3H8), and acetylene (C2H2). A non-limiting example of a tungsten precursor may be tungsten hexafluoride (WF6).

[0050] In at least one embodiment of the present disclosure, the top electrode 502 may be a titanium nitride material. The titanium nitride material may be formed by ALD. For example, the titanium nitride material may be formed using a titanium nitride ALD scheme. In at least one embodiment, the titanium nitride ALD scheme may be a TN ALD scheme; however, the embodiments of the present disclosure are not limited thereto. The TN ALD scheme may include introducing a titanium precursor into a semiconductor fabrication apparatus (T), and then the semiconductor fabrication apparatus may be purged. Subsequently, a nitrogen precursor may be introduced into a semiconductor fabrication apparatus (N), and then the semiconductor fabrication apparatus may be purged. Non-limiting examples of nitride precursors include ammonia, hydrazine, and amino derivatives.

[0051] The precursor may be introduced into the semiconductor fabrication equipment before the nitrogen precursor is introduced into the semiconductor fabrication equipment or after the nitrogen precursor is purged from the semiconductor fabrication equipment. For example, the silicon precursor may be introduced into the semiconductor fabrication equipment containing the dielectric material 504 during the formation of the top electrode 502. The silicon precursor may be introduced into the semiconductor fabrication equipment at a flow rate of about 1 standard cubic centimeter per minute (sccm) to 1,000 sccm. The silicon precursor may be introduced into the semiconductor fabrication equipment, for example, for up to about 120 seconds. The silicon precursor may be introduced into the semiconductor fabrication equipment at a temperature in the range of about 150° C. to 700° C.

[0052] Forming the top electrode 502 may include multiple cycles of a titanium nitride ALD regimen. Controlling when the precursors are introduced into the semiconductor fabrication equipment during the formation of the top electrode 502 controls where the barrier material 522 is formed within or on the top electrode 502. Figure 5A A cross-sectional view of a semiconductor structure 520 is shown with a barrier material 522 formed near or on a top surface 514 of a top electrode 502 . Figure 5B A cross-sectional view of a semiconductor structure 521 with a barrier material 522 formed within a top electrode 502 is shown. Figure 5C A cross-sectional view of a semiconductor structure 523 is shown with a barrier material 522 formed near the interface 516 of the top electrode 502 .

[0053] like Figures 5A-5C The position of the control nitride material 522 in or on the top electrode 502 can be adjusted to include a storage node (e.g., in conjunction with Figures 1A-1C The performance of the storage node of the memory cell with the top electrode 502 as the electrode of the capacitor 130, 132 and 134 and the dielectric material 504 as the storage node material can be adjusted by controlling the position of the nitride material 522 in or on the top electrode 502. Non-limiting examples of performance factors of the storage node that can be adjusted by controlling the position of the nitride material 522 in or on the top electrode 502 include cell leakage, cell resistance and breakdown voltage. For example, Figure 5BAs shown, the barrier material 522 is formed in the middle of the top electrode 502 of the semiconductor structure 521. Figure 5C As shown, forming barrier material 522 near interface 516 of semiconductor structure 523 can further reduce cell leakage. Figure 5C Compared with forming a barrier material 522 near the interface 516 of the semiconductor structure 523, as shown in Figure 5B Forming the barrier material 522 in the middle of the top electrode 502 of the semiconductor structure 521 may result in a higher breakdown voltage.

[0054] exist Figure 5A In the exemplary embodiment shown, the precursor is introduced into the semiconductor fabrication equipment during the formation of the top electrode 502, such that the barrier material 522 is formed near the top surface 514 of the top electrode 502, rather than near the interface 516 of the top electrode 502 and the dielectric material 504. For example, the silicon precursor may be introduced during one or more of the final cycles of the TN ALD scheme described herein, such that the barrier material 522 is formed near the top surface 514 of the top electrode 502. The cycle of introducing the silicon precursor may include introducing the silicon precursor into the semiconductor fabrication equipment, purging the semiconductor fabrication equipment, introducing the nitrogen precursor into the semiconductor fabrication equipment, and purging the semiconductor fabrication equipment. Although Figure 5A Although not specifically shown in FIG. 5 , a layer of the top electrode 502 may be formed on the barrier material 522 when at least one cycle of ALD of the top electrode 502 occurs after the precursors are introduced into the semiconductor fabrication equipment.

[0055] exist Figure 5B In the exemplary embodiment shown, the precursor is introduced into the semiconductor fabrication equipment during the formation of the top electrode 502, such that the barrier material 522 is formed approximately in the middle of the top electrode 502, rather than near the top surface 514 of the top electrode 502 or the interface 516 of the top electrode 502 and the dielectric material 504. For example, the silicon precursor can be introduced midway through one or more cycles of the TN ALD scheme described herein by forming a titanium nitride material on the dielectric material 504, such that the barrier material 522 is formed within the titanium nitride material. In this manner, a first deposition including the material of the top electrode 502 can be formed on the dielectric material 504, and the barrier material 522 can be formed on the first deposition including the material of the top electrode 502. A second deposition including the material of the top electrode 502 can be formed on the barrier material 522.

[0056] exist Figure 5CIn the exemplary embodiment shown, the precursor is introduced into the semiconductor fabrication tool during the formation of the top electrode 502, so that the barrier material 522 is formed approximately near the interface 516 between the top electrode 502 and the dielectric material 504, rather than near the surface 514. For example, the silicon precursor can be introduced during one or more of the initial cycles of the TN ALD scheme described herein, so that the barrier material 522 is formed near the interface 516 of the titanium nitride material and the dielectric material 504. Although Figure 5C Not specifically shown, when at least one cycle of ALD of the top electrode 502 occurs before the precursors are introduced into the semiconductor fabrication equipment, a layer of the top electrode 502 may be formed on the top electrode 502 between the dielectric material 504 and the barrier material 522.

[0057] As described herein, barrier material 522 may act as a barrier to prevent oxidation of top electrode 502. Figures 5A-5C As shown, the barrier material 522 may at least partially fill the gaps 508 between the grain boundaries of the grains 506 of the top electrode 502. Figure 5A As shown, the barrier material 522 can at least partially fill the gap 508 and / or amorphize the top surface 514 of the top electrode 502. In contrast to the structured granular nature of the material comprising the top electrode 502 (e.g., titanium nitride material), the barrier material 522 can be an amorphous material, thereby preventing access to the gap 508 between the grain boundaries of the grains 506 of the material comprising the top electrode 502. Therefore, the barrier material 522 can protect the dielectric material 504 from oxygen scavenging by chemicals used in subsequent semiconductor fabrication sequences. The barrier material 522 can protect the dielectric material 504 from chlorine corrosion due to reactive gases used in subsequent semiconductor fabrication sequences. The barrier material 522 can protect the dielectric material 504 from boron diffusion from the subsequent semiconductor fabrication sequence through the gap 508 to the dielectric material 504 (which may cause cell leakage). Therefore, relative to previous methods, the barrier material 522 can minimize or prevent a decrease in cell capacitance, minimize or prevent an increase in cell resistance, reduce cell leakage, and / or increase breakdown voltage.

[0058] although Figures 5A-5C A single instance of barrier material 522 is shown, but at least one embodiment of the present disclosure may include more than one instance of barrier material 522 formed at different locations on and / or within top electrode 502. For example, at least one embodiment may include a combination of Figure 5A The barrier material 522 is formed on the top electrode 502 in the first embodiment, and as combined Figure 5B The barrier material 522 is formed in the second example of the top electrode 502. At least one embodiment may include a combination of Figure 5BMultiple instances of the barrier material 522 are formed at different locations within the top electrode 502 .

[0059] Figure 6 6 is a functional block diagram of an apparatus 640 for implementing an example semiconductor fabrication sequence according to various embodiments of the present disclosure. The system 640 may include a processing apparatus 641 (eg, a semiconductor fabrication apparatus). The processing apparatus 641 may be configured to enable in-situ formation of a barrier material on a top electrode.

[0060] The processing device 641 may include a semiconductor processing chamber 642 for enclosing a semiconductor device configured to be disposed in the semiconductor processing chamber 642 at a top electrode (e.g., in combination with Figures 1A-5C The barrier material is formed in situ on the top electrode 102, 202, 302, 402 and 502 described above (for example, in combination with Figure 1A-2 and Figure 4-5C 115, 215, 412, and 522 described herein). The semiconductor processing chamber 642 may further enclose a carrier 643 for accommodating a batch of semiconductor wafers 644 including a top electrode. The processing equipment 641 may include and / or be associated with a tool configured to introduce and remove precursors as described herein to form a barrier material on the top electrode, the tool including, for example, a pump unit 645 and a purge unit 646. In at least one embodiment, the processing equipment 641 may include and / or be associated with a tool configured to introduce and remove precursors as described herein to form a top electrode and a barrier material on the top electrode, the tool including a pump unit 645 and a purge unit 646. The processing equipment 641 may further include a temperature control unit 647 configured to maintain the semiconductor processing chamber 642 at an appropriate temperature as described herein (e.g., between about 150° C. and about 700° C.).

[0061] The system 640 can further include a controller 648. The controller 648 can include or be associated with circuitry and / or programming for implementing, for example, in-situ formation of a barrier material on the top electrode. Adjustments to such deposition and purge operations by the controller 648 can control the thickness of the barrier material and / or the location of the barrier material within or on the top electrode, as described herein.

[0062] In various embodiments, the controller 648 may be configured to use hardware as a control circuit system. Such control circuit system may be, for example, an application specific integrated circuit (ASIC) having logic for controlling the fabrication steps of in-situ forming the barrier material on the top electrode through associated deposition and purge processes.

[0063] Figure 7750 is a flow chart of an example method 750 for forming a barrier material on a top electrode according to various embodiments of the present disclosure. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, multiple method embodiments described herein or elements thereof may be performed at the same time point or substantially the same time point.

[0064] At block 752, method 750 may include forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence. At block 754, method 750 may include forming a barrier material on the top electrode in situ in a semiconductor fabrication facility to reduce damage to the dielectric material when in an ex-situ location in the semiconductor fabrication facility.

[0065] In at least one embodiment, the method may include forming a barrier material on the top electrode to reduce oxidation of the top electrode that occurs when in an ex-situ position of the semiconductor fabrication equipment. In at least one embodiment, forming the barrier material may include forming a silicon barrier material on the top electrode. Forming the silicon barrier material may include exposing the top electrode to a silicon precursor. Exposing the top electrode to the silicon precursor may include exposing the top electrode to a silane-based gas. Exposing the top electrode to the silane-based gas may include exposing the top electrode to multiple cycles of the silane-based gas, each cycle forming a sub-monolayer of the silicon barrier material. In at least one embodiment, forming the barrier material may include forming a nitride barrier material on the top electrode. In at least one embodiment, forming the barrier material may include forming a boron barrier material on the top electrode. Forming the silicon barrier material may include exposing the top electrode to a boron precursor. In at least one embodiment, forming the barrier material may include forming an aluminum barrier material on the top electrode. Forming the aluminum barrier material may include exposing the top electrode to an aluminum precursor. Forming the barrier material may include forming a carbide barrier material on the top electrode. Forming the carbide barrier material may include exposing the top electrode to a carbon precursor.

[0066] Although not specifically shown, an example method for forming a silicon barrier material on a top electrode according to multiple embodiments of the present disclosure may include: forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence; and forming a silicon barrier material in situ on the top electrode in a semiconductor fabrication device to reduce damage to the dielectric material that occurs when it is in an ex-situ position of the semiconductor fabrication device. In at least one embodiment, forming the top electrode may include forming a first portion of the top electrode, and forming the silicon barrier material may include forming the barrier material on the first portion of the top electrode. The method may further include forming a second portion of the top electrode so that the silicon barrier material is formed between the first portion and the second portion of the top electrode. In at least one embodiment, forming the top electrode may include forming the top electrode to a thickness in a range of 10 angstroms to 60 angstroms. Forming the silicon nitride material may include forming the silicon barrier material to a thickness in a range of 0.1 angstroms to 5 angstroms. Forming the silicon barrier material includes exposing the top electrode to multiple cycles of a silane-based gas, each cycle forming a sub-monolayer of the silicon barrier material. In at least one embodiment, forming the silicon barrier material may include ALD of the silicon barrier material on the top electrode. The method may further include exposing the top electrode to a silicon precursor and heating a semiconductor fabrication equipment to a temperature in a range of about 150° C. to 700° C. The method may further include introducing the silicon precursor into the semiconductor fabrication equipment at a flow rate in a range of about 1 sccm to 1,000 sccm. In one example, the method may further include exposing the top electrode to the silicon precursor for up to about 120 seconds.

[0067] Figure 8 is a functional block diagram of a computing system 860 including at least one memory array having a structure formed according to various embodiments of the present disclosure. Figure 8 In the example shown, the system 864 includes a memory interface 866, a plurality of memory devices 870-1, ..., 870-N, and a controller 868 selectively coupled to the memory interface 866 and the memory devices 870-1, ..., 870-N. The system 864 can be, for example, a solid state drive (SSD). The memory interface 866 can be used to transfer information between the system 860 and another device such as a host 862. The host 862 can include a processor (not shown). As used herein, a "processor" can be a plurality of processors (such as a parallel processing system), a plurality of coprocessors, etc. Example hosts can include or be implemented in laptop computers, personal computers, digital cameras, digital recording and playback devices, mobile phones, PDAs, memory card readers, interface hubs, etc.

[0068] In various examples, the host 862 can be associated with (e.g., include or be coupled to) a host interface 863. The host interface 863 can enable input of scaled preferences (e.g., in digitally and / or structurally defined gradients) to define, for example, a critical dimension (CD) of a final structure or intermediate structure of a memory device (e.g., memory device 870-1) and / or a memory cell array formed thereon (e.g., memory array 867) for implementation by a processing device. The scaled preferences can be provided to the host interface 863 via input of a plurality of preferences stored by the host 862, input of preferences from another storage system (not shown), and / or input of preferences by a user (e.g., a human operator).

[0069] The memory interface 866 may take the form of a standardized physical interface. For example, when the system 864 is used to store information (e.g., data) in the computing system 860, the memory interface 866 may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, as well as other physical connectors and / or interfaces. However, in general, the memory interface 866 may provide an interface for passing control, addresses, information, scaled preferences, and / or other signals between a controller 868 of the system 864 and a host 862 (e.g., via a host interface 863).

[0070] Controller 868 may include, for example, firmware and / or control circuitry (e.g., hardware). Controller 868 may be operably coupled to and / or included on the same physical device (e.g., die) as one or more of memory devices 870-1, ..., 870-N. For example, controller 868 may be or may include an ASIC in hardware that is operably coupled to circuitry (e.g., printed circuit board) that includes memory interface 866 and memory devices 870-1, ..., 870-N. Alternatively, controller 868 may be included on a separate physical device that is communicatively coupled to a physical device (e.g., die) that includes one or more of memory devices 870-1, ..., 870-N.

[0071] Controller 868 can communicate with memory devices 870-1, ..., 870-N to instruct operations for sensing (e.g., reading), programming (e.g., writing), and / or erasing information and implement other functions and / or operations for managing memory cells. Controller 868 can have circuitry that can include multiple integrated circuits and / or discrete components. In multiple examples, the circuitry in controller 868 can include control circuitry for controlling access across memory devices 870-1, ..., 870-N and / or circuitry for providing a translation layer between host 862 and system 864.

[0072] Memory devices 870-1, ..., 870-N may include, for example, a plurality of memory arrays 867 (eg, arrays of volatile and / or non-volatile memory cells). For example, memory devices 870-1, ..., 870-N may include a plurality of memory arrays 867 (eg, arrays of volatile and / or non-volatile memory cells). Figure 1A-2 and Figure 4-5C As will be appreciated, the memory cells in the memory array 867 of the memory devices 870-1, ..., 870-N may be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash memory architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM and / or flash memory cell architecture, or some other memory array architecture that includes a barrier material formed in situ on a top electrode as described herein.

[0073] Memory devices 870-1, ..., 870-N may be formed on the same die. A memory device (e.g., memory device 870-1) may include one or more memory cell arrays formed on a die in a memory cell array 867. Memory device 870-1 may include a sensing circuit system 865 and a control circuit system 861 or a portion thereof associated with one or more memory arrays 867 formed on a die. For example, sensing circuit system 865 may be used to determine (sense) a specific data value (e.g., 0 or 1) stored at a specific memory cell in a row of array 867. In addition to indicating storage, erasure, etc. of a data value in response to a command from host 862 and / or host interface 863, control circuit system 861 may also be used to instruct sensing circuit system 865 to sense a specific data value. The command may be sent directly to control circuit system 861 via memory interface 866 or sent to control circuit system 861 via controller 868.

[0074] Figure 8The examples shown in the drawings may include additional circuitry that is not shown so as not to obscure the examples of the present disclosure. For example, the memory devices 870-1, ..., 870-N may include address circuitry to latch address signals provided on the I / O connectors by the I / O circuitry. The address signals may be received and decoded by the row decoders and column decoders to access the memory array 867. It should be understood that the number of address input connectors may depend on the density and / or architecture of the memory devices 870-1, ..., 870-N and / or the memory array 867.

[0075] In the above detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of the detailed description and in which one or more embodiments of the present disclosure are shown by way of illustration how the present disclosure may be practiced. The embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it should be understood that other embodiments may be utilized and that process changes, electrical changes and / or structural changes may be made without departing from the scope of the present disclosure.

[0076] It should be understood that the terms used herein are used only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" include singular and plural referents, as do "a number of", "at least one" and "one or more" (for example, a plurality of memory arrays may refer to one or more memory arrays), while "plurality of" means more than one such thing. In addition, throughout this application, the words "can" and "may" are used in a permissive sense (i.e., it is possible, able to) rather than a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". The terms "coupled" and "coupling" refer to a physical direct or indirect connection, and unless otherwise specified, may include a wireless connection for accessing and / or moving (transmitting) instructions (e.g., control signals, address signals, etc.) and data depending on the context.

[0077] Although example embodiments including various combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches, and other materials and / or components related to a covering that determines the characteristics of a memory array have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly listed herein. Combinations and configurations other than the combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches related to a covering that determines the characteristics of a memory array disclosed herein are expressly included within the scope of the present disclosure.

[0078] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements intended to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and non-restrictive manner. After reading the above description, the combination of the above-described embodiments and other embodiments not specifically described herein will be apparent to those of skill in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims together with the full scope of equivalents to which such claims are assigned.

[0079] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for making a semiconductor device, comprising: forming (752) a top electrode (102, 202, 302, 402, 502) of a storage node (130, 132, 134) on a dielectric material (104, 204, 304, 404, 504) using a semiconductor fabrication sequence; as well as forming (754) a barrier material (115, 215, 412, 522) in-situ on the top electrode in a semiconductor fabrication apparatus (641) to reduce damage to the dielectric material when in an ex-situ location in the semiconductor fabrication apparatus, Wherein forming the barrier material on the top electrode comprises at least partially filling gaps between grain boundaries of the top electrode with the barrier material through a self-limiting process to block diffusion paths to the dielectric material, thereby reducing damage to the dielectric material during subsequent processing of the storage node, and wherein the self-limiting process comprises exposing the top electrode to a silane-based gas.

2. The method according to claim 1, further comprising: The barrier material (115, 215, 412, 522) is formed on the top electrode (102, 202, 302, 402, 502) to reduce oxidation of the top electrode when in an ex-situ location of the semiconductor fabrication equipment (641).

3. The method of any one of claims 1-2, wherein forming the barrier material (115, 215, 412, 522) comprises forming a silicon barrier material on the top electrode (102, 202, 302, 402, 502) by exposing the top electrode to the silane-based gas.

4. The method of claim 3, wherein forming the silicon barrier material comprises exposing the top electrode (102, 202, 302, 402, 502) to a plurality of cycles of the silane-based gas, each cycle forming a sub-monolayer of the silicon barrier material.

5. The method of claim 3, wherein forming the silicon barrier material comprises atomic layer deposition (ALD) of the silicon barrier material on the top electrode (102, 202, 302, 402, 502).

6. The method of any of claims 1-2, wherein forming the barrier material (115, 215, 412, 522) further comprises forming a nitride barrier material on the top electrode (102, 202, 302, 402, 502).

7. The method of any one of claims 1-2, wherein forming the barrier material (115, 215, 412, 522) further comprises forming a boron barrier material on the top electrode (102, 202, 302, 402, 502) by exposing the top electrode to a boron precursor.

8. The method of any one of claims 1-2, wherein forming the barrier material (115, 215, 412, 522) further comprises forming an aluminum barrier material on the top electrode (102, 202, 302, 402, 502) by exposing the top electrode to an aluminum precursor.

9. The method of any one of claims 1-2, wherein forming the barrier material (115, 215, 412, 522) further comprises forming a carbide barrier material on the top electrode (102, 202, 302, 402, 502) by exposing the top electrode to a carbon precursor.

10. A semiconductor device comprising: Top electrode (102, 202, 302, 402, 502); a barrier material (115, 215, 412, 522) formed on a first surface (414, 514) of the top electrode; and a dielectric material (104, 204, 304, 404, 504), wherein the second surface (416, 516) of the top electrode is in direct contact with the dielectric material, The barrier material at least partially fills gaps between grain boundaries of the top electrode to block diffusion paths to the dielectric material through a self-limiting process, thereby reducing damage to the dielectric material, and wherein the self-limiting process includes exposing the top electrode to a silane-based gas.

11. The semiconductor device of claim 10, wherein the barrier material (115, 215, 412, 522) has a higher resistivity than the top electrode (102, 202, 302, 402, 502).

12. The semiconductor device according to any one of claims 10 to 11, wherein the semiconductor device is a memory device (870-1, 870-N) comprising a memory cell array (867), and At least one memory cell of the array includes a storage node (130, 132, 134) comprising the barrier material (115, 215, 412, 522), the top electrode (102, 202, 302, 402, 502) and the dielectric material (104, 204, 304, 404, 504).

13. The semiconductor device of claim 10, wherein the barrier material (115, 215, 412, 522) amorphizes the first surface (414, 514) of the top electrode (102, 202, 302, 402, 502).

14. The semiconductor device according to any one of claims 10, 11 and 13, wherein the barrier material (115, 215, 412, 522) comprises at least one of the following: boron nitride material, zirconium nitride material, hafnium nitride material, germanium nitride material, tungsten nitride material, aluminum nitride material, tantalum nitride material and gallium nitride material.

15. A semiconductor device comprising: A top electrode (502); a barrier material (522) formed within the top electrode; as well as a dielectric material (504), wherein a surface (516) of the top electrode is in direct contact with the dielectric material, wherein the top electrode (502) comprises: a first deposit of a metallic material on the dielectric material (504); as well as a second deposit of the metallic material on the barrier material (522) such that the barrier material is located between the first deposit and the second deposit of the metallic material, wherein the barrier material at least partially fills gaps between grain boundaries of the first deposit of the metal material to block diffusion paths to the dielectric material through a self-limiting process, thereby reducing damage to the dielectric material, and wherein the self-limiting process includes exposing the first deposit of the metal material to a silane-based gas.

16. The semiconductor device of claim 15, wherein the barrier material (522) comprises at least one of: a tungsten carbon nitride material, a tungsten boron nitride material, a titanium carbide material, a tungsten carbide material, and an aluminum carbide material.

17. The semiconductor device of claim 15, wherein the barrier material (522) comprises an alloy of a carbide material and a nitride material.

18. The semiconductor device of claim 15, wherein the second deposit is composed of the same material as the first deposit.

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